Package substrate and manufacturing method therefor, and semiconductor package

Abstract

The present application relates to the technical field of semiconductors, and discloses a package substrate and a manufacturing method therefor, and a semiconductor package. The package substrate comprises a circuit base layer, a plurality of circuit build-up layers, and a solder mask layer sequentially stacked. Each circuit build-up layer comprises: an insulating medium, a patterned metal layer, and a via interconnection. Each patterned metal layer is arranged on the side of the insulating medium away from the corresponding circuit base layer. Each via interconnection at least partially passes through the corresponding insulating medium. Each circuit base layer and the corresponding patterned metal layer of the circuit build-up layer adjacent to the circuit base layer are electrically connected to the corresponding via interconnection, and the patterned metal layers of any two adjacent circuit build-up layers are electrically connected by means of the corresponding via interconnection. At least some of the plurality of circuit build-up layers are embedded circuit build-up layers, and the patterned metal layer of each embedded circuit build-up layer is embedded in a side surface of the insulating medium corresponding to the patterned metal layer. By integrating embedded circuit build-up layers based on an ETS process into PCB build-up layers, highly refined and high-density circuits can be achieved in the PCB build-up layers at low costs.

Description

Package substrate, method for manufacturing the same, and semiconductor package

[0001] The present application claims priority from the Chinese patent application No. 202411338228.1, filed on September 24, 2024, and entitled "Package substrate, method for manufacturing the same, and semiconductor package", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a package substrate, a method for manufacturing the same, and a semiconductor package. BACKGROUND

[0003] A package substrate, also known as an IC carrier board, can connect a die and a printed circuit board (PCB) and transmit signals therebetween, and is widely used in semiconductor packaging. With the miniaturization and high-density development of semiconductor packages, it is necessary to reduce the circuit line width and the solder ball pitch of the package substrate to improve its packaging density.

[0004] In terms of realizing PCB layering, the line processing of the PCB currently usually adopts a Tenting process, which has a low cost, but the line level formed thereby is greater than or equal to 50 μm, and fine line processing cannot be realized. At present, although the semi-additive process (SAP) and the modified semi-additive process (MSAP) can be used for fine line processing, they have high requirements for processing equipment and are high in cost. It can be seen that it is necessary to realize fine line processing at a low cost based on PCB resources.

[0005] DISCLOSURE

[0006] The embodiments of the present disclosure provide a package substrate, a method for manufacturing the same, and a semiconductor package, which can solve the technical problems existing in the related art, and the technical solutions are as follows.

[0007] In one aspect, a package substrate is provided, comprising: a circuit base layer, a plurality of circuit build-up layers and a solder mask layer arranged in sequence, each of the circuit build-up layers comprising: an insulating medium, a patterned metal layer disposed on a side of the insulating medium distal to the circuit base layer, and a via interconnect at least partially penetrating the insulating medium; the circuit base layer and the patterned metal layer of the circuit build-up layer adjacent thereto, and the patterned metal layers of any two adjacent circuit build-up layers, are electrically connected through the corresponding via interconnects; wherein at least some of the plurality of circuit build-up layers are embedded circuit build-up layers, and the patterned metal layer of the embedded circuit build-up layer is embedded in a side surface of the corresponding insulating medium.

[0008] The package substrate provided by the embodiments of the present disclosure realizes PCB build-up by disposing multiple circuit build-up layers on the circuit base layer. At least some of the multiple circuit build-up layers are embedded circuit build-up layers based on the ETS process. According to the principle of the ETS process, the patterned metal layer of the embedded circuit build-up layer can be pre-processed on a carrier plate through the ETS process and exhibit as a fine circuit with high precision. Subsequently, by pressing and embedding the patterned metal layer of the embedded circuit build-up layer into the insulating medium and removing the carrier plate, and etching the copper seed layer, the embedded circuit build-up layer can be combined to the circuit base layer or other circuit build-up layers through the insulating medium. On this basis, by punching (e.g., laser punching) the insulating medium of the embedded circuit build-up layer and metalizing the holes, a via interconnect can be formed in the insulating medium of the embedded circuit build-up layer to realize the interlayer connection of the embedded circuit build-up layer and the circuit base layer or other circuit build-up layers adjacent thereto. It can be seen that, by combining the embedded circuit build-up layer based on the ETS process into the PCB build-up, the package substrate provided by the embodiments of the present disclosure can obtain a highly fine and high-density circuit in the PCB build-up. The ETS process is simple to operate and has low cost, so that the embodiments of the present disclosure realize the processing of fine circuits based on PCB resources at low cost, and overcome the technical bottleneck and high cost problem of PCB in processing fine circuits.

[0009] In some possible implementations, some of the plurality of circuit build-up layers are exposed circuit build-up layers, and the patterned metal layer of the exposed circuit build-up layer is arranged protruding on a side surface of the corresponding insulating medium; wherein the line width and the line spacing of the patterned metal layer of the exposed circuit build-up layer are greater than the line width and the line spacing of the patterned metal layer of the embedded circuit build-up layer, respectively.

[0010] In some possible implementations, the patterned metal layer comprises: a trace and a pad electrically connected to the trace, and the pad is further electrically connected to the via interconnect; and the pad of the embedded circuit build-up layer comprises at least one of a hole-free pad and a hole-containing pad.

[0011] In some possible implementation manners, the pad of the buried build-up layer is a via pad, and correspondingly, the via interconnect of the buried build-up layer comprises a first type of via interconnect, the first type of via interconnect comprising: a via portion, and a landing pad connected to the via portion; the via portion penetrating through the insulating medium and the pad of the current buried build-up layer, and the landing pad overlapping the surface of the pad of the current buried build-up layer.

[0012] In some possible implementation manners, the thickness of the landing pad is greater than the thickness of the overlapped pad; wherein the pad thickness is the dimension of the pad in the direction perpendicular to the insulating medium.

[0013] In some possible implementation manners, the pad of the buried build-up layer is a non-via pad, and correspondingly, the via interconnect of the buried build-up layer comprises a second type of via interconnect; the second type of via interconnect penetrating through the insulating medium of the current buried build-up layer, and two ends of the second type of via interconnect being connected to the pad of the current buried build-up layer and the pad of another build-up layer adjacent to the current buried build-up layer respectively, wherein the second type of via interconnect is formed by curing of conductive paste.

[0014] In some possible implementation manners, in the direction away from the circuit base layer, an exposed build-up layer is arranged on the buried build-up layer in a stacked manner, the via interconnect of the buried build-up layer and the via interconnect of the exposed build-up layer are integrally connected and form a third type of via interconnect; the pad of the buried build-up layer is a via pad, the pad of the exposed build-up layer is a non-via pad, the third type of via interconnect penetrating through the insulating medium and the pad of the buried build-up layer and the insulating medium of the exposed build-up layer in sequence, and the sidewall of the third type of via interconnect being connected to the pad of the buried build-up layer, and one end of the third type of via interconnect being connected to the pad of the exposed build-up layer.

[0015] In another aspect, a preparation method of a packaging substrate is provided, the packaging substrate being any of the above described, the preparation method of the packaging substrate comprising:

[0016] providing a circuit base layer, and sequentially preparing a plurality of build-up layers and solder mask layers on the circuit base layer to obtain the packaging substrate;

[0017] wherein at least part of the plurality of build-up layers is a buried build-up layer, and the preparation method of the buried build-up layer comprises:

[0018] preparing a patterned metal layer on a carrier substrate by a buried circuit preparation process to obtain a buried build-up layer intermediate;

[0019] Under the guiding action of the alignment device, the buried circuit build-up intermediate is aligned with the interlayer interconnection position of the circuit base layer or other prepared circuit build-up layers, and the buried circuit build-up intermediate is laminated to the circuit base layer or other prepared circuit build-up layers by a prepreg, and the prepreg forms the insulating medium.

[0020] The carrier plate is removed, and the hole interconnection of the buried circuit build-up is prepared at the interlayer interconnection position of the buried circuit build-up intermediate before or after the lamination operation, and the buried circuit build-up is obtained.

[0021] The preparation method of the packaging substrate provided by the embodiments of the present disclosure can realize high-precision and high-density buried circuits in any layer by designing an any layer embedded pattern (AEP) in a PCB build-up, so that the precision of line width / line spacing is more excellent and easier to control. Moreover, the preparation method of the packaging substrate is relatively simple in process, and the high-density buried circuit layer is processed in advance. Under the assistance of high-precision alignment, the interlayer combination is realized by a prepreg, and then the interlayer interconnection of the newly added circuit build-up is performed. The hole interconnection is formed between any two adjacent circuit build-ups, which is relatively simple in operation, low in cost, and avoids mechanical drilling with a large hole diameter on multiple circuit build-ups at the same time, thereby ensuring the realization of high-density circuits.

[0022] In some possible implementation manners, the pad of the buried circuit build-up is a hole pad, and the hole interconnection of the buried circuit build-up includes a first type of hole interconnection; the first type of hole interconnection is prepared after the lamination operation, and the preparation method of the first type of hole interconnection includes: punching at the interlayer interconnection position of the insulating medium of the buried circuit build-up, and forming the first type of hole interconnection at the punching position by an electroplating process.

[0023] In some possible implementation manners, the pad of the buried circuit build-up is a holeless pad, and the hole interconnection of the buried circuit build-up includes a second type of hole interconnection; the second type of hole interconnection is prepared before the lamination operation, and the preparation method of the second type of hole interconnection includes: pre-laminating the prepreg to the circuit base layer or other prepared circuit build-up, and the prepreg forms the insulating medium; under the guiding action of the alignment device, punching at the interlayer interconnection position of the insulating medium of the buried circuit build-up, filling conductive paste into the punching position, and then performing the lamination operation, so as to form the second type of hole interconnection by the conductive paste.

[0024] In some possible implementation manners, the buried build-up layer is arranged with an exposed build-up layer in a direction away from the circuit substrate, the via interconnection of the buried build-up layer and the via interconnection of the exposed build-up layer are matched to form a third type of via interconnection, and the pad of the buried build-up layer is a via pad and the pad of the exposed build-up layer is a non-via pad; the third type of via interconnection is prepared after the pressing operation, and the preparation method of the third type of via interconnection comprises the following steps: after the insulating medium and the patterned metal layer of the buried build-up layer are formed through the pressing operation, another prepreg is pre-pressed to the insulating medium of the buried build-up layer, and the other prepreg forms the insulating medium of the exposed build-up layer; punching is simultaneously performed at the interlayer interconnection positions of the insulating medium of the exposed build-up layer and the insulating medium of the buried build-up layer, and the third type of via interconnection is formed at the punching positions through an electroplating process.

[0025] In still another aspect, a semiconductor package is provided, comprising: a package substrate as described in any of the above or prepared by the preparation method described in any of the above; and an electronic component connected to an outermost build-up layer of the plurality of build-up layers of the package substrate. BRIEF DESCRIPTION OF DRAWINGS

[0026] FIG. 1 is a structural schematic diagram of a first exemplary package substrate provided by an embodiment of the present disclosure;

[0027] FIG. 2 is a structural schematic diagram of an exemplary printed circuit substrate provided by an embodiment of the present disclosure;

[0028] FIG. 3 is a preparation process one of a second exemplary package substrate provided by an embodiment of the present disclosure;

[0029] FIG. 4 is a preparation process two of the second exemplary package substrate provided by an embodiment of the present disclosure;

[0030] FIG. 5 is a preparation process three of the second exemplary package substrate provided by an embodiment of the present disclosure;

[0031] FIG. 6 is a preparation process four of the second exemplary package substrate provided by an embodiment of the present disclosure;

[0032] FIG. 7 is a preparation process five of the second exemplary package substrate provided by an embodiment of the present disclosure and a structural schematic diagram of the second exemplary package substrate;

[0033] FIG. 8 is a structural schematic diagram of a third exemplary package substrate provided by an embodiment of the present disclosure;

[0034] FIG. 9 is a structural schematic diagram of a fourth exemplary package substrate provided by an embodiment of the present disclosure;

[0035] FIG. 10 is a structural schematic diagram of a fifth exemplary packaging substrate according to an embodiment of the present disclosure;

[0036] FIG. 11 is a structural schematic diagram of a sixth exemplary packaging substrate according to an embodiment of the present disclosure;

[0037] FIG. 12 is a structural schematic diagram of an exemplary semiconductor package according to an embodiment of the present disclosure.

[0038] The reference signs represent: 001, packaging substrate; 002, electronic component; 1, circuit base layer; 2, circuit build-up layer; 201, embedded circuit build-up layer; 202, exposed circuit build-up layer; 21, insulating medium; 22, patterned metal layer; 221, trace; 222, pad; 23, via interconnection; 231, first type of via interconnection; 2311, via portion; 2312, stepped pad; 232, second type of via interconnection; 233, third type of via interconnection; 3, solder resist layer; 4, carrier substrate; 5, copper seed layer.

[0039] In the packaging substrates exemplified in the above figures, the number of circuit layers included in the circuit build-up layer is exemplified as small, for example, two or three, for the purpose of simplifying the structure of the packaging substrate for the purpose of facilitating the illustration of the figures, and is not intended to limit the number of circuit layers included in the circuit build-up layer to be more, and based on the structure shown in the figures, the number and structure of the circuit build-up layer of the packaging substrate can be expanded. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0041] In the description of the embodiments of the present disclosure, it should be understood that the terms “upper”, “lower”, “length”, “width”, “thickness” and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0042] At present, the demand for chips is gradually increasing, and it is expected that the chip will be lighter and thinner, the data transmission rate will be faster, and the power consumption will be smaller, which makes it impossible to simply rely on the advanced process of the chip to improve the performance of the chip. The advanced process of the chip is difficult to break through, and Moore's law is facing a bottleneck that is difficult to break through. Therefore, in the post-Moore era, advanced packaging has become a breakthrough direction for improving chip packaging density and I / O.

[0043] For the traditional chip packaging architecture, the chip Die is re-wired through the redistribution layer (RDL), and then connected on the carrier board through flip, wire bonding and other connection methods to complete packaging. The packaging module is fixed on the PCB board through surface mount technology (SMT) to form a 2.5D / 3D packaging structure of Die (RDL) + flip chip ball grid array packaging (FCBGA) + PCB. The pin number and packaging density are high, and it is widely used in various types of high operation performance chip packaging.

[0044] With the increase of pin number and packaging density, the following physical indicators of the PCB board: solder ball pitch, line width / line spacing directly determine the wiring density, wiring layer number and processing cost of the packaging substrate.

[0045] The line processing of the PCB currently usually adopts Tenting process, which has low cost, but the formed line level is greater than or equal to 50μm, which cannot realize the processing of fine lines. Although the semi-additive process (SAP) and the modified semi-additive process (MSAP) can be used for fine line processing, they have high requirements for processing equipment and high cost. Therefore, it is necessary to realize the processing of fine lines based on the PCB resources at low cost.

[0046] To solve the technical problems in the related art, the present embodiment provides a packaging substrate 001, and FIG. 1 shows the structure of an example packaging substrate 001. As shown in FIG. 1, the packaging substrate 001 includes: a circuit base layer 1, a plurality of circuit additional layers 2 and a solder mask layer 3 arranged in sequence. Each circuit additional layer 2 includes: an insulating medium 21, a patterned metal layer 22 and a hole interconnection 23. The patterned metal layer 22 is arranged on the side of the insulating medium 21 away from the circuit base layer 100, and the hole interconnection 23 at least partially penetrates the insulating medium 21. The circuit base layer 1 and the patterned metal layer 22 of the circuit additional layer 2 adjacent to the circuit base layer 1 are electrically connected through the corresponding hole interconnection 23. The patterned metal layer 22 of any two adjacent circuit additional layers 2 is electrically connected through the corresponding hole interconnection 23. At least part of the plurality of circuit additional layers 2 is a buried circuit additional layer 201, and the patterned metal layer 22 of the buried circuit additional layer 201 is embedded in the side surface of the corresponding insulating medium 21.

[0047] It should be noted that the "buried circuit additional layer" involved in the present embodiment refers to a circuit layer prepared by an embedded trace substrate (ETS) preparation process.

[0048] The process of preparing a buried circuit by an ETS process is generally as follows: a copper seed layer 5 (for example, an ultra-thin copper foil) is arranged on one side or both sides of a carrier plate 4, a rough copper tooth is formed on the copper seed layer 5, and then a dry film (i.e., a mask film) is covered thereon. After pattern exposure, development, electroplating, and film stripping, a patterned metal layer is obtained, which is a high-precision fine circuit. Then, the insulating resin (a prepreg is used in the present embodiment) is pre-pressed to the prepared patterned metal layer, so that the patterned metal layer is embedded in one side of the insulating resin.

[0049] When the ETS process is used to prepare the buried circuit additional layer 201 of the present embodiment, it can be exemplarily explained in combination with FIGS. 3-5. As shown in FIG. 3, the pattern electroplating is performed on one side of the carrier plate 4 with the copper seed layer 5 to obtain a high-precision buried circuit additional layer 201. As shown in FIG. 4, under the guidance of an alignment device, the buried circuit additional layer 201 supported by the carrier plate 4 is aligned and combined with the circuit base layer 1 or other circuit additional layers 2 (an exposed circuit additional layer 202 is exemplified in FIG. 4) through the prepreg. After pressing treatment, the prepreg forms the insulating medium 21 of the buried circuit additional layer 201, the high-precision patterned metal layer 22 is embedded in the side surface of the insulating medium 21, the carrier plate 4 is removed, and the copper seed layer 5 is etched to expose the patterned metal layer 22 of the buried circuit additional layer 201. Then, as shown in FIG. 5, the hole interconnection 23 of the buried circuit additional layer 201 is made to realize the interlayer interconnection.

[0050] The embedded line build-up 201 based on the ETS process can avoid side etching of the line during etching operation, because the patterned metal layer 22 (e.g. copper layer) is embedded in the insulating medium 21, so that the embedded line build-up 201 has strong advantages in fine line production, for example, the line width / line spacing of the embedded line build-up 201 can be less than 15 μm / 15 μm, the line width compensation can be not compensated, or the line width compensation is less than 2 um, the line precision is + / - 2 um, the line etching process is eliminated, the line width precision is defined by exposure, the line width and impedance fluctuation is reduced, and the impedance precision is improved, for example, compared with the Tenting and mSAP processes, the impedance fluctuation is improved to 8%-10%.

[0051] It should be noted that the "line base layer 1" involved in the embodiments of the present disclosure can be a semi-finished product of a multi-layer printed circuit board, that is, an intermediate state of a multi-layer PCB board, which can include one or more line layers, for example, FIG. 2 illustrates that the line base layer 1 is a single line layer, which includes: a glass fiber medium and a line layer protrudingly arranged on the surface of the glass fiber medium, the line layer can be prepared by using a conventional PCB line production process, for example, a Tenting process, the line layer includes a trace and a plurality of pads connected to the trace, and the plurality of pads of the line layer are used for interlayer interconnection with the line build-up layer 2.

[0052] FIG. 1 illustrates that the line build-up layer 2 is provided as two layers, and FIG. 2 further illustrates that a first line build-up layer 2 (referred to as BU01) is provided on the line base layer 1, the first line build-up layer 2 (BU01) can also be prepared by using a conventional PCB line production process, for example, a Tenting process, so that the first line build-up layer 2 (BU01) is an exposed line build-up layer 202. It can be seen that FIG. 1 illustrates that the line build-up layer 2 close to the line base layer 1 in the two line build-up layers 2 is an exposed line build-up layer 202 (i.e. the first line build-up layer 2, BU01), and the line build-up layer 2 far away from the line base layer 1 is an embedded line build-up layer 201 (i.e. the second line build-up layer 2, BU02).

[0053] The packaging substrate 001 provided by the embodiments of the present disclosure realizes PCB build-up by arranging a plurality of circuit build-up layers 2 on the circuit base layer 1. At least part of the plurality of circuit build-up layers 2 is an embedded circuit build-up layer 201 based on the ETS process. According to the principle of the ETS process, the patterned metal layer 22 of the embedded circuit build-up layer 201 can be pre-processed on the carrier plate 4 by the ETS process and exhibit high-precision fine circuits. Subsequently, the patterned metal layer 22 of the embedded circuit build-up layer 201 is pressed and embedded into the insulating medium 21, the carrier plate 4 is removed, and the copper seed layer 5 is etched, so that the embedded circuit build-up layer 201 is combined to the circuit base layer 1 or other circuit build-up layers 2 through the insulating medium 21. On this basis, by punching (for example, laser punching) the insulating medium 21 of the embedded circuit build-up layer 201 and metalizing the holes, a hole interconnection 23 can be formed in the insulating medium 21 of the embedded circuit build-up layer 201 to realize the interlayer connection of the embedded circuit build-up layer 201 and the circuit base layer 1 or other circuit build-up layers 2 adjacent thereto. It can be seen that, by combining the embedded circuit build-up layer 201 based on the ETS process into the PCB build-up, the packaging substrate 001 provided by the embodiments of the present disclosure can obtain highly fine and high-density circuits in the PCB build-up. The ETS process is simple to operate and low in cost, so that the embodiments of the present disclosure realize the processing of fine circuits based on the PCB resources at low cost, and overcome the technical bottleneck and high cost problem of PCB in processing fine circuits.

[0054] The packaging substrate related by the embodiments of the present disclosure is arranged in multiple layers, and the multiple circuit build-up layers can be arranged on one side of the circuit base layer 1 (not shown in the figure) or symmetrically arranged on opposite sides of the circuit base layer 1 (see FIG. 1). When arranged on both sides, it is more advantageous to improve the packaging density of the packaging substrate 001.

[0055] In some examples, all of the circuit build-up layers 2 can be arranged as embedded circuit build-up layers 201 (not shown in the figure). In other examples, part of the circuit build-up layers 2 can be arranged as embedded circuit build-up layers 201, and the other part of the circuit build-up layers 2 can be arranged as exposed circuit build-up layers 202. The patterned metal layer 22 of the exposed circuit build-up layer 202 is arranged on one side surface of the corresponding insulating medium 21, which can be prepared by a conventional PCB circuit manufacturing process, such as the Tenting process. This makes the line width and line spacing of the patterned metal layer 22 of the exposed circuit build-up layer 202 greater than those of the patterned metal layer 22 of the embedded circuit build-up layer 201. By combining the embedded circuit build-up layer 201 and the exposed circuit build-up layer 202 to form the multiple circuit build-up layers 2, the circuit arrangement is more flexible, and the packaging substrate 001 has both fine circuits and thick circuits.

[0056] When the multi-layered build-up layer 2 is a combination of the buried build-up layer 201 and the exposed build-up layer 202, the combination form can be set in multiple types according to actual needs, which includes but is not limited to the following examples: circuit base layer 1-single layer exposed build-up layer 202-single layer or multi-layer buried build-up layer 201; circuit base layer 1-single layer exposed build-up layer 202-single layer or multi-layer buried build-up layer 201-single layer exposed build-up layer 202; circuit base layer 1-single layer or multi-layer buried build-up layer 201-single layer exposed build-up layer 202; circuit base layer 1-multi-layer exposed build-up layer 202-multi-layer buried build-up layer 201-single layer exposed build-up layer 202; circuit base layer 1-multi-layer buried build-up layer 201-single layer or multi-layer exposed build-up layer 202, and the like.

[0057] Taking the package substrate 001 shown in FIG. 1 as an example, it is illustrated that the combination form of the circuit base layer 1-single layer exposed build-up layer 202-single layer buried build-up layer 201-solder mask layer 3. By setting a layer of exposed build-up layer 202 as the first build-up layer 2 (BU01) on the circuit base layer 1, a relatively thick circuit is formed at the middle position of the package substrate 001. Further, a layer of buried build-up layer 201 is set as the second build-up layer 2 (referred to as BU02) on the first build-up layer 2 (BU01), so as to realize the processing of fine circuits in the package substrate 001.

[0058] For the build-up layer 2 (i.e. the buried build-up layer 201 and the exposed build-up layer 202) involved in the embodiments of the present disclosure, as shown in FIG. 4, the patterned metal layer 22 includes: a trace 221 and a pad 222 electrically connected to the trace 221, and the pad 222 is also electrically connected to the via interconnection 23. Wherein, the trace 221 is used as a signal transmission wiring.

[0059] The pad 222 of the buried build-up layer 201 includes at least one of a hole-free pad and a hole pad, wherein, similarly, the hole pad refers to having a via in the direction perpendicular to the insulating medium 21, so that the pad is a discontinuous structure, so as to facilitate laser punching of the insulating medium 21 exposed to the discontinuous area of the pad, and ensure the implementability and fineness control of the punching.

[0060] According to the type of the via interconnection 23, the type of the pad 222 of the buried build-up layer 201 can be determined. The pad 222 of the exposed build-up layer 202 is usually a hole-free pad.

[0061] The arrangement of the circuitry build-up layers 2 and the interlayer connection manner will be described in combination with the package substrate 001 shown in FIG. 1. As shown in FIG. 1, the package substrate 001 includes a circuit substrate layer 1, two circuitry build-up layers 2 and a solder mask layer 3 arranged in sequence. The first circuitry build-up layer 2 (BU01) is an exposed circuitry build-up layer 202, which includes a patterned metal layer 22 protruding from the surface of the insulating medium 21 of the exposed circuitry build-up layer 202. The patterned metal layer 22 includes a plurality of pads 222. The second circuitry build-up layer 2 (BU02) is a buried circuitry build-up layer 201, which includes a patterned metal layer 22 protruding from the surface of the insulating medium 21 of the buried circuitry build-up layer 201. The patterned metal layer 22 includes a plurality of pads 222. The line width and the line spacing of the patterned metal layer 22 of the first circuitry build-up layer 2 (BU01) are both greater than the line width and the line spacing of the patterned metal layer 22 of the second circuitry build-up layer 2 (BU02), that is, the patterned metal layer 22 of the second circuitry build-up layer 2 (BU02) is a high-precision fine circuit.

[0062] The plurality of pads 222 of the first circuitry build-up layer 2 (BU01) are in one-to-one correspondence with the plurality of pads 222 of the second circuitry build-up layer 2 (BU02), and each pad 222 of the first circuitry build-up layer 2 (BU01) is electrically connected to a pad 222 of the second circuitry build-up layer 2 (BU02) through a hole interconnection 23 of the second circuitry build-up layer 2 (BU02).

[0063] In the embodiments of the present disclosure, the hole interconnection 23 of the buried circuitry build-up layer 201 can be located in the hole of the insulating medium 21 and connected to the pad 222, or the hole interconnection 23 of the buried circuitry build-up layer 201 not only includes the part located in the hole of the insulating medium 21, but also further includes the pad part located on the surface of the insulating medium 21, which will be described in the following examples:

[0064] In some examples, as shown in FIGS. 5-7, the pad 222 of the buried circuitry build-up layer 201 is a hole pad, and accordingly, the hole interconnection 23 of the buried circuitry build-up layer 201 includes a first type of hole interconnection 231, which includes a via part 2311 and a stepped pad 2312 connected to the via part 2311. The via part 2311 penetrates the insulating medium 21 and the pad 222 of the current buried circuitry build-up layer 201, and the stepped pad 2312 overlaps the surface of the pad 222 of the current buried circuitry build-up layer 201.

[0065] Further in combination with FIG. 5, the second build-up layer 2 (BU02) is a buried build-up layer 201, one end of the via portion 2311 of the first type of hole interconnection 231 is connected to the pad 222 of the first build-up layer 2 (BU01), and the other end of the via portion 2311 is connected to the step pad 2312, and the step pad 2312 is overlapped to the pad 222 of the current buried build-up layer 201, thereby realizing the interlayer conduction between the first build-up layer 2 (BU01) and the second build-up layer 2 (BU02).

[0066] In the direction parallel to the insulating medium 21, the radial dimension of the step pad 2312 of the first type of hole interconnection 231 is generally smaller than the radial dimension of the overlapped pad 222, thereby avoiding the deposition of the step pad 2312 to the insulating medium 21 to cause line interference on the basis of realizing the interconnection.

[0067] When the buried build-up layer 201 is provided as a multi-layer, the hole interconnection 23 of the multi-layer buried build-up layer 201 can be the first type of hole interconnection 231, or part of the hole interconnection 23 of the buried build-up layer 201 can be the first type of hole interconnection 231, which can be designed according to actual needs.

[0068] Further, as shown in FIG. 10, the thickness of the step pad 2312 can be greater than the thickness of the pad 222 of the current buried build-up layer 201; wherein the pad thickness is the dimension of the pad 222 along the direction perpendicular to the insulating medium 21.

[0069] The buried build-up layer 201 where the step pad 2312 is currently located can be locally thickened or integrally thickened, for example, based on the MSAP electroplating process, the thickening design of the buried build-up layer 201 can be realized, the thickness of the patterned metal layer is increased, which is not only beneficial to the conduction and flow-through between the interconnection structures, but also beneficial to improve the heat dissipation effect between the interconnection structures.

[0070] In other examples, as shown in FIG. 8, the pad 222 of the buried build-up layer 201 is a non-hole pad, and accordingly, the hole interconnection 23 of the buried build-up layer 201 includes a second type of hole interconnection 232. The second type of hole interconnection 232 penetrates the insulating medium 21 of the current buried build-up layer 201, and two ends of the second type of hole interconnection 232 are respectively connected to the pad 222 of the current buried build-up layer 201 and the pad 222 of another build-up layer 2 adjacent to the current buried build-up layer 201, wherein the second type of hole interconnection 232 is formed by conductive paste curing.

[0071] For this example, the second type of hole interconnection 232 can be formed before the pad 222 of the current embedded build-up layer 201, for example, by punching a hole in the prepreg corresponding to the insulating medium 21 of the current embedded build-up layer 201, and filling the punched hole with a conductive paste, such as a metal conductive paste (copper paste, etc.), and then heating and curing the prepreg and the conductive paste, so as to prepare the second type of hole interconnection 232 to realize interlayer interconnection.

[0072] The second type of hole interconnection 232 does not form a step on the surface of the pad 222 of the current embedded build-up layer 201, so as to avoid the existence of a step difference between the interconnection structures, which can reduce signal loss.

[0073] When the embedded build-up layer 201 is provided as multiple layers, the hole interconnections 23 of the multiple embedded build-up layers 201 can all be the second type of hole interconnection 232, or part of the hole interconnections 23 of the embedded build-up layers 201 can be the second type of hole interconnection 232, which can be designed according to actual needs.

[0074] In yet another example, as shown in FIG. 9, in the direction away from the line base layer 1, the embedded build-up layer 201 is arranged to be stacked with an exposed build-up layer 202, the hole interconnection 23 of the embedded build-up layer 201 and the hole interconnection 23 of the exposed build-up layer 202 are integrally connected and form a third type of hole interconnection 233; the pad 222 of the embedded build-up layer 201 is a hole pad, the pad 222 of the exposed build-up layer 202 is a non-hole pad, the third type of hole interconnection 233 penetrates the insulating medium 21 and the pad 222 of the embedded build-up layer 201 and the insulating medium 21 of the exposed build-up layer 202 in sequence, and the sidewall of the third type of hole interconnection 233 is connected to the pad 222 of the embedded build-up layer 201, and one end of the third type of hole interconnection 233 is connected to the pad 222 of the exposed build-up layer 202.

[0075] The laser punching can be performed on the insulating medium 21 of the embedded build-up layer 201 and the insulating medium 21 of the exposed build-up layer 202 at the same time, for example, a deep V hole is punched as shown in FIG. 9, and then a third type of hole interconnection 233 is formed in the punched hole through an electroplating process, so as to integrally connect the hole interconnection 23 of the embedded build-up layer 201 and the hole interconnection 23 of the exposed build-up layer 202. By such arrangement, not only the step pad is avoided on the surface of the pad 222 of the embedded build-up layer 201, but also the transmission loss caused by the existence of a step difference between the interconnection pads is avoided, and the structure of the interlayer interconnection structure is simplified, and the preparation process is simplified.

[0076] When the combination of the embedded line increasing layer 201 and the exposed line increasing layer 202 is arranged in multiple, the hole interconnections 23 involved in the multiple combinations can all be the third type of hole interconnection 233, or part of the hole interconnections 23 in the combination can be the third type of hole interconnection 233, which can be designed according to actual needs.

[0077] The combination scheme of the multi-layer line increasing layer 2 will be exemplarily described below in combination with FIGS. 7-11, which only show a small number of line increasing layers 2. Based on the concept of the combination scheme of the line increasing layer 2 described below, further adaptive modifications (for example, increasing the number of line increasing layers 2), equivalent replacements or improvements can be made, which all belong to the structure of the package substrate 001 provided by the embodiments of the present disclosure.

[0078] In some embodiments (1), as shown in FIG. 7, the package substrate 001 includes the circuit substrate layer 1-first line increasing layer 2 (BU01)-second line increasing layer 2 (BU02)-third line increasing layer 2 (BU03)-fourth line increasing layer 2 (BU04)-solder resist layer 3 arranged in sequence. Among them, the first line increasing layer 2 (BU01) and the fourth line increasing layer 2 (BU04) are both exposed line increasing layers 202, and the second line increasing layer 2 (BU02) and the third line increasing layer 2 (BU03) are both embedded line increasing layers 201. The hole interconnections 23 of the second line increasing layer 2 (BU02) and the third line increasing layer 2 (BU03) are both the first type of hole interconnection 231. The pads 222 of the second line increasing layer 2 (BU02) and the third line increasing layer 2 (BU03) are hole pads.

[0079] For the second line increasing layer 2 (BU02), the via portion 2311 of the first type of hole interconnection 231 penetrates the insulating medium 21 and the pad 222 of the second line increasing layer 2 (BU02), and the two ends of the via portion 2311 of the first type of hole interconnection 231 are connected to the pad 222 of the first line increasing layer 2 (BU01) and the current step pad 2312, respectively. The step pad 2312 of the first type of hole interconnection 231 is overlapped to the surface of the pad 222 of the second line increasing layer 2 (BU02).

[0080] For the third line increasing layer 2 (BU03), the via portion 2311 of the first type of hole interconnection 231 penetrates the insulating medium 21 and the pad 222 of the third line increasing layer 2 (BU03), and the two ends of the via portion 2311 of the first type of hole interconnection 231 are connected to the step pad 2312 of the second line increasing layer 2 (BU02) and the current step pad 2312, respectively. The step pad 2312 of the first type of hole interconnection 231 is overlapped to the surface of the pad 222 of the third line increasing layer 2 (BU03).

[0081] In some embodiments (2), as shown in FIG. 8, the package substrate 001 comprises a circuit base layer 1 - a first build-up layer 2 (BU01 ) - a second build-up layer 2 (BU02) - a third build-up layer 2 (BU03) - a fourth build-up layer 2 (BU04) - a solder resist layer 3, which are arranged in sequence. Among them, the first build-up layer 2 (BU01 ) and the fourth build-up layer 2 (BU04) are both exposed build-up layers 202, and the second build-up layer 2 (BU02) and the third build-up layer 2 (BU03) are both buried build-up layers 201. The via interconnections 23 of the second build-up layer 2 (BU02) and the third build-up layer 2 (BU03) are both second-type via interconnections 232 (i.e. solid cylinders). The pads 222 of the second build-up layer 2 (BU02) and the third build-up layer 2 (BU03) are both non-via pads.

[0082] For the second build-up layer 2 (BU02), the second-type via interconnections 232 thereof penetrate the insulating medium 21 of the second build-up layer 2 (BU02), and the two ends of the second-type via interconnections 232 are respectively connected to the pads 222 of the second build-up layer 2 (BU02) and the pads 222 of the first build-up layer 2 (BU01 ).

[0083] For the third build-up layer 2 (BU03), the second-type via interconnections 232 thereof penetrate the insulating medium 21 of the third build-up layer 2 (BU03), and the two ends of the second-type via interconnections 232 are respectively connected to the pads 222 of the third build-up layer 2 (BU03) and the pads 222 of the second build-up layer 2 (BU02).

[0084] In some embodiments (3), as shown in FIG. 9, the package substrate 001 comprises a circuit base layer 1 - a first build-up layer 2 (BU01 ) - a second build-up layer 2 (BU02) - a third build-up layer 2 (BU03) - a fourth build-up layer 2 (BU04) - a solder resist layer 3, which are arranged in sequence. Among them, the first build-up layer 2 (BU01 ), the third build-up layer 2 (BU03) and the fourth build-up layer 2 (BU04) are all exposed build-up layers 202, and the second build-up layer 2 (BU02) is a buried build-up layer 201. The via interconnections 23 of the second build-up layer 2 (BU02) and the third build-up layer 2 (BU03) are integrally connected to form third-type via interconnections 233. The pads 222 of the second build-up layer 2 (BU02) are via pads.

[0085] The third type of hole interconnection 233 penetrates the insulating medium 21 of the second build-up layer 2 (BU02) and the pad 222 in turn, and the insulating medium 21 of the third build-up layer 2 (BU03), and the sidewall of the third type of hole interconnection 233 is connected to the pad 222 of the second build-up layer 2 (BU02), and the two ends of the third type of hole interconnection 233 are connected to the pad 222 of the first build-up layer 2 (BU01) and the pad 222 of the third build-up layer 2 (BU03) respectively.

[0086] Of course, it is not excluded that for the scheme of laminating the buried build-up layer 201 and the exposed build-up layer 202, the structure of the hole interconnection 23 is not limited to the above-mentioned embodiment (3), but can also be as shown in FIGS. 10 and 11, which are further illustrated below.

[0087] In some embodiments (4), as shown in FIG. 10, the package substrate 001 comprises a circuit substrate 1-first build-up layer 2 (BU01)-second build-up layer 2 (BU02)-third build-up layer 2 (BU03)-solder resist layer 3 arranged in turn. Among them, the first build-up layer 2 (BU01) and the third build-up layer 2 (BU03) are both exposed build-up layers 202, and the second build-up layer 2 (BU02) is a buried build-up layer 201.

[0088] The hole interconnection 23 of the second build-up layer 2 (BU02) adopts the first type of hole interconnection 231. The pad 222 of the second build-up layer 2 (BU02) is a hole pad.

[0089] For the second build-up layer 2 (BU02), the via portion 2311 of the first type of hole interconnection 231 thereof penetrates the insulating medium 21 and the pad 222 of the second build-up layer 2 (BU02), and the two ends of the via portion 2311 of the first type of hole interconnection 231 are connected to the pad 222 of the first build-up layer 2 (BU01) and the current step pad 2312 respectively, the step pad 2312 of the first type of hole interconnection 231 is overlapped to the surface of the pad 222 of the second build-up layer 2 (BU02), and the thickness of the step pad 2312 is greater than the thickness of the overlapped pad 222 of the second build-up layer 2 (BU02).

[0090] For the third build-up layer 2 (BU03), the hole interconnection 23 is arranged in the insulating medium 21 of the third build-up layer 2 (BU03) in turn, and the two ends of the hole interconnection 23 of the third build-up layer 2 (BU03) are connected to the step pad 2312 of the first type of hole interconnection 231 and the pad 222 of the third build-up layer 2 (BU03) respectively.

[0091] In some embodiments (5), as shown in FIG. 11, the packaging substrate 001 comprises a circuit base layer 1 - a first circuit build-up layer 2 (BU01) - a second circuit build-up layer 2 (BU02) - a third circuit build-up layer 2 (BU03) - a solder resist layer 3 arranged in sequence. Among them, the first circuit build-up layer 2 (BU01) and the third circuit build-up layer 2 (BU03) are both exposed circuit build-up layers 202, and the second circuit build-up layer 2 (BU02) is a buried circuit build-up layer 201.

[0092] The hole interconnects 23 of the second circuit build-up layer 2 (BU02) are the second type of hole interconnects 232. The pads 222 of the second circuit build-up layer 2 (BU02) and the third circuit build-up layer 2 (BU03) are hole-free pads.

[0093] For the second circuit build-up layer 2 (BU02), the second type of hole interconnects 232 thereof penetrate the insulating medium 21 of the second circuit build-up layer 2 (BU02), and the two ends of the second type of hole interconnects 232 are connected to the pads 222 of the second circuit build-up layer 2 (BU02) and the pads 222 of the first circuit build-up layer 2 (BU01), respectively.

[0094] For the third circuit build-up layer 2 (BU03), the hole interconnects 23 of the third circuit build-up layer 2 (BU03) are arranged to penetrate the insulating medium 21 of the third circuit build-up layer 2 (BU03), and the two ends of the hole interconnects 23 of the third circuit build-up layer 2 (BU03) are connected to the pads 222 of the second circuit build-up layer 2 (BU02) and the pads 222 of the third circuit build-up layer 2 (BU03), respectively.

[0095] For any of the packaging substrates 001 described above, the insulating medium 21 of the buried circuit build-up layer 201 and the insulating medium 21 of the exposed circuit build-up layer 202 can be prepared by using a prepreg (PP). The prepreg, also known as a pre-impregnated material, can provide good bonding. The prepreg comprises a resin and a reinforcing material, which includes but is not limited to glass fiber (referred to as glass fiber), paper-based, composite reinforcing material, etc. For example, the insulating medium described in the embodiments of the present disclosure can use glass fiber as the reinforcing material, and the resin type can use epoxy resin, so that when laminated, the epoxy resin of the prepreg melts, flows, and solidifies, thereby pressing the circuit layers of each layer and forming a reliable insulating medium.

[0096] For any of the packaging substrates 001 described above, the patterned metal layer 22 can be formed by using a metal with good conductivity, for example, the metal can be copper.

[0097] In summary, the structure of the multi-layer circuit layer 2 of the packaging substrate 001 can be adaptively determined according to the actual application requirements and application scenarios of the packaging substrate 001, the buried circuit layer 201 is prepared by using the ETS process, the exposed circuit layer 202 is prepared by using the conventional PCB layering process, and the fine circuit layer with high precision and high density is arranged on any layer of the PCB layering, so that the wiring density is improved and the fine circuit is processed at low cost based on any inner layer of the PCB of the packaging substrate 001.

[0098] In another aspect, the disclosure also provides a preparation method of any of the above-mentioned packaging substrates 001. The packaging substrate 001 can refer to any of the above-mentioned packaging substrates 001. FIG. 3 to FIG. 7 illustrate a preparation process of an exemplary packaging substrate 001. In combination with FIG. 3 to FIG. 7, the preparation method of the packaging substrate 001 includes: providing a circuit base layer 1, and sequentially preparing a plurality of circuit layers 2 and a solder mask layer 3 on the circuit base layer 1 to obtain the packaging substrate 001.

[0099] In the plurality of circuit layers 2, at least part of the circuit layers 2 are buried circuit layers 201. The preparation method of the buried circuit layer 201 includes:

[0100] In step S1, as shown in FIG. 3, a patterned metal layer 22 is prepared on a carrier plate 4 by using a buried circuit preparation process to obtain a buried circuit layer intermediate body.

[0101] In step S2, under the guidance of an alignment device, the buried circuit layer intermediate body is aligned with an interlayer interconnection position of the circuit base layer 1 or other prepared circuit layers 2, and the buried circuit layer intermediate body is pressed to the circuit base layer 1 or other prepared circuit layers 2 by using a prepreg, and the prepreg forms an insulating medium 21.

[0102] In step S3, the carrier plate 4 is removed, and a hole interconnection 23 of the buried circuit layer 201 is prepared at the interlayer interconnection position of the buried circuit layer intermediate body before or after the pressing operation to obtain the buried circuit layer 201.

[0103] The carrier plate 4 has a roughened copper seed layer 5, and the patterned metal layer 22 is formed on the copper seed layer 5 of the carrier plate 4. Therefore, the structure of the buried circuit layer intermediate body is shown in FIG. 3, which includes the patterned metal layer 22, the copper seed layer 5, and the carrier plate 4 arranged in sequence.

[0104] After the preparation of the patterned metal layer 22 with fine circuits is completed, as shown in FIG. 4, the patterned metal layer 22 is pressed with a first circuit layer 2 (BU01). The first circuit layer 2 (BU01) can be prepared on the circuit base layer 1 in advance.

[0105] When step S2 is performed, it is necessary to ensure that the embedded circuit build-up intermediate body is aligned with the interlayer interconnection position of the circuit base layer 1 or other prepared circuit build-up layer 2, as shown in FIG. 4, so that the plurality of pads 222 of the first circuit build-up layer 2 (BU01) is aligned with the plurality of pads 222 of the second circuit build-up layer 2 (BU02), achieving high-precision alignment, which is particularly important for the interlayer interconnection accuracy of the packaging substrate 001.

[0106] The embodiments of the present disclosure achieve high-precision alignment between layers through the guidance of the alignment device, which is selected from at least one of an X-Ray alignment device, a visual alignment device (for example, a Bonding visual alignment device, a Charge-Coupled Device (CCD) visual alignment device), and the like. The above-mentioned alignment devices have the advantages of high positioning accuracy and high reliability.

[0107] When positioning, a certain point on the layer to be aligned can be taken as a target, for example, the pad 222 on the second circuit build-up layer 2 (BU02) can be taken as a target (for example, the pad size can be designed to be larger), and the pad 222 on the first circuit build-up layer 2 (BU01) can be taken as another target. The positioning device can complete accurate alignment by recognizing the two targets.

[0108] Taking the X-Ray alignment device as an example, a ray beam can penetrate through the layers to develop an image of the target, and then the center of the target can be positioned to ensure that the two targets overlap, achieving positioning.

[0109] Taking the CCD visual alignment device as an example, the two targets on the CCD visual alignment device are calculated to determine the target position, so as to ensure that the two targets overlap, achieving positioning.

[0110] Steps S1-S3 achieve the preparation of the embedded circuit build-up layer 201 and the interlayer interconnection. On this basis, whether step S4 needs to be further implemented can be determined according to the specific structure of the circuit build-up layer 2.

[0111] Step S4, as shown in FIG. 6, determines whether to continue to build up according to the structure of the circuit build-up layer 2. After the preparation of the circuit build-up layer 2 is completed, a solder resist layer 3 is prepared on the outermost circuit build-up layer 2, obtaining the packaging substrate 001.

[0112] In the above, FIG. 6 illustrates that a third build-up layer 2 (BU03) in the form of a buried build-up layer is continuously prepared on the second build-up layer 2 (BU02), and FIG. 7 illustrates that a fourth build-up layer 2 (BU04) in the form of an exposed build-up layer is prepared on the third build-up layer 2 (BU03) as a surface layer, and a solder resist layer 3 is prepared on the fourth build-up layer 2 (BU04) to complete the preparation of the packaging substrate 001.

[0113] The solder resist layer 3, commonly known as green oil, is prepared by using a solder resist to protect the outermost traces from oxidation and influences of moisture, mechanical stress, etc.

[0114] It should be noted that, in the preparation process of the multi-layer build-up layer 2, if the build-up layer 2 is in the form of a buried line, the preparation method of the build-up layer 2 in the form of a buried line is referred to as described above, and if the build-up layer 2 is in the form of an exposed line, a known PCB line processing technology can be used to complete the preparation of the packaging substrate 001.

[0115] As can be seen from the above, the preparation method of the packaging substrate 001 provided by the embodiments of the present disclosure can perform Any Layer Embedded Pattern (AEP) design in the PCB build-up layer, and can realize high-precision and high-density buried lines in any layer, so that the precision of the line width / line spacing is more excellent and easier to control. Moreover, the preparation method of the packaging substrate 001 uses a relatively simple ETS process to pre-process a high-density buried line layer, and realizes interlayer bonding through a prepreg under the assistance of high-precision alignment, and then performs interlayer interconnection on the newly added build-up layer 2, and the hole interconnection 23 is formed between any two adjacent build-up layers 2, which is relatively simple to operate, has low cost, and avoids mechanical drilling with a large hole diameter to drill multiple build-up layers at the same time, thereby ensuring the realization of high-density lines.

[0116] According to the specific structure of the build-up layer 2 in the packaging substrate 001, different interlayer interconnection operations can be implemented, and the preparation processes of different types of packaging substrates 001 are further exemplarily described below in combination with the above-described various types of packaging substrates 001.

[0117] In some examples, in combination with the packaging substrate 001 related to the above-mentioned embodiment (1), as shown in FIG. 7, the pad 222 of the buried build-up layer 201 is a hole pad, and the hole interconnection 23 of the buried build-up layer 201 includes a first type of hole interconnection 231; the preparation of the first type of hole interconnection 231 occurs after the pressing operation, and the preparation method of the first type of hole interconnection 231 includes punching at the interlayer interconnection position of the insulating medium 21 of the buried build-up layer 201, and forming the first type of hole interconnection 231 at the punching position by an electroplating process.

[0118] Accordingly, the preparation method of the packaging substrate 001 involved in the embodiment (1) is shown as follows:

[0119] Step S11, as shown in FIG. 3, a patterned metal layer 22 is prepared on the carrier board 4 by using a buried line preparation process, to obtain a buried line build-up intermediate.

[0120] Step S12, as shown in FIG. 4, under the guidance of the alignment device, the buried line build-up intermediate is aligned with the interlayer interconnection position of the prepared first line build-up layer 2 (BU01), and the buried line build-up intermediate is pressed to the first line build-up layer 2 (BU01) through a semi-cured sheet, and the semi-cured sheet forms an insulating medium 21 of the buried line build-up layer 201 (BU02).

[0121] Step S13, as shown in FIG. 5, the carrier board 4 is removed, and after the pressing operation, a hole is punched at the interlayer interconnection position of the insulating medium 21 of the buried line build-up layer 201 (that is, the position exposed by the via on the hole pad), and the formed hole penetrates the insulating medium 21 and exposes the pad 222 on the first line build-up layer 2 (BU01). The punching can be laser punching. Then, a first type of hole interconnection 231 is formed at the punching position through an electroplating process, to obtain a second line build-up layer 2 (BU02) in the form of a buried line.

[0122] As shown in FIG. 5, the via portion 2311 of the first type of hole interconnection 231 penetrates the insulating medium 21 and the pad 222 of the second line build-up layer 2 (BU02), and the two ends of the via portion 2311 of the first type of hole interconnection 231 are respectively connected to the pad 222 of the first line build-up layer 2 (BU01) and the current step pad 2312, and the step pad 2312 of the first type of hole interconnection 231 is lapped to the surface of the pad 222 of the second line build-up layer 2 (BU02).

[0123] The pad 222 is a hole pad, and a discontinuous pad can be formed on the pad 222 through an ETS process, so that the via is formed at the same time when the first pad 213 is prepared, and this method has the advantages of simple operation and high efficiency. Of course, it is also possible to form a pad 222 with a continuous structure through an ETS process, and it is also possible to form a via by etching a conformal mask (CFM) on the pad 222.

[0124] Step S14, in combination with FIG. 6, the third build-up layer 2 (BU03) is continued to be prepared on the second build-up layer 2 (BU02) according to the same preparation method as the second build-up layer 2 (BU02), in which the via portion 2311 of the first type of hole interconnection 231 penetrates the insulating medium 21 and the pad 222 of the third build-up layer 2 (BU03), and the two ends of the via portion 2311 of the first type of hole interconnection 231 are connected to the step pad 2312 of the second build-up layer 2 (BU02) and the current step pad 2312, respectively, and the step pad 2312 of the first type of hole interconnection 231 is overlapped to the surface of the pad 222 of the third build-up layer 2 (BU03).

[0125] Step S15, in combination with FIG. 7, the fourth build-up layer 2 (BU04) is prepared on the third build-up layer 2 (BU03) by using the conventional PCB line processing technology. According to the structural arrangement of the plurality of build-up layers 2, it is determined whether to continue to build up on the fourth build-up layer 2 (BU04), and FIG. 7 illustrates that the build-up is not continued, so that the solder resist layer 3 is prepared on the fourth build-up layer 2 (BU04) to obtain the package substrate 001 involved in the embodiment (1).

[0126] In addition, the preparation method of the package substrate 001 shown in the embodiment (4) can also use the preparation method of the package substrate 001 shown in the above-mentioned embodiment (1), and the difference is that the thickness of the step pad 2312 of the first type of hole interconnection 231 in the embodiment (4) is greater than the thickness of the pad 222 of the overlapped second build-up layer 2 (BU02), which can be formed by the MSAP process.

[0127] In some examples, in combination with the package substrate 001 involved in the above-mentioned embodiment (2), as shown in FIG. 8, the pad 222 of the buried build-up layer 201 is a non-hole pad, and the hole interconnection 23 of the buried build-up layer 201 includes a second type of hole interconnection 232; the preparation of the second type of hole interconnection 232 occurs before the pressing operation, and the preparation method of the second type of hole interconnection 232 includes: pressing the prepreg to the line base layer 1 or other build-up layers 2 that have been prepared, and the prepreg forms the insulating medium 21; under the guidance of the alignment device, punching is performed at the interlayer interconnection position of the insulating medium 21 of the buried build-up layer 201, and the punched position is filled with conductive paste, and then the pressing operation is performed, so that the second type of hole interconnection 232 is formed by the conductive paste.

[0128] Correspondingly, the preparation method of the package substrate 001 involved in the embodiment (2) is as follows:

[0129] Step S21, a patterned metal layer 22 is prepared on the carrier plate 4 by using a buried via process, to obtain a buried via build-up intermediate. The operation flow of step S21 can still refer to FIG. 3.

[0130] Step S22, a prepreg is pre-pressed to the prepared first build-up layer 2 (BU01), and the prepreg provides an insulating medium 21 of a second build-up layer 2 (BU02) in the form of a buried via. Under the guidance of an alignment device, a hole is punched at an interlayer connection position of the insulating medium 21 of the second build-up layer 2 (BU02) to expose the pad 222 of the first build-up layer 2 (BU01), and a conductive paste is filled into the punched position, and then a pressing operation is performed to form a second type of hole interconnection 232 from the conductive paste. The conductive paste mentioned above can be a copper paste, and after it is cured, a second type of hole interconnection 232 in the form of a solid cylinder is formed.

[0131] Step S23, the carrier plate 4 is removed, and thus the preparation of the second build-up layer 2 (BU02) is completed, as shown in FIG. 8, the second type of hole interconnection 232 penetrates the insulating medium 21 of the second build-up layer 2 (BU02), and the two ends of the second type of hole interconnection 232 are connected to the pad 222 of the second build-up layer 2 (BU02) and the pad 222 of the first build-up layer 2 (BU01), respectively.

[0132] Step S24, the third build-up layer 2 (BU03) is continuously prepared on the second build-up layer 2 (BU02) in the same preparation method as the second build-up layer 2 (BU02), and in the third build-up layer 2 (BU03), the second type of hole interconnection 232 penetrates the insulating medium 21 of the third build-up layer 2 (BU03), and the two ends of the second type of hole interconnection 232 are connected to the pad 222 of the third build-up layer 2 (BU03) and the pad 222 of the second build-up layer 2 (BU02), respectively.

[0133] Step S25, the fourth build-up layer 2 (BU04) is prepared on the third build-up layer 2 (BU03) by using a conventional PCB circuit processing technology. According to the structural arrangement of the plurality of build-up layers 2, it is determined whether to continue to build up on the fourth build-up layer 2 (BU04), and FIG. 8 illustrates that no further build-up is continued, so a solder mask layer 3 is prepared on the fourth build-up layer 2 (BU04) to obtain the package substrate 001 involved in the embodiment (2).

[0134] In addition, the preparation method of the package substrate 001 shown in the embodiment (5) can also use the preparation method of the package substrate 001 shown in the embodiment (2) involved above, which will not be described here.

[0135] In some examples, in combination with the package substrate 001 related to the above-mentioned embodiment (3), as shown in FIG. 9, in the direction away from the circuit base layer 1, the embedded circuit layer 201 is stacked with the exposed circuit layer 202, the hole interconnections 23 of the embedded circuit layer 201 and the hole interconnections 23 of the exposed circuit layer 202 cooperate to form the third type of hole interconnections 233, and the pads 222 of the embedded circuit layer 201 are hole pads, and the pads 222 of the exposed circuit layer 202 are non-hole pads.

[0136] The preparation of the third type of hole interconnections 233 occurs after the pressing operation, and the preparation method of the third type of hole interconnections 233 includes: after the insulating medium 21 and the patterned metal layer 22 of the embedded circuit layer 201 are formed by the pressing operation, pressing another prepreg to the insulating medium 21 of the embedded circuit layer 201, the prepreg forms the insulating medium 21 of the exposed circuit layer 202; simultaneously punching at the interlayer interconnection positions of both the insulating medium 21 of the exposed circuit layer 202 and the insulating medium 21 of the embedded circuit layer 201, and forming the third type of hole interconnections 233 at the punching positions by an electroplating process.

[0137] Correspondingly, the preparation method of the package substrate 001 related to the above-mentioned embodiment (3) is as follows:

[0138] Step S31, using the embedded circuit preparation process, preparing the patterned metal layer 22 on the carrier board 4 to obtain the embedded circuit layer intermediate.

[0139] Step S32, under the guidance of the alignment device, aligning the embedded circuit layer intermediate with the interlayer interconnection position of the prepared first circuit layer 2 (BU01), and pressing the embedded circuit layer intermediate to the first circuit layer 2 (BU01) by the prepreg, the prepreg forms the insulating medium 21 of the second circuit layer 2 (BU02) in the form of embedded circuit.

[0140] Step S33, removing the carrier board 4, and after the pressing operation, pressing another prepreg to the insulating medium 21 of the embedded circuit layer 201, the prepreg forms the insulating medium 21 of the third circuit layer 2 (BU03); simultaneously punching at the interlayer interconnection positions of both the insulating medium 21 of the second circuit layer 2 (BU02) and the third circuit layer 2 (BU03), and forming the third type of hole interconnections 233 at the punching positions by an electroplating process. Wherein, the above-mentioned punching can be performed by a laser punching process.

[0141] Step S34, forming the patterned metal layer 22 of the third build-up layer 2 (BU03) on the insulating medium 21 of the third build-up layer 2 (BU03) by a conventional PCB circuit processing technology, and completing the preparation of the third build-up layer 2 (BU03).

[0142] The third type of hole interconnect 233 penetrates the insulating medium 21 and the pad 222 of the second build-up layer 2 (BU02) and the insulating medium 21 of the third build-up layer 2 (BU03) in sequence, and the sidewall of the third type of hole interconnect 233 is connected to the pad 222 of the second build-up layer 2 (BU02), and the two ends of the third type of hole interconnect 233 are respectively connected to the pad 222 of the first build-up layer 2 (BU01) and the pad 222 of the third build-up layer 2 (BU03).

[0143] Step S35, preparing the fourth build-up layer 2 (BU04) from the third build-up layer 2 (BU03) by a conventional PCB circuit processing technology. According to the structural arrangement of the plurality of build-up layers 2, it is determined whether to continue to build up on the fourth build-up layer 2 (BU04). As shown in FIG. 9, the build-up is not continued, so a solder resist layer 3 is prepared on the fourth build-up layer 2 (BU04) to obtain the package substrate 001 involved in the embodiment (3).

[0144] In an aspect, the embodiments of the present disclosure also provide a semiconductor package. As shown in FIG. 12, a semiconductor package containing the package substrate 001 shown in FIG. 7 includes the package substrate 001 and an electronic component 002. The package substrate 001 is any of the package substrates 001 described above, or is prepared by any of the preparation methods of the package substrates 001 described above. The electronic component 002 is connected to the outermost one of the plurality of build-up layers 2 of the package substrate 001.

[0145] The semiconductor package provided by the embodiments of the present disclosure has all the advantages of the package substrate 001 and the preparation method thereof described above, which will not be repeated here.

[0146] In some examples, the electronic component 002 described above includes but is not limited to a die, a chip, a wafer, an integrated device, an integrated passive device, a die package, an integrated circuit device, a device package, an integrated circuit package, a semiconductor device, a laminate package device, an interposer, etc.

[0147] The semiconductor package provided by the embodiments of the present disclosure can be applied to various scenarios, for example, this includes but is not limited to the following: central processing unit (CPU), graphics processing unit (GPU), application specific integrated circuit (ASIC) device, system on chip (SOC), high performance computing (HPC) device, artificial intelligence (AI) device, data center switch, mobile phone device, computer device, wearable device, communication device, navigation device, set top box, music player, video player, Internet of Things device, indoor baseband processing unit, server, router, etc.

[0148] The above is only for the convenience of those skilled in the art to understand the technical solutions of the present disclosure, and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A package substrate, wherein, The packaging substrate (001) comprises: a circuit base layer (1), a plurality of circuit additional layers (2) and a solder resist layer (3) arranged in sequence, each circuit additional layer (2) comprises: an insulating medium (21), a patterned metal layer (22) arranged on the side of the insulating medium (21) away from the circuit base layer (100), and a hole interconnection (23) at least partially penetrating the insulating medium (21); The circuit base layer (1) and the patterned metal layer (22) of the circuit additional layer (2) adjacent thereto, and the patterned metal layers (22) of any two adjacent circuit additional layers (2), are electrically connected through the corresponding hole interconnections (23); At least part of the plurality of circuit additional layers (2) is a buried circuit additional layer (201), and the patterned metal layer (22) of the buried circuit additional layer (201) is embedded in one side surface of the corresponding insulating medium (21).

2. The package substrate of claim 1, wherein, Part of the plurality of circuit additional layers (2) is an exposed circuit additional layer (202), and the patterned metal layer (22) of the exposed circuit additional layer (202) is arranged protruding on one side surface of the corresponding insulating medium (21); The line width and line spacing of the patterned metal layer (22) of the exposed circuit additional layer (202) are greater than the line width and line spacing of the patterned metal layer (22) of the buried circuit additional layer (201), respectively.

3. The package substrate of any one of claims 1-2, wherein, The patterned metal layer (22) comprises a trace (221) and a pad (222) electrically connected to the trace (221), and the pad (222) is also electrically connected to the hole interconnection (23); The pad (222) of the buried circuit additional layer (201) comprises at least one of a hole-free pad and a hole pad.

4. The package substrate of claim 3, wherein, The pad (222) of the buried circuit additional layer (201) is a hole pad, and correspondingly, the hole interconnection (23) of the buried circuit additional layer (201) comprises a first type of hole interconnection (231), and the first type of hole interconnection (231) comprises a via portion (2311) and a stepped pad (2312) connected to the via portion (2311). The via portion (2311) penetrates the insulating medium (21) and the pad (222) of the current buried circuit additional layer (201), and the stepped pad (2312) is lapped to the surface of the pad (222) of the current buried circuit additional layer (201).

5. The package substrate of claim 4, wherein, The thickness of the stepped pad (2312) is greater than the thickness of the lapped pad (222). The pad thickness is the dimension of the pad (222) in the direction perpendicular to the insulating medium (21).

6. The package substrate of claim 3, wherein, The pad (222) of the buried circuit additional layer (201) is a hole-free pad, and correspondingly, the hole interconnection (23) of the buried circuit additional layer (201) comprises a second type of hole interconnection (232). The second type of hole interconnect (232) penetrates the insulating medium (21) of the current embedded line layer (201), and two ends of the second type of hole interconnect (232) are connected to the pad (222) of the current embedded line layer (201) and the pad (222) of another line layer (2) adjacent to the current embedded line layer (201) respectively; The second type of hole interconnect (232) is formed by conductive paste curing.

7. The package substrate of claim 3, wherein, In the direction away from the line base layer (1), the embedded line layer (201) is arranged in a stack with an exposed line layer (202), the hole interconnect (23) of the embedded line layer (201) and the hole interconnect (23) of the exposed line layer (202) are integrally connected and form a third type of hole interconnect (233); The pad (222) of the embedded line layer (201) is a hole pad, the pad (222) of the exposed line layer (202) is a non-hole pad, the third type of hole interconnect (233) penetrates the insulating medium (21) and the pad (222) of the embedded line layer (201) and the insulating medium (21) of the exposed line layer (202) in sequence, and the sidewall of the third type of hole interconnect (233) is connected to the pad (222) of the embedded line layer (201), one end of the third type of hole interconnect (233) is connected to the pad (222) of the exposed line layer (202).

8. A method of manufacturing a package substrate, wherein, The package substrate (001) is as claimed in any one of claims 1-7, and a preparation method of the package substrate (001) comprises: providing a line base layer (1), and sequentially preparing a plurality of line layers (2) and solder masks (3) on the line base layer (1) to obtain the package substrate (001); At least part of the plurality of line layers (2) is an embedded line layer (201), and a preparation method of the embedded line layer (201) comprises: using an embedded line preparation process to prepare a patterned metal layer (22) on a carrier plate (4) to obtain an embedded line layer intermediate body; under the guidance of an alignment device, the embedded line layer intermediate body is aligned with the interlayer interconnect position of the line base layer (1) or other prepared line layers (2), the embedded line layer intermediate body is pressed to the line base layer (1) or other prepared line layers (2) through a prepreg, and the prepreg forms an insulating medium (21); the carrier plate (4) is removed, and the hole interconnect (23) of the embedded line layer (201) is prepared at the interlayer interconnect position of the embedded line layer intermediate body before or after the pressing operation to obtain the embedded line layer (201).

9. The method of producing a package substrate according to claim 8, wherein The pad (222) of the embedded line layer (201) is a hole pad, and the hole interconnect (23) of the embedded line layer (201) comprises a first type of hole interconnect (231). The first type of via interconnect (231) is prepared after the lamination operation, and the preparation method of the first type of via interconnect (231) comprises: Punching is performed at the interlayer interconnect position of the insulating medium (21) of the buried wiring layer (201), and the first type of via interconnect (231) is formed at the punched position by an electroplating process.

10. The method of producing a package substrate according to claim 8, wherein The pad (222) of the buried wiring layer (201) is a non-via pad, and the via interconnect (23) of the buried wiring layer (201) comprises a second type of via interconnect (232); The second type of via interconnect (232) is prepared before the lamination operation, and the preparation method of the second type of via interconnect (232) comprises: The prepreg is pre-pressed to the wiring base layer (1) or other prepared wiring layer (2), and the prepreg forms the insulating medium (21); Under the guidance of an alignment device, punching is performed at the interlayer interconnect position of the insulating medium (21) of the buried wiring layer (201), and the punched position is filled with conductive paste, and then the lamination operation is performed, so that the second type of via interconnect (232) is formed from the conductive paste.

11. The method of producing a package substrate according to claim 8, wherein In a direction away from the wiring base layer (1), an exposed wiring layer (202) is arranged on the buried wiring layer (201) in a stacked manner, the via interconnect (23) of the buried wiring layer (201) and the via interconnect (23) of the exposed wiring layer (202) cooperate to form a third type of via interconnect (233), and the pad (222) of the buried wiring layer (201) is a via pad, and the pad (222) of the exposed wiring layer (202) is a non-via pad; The third type of via interconnect (233) is prepared after the lamination operation, and the preparation method of the third type of via interconnect (233) comprises: After the insulating medium (21) and the patterned metal layer (22) of the buried wiring layer (201) are formed by the lamination operation, another prepreg is pre-pressed to the insulating medium (21) of the buried wiring layer (201), and the other prepreg forms the insulating medium (21) of the exposed wiring layer (202); Punching is performed at the interlayer interconnect position of both the insulating medium (21) of the exposed wiring layer (202) and the insulating medium (21) of the buried wiring layer (201), and the third type of via interconnect (233) is formed at the punched position by an electroplating process.

12. A semiconductor package, wherein, The semiconductor package comprises a package substrate (001) and an electronic component (002), the package substrate (001) is as claimed in any one of claims 1-7 or is prepared by the preparation method as claimed in any one of claims 8-11; The electronic component (002) is connected to the outermost wiring layer (2) of the plurality of wiring layers (2) of the package substrate (001).

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