Oscillatory vector matrix multiplication for analog in-memory compute (AIMC)

WO2026069027A1PCT designated stage Publication Date: 2026-04-02INTERNATIONAL BUSINESS MACHINE CORPORATION +2
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-08-15
Publication Date
2026-04-02

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Abstract

An oscillatory matrix-vector multiplication device includes one or more oscillatory matrix-vector multiplication circuits. Each oscillatory matrix-vector multiplication circuit includes a first tunable resistive circuit that comprises a first complementary metal-oxide semiconductor (CMOS) transistor, a first activation input, and a first tunable resistive circuit output, wherein the first complementary metal-oxide semiconductor (CMOS) transistor includes a first gate input, a first input coupled to the first activation input and a first output coupled to the first tunable resistive circuit output, and wherein the first activation input is configured to receive an activation signal; and a programmable oscillator circuit coupled to the first gate input of the first tunable resistive circuit and configured to produce a control signal based on a given conductance.
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Description

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Claims

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Citation Information

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