Multilayer ceramic electronic component

Abstract

In this multilayer ceramic capacitor (1), a first external electrode (40A) is disposed on a first end surface (LS1). A second external electrode (40B) is disposed on a second end surface (LS2). Each of the first external electrode (40A) and the second external electrode (40B) has a Ni-plated layer (61A, 61B) and a Sn-plated layer (62A, 62B) positioned on the Ni-plated layer (61A, 61B). Each of the first external electrode (40A) and the second external electrode (40B) has a groove (63) extending in the lamination direction (T). A metal containing Ni is exposed on the bottom surface of the groove (63).

Description

Multilayer ceramic electronic components

[0001] This invention relates to multilayer ceramic electronic components.

[0002] Multilayer ceramic capacitors have been known for some time. Generally, multilayer ceramic capacitors comprise a ceramic sintered body made of a dielectric ceramic such as barium titanate. Inside this ceramic sintered body, multiple internal electrodes are arranged so as to overlap via ceramic layers. External electrodes are formed on one end face and the other end face of this ceramic sintered body so as to be electrically connected to the internal electrodes. For example, Patent Document 1 discloses a multilayer ceramic capacitor having a plating layer as an external electrode. The plating layer in Patent Document 1 comprises a Ni plating layer for suppressing solder corrosion and a Sn plating layer formed on the Ni plating layer to improve solderability.

[0003] Japanese Patent Publication No. Hei 8-306580 Japanese Patent Publication No. 2013-110239

[0004] In recent years, dense Sn plating layers with excellent solderability have been sought as plating layers for external electrodes. However, dense Sn plating layers are impermeable to hydrogen, so hydrogen generated during plating remains absorbed in the Ni plating layer, the base electrode layer, and the internal electrode layer. This residual hydrogen can degrade the electrical characteristics of multilayer ceramic capacitors, particularly the insulation resistance characteristics (IR characteristics). Patent document 2 discloses a configuration that reduces the amount of hydrogen absorbed in the Ni plating layer by providing openings in the Sn layer provided on the Ni plating layer.

[0005] However, in the configuration of Patent Document 2, since openings are scattered in the Ni plating layer, when the number of openings was increased in order to sufficiently reduce the amount of hydrogen absorbed in the Ni plating layer, solder wetting during mounting was sometimes hindered. In other words, in the configuration of Patent Document 2, it was difficult to sufficiently reduce the amount of hydrogen absorbed in the Ni plating layer while ensuring solder wetting during mounting.

[0006] The objective of the present invention is to provide a multilayer ceramic electronic component that can ensure solder wetting and thus secure bonding during mounting, while suppressing a decrease in insulation resistance characteristics.

[0007] The multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, wherein the first external electrode comprises a first end surface-side external electrode disposed on the first end surface, and the second external electrode comprises a second end surface-side external electrode disposed on the second end surface, each of the first end surface-side external electrode and the second end surface-side external electrode has a Ni plating layer and a Sn plating layer located on the Ni plating layer, each of the first end surface-side external electrode and the second end surface-side external electrode has a groove extending in the stacking direction, and a metal containing Ni is exposed at the bottom of the groove.

[0008] According to the present invention, it is possible to provide a multilayer ceramic electronic component that ensures solder wetting and thus secures bonding during mounting, while suppressing a decrease in insulation resistance characteristics.

[0009] This is an external perspective view of a multilayer ceramic capacitor of the first embodiment. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line II-II. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line III-III. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IV-IV. This is a view of the multilayer ceramic capacitor shown in Figure 2 from the direction of arrow V, and is a side view showing the end face of the ceramic capacitor. This is a side view showing the end face of a multilayer ceramic capacitor of the second embodiment. This is a side view showing the end face of a multilayer ceramic capacitor of the third embodiment. This is a diagram showing a double-gang multilayer ceramic capacitor. This is a diagram showing a triple-gang multilayer ceramic capacitor. This is a diagram showing a quadruple-gang multilayer ceramic capacitor.

[0010] (First Embodiment) A multilayer ceramic capacitor 1 according to the first embodiment of the present disclosure will be described with reference to Figures 1 to 4. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line III-III. Figure 4 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line IV-IV.

[0011] The multilayer ceramic capacitor 1 comprises a laminate 10 and an external electrode 40.

[0012] Figures 1 to 4 show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T, which is the height direction of the multilayer ceramic capacitor 1 and the laminate 10, corresponds to the Z direction. Here, the cross section shown in Figure 2 is also called the LT cross section. The cross section shown in Figure 3 is also called the WT cross section. The cross section shown in Figure 4 is also called the LW cross section.

[0013] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W. The mounting surface of the multilayer ceramic capacitor 1 is the first main surface TS1. The mounting surface is the surface that faces the wiring board when the multilayer ceramic capacitor 1 is mounted on a wiring board or the like.

[0014] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension in the length direction L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension in the stacking direction T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.05 mm or more and 10 mm or less. If the dimension in the width direction W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 5 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12 and a second main surface-side outer layer 13 arranged to sandwich the inner layer 11 in the lamination direction T.

[0017] The inner layer 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0018] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as those mentioned above. Furthermore, the dielectric material may be obtained by adding minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components.

[0019] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 15 or more and 1200 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 are arranged on a plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on a plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10 via the dielectric layers 20. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0021] The first internal electrode layer 31 has a first opposing portion 31A that faces the second internal electrode layer 32, and a first leading portion 31B that is drawn out from the first opposing portion 31A to the first end face LS1. The first leading portion 31B is exposed to the first end face LS1.

[0022] The second internal electrode layer 32 has a second opposing portion 32A that faces the first internal electrode layer 31, and a second leading portion 32B that is drawn out from the second opposing portion 32A to the second end face LS2. The second leading portion 32B is exposed to the second end face LS2.

[0023] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first drawer portion 31B and the second drawer portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0025] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 1000 or less.

[0028] The first main surface-side outer layer 12 is located on the second main surface TS2 side of the laminate 10. The first main surface-side outer layer 12 is an aggregate of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface-side outer layer 12 may be the same as the dielectric layers 20 used in the inner layer 11.

[0029] The second main surface-side outer layer 13 is located on the first main surface TS1 side of the laminate 10. The second main surface-side outer layer 13 is an aggregate of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0030] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figure 4 shows the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0031] The laminate 10 has a side outer layer WG. The side outer layer WG has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3 and 4 show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer WG is also called a W gap or side gap.

[0032] The laminate 10 has an end-face outer layer LG. The end-face outer layer LG has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end-face outer layer LG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figures 2 and 4 show the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer LG is also called an L gap or end gap.

[0033] The external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side.

[0034] The first external electrode 40A mainly has a first end-face side external electrode positioned on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B mainly has a second end-face side external electrode located on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be located on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, within the laminate 10, capacitance is formed by the opposition of the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0037] The first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A.

[0038] The second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0039] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. In the present embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a part of the first main face TS1, a part of the second main face TS2, a part of the first side face WS1, and a part of the second side face WS2.

[0040] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a part of the first main face TS1, a part of the second main face TS2, a part of the first side face WS1, and a part of the second side face WS2.

[0041] The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a baking layer, a conductive resin layer, a thin film layer, and the like.

[0042] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are baking layers. The baking layer preferably contains either a metal component and a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag - Pd alloy, Au, and the like. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, and the like. The ceramic component may use the same type of ceramic material as the dielectric layer 20 or a different type of ceramic material. The ceramic component includes at least one selected from, for example, BaTiO ３ , CaTiO ３ , (Ba, Ca)TiO ３ , SrTiO ３ , CaZrO ３ and the like.

[0043] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, or by firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate, and then applying the conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a material with a ceramic component added instead of glass. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0044] The thickness of the first base electrode layer 50A located at the first end face LS1 in the longitudinal direction L is preferably, for example, 2 μm to 220 μm at the center of the first base electrode layer 50A in the lamination direction T and width direction W. As shown in Figure 2, the thickness of the first base electrode layer 50A in the longitudinal direction L gradually decreases from the center of the lamination direction T to both sides of the lamination direction T.

[0045] The thickness of the second base electrode layer 50B located at the second end face LS2 in the longitudinal direction L is preferably, for example, 2 μm to 2200 μm at the center of the second base electrode layer 50B in the lamination direction T and width direction W. As shown in Figure 2, the thickness of the second base electrode layer 50B in the longitudinal direction L gradually decreases from the center of the lamination direction T to both sides of the lamination direction T.

[0046] When the first base electrode layer 50A is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A provided in this part in the lamination direction T is, for example, 3 μm or more and 40 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this part.

[0047] When the first base electrode layer 50A is provided on a part of at least one of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the first base electrode layer 50A provided in this portion is preferably, for example, 3 μm or more and 40 μm or less at the center of the first base electrode layer 50A provided in the length direction L and the lamination direction T.

[0048] When a second base electrode layer 50B is provided on at least one of the surfaces of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B provided in this portion in the lamination direction is, for example, 3 μm to 40 μm at the center of the length L and width W of the second base electrode layer 50B provided in this portion.

[0049] When a second base electrode layer 50B is provided on at least one of the surfaces of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B in the width direction provided in this portion is preferably, for example, 3 μm to 40 μm at the center of the second base electrode layer 50B in the length direction L and the lamination direction T.

[0050] The first base electrode layer 50A and the second base electrode layer 50B are not limited to baked layers, but may also be thin film layers. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0051] The first plating layer 60A is arranged to cover the first underlay electrode layer 50A. The first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0052] The second plating layer 60B is arranged to cover the second under electrode layer 50B. The second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0053] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by the solder used when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder used when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of the Ni plating layer and the Sn plating layer are preferably 2 μm to 15 μm.

[0054] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Also, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.05 mm and 10 mm. Furthermore, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0055] Here, the basic structure of each layer constituting the first external electrode 40A and the second external electrode 40B is the same. Also, the first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the WT cross section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, when there is no need to explain the first external electrode 40A and the second external electrode 40B separately, they may be collectively referred to as the external electrode 40. The same applies to each layer constituting the first external electrode 40A and the second external electrode 40B. For example, when there is no need to explain the first base electrode layer 50A and the second base electrode layer 50B separately, they may be collectively referred to as the base electrode layer 50. Furthermore, if there is no need to specifically distinguish between the first plating layer 60A and the second plating layer 60B, the first plating layer 60A and the second plating layer 60B may be collectively referred to as the plating layer 60. Similarly, if there is no need to specifically distinguish between the first Ni plating layer 61A and the second Ni plating layer 61B, the first Ni plating layer 61A and the second Ni plating layer 61B may be collectively referred to as the Ni plating layer 61. Furthermore, if there is no need to specifically distinguish between the first Sn plating layer 62A and the second Sn plating layer 62B, the first Sn plating layer 62A and the second Sn plating layer 62B may be collectively referred to as the Sn plating layer 62.

[0056] As shown in Figures 1, 2, 4, and 5, the first external electrode 40A (first end-face side external electrode) and the second external electrode 40B (second end-face side external electrode) each have grooves 63A and 63B extending in the stacking direction T. Specifically, the grooves 63A and 63B are recesses formed by removing the first Sn plating layer 62A and the second Sn plating layer 62B, respectively, and recessing them in the longitudinal direction L. Figure 5 is a view of the multilayer ceramic capacitor shown in Figure 2 from the direction of arrow V, and is a side view showing the end face of the ceramic capacitor. In Figure 2, the edge 62A1 of the first Sn plating layer 62A that defines the groove 63A and the edge 62B1 of the second Sn plating layer 62B that defines the groove 63B are shown.

[0057] A metal containing Ni is exposed at the bottom of grooves 63A and 63B. Specifically, the metal exposed at the bottom of 63A and 63B includes the metal that constitutes the Ni plating.

[0058] The structure and composition of the grooves 63A and 63B described above make it difficult for solder wetting in the stacking direction T to be inhibited. Therefore, proper solder wetting ensures mechanical and electrical bonding during mounting of the multilayer ceramic capacitor 1, while suppressing a decrease in insulation resistance characteristics.

[0059] As shown in Figures 1 and 2, multiple grooves 63A and 63B are arranged in the width direction W. Furthermore, as shown in Figures 1 and 2, multiple grooves 63A and 63B are arranged in the stacking direction T. In this embodiment, a total of 10 grooves 63A and 63B are arranged in a configuration of 5 in the width direction and 2 in the stacking direction.

[0060] The grooves 63A and 63B terminate at both ends in the stacking direction T within the first end face LS1 and the second end face LS2. In other words, the grooves 63A and 63B do not open to the first main surface TS1 and the second main surface TS2.

[0061] Due to the formation positions of the grooves 63A and 63B described above, solder wetting is less likely to be hindered at the point where solder wetting begins during mounting of the multilayer ceramic capacitor 1. Therefore, proper solder wetting ensures mechanical and electrical bonding during mounting of the multilayer ceramic capacitor 1, while suppressing a decrease in insulation resistance characteristics.

[0062] As shown in Figure 5, when viewed in the longitudinal direction L, the grooves 63A and 63B are arranged to straddle the boundary between the first main surface-side outer layer 12 and the second main surface-side outer layer 13 of the laminate 10 and the inner layer 11.

[0063] As shown in Figure 2, the thickness of the first base electrode layer 50A in the longitudinal direction L is thinnest on both sides in the lamination direction T. Therefore, the internal electrode layer 30 near the boundary with the first main surface side outer layer 12 or the second main surface side outer layer 13 tends to be close to the surface of the external electrode 40. However, the shape of the first groove 63A and the second groove 65A extending in the lamination direction T makes it easier for hydrogen absorbed in the internal electrode layer 30 to be discharged, thereby suppressing a decrease in insulation resistance characteristics.

[0064] As shown in Figure 5, when viewed in the longitudinal direction L, the grooves 63A and 63B are arranged to span one or more internal electrode layers 30. In this embodiment, the grooves 63A and 63B are arranged to span multiple (three in this embodiment) internal electrode layers 30. Preferably, the grooves 63A and 63B are arranged to span five or more internal electrode layers 30.

[0065] The arrangement of the grooves 63A and 63B in the stacking direction T allows for easier discharge of absorbed hydrogen, thereby suppressing a decrease in insulation resistance characteristics.

[0066] When the end face is viewed along the length L, the total area of ​​the grooves 63A and 63B is between 5% and 40% of the area of ​​the external electrode 40 when viewed along the length L.

[0067] If the total area of ​​grooves 63A and 63B is too large, solder wetting may be hindered, so it is preferable that the total area of ​​each groove 63A and 63B be 40% or less. If the total area of ​​grooves 63A and 63B is too small, hydrogen will not be easily discharged, so it is preferable that the total area of ​​each groove 63A and 63B be 5% or more. By setting the area to 5% or more and 40% or less, proper solder wetting can be ensured, thereby securing the mechanical and electrical bonding performance when mounting the multilayer ceramic capacitor 1, and suppressing a decrease in insulation resistance characteristics.

[0068] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0069] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known substances.

[0070] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0071] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer portion 12 on the first main surface TS1 side. On top of this, dielectric sheets with printed patterns for the first internal electrode layer 31 and dielectric sheets with printed patterns for the second internal electrode layer 32 are sequentially stacked to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer portion 13 on the second main surface TS2 side. This completes the production of the laminated sheet.

[0072] Laminated sheets are pressed in the lamination direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0073] The laminated block is cut to a predetermined size, thereby producing laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0074] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0075] A conductive paste, which will serve as the base electrode layer, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer is a baked layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer. The temperature of this baking process is preferably 700°C to 900°C.

[0076] Furthermore, when firing the laminated chip before firing and the conductive paste applied to the laminated chip simultaneously, it is preferable to form the baked layer by baking a ceramic material added instead of the glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminate 10 with a baked layer.

[0077] Subsequently, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Also, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0078] Grooves 63A and 63B extending in the stacking direction T are formed in the first Sn plating layer 62A and the second Sn plating layer 62B, respectively. Specifically, a portion of the first Sn plating layer 62A and the second Sn plating layer 62B are removed by laser processing to form grooves 63A and 63B extending in the stacking direction T.

[0079] It is preferable to use a pulsed laser as the laser. By adjusting the laser conditions, only the first Sn plating layer 62A and the second Sn plating layer 62B are removed while the first Ni plating layer 61A and the second Ni plating layer 61B remain. As a result, grooves 63A and 63B are formed on the bottom surface in which the Ni-containing metal is exposed. Specifically, grooves 63A and 63B are formed on the bottom surface in which the metal constituting the Ni plating is exposed.

[0080] Through this manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0081] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0082] (1) The multilayer ceramic capacitor 1 includes a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 30, and has a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W, and a first external electrode 40A disposed on the first end surface LS1 and a second external electrode 40B disposed on the second end surface LS2. The first external electrode 40A includes a first end surface side external electrode disposed on the first end surface LS1. The second external electrode 40B includes a second end surface side external electrode disposed on the second end surface LS2. Each of the first end-face external electrode and the second end-face external electrode has a Ni plating layer 61 and a Sn plating layer 62 located on the Ni plating layer 61. Each of the first end-face external electrode and the second end-face external electrode has grooves 63A and 63B extending in the stacking direction T. A metal containing Ni is exposed at the bottom of the grooves 63A and 63B.

[0083] This results in a multilayer ceramic capacitor 1 that ensures solder wetting and thus secures bonding during mounting, while suppressing a decrease in insulation resistance characteristics.

[0084] (2) The metal exposed on the bottom surface of grooves 63A and 63B includes the metal that constitutes the Ni plating.

[0085] This results in a multilayer ceramic capacitor 1 that ensures solder wetting and thus secures bonding during mounting, while suppressing a decrease in insulation resistance characteristics.

[0086] (3) Each of the first end face side external electrode and the second end face side external electrode has an under electrode layer 50 between the laminate 10 and the plating layer 60.

[0087] This results in a multilayer ceramic capacitor 1 that ensures solder wetting and thus secures bonding during mounting, while suppressing a decrease in insulation resistance characteristics.

[0088] (4) Multiple grooves 63A and 63B are arranged in the width direction W.

[0089] This makes it easier for hydrogen absorbed into the Ni plating layer 61 to be released, thereby suppressing the decrease in insulation resistance characteristics.

[0090] (5) The grooves 63A and 63B are terminated at both ends in the stacking direction T within the first end face LS1 and the second end face LS2.

[0091] As a result, solder wetting is less likely to be inhibited at the point where solder wetting begins during mounting of the multilayer ceramic capacitor 1. Therefore, proper solder wetting ensures mechanical and electrical bonding during mounting of the multilayer ceramic capacitor 1, while suppressing a decrease in insulation resistance characteristics.

[0092] (6) When viewed in the longitudinal direction L, the grooves 63A and 63B are arranged to straddle the boundary between the first main surface side outer layer 12 or the second main surface side outer layer 13 of the laminate 10 and the inner layer 11.

[0093] This makes it easier for hydrogen absorbed into the Ni plating layer 61 to be released, thereby suppressing the decrease in insulation resistance characteristics.

[0094] (7) When viewed in the longitudinal direction, the grooves 63A and 63B are arranged to span one or more of the multiple internal electrode layers 30.

[0095] This makes it easier for hydrogen absorbed into the Ni plating layer 61 to be released, thereby suppressing the decrease in insulation resistance characteristics.

[0096] (Second Embodiment) The shape, number, and position of the grooves are not limited to the first embodiment.

[0097] The second embodiment will be described using Figure 6. Figure 6 is a side view showing the end face of the multilayer ceramic capacitor of the second embodiment. Note that the basic structure of the second embodiment is the same as the basic structure of the first embodiment, so only the differences will be described below. In addition, only the first external electrode 40A will be described, but since the structure of the second external electrode 40B is the same as the structure of the first external electrode 40A, the description of the second external electrode 40B will be omitted.

[0098] As shown in Figure 6, in the multilayer ceramic capacitor 1A, the first external electrode 40A (first end-face side external electrode) has a first groove 63A and a second groove 64A extending in the stacking direction T. Specifically, the first groove 63A and the second groove 64A are recesses formed by removing the first Sn plating layer 62A, respectively, and recessing them in the longitudinal direction L.

[0099] A metal containing Ni is exposed at the bottom surfaces of the first groove 63A and the second groove 64A. Specifically, the metal exposed at the bottom surface of the groove 100 includes the metal that constitutes the Ni plating.

[0100] The structure and composition of the first groove 63A and the second groove 64A described above make it difficult for solder wetting in the stacking direction T to be inhibited. Therefore, proper solder wetting ensures mechanical and electrical bonding during mounting of the multilayer ceramic capacitor 1, while suppressing a decrease in insulation resistance characteristics.

[0101] Multiple (three in this embodiment) first grooves 63A are arranged in the width direction W. Specifically, the first grooves 63A are short grooves in the stacking direction T and are located on the first main surface TS1 side. The first grooves 63A are located in the middle of the width direction W.

[0102] Multiple (two in this embodiment) second grooves 64A are arranged side by side in the width direction W. Specifically, the second grooves 64A are long in the stacking direction T, and both ends in the stacking direction T are close to the first main surface TS1 and the second main surface TS2. The second grooves 64A are located on both sides of the first groove 63A in the width direction W.

[0103] The first groove 63A and the second groove 64A terminate at both ends in the stacking direction T within the first end face LS1 and the second end face LS2. In other words, the first groove 63A and the second groove 64A do not open to the first main surface TS1 and the second main surface TS2.

[0104] Due to the formation positions of the first groove 63A and the second groove 64A described above, solder wetting is less likely to be hindered at the point where solder wetting begins during mounting of the multilayer ceramic capacitor 1. Therefore, proper solder wetting ensures mechanical and electrical bonding during mounting of the multilayer ceramic capacitor 1, while suppressing a decrease in insulation resistance characteristics.

[0105] When viewed in the longitudinal direction L, the first groove 63A is positioned to straddle the boundary between the second main surface-side outer layer 13 and the inner layer 11 of the laminate 10. The second groove 64A is positioned to straddle the boundary between the first main surface-side outer layer 12 and the second main surface-side outer layer 13 and the inner layer 11 of the laminate 10.

[0106] The arrangement of the first groove 63A and the second groove 64A in the stacking direction T makes it easier for hydrogen absorbed in the Ni plating layer 61 to be released, thereby suppressing a decrease in insulation resistance characteristics.

[0107] In this embodiment, by providing a second groove 64A that is longer in the stacking direction T, in addition to the first groove 63A, the region from which hydrogen can be desorbed is increased. Furthermore, the wetting shape of the solder can be controlled.

[0108] (Third Embodiment) The third embodiment will be described using Figure 7. Figure 7 is a side view showing the end face of the multilayer ceramic capacitor of the third embodiment. The basic structure of the third embodiment is the same as that of the first embodiment, so only the differences will be described below. In addition, only the first external electrode 40A will be described, but the structure of the second external electrode 40B is the same as that of the first external electrode 40A, so the description of the second external electrode 40B will be omitted.

[0109] As shown in Figure 7, in the multilayer ceramic capacitor 1B, the first external electrode 40A (first end-face side external electrode) has a first groove 63A and a second groove 65A extending in the stacking direction T. Specifically, the first groove 63A and the second groove 65A are recesses formed by removing the first Sn plating layer 62A, respectively, and recessing them in the longitudinal direction L.

[0110] A metal containing Ni is exposed at the bottom surfaces of the first groove 63A and the second groove 65A. Specifically, the metal exposed at the bottom surface of the groove 100 includes the metal that constitutes the Ni plating.

[0111] The structure and composition of the first groove 63A and the second groove 65A described above make it difficult for solder wetting in the stacking direction T to be inhibited. Therefore, proper solder wetting ensures mechanical and electrical bonding when mounting the multilayer ceramic capacitor 1, and suppresses a decrease in insulation resistance characteristics.

[0112] Multiple (three in this embodiment) first grooves 63A are arranged in the width direction W. Specifically, the first grooves 63A are short grooves in the stacking direction T and are located on the first main surface TS1 side. The first grooves 63A are located in the middle of the width direction W.

[0113] The second groove 65A has a first region 66A and a second region 67A. The first region 66A is a rectangular recess located on the side of the second main surface TS2. The first region 66A extends in the width direction W. The second region 67A is a recess extending from both ends of the first region 66A in the width direction W towards the first main surface TS1. Specifically, the second groove 65A is a groove that is long in the stacking direction T, and both ends in the stacking direction T are close to the first main surface TS1 and the second main surface TS2. The second region 67A is provided on both sides of the first groove 63A in the width direction W.

[0114] The first groove 63A and the second groove 65A terminate at both ends in the stacking direction T within the first end face LS1 and the second end face LS2. In other words, the first groove 63A and the second groove 65A do not open to the first main surface TS1 and the second main surface TS2.

[0115] Due to the formation positions of the first groove 63A and the second groove 65A described above, solder wetting is less likely to be hindered at the point where solder wetting begins during mounting of the multilayer ceramic capacitor 1. Therefore, proper solder wetting ensures mechanical and electrical bonding during mounting of the multilayer ceramic capacitor 1, while suppressing a decrease in insulation resistance characteristics.

[0116] When viewed in the longitudinal direction L, the first groove 63A is positioned to straddle the boundary between the second main surface-side outer layer 13 and the inner layer 11 of the laminate 10. The second groove 65A is positioned to straddle the boundary between the first main surface-side outer layer 12 and the second main surface-side outer layer 13 and the inner layer 11 of the laminate 10.

[0117] The arrangement of the first groove 63A and the second groove 65A in the stacking direction T makes it easier for hydrogen absorbed in the Ni plating layer 61 to be released, thereby suppressing a decrease in insulation resistance characteristics.

[0118] In this embodiment, by providing a first region 66A of the second groove 65A extending in the width direction W, the region from which hydrogen escapes is increased.

[0119] In this embodiment, by positioning the first region 66A of the second groove 65A on the second main surface TS2 side (opposite side of mounting), it becomes possible to allow solder wetting on the first main surface TS1 side (mounting side) while preventing excessive solder wetting by the groove extending in the width direction, thereby appropriately adjusting the amount of solder wetting. If the solder wetting is excessive, stress load will be placed on the laminate 10, which may cause cracks. On the other hand, with the configuration of this embodiment, the amount of solder wetting can be appropriately adjusted. Therefore, it is possible to ensure highly reliable electrical and mechanical bonding while suppressing the occurrence of cracks in the laminate 10.

[0120] (Fourth Embodiment) The metal exposed at the bottom of the groove formed in the external electrode may contain an intermetallic compound mainly composed of Ni and Sn.

[0121] The fourth embodiment will be described below. The basic structure of the multilayer ceramic capacitor 1 is the same as that of the first to third embodiments. The fourth embodiment will be described below using the drawings of the first embodiment.

[0122] As shown in Figures 1, 2, 4, and 5, the first external electrode 40A (first end-face side external electrode) and the second external electrode 40B (second end-face side external electrode) each have grooves 63A and 63B extending in the stacking direction T. Specifically, the grooves 63A and 63B are recesses formed by the removal of the first Sn plating layer 62A and the second Sn plating layer 62B, respectively, in the longitudinal direction L.

[0123] Intermetallic compounds mainly composed of Ni and Sn are exposed at the bottom surfaces of grooves 63A and 63B. Specifically, the metal exposed at the bottom surfaces of grooves 63A and 63B contains intermetallic compounds mainly composed of Ni and Sn.

[0124] The structure and composition of the grooves 63A and 63B described above make it difficult for solder wetting in the stacking direction T to be inhibited. Therefore, proper solder wetting ensures mechanical and electrical bonding during mounting of the multilayer ceramic capacitor 1, while suppressing a decrease in insulation resistance characteristics.

[0125] Intermetallic compounds allow hydrogen to pass through more easily than Sn. Therefore, the intermetallic compounds function as hydrogen permeable zones that allow hydrogen to pass from the surface of the Ni plating layer 61 to the outer surface of the Sn plating layer 62. Thus, hydrogen generated during plating and absorbed into the Ni plating layer 61 is released to the outer surface of the multilayer ceramic capacitor 1 through the hydrogen permeable zones formed by the intermetallic compounds. This suppresses the deterioration of the insulation resistance characteristics of the multilayer ceramic capacitor 1.

[0126] The intermetallic compound may be formed in layers at least on the bottom surfaces of the grooves 63A and 63B. The thickness of the layered intermetallic compound is thinner than the thickness of the Sn plating layer 62.

[0127] By allowing the exposed metal at the bottom of grooves 63A and 63B to include intermetallic compounds, the degree of freedom in the amount of machining performed on grooves 63A and 63B is increased, and the cost of machining can be reduced.

[0128] In order to make the bottom surfaces of grooves 63A and 63B surfaces containing an intermetallic compound mainly composed of Ni and Sn, for example, the laser processing is completed while a small amount of Sn plating layer remains during groove machining.

[0129] The metal compound is composed of crystals formed by the rearrangement of Sn in the Sn plating layer 62 and Ni diffused into the Sn plating layer 62 in a specific composition. As a result, the Sn plating layer 62 having the intermetallic compound is formed as a film structure of approximately constant thickness without having through holes penetrating in the thickness direction. The intermetallic compound has the function of releasing hydrogen absorbed in the Ni plating layer 61 to the outside of the Sn plating layer 62 while suppressing the intrusion of moisture into the interior of the multilayer ceramic capacitor 1. Furthermore, since the Sn plating layer 62 with the intermetallic compound is formed as a film structure of approximately constant thickness, the substrate mountability of the multilayer ceramic capacitor 1 is good.

[0130] The intermetallic compound is preferably a compound mainly composed of Ni and Sn. This makes it easier for hydrogen to pass through. The intermetallic compound is NiSn ４ It is preferable that NiSn ４Because it has a flattened (plate-like) shape, it easily grows into a shape that penetrates the Sn plating layer 62 in the thickness direction. Therefore, the effects of this embodiment can be made more pronounced.

[0131] Intermetallic compounds can be identified by the following method. First, the multilayer ceramic capacitor 1 is cross-polished to half its W dimension to expose a specific LT cross-section. Then, at the specific LT cross-section, it is confirmed that a flattened (plate-shaped) metal exists in the Sn plating layer 62, penetrating in the thickness direction of the Sn plating layer 62. Subsequently, a compositional analysis is performed on the identified flattened (plate-shaped) metal portion using EDX. As a result of this compositional analysis, if the molar ratio x:y of Ni to Sn, where x and y are integers, the metal portion is determined to be an intermetallic compound. By confirming that the molar ratio x:y of Ni to Sn is 1:4, it can be determined that the intermetallic compound is NiSn ４ It can be confirmed that this is the case.

[0132] (Fifth Embodiment) The external electrode 40 may have a conductive resin layer. The conductive resin layer includes, for example, conductive particles and a thermosetting resin. When a conductive resin layer is provided as the base electrode layer 50, the conductive resin layer may be arranged to cover the baking layer, or it may be placed directly on the laminate 10 without providing a baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is placed between the baking layer and the plating layer 60. The conductive resin layer may completely cover the baking layer, or it may cover a part of the baking layer.

[0133] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0134] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0135] Furthermore, the conductive particles may be metal powder with an Ag coating on its surface. When using metal powder with an Ag coating on its surface, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy of these. It is preferable to use Ag-coated metal powder in order to maintain the properties of Ag while making the base metal inexpensive.

[0136] Furthermore, the conductive particles may be Cu or Ni that have been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Sn, Ni, or Cu on the surface of the metal powder. When using metal powder coated with Sn, Ni, or Cu on the surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0137] The shape of the conductive particles is not particularly limited. Conductive particles can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0138] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0139] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0140] The conductive resin layer may be formed from multiple layers. Preferably, the thickness of the thickest part of the conductive resin layer is 10 μm or more and 150 μm or less.

[0141] Furthermore, the external electrode 40 may be formed using only the plating layer 60 without providing the undercoat electrode layer 50. In other words, the multilayer ceramic capacitor 1 may include a plating layer 60 that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer 60 may be formed after a catalyst is placed on the surface of the laminate 10 as a pretreatment.

[0142] (Other configurations of multilayer ceramic capacitors) The configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 7. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 8A, 8B, and 8C.

[0143] The multilayer ceramic capacitor 1 shown in Figure 8A is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 8B is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 8C is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0144] The multilayer ceramic capacitor 1 may be a two-terminal type with two external electrodes, or a multi-terminal type with multiple external electrodes.

[0145] In the embodiments described above, a multilayer ceramic capacitor was given as an example in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, thermistors using semiconductor ceramic as the ceramic layer, and inductors using magnetic ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ferrite and other ceramics.

[0146] <1> A laminate comprising a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the first external electrode comprises a first end surface-side external electrode disposed on the first end surface, the second external electrode comprises a second end surface-side external electrode disposed on the second end surface, each of the first end surface-side external electrode and the second end surface-side external electrode has a Ni plating layer and a Sn plating layer located on the Ni plating layer, and each of the first end surface-side external electrode and the second end surface-side external electrode has a groove extending in the stacking direction. A multilayer ceramic electronic component in which a metal containing Ni is exposed at the bottom surface of the groove.

[0147] <2> The multilayer ceramic electronic component according to <1>, wherein the metal exposed on the bottom surface of the groove includes the metal constituting the Ni plating.

[0148] <3> The multilayer ceramic electronic component according to <1>, wherein the metal exposed at the bottom of the groove contains an intermetallic compound mainly composed of Ni and Sn.

[0149] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein each of the first end-face side external electrode and the second end-face side external electrode has an under electrode layer between the laminate and the Ni plating layer.

[0150] <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the grooves are arranged in a plurality in the width direction.

[0151] <6> The multilayer ceramic electronic component according to any one of <1> to <5>, wherein both ends of the groove portion in the stacking direction T are terminated within the first end face and the second end face.

[0152] <7> The multilayer ceramic electronic component according to any one of <1> to <6>, wherein, when viewed in the longitudinal direction, the groove is arranged to straddle the boundary between the outer layer and the inner layer of the laminate.

[0153] <8> The multilayer ceramic electronic component according to any one of <1> to <7>, wherein, when viewed in the longitudinal direction, the groove is arranged to span one or more internal conductor layers among the plurality of internal conductor layers.

[0154] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0155] 1: Multilayer ceramic capacitor (multilayer ceramic electronic component) 10: Laminate 11: Inner layer 12: First main surface side outer layer (outer layer) 13: Second main surface side outer layer (outer layer) 20: Dielectric layer (ceramic layer) 30: Internal electrode layer (internal conductor layer) 40: External electrode 40A: First external electrode (first end face side external electrode) 40B: Second external electrode (second end face side external electrode) 50: Underlay electrode layer 50A: First underlay electrode layer 50B: Second underlay electrode layer 60: Plating layer 60A: First plating layer 60B: Second plating layer 61A: First Ni plating layer 61B: Second Ni plating layer 62A: First Sn plating layer 62B : Second Sn plating layer 63B : Groove 64A : Second groove 65A : Second groove 66A : First region 67A : Second region L : Longitudinal direction LS1 : First end face LS2 : Second end face T : Lamination direction TS1 : First main surface TS2 : Second main surface W : Width direction WS1 : First side surface WS2 : Second side surface

Claims

1. A laminate comprising a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the first external electrode comprises a first end surface-side external electrode disposed on the first end surface, the second external electrode comprises a second end surface-side external electrode disposed on the second end surface, each of the first end surface-side external electrode and the second end surface-side external electrode comprises a Ni plating layer and a Sn plating layer located on the Ni plating layer, and each of the first end surface-side external electrode and the second end surface-side external electrode comprises a groove extending in the stacking direction. A multilayer ceramic electronic component in which a metal containing Ni is exposed at the bottom surface of the groove.

2. The multilayer ceramic electronic component according to claim 1, wherein the metal exposed on the bottom surface of the groove includes the metal constituting the Ni plating.

3. The multilayer ceramic electronic component according to claim 1, wherein the metal exposed at the bottom of the groove contains an intermetallic compound mainly composed of Ni and Sn.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein each of the first end-face side external electrode and the second end-face side external electrode has an under electrode layer between the laminate and the Ni plating layer.

5. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the grooves are arranged in a plurality in the width direction.

6. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein both ends of the groove in the stacking direction T are terminated within the first end face and the second end face.

7. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein, when viewed in the longitudinal direction, the groove is arranged to straddle the boundary between the outer layer and the inner layer of the laminate.

8. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein, when viewed in the longitudinal direction, the groove is arranged to span one or more internal conductor layers among the plurality of internal conductor layers.

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