Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that makes it possible to improve high-temperature load reliability by suppressing insulation deterioration due to dielectric layers.　A multilayer ceramic capacitor 10 according to the present invention comprises: a multilayer body that includes a plurality of dielectric layers and a plurality of internal electrode layers; and an external electrode that is provided on an outer surface of the multilayer body, and is electrically connected to the plurality of internal electrode layers at a portion in which the plurality of internal electrode layers are exposed in the multilayer body. The internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers that are exposed on different surfaces of the multilayer body, and the external electrode includes a first external electrode that is electrically connected to the first internal electrode layers and a second external electrode that is electrically connected to the second internal electrode layers. The internal electrode layers contain Ni as a main component, and an interface region that contains at least one oxide of Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, or V is disposed in the vicinity of the interface between a first internal electrode layer and a dielectric layer and in the vicinity of the interface between a second internal electrode layer and a dielectric layer.

Description

Multilayer ceramic capacitor

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] With the recent progress of electronics technology, multilayer ceramic capacitors are required to be miniaturized and have a large capacitance. To meet these requirements, the dielectric layers of multilayer ceramic capacitors are being thinned. However, when the dielectric layer is thinned, the electric field strength applied to each layer becomes relatively high. Therefore, improvement in reliability against insulation during voltage application is required.

[0003] A multilayer ceramic capacitor generally includes a laminate having a plurality of stacked dielectric layers and a plurality of internal electrode layers formed along the interfaces between the dielectric layers, and a plurality of external electrodes formed on the outer surface of the laminate and electrically connected to the internal electrode layers. And, for example, as in Patent Document 1, when Ni is used as the main component of the internal electrode, and the internal electrode contains Sn, and the molar ratio of Sn to the total of Ni and Sn in the internal electrode layer is 0.001 or more and 0.1 or less, it is known that even when the dielectric layer is further thinned and a voltage with a high electric field strength is applied, good dielectric characteristics and excellent reliability are exhibited.

[0004] Japanese Patent Application Laid-Open No. 2014-57097

[0005] However, in the multilayer ceramic capacitor disclosed in Patent Document 1 described above, there is room for improvement from the viewpoint of high-temperature load reliability.

[0006] Therefore, the main object of this invention is to provide a multilayer ceramic capacitor capable of improving high-temperature load reliability by suppressing insulation deterioration of the dielectric layer.

[0007] The multilayer ceramic capacitor according to this invention comprises a laminate including a plurality of dielectric layers and a plurality of internal electrode layers, and an external electrode provided on the outer surface of the laminate and electrically connected to the plurality of internal electrode layers in the portion where the plurality of internal electrode layers are exposed in the laminate, wherein the internal electrode layer has a plurality of first internal electrode layers and a plurality of second internal electrode layers exposed on different surfaces of the laminate, and the external electrode has a first external electrode electrically connected to the first internal electrode layer and a second external electrode electrically connected to the second internal electrode layer, wherein the internal electrode layer is mainly composed of Ni, and interface regions containing at least one oxide from Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, and V are arranged near the interface between the first internal electrode layer and the dielectric layer, and near the interface between the second internal electrode layer and the dielectric layer.

[0008] According to the multilayer ceramic capacitor of this invention, the internal electrode layer is mainly composed of Ni, and interface regions containing at least one oxide from Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, and V are arranged near the interface between the first internal electrode layer and the dielectric layer, and near the interface between the second internal electrode layer and the dielectric layer. Therefore, the first interface region arranged in the first internal electrode layer contains an oxide with a higher ionization energy depending on its oxidation state than Ni, thereby increasing the Schottky barrier between the first internal electrode layer and the dielectric layer due to the metal. Similarly, the second interface region arranged in the second internal electrode layer contains an oxide with a higher ionization energy depending on its oxidation state than Ni, thereby increasing the Schottky barrier between the second internal electrode layer and the dielectric layer due to the oxide. As a result, when a voltage is applied to the multilayer ceramic capacitor, the insulation degradation of the relatively thin dielectric layer can be suppressed, and the high-temperature load reliability of the multilayer ceramic capacitor can be improved.

[0009] According to this invention, it is possible to provide a multilayer ceramic capacitor that can improve high-temperature load reliability by suppressing the insulating degradation of the dielectric layer.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings.

[0011] This is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. This is a cross-sectional view taken along line II-II in Figure 1. This is a cross-sectional view taken along line III-III in Figure 1. This is an enlarged cross-sectional view of section A in Figure 2.

[0012] An example of a multilayer ceramic capacitor according to an embodiment of this invention will be described. In this embodiment, the multilayer ceramic capacitor is a two-terminal type multilayer ceramic capacitor.

[0013] Figure 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line II-II in Figure 1. Figure 3 is a cross-sectional view taken along line III-III in Figure 1. Figure 4 is an enlarged cross-sectional view of section A in Figure 2.

[0014] As shown in Figures 1 to 3, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 arranged at both ends of the laminate 12.

[0015] The laminate 12 has a first main surface 12a and a second main surface 12b facing each other in the height direction x (lamination direction), a first side surface 12c and a second side surface 12d facing each other in the width direction y perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f facing each other in the length direction z perpendicular to the height direction x and the width direction y. The laminate 12 of this embodiment has rounded corners and edges. A corner is the part where three adjacent surfaces of the laminate 12 intersect, and an edge is the part where two adjacent surfaces of the laminate 12 intersect. In addition, some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may have irregularities or other features formed on them.

[0016] As shown in Figures 2 and 3, the laminate 12 has an inner layer portion 16 in which dielectric layers 14 and internal electrode layers 20 are alternately laminated in the lamination direction connecting the first main surface 12a and the second main surface 12b; a first outer layer portion 18a formed from a plurality of dielectric layers 14 located between the internal electrode layer 20 located closest to the first main surface 12a and the first main surface 12a; and a second outer layer portion 18b formed from a plurality of dielectric layers 14 located between the internal electrode layer 20 located closest to the second main surface 12b and the second main surface 12b.

[0017] The inner layer 16 is composed of multiple dielectric layers 14. The inner layer 16 is arranged such that multiple internal electrode layers 20 face each other via the dielectric layers 14.

[0018] The first outer layer 18a is located on the side of the first main surface 12a of the laminate 12, and is situated between the first main surface 12a and the internal electrode layer 20 that is closest to the first main surface 12a.

[0019] The second outer layer 18b is located on the second main surface 12b side of the laminate 12, and is situated between the second main surface 12b and the internal electrode layer 20 closest to the second main surface 12b. The region sandwiched between the first outer layer 18a and the second outer layer 18b is the inner layer 16.

[0020] The first outer layer 18a and the second outer layer 18b are each formed of an insulating material. The materials of the outer layers 18a and 18b and the material of the dielectric layer 14 of the inner layer 16 may be made of different components, for example, components with good moisture resistance, weather resistance, or strength resistance may be used.

[0021] The dimensions of the laminate 12 are not particularly limited, but for example, the length z dimension is 0.39 mm or more and 3.30 mm or less, the height x dimension is 0.21 mm or more and 2.70 mm or less, and the width y dimension is 0.21 mm or more and 2.70 mm or less.

[0022] As the dielectric material for forming the dielectric layer 14, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. Furthermore, the dielectric layer 14 may contain components such as rare earth elements, Si, Al, Mg, Mn, Ni, Fe, Cu, and V in amounts that do not hinder the effects of the present invention. These components may be in the form of oxides or carbonates, for example. The type of rare earth element is not particularly limited, but it is preferable to include at least one selected from the group consisting of Y (yttrium), La (lanthanum), Ce (cerium), Pr (praseodymium), Nd (neodymium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), Yb (ytterbium), and Lu (lutetium), and it is more preferable to include Dy.

[0023] The thickness of the dielectric layer 14 after firing is preferably 0.2 μm or more and 1.2 μm or less. Furthermore, in order to improve the reliability of the multilayer ceramic capacitor 10 according to the present invention, it is preferably 0.8 μm or less, and more preferably 0.4 μm or less. This makes it possible to increase the number of layers while satisfying the miniaturization of the multilayer ceramic capacitor 10, and can contribute to higher capacitance.

[0024] The laminate 12 has a plurality of internal electrode layers 20, consisting of a plurality of first internal electrode layers 20a drawn out from the first end face 12e and a plurality of second internal electrode layers 20b drawn out from the second end face 12f. The plurality of first internal electrode layers 20a and the plurality of second internal electrode layers 20b are embedded in the inner layer portion 18 so as to be alternately arranged at equal intervals along the height direction x of the laminate 12, with the dielectric layer 14 in between. The surfaces of the plurality of first internal electrode layers 20a and the plurality of second internal electrode layers 20b are generally parallel to the first main surface 12a and the second main surface 12b, and are, for example, roughly rectangular in plan view.

[0025] The first internal electrode layer 20a is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The first internal electrode layer 20a has a first opposing electrode portion 22a facing the second internal electrode layer 20b, and a first drawn-out electrode portion 24a located on one end side of the first internal electrode layer 20a, extending from the first opposing electrode portion 22a to the first end face 12e of the laminate 12. The end of the first drawn-out electrode portion 24a is drawn out to the surface of the first end face 12e and exposed from the laminate 12. In other words, the first drawn-out electrode portion 24a is not exposed on the first main surface 12a, the second main surface 12b, the first side surface 12c, the second side surface 12d, and the second end face 12f.

[0026] The shape of the first opposing electrode portion 22a of the first internal electrode layer 20a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0027] The shape of the first lead-out electrode portion 24a of the first internal electrode layer 20a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0028] The width of the first opposing electrode portion 22a of the first internal electrode layer 20a and the width of the first leading electrode portion 24a of the first internal electrode layer 20a may be the same width, or one of them may be narrower.

[0029] The second internal electrode layer 20b is arranged on a plurality of dielectric layers 14 and is located inside the laminate 12. The second internal electrode layer 20b has a second opposing electrode portion 22b facing the first internal electrode layer 20a, and a second drawn-out electrode portion 24b located on one end side of the second internal electrode layer 20b, extending from the second opposing electrode portion 22b to the second end face 12f of the laminate 12. The end of the second drawn-out electrode portion 24b is drawn out to the surface of the second end face 12f and exposed from the laminate 12. In other words, the second drawn-out electrode portion 24b is not exposed on the first main surface 12a, the second main surface 12b, the first side surface 12c, the second side surface 12d, and the first end face 12e.

[0030] The shape of the second opposing electrode portion 22b of the second internal electrode layer 20b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0031] The shape of the second lead-out electrode portion 24b of the second internal electrode layer 20b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0032] The width of the second opposing electrode portion 22b of the second internal electrode layer 20b and the width of the second leading electrode portion 24b of the second internal electrode layer 20b may be the same, or one of them may be narrower.

[0033] The laminate 12 includes a side portion 26a of the laminate 12 formed between one end of the first opposing electrode portion 22a and the second opposing electrode portion 22b in the width direction y and the first side surface 12c, and a side portion 26b of the laminate 12 formed between the other end of the first opposing electrode portion 22a and the second opposing electrode portion 22b in the width direction y and the second side surface 12d. Furthermore, the laminate 12 includes an end portion 27b of the laminate 12 formed between the end of the first internal electrode layer 20a opposite to the first extraction electrode portion 24a and the second end surface 12f, and an end portion 27a of the laminate 12 formed between the end of the second internal electrode layer 20b opposite to the second extraction electrode portion 24b and the first end surface 12e.

[0034] The first internal electrode layer 20a and the second internal electrode layer 20b are, for example, mainly composed of Ni. Furthermore, it is preferable that the first internal electrode layer 20a and the second internal electrode layer 20b contain a common material. The common material is preferably of the same composition as the ceramic that forms the main component of the dielectric layer 14.

[0035] The thickness of the internal electrode layer 20, that is, the first internal electrode layer 20a and the second internal electrode layer 20b, is preferably 0.2 μm or more and 1.2 μm or less. Furthermore, in order to improve the reliability of the multilayer ceramic capacitor 10 according to the configuration of the present invention, it is preferably 0.8 μm or less, and more preferably 0.4 μm or less.

[0036] Interface regions 40 are arranged near the interface between the dielectric layer 14 and both sides of the first internal electrode layer 20a facing each other in the stacking direction. Specifically, a first interface region 40a is arranged at the interface between each first internal electrode layer 20a and the dielectric layer 14 located on the first main surface 12a side, and near that interface, and a second interface region 40b is arranged at the interface between each first internal electrode layer 20a and the dielectric layer 14 located on the second main surface 12b side, and near that interface. Note that the interface regions 40 may be arranged only near the interface between the dielectric layer 14 and one of the two sides of the first internal electrode layer 20a facing each other in the stacking direction.

[0037] The interface region 40 contains at least one oxide from among Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, and V. These metals are oxides with higher ionization energies depending on their oxidation state than Ni. By including these oxides in the interface region 40, the Schottky barrier can be increased at and near the interface between the first internal electrode layer 20a and the dielectric layer 14. Therefore, even with a relatively thin dielectric layer 14, its insulation degradation can be suppressed and its high-temperature load reliability can be improved.

[0038] Furthermore, interface regions 42 are arranged near the interface between the dielectric layer 14 and both sides of the second internal electrode layer 20b facing each other in the stacking direction. Specifically, a third interface region 42a is arranged at the interface between each second internal electrode layer 20b and the dielectric layer 14 located on the first main surface 12a side, and near that interface, and a fourth interface region 42b is arranged at the interface between each second internal electrode layer 20b and the dielectric layer 14 located on the second main surface 12b side, and near that interface. Note that the interface regions 42 may be arranged only near the interface between the dielectric layer 14 and one of the two sides of the second internal electrode layer 20b facing each other in the stacking direction.

[0039] The interface region 42 contains at least one oxide from among Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, and V. These metals are oxides with higher ionization energies depending on their oxidation state than Ni. By including these oxides in the interface region 40, the Schottky barrier can be increased at and near the interface between the first internal electrode layer 20a and the dielectric layer 14. Therefore, even with a relatively thin dielectric layer 14, its insulation degradation can be suppressed and its high-temperature load reliability can be improved.

[0040] The thickness of interface region 40 and interface region 42 is 0.5 nm or more and 20 nm or less. More preferably, it is 0.5 nm or more and 5.0 nm or less.

[0041] The interface regions 40 and 42 can be confirmed as follows. That is, in the TEM (transmission electron microscope) image of the multilayer ceramic capacitor 10, the presence of the interface region 40 can be confirmed by performing line analysis of the concentration of each component element for each sample point along the stacking direction of the dielectric layer 14 and the internal electrode layer 20. More specifically, the presence or absence of the interface regions 40 and 42 is confirmed by detecting the concentration of each metal contained in the interface regions 40 and 42.

[0042] On the first end face 12e side and the second end face 12f side of the laminate 12, as shown in FIGS. 1 to 3, external electrodes 30 are disposed.

[0043] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0044] The first external electrode 30a is connected to the first internal electrode layer 20a and is disposed at least on the surface of the first end face 12e. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode layer 20a. In the present embodiment, the first external electrode 30a extends from the first end face 12e and is also disposed on a part of the first main face 12a, a part of the second main face 12b, a part of the first side face 12c, and a part of the second side face 12d.

[0045] The second external electrode 30b is connected to the second internal electrode layer 20b and is disposed at least on the surface of the second end face 12f. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode layer 20b. In the present embodiment, the second external electrode 30b extends from the second end face 12f and is also disposed on a part of the first main face 12a, a part of the second main face 12b, a part of the first side face 12c, and a part of the second side face 12d.

[0046] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode layer 20a and the second opposing electrode portion 22b of the second internal electrode layer 20b face each other through the dielectric layer 14, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a to which the first internal electrode layer 20a is connected and the second external electrode 30b to which the second internal electrode layer 20b is connected, and the characteristics of the capacitor are exhibited.

[0047] The external electrode 30 is preferably composed of a base electrode layer 32 and a plating layer 34. In the present embodiment, the external electrode 30 includes a base electrode layer 32 and a plating layer 34 disposed on the base electrode layer 32. The plating layer 34 includes a first plating layer 34a and a second plating layer 34b. The first external electrode 30a has a first base electrode layer 32a, a first lower plating layer 34a1 disposed on the first base electrode layer 32a, and a first upper plating layer 34a2 disposed on the first lower plating layer 34a1. The second external electrode 30b has a second base electrode layer 32b, a second lower plating layer 34b1 disposed on the second base electrode layer 32b, and a second upper plating layer 34b2 disposed on the second lower plating layer 34b1.

[0048] The first base electrode layer 32a is connected to the first internal electrode layer 20a and is disposed on the surface of the first end face 12e. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode layer 20a. In the present embodiment, the first base electrode layer 32a extends from the first end face 12e and is also disposed on a part of the first main face 12a, a part of the second main face 12b, a part of the first side face 12c, and a part of the second side face 12d.

[0049] The second base electrode layer 32b is connected to the second internal electrode layer 20b and is disposed on the surface of the second end face 12f. In this case, the second base electrode layer 32b is electrically connected to the second lead-out electrode portion 24b of the second internal electrode layer 20b. In the present embodiment, the second base electrode layer 32b extends from the second end face 12f and is also disposed on a part of the first main face 12a, a part of the second main face 12b, a part of the first side face 12c, and a part of the second side face 12d.

[0050] The base electrode layer 32 includes a conductive metal and glass. The conductive metal of the base electrode layer 32 includes at least one selected from, for example, Cu, Ni, Ag, Pb, Ag-Pb alloy, or Au. In this embodiment, the conductive metal is mainly Cu. The glass of the base electrode layer 32 mainly includes Si and Ba. Furthermore, the glass of the base electrode layer 32 preferably includes at least one selected from Al, B, Pd, Mg, or Li.

[0051] The base electrode layer 32 may consist of multiple layers. The base electrode layer 32 is formed by applying a conductive paste containing metal powder and glass powder to the laminate 12 and baking it. It may be baked simultaneously with the dielectric layer 14 and the internal electrode layer 20, or it may be baked after the dielectric layer 14 and the internal electrode layer 20 have been baked. The inclusion of glass in the base electrode layer 32 improves the adhesion between the laminate 12 and the base electrode layer 32.

[0052] The thickness of the first and second baked layers in the central part of the height direction x of the first and second base electrode layers 32a and 32b located on the first end face 12e and the second end face 12f is preferably, for example, 3 μm or more and 20 μm or less. Furthermore, when the base electrode layer 32 is provided on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, the thickness of the first and second baked layers in the central part of the length direction z of the first and second base electrode layers 32a and 32b located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is preferably, for example, 1 μm or more and 20 μm or less.

[0053] Next, the first plating layer 34a and the second plating layer 34b, which are plating layers 34 placed on the base electrode layer 32, will be described with reference to Figures 1 to 3.

[0054] The first plating layer 34a is arranged to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be arranged to cover the first base electrode layer 32a on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d. However, the first plating layer 34a may be arranged only on the first base electrode layer 32a on the first end face 12e side.

[0055] The second plating layer 34b is arranged to cover the second base electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may be arranged to cover the second base electrode layer 32b on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d side. However, the second plating layer 34b may be arranged only on the second base electrode layer 32b on the second end face 12f side.

[0056] The first plating layer 34a and the second plating layer 34b include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0057] The plating layer 34 may be formed from multiple layers. For example, the first plating layer 34a has a two-layer structure consisting of a first lower plating layer 34a1 and a first upper plating layer 34a2 covering the first lower plating layer 34a1, and the second plating layer 34b has a two-layer structure consisting of a second lower plating layer 34b1 and a second upper plating layer 34b2 covering the second lower plating layer 34b1. Preferably, the first lower plating layer 34a1 and the second lower plating layer 34b1 are Ni plating layers, and the first upper plating layer 34a2 and the second upper plating layer 34b2 are Sn plating layers.

[0058] The first and second lower plating layers 34a1 and 34b1, made of Ni plating, are used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10. The first and second upper plating layers 34a2 and 34b2, made of Sn plating, are used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating easier mounting.

[0059] The first and second lower plating layers 34a1 and 34b1, which are Ni plating layers, are preferably 1 μm or more and 15 μm or less in thickness. The first and second upper plating layers 34a2 and 34b2, which are Sn plating layers, are preferably 1 μm or more and 15 μm or less in thickness.

[0060] The first and second upper plating layers 34a2 and 34b2 may be omitted. Furthermore, the plating layer 34 may consist of the first and second upper plating layers 34a2 and 34b2 as the outermost layers, or other plating electrodes may be formed on the surfaces of the first and second upper plating layers 34a2 and 34b2.

[0061] Furthermore, a resin electrode layer containing resin and a powder made of a conductive metal may be placed between the base electrode layer 32 and the plating layer 34.

[0062] In the multilayer ceramic capacitor 10 shown in Figure 1, the interface region 40 located in the first internal electrode layer 20a contains an oxide with a higher ionization energy than Ni depending on its oxidation state, thereby increasing the Schottky barrier between the first internal electrode layer 20a and the dielectric layer 14 due to this metal. Similarly, the interface region 42 located in the second internal electrode layer 20b contains an oxide with a higher ionization energy than Ni depending on its oxidation state, thereby increasing the Schottky barrier between the second internal electrode layer 20b and the dielectric layer 14 due to this metal. As a result, when a voltage is applied to the multilayer ceramic capacitor 10, the insulation degradation of the relatively thin dielectric layer 14 can be suppressed, and the high-temperature load reliability of the multilayer ceramic capacitor 10 can be improved. In other words, the multilayer ceramic capacitor 10 has higher high-temperature load reliability than a multilayer ceramic capacitor that does not have interface regions 40 and 42.

[0063] Furthermore, as shown in Figure 1, the multilayer ceramic capacitor 10 has an oxide with a higher ionization energy than Ni, depending on its oxidation state, placed in the interface region. Therefore, it can achieve higher high-temperature load reliability than when a metal is used.

[0064] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, interface regions 40 are arranged near the interface between both sides of the first internal electrode layer 20a facing each other in the stacking direction and the dielectric layer 14, and interface regions 42 are arranged near the interface between both sides of the second internal electrode layer 20b facing each other in the stacking direction and the dielectric layer 14. Therefore, compared to the case where interface regions are arranged only on one of the internal electrode layers 20, it is possible to mount the capacitor without considering the polarity based on the direction of voltage application between the first external electrode 30a and the second external electrode 30b.

[0065] Next, we will explain the manufacturing method of multilayer ceramic capacitors.

[0066] (Step 1) First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known.

[0067] (Step 2) A conductive paste for the internal electrode layer is then printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer formed on it, and a dielectric sheet with the pattern of the second internal electrode layer formed on it. The patterns of the internal electrode layers can also be formed by sputtering.

[0068] (Step 3) Next, an interface region pattern is formed (interface region pattern formation step). The interface region pattern for forming interface region 40 is formed, for example, by sputtering onto the surface of the pattern of the first internal electrode layer, which is formed by drying a dielectric sheet on which a conductive paste for the internal electrode layer is printed. The oxide used for sputtering is at least one oxide from among Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, and V. The interface region pattern for forming interface region 42 is formed, for example, by sputtering onto the surface of the pattern of the second internal electrode layer, which is formed by drying a dielectric sheet on which a conductive paste for the internal electrode layer is printed. The oxide used for sputtering is at least one oxide from among Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, and V. By forming the patterns for each interface region by sputtering, it is possible to suppress the mixing of the metals of each layer. For each interface region pattern, the firing temperature, heating rate, atmosphere, etc., are appropriately adjusted according to the thickness and material to form each interface region 40, 42 at and near the interface between the internal electrode layer and the dielectric layer. In particular, since oxide is formed in interface region 40 by sputtering, the oxide can be placed in the interface region by controlling the atmosphere during sputtering and firing. Furthermore, by making the adjustments described above during the pattern formation process of each interface region, even if each metal diffuses to the dielectric layer and internal electrode layer during the firing process, each interface region can be formed at and near the interface of the internal electrode layer obtained after the firing process. In addition, when forming interface regions 40 on both sides facing the stacking direction of the first internal electrode layer, the interface region pattern is first deposited on the dielectric sheet by sputtering, the pattern of the first internal electrode layer is formed on the surface of the interface region pattern, and then each interface region is formed by sputtering on the surface of the pattern of the first internal electrode layer.Similarly, when forming interface regions 42 on both sides facing the stacking direction of the second internal electrode layer, the interface region pattern is first deposited on the dielectric sheet by sputtering, the pattern of the second internal electrode layer is formed on the surface of the interface region pattern, and then the interface region is formed by sputtering on the surface of the second internal electrode layer pattern. In addition, since oxide is formed in the interface region 42 by sputtering, the oxide can be placed in the interface region by controlling the atmosphere during sputtering and firing. Note that the method of forming the patterns of each interface region is not limited to sputtering.

[0069] Furthermore, in the process of forming the interface region pattern, the patterns of each internal electrode layer can be formed by sputtering. First, a Ni target for forming the pattern of the first internal electrode layer and a target of the metal element used for the interface region pattern are placed. When forming interface region patterns on both sides, the amount of metal element extruded from each corresponding target is adjusted so that the patterns are formed in the order of interface region pattern → first internal electrode layer pattern → interface region pattern. In other words, the collision of Ar ions with each target is suppressed during the adjustment. When forming the interface region pattern, Ar ions are given priority to collide with the target of the metal element used for the interface region pattern, and when forming the pattern of the first internal electrode layer, Ar ions are given priority to collide with the Ni target. The same method can also be used to form the interface region 42 for the second internal electrode layer. Through these controls, the interface region pattern and the internal electrode layer pattern can be formed continuously. Note that in this case, the interface region pattern may contain Ni, or the internal electrode layer pattern may contain the metal element used for the interface region pattern.

[0070] Furthermore, regarding the dielectric sheets, dielectric sheets for the outer layer that do not have the pattern of the internal electrode layer printed on them will also be prepared.

[0071] (Step 4) A predetermined number of dielectric sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are stacked. On top of these, dielectric sheets with the pattern of the first internal electrode layer printed on them and dielectric sheets with the pattern of the second internal electrode layer printed on them are stacked sequentially to form the inner layer portion 18. On top of this inner layer portion 18, a predetermined number of dielectric sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are stacked. This forms a laminated sheet having an inner layer portion 18 and an outer layer portion. Note that the dielectric sheets for the outer layer may be stacked as a single sheet or as a multiple sheet.

[0072] (Step 5) Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block.

[0073] (Step 6) The laminated block is then cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or the like.

[0074] (Step 7) Next, the laminated chips are fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer and the internal electrode layer, but for example, it is between 900°C and 1400°C. Steps 1 to 6 are the laminated body formation steps. In addition, during the firing process, some of the metal used to form the pattern in the interface region may be diffused into the dielectric layer and the internal electrode layer.

[0075] (Step 8) Next, the first external electrode 30a and the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the laminate 12. That is, first, a paste for the base electrode layer is applied to the first end face 12e and the second end face 12f of the laminate 12 and baked, forming the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b. The baking temperature is, for example, 700°C to 900°C. The paste for the base electrode layer contains metal powder, which is Cu as the main component, and glass powder, which contains Si, Ba and Al as components. The metal powder and glass powder in the paste for the base electrode layer are incorporated as conductive metal and glass in the base electrode layer 32 by the aforementioned baking.

[0076] (Step 9) Next, a plating layer 34 is formed. In this embodiment, the plating layer 34 is formed on the surface 33 of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. When performing the plating process, either electrolytic plating or electroless plating may be used, but electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is generally preferable to use electrolytic plating. As for the plating method, it is preferable to use barrel plating.

[0077] As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0078] <Modification> In the above embodiment, a two-terminal multilayer ceramic capacitor having two terminals, a first external electrode 30a and a second external electrode 30b, was described as a multilayer ceramic capacitor. However, the present invention is not limited to a two-terminal multilayer ceramic capacitor, and is applicable to any multilayer ceramic capacitor having external electrodes. For example, the present invention may be applied to a three-terminal multilayer ceramic capacitor. The three-terminal multilayer ceramic capacitor has a laminate 12 similar to that in the above embodiment, and first to fourth external electrodes. The internal electrode layer 20 has a first internal electrode layer drawn out to the first end face 12e and the second end face 12f, and a second internal electrode layer drawn out to the first side surface 12c and the second side surface 12d. The first external electrode is arranged on the first end face 12e of the laminate 12. The first external electrode is electrically connected to the first internal electrode layer exposed on the first end face 12e of the laminate 12. The second external electrode is arranged on the second end face 12f of the laminate 12. The second external electrode is electrically connected to the first internal electrode layer exposed on the second end face 12f of the laminate 12. A third external electrode is positioned on the first side surface 12c of the laminate 12. The third external electrode is electrically connected to the second internal electrode layer exposed on the first side surface 12c of the laminate 12. A fourth external electrode is positioned on the second side surface 12d of the laminate 12. The fourth external electrode is electrically connected to the second internal electrode layer exposed on the second side surface 12d of the laminate 12.

[0079] In this case, the first internal electrode layer becomes the positive electrode, and the second internal electrode layer becomes the negative electrode. The device is then configured so that a voltage is applied between two sets of external electrodes: the first external electrode and the second external electrode, and the third external electrode and the fourth external electrode.

[0080] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0081] In other words, without departing from the scope of the technical idea and objectives of the present invention, various changes can be made to the embodiments and each of the modifications described above in terms of mechanism, shape, material, quantity, position or arrangement, etc., and these are included in the present invention.

[0082] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of dielectric layers and a plurality of internal electrode layers; an external electrode provided on the outer surface of the laminate and electrically connected to the plurality of internal electrode layers in the portion where the plurality of internal electrode layers are exposed in the laminate; wherein the internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers exposed on different surfaces of the laminate; the external electrode has a first external electrode electrically connected to the first internal electrode layer and a second external electrode electrically connected to the second internal electrode layer; the internal electrode layers are mainly composed of Ni; and interface regions containing at least one oxide from Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, V are arranged near the interface between the first internal electrode layer and the dielectric layer, and near the interface between the second internal electrode layer and the dielectric layer.

[0083] <2> The multilayer ceramic capacitor according to <1>, wherein the first interface region is arranged on both sides of the first internal electrode layer.

[0084] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the second interface region is arranged on both sides of the second internal electrode layer.

[0085] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the thickness of the first interface region is 0.5 nm or more and 20 nm or less.

[0086] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the thickness of the second interface region is 0.5 nm or more and 20 nm or less.

[0087] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the thickness of the first internal electrode layer and the second internal electrode layer is 1.2 μm or less.

[0088] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the thickness of the dielectric layer is 1.2 μm or less.

[0089] 10: Multilayer ceramic capacitor 12: Laminate 12a: First main surface 12b: Second main surface 12c: First side surface 12d: Second side surface 12e: First end surface 12f: Second end surface 14: Dielectric layer 14a: Inner dielectric layer 14b: Outer dielectric layer 16: Inner layer portion 18a: First outer layer portion 18b: Second outer layer portion 20: Internal electrode layer 20a, 20b: First and second internal electrode layers 22a, 22b: First and second opposing electrode portions 24a, 24b: First and second lead electrode portions 26a, 26b: Side portion 27a, 27b: End portion 30: External electrode 30a, 30b : First and second external electrodes 32: Underlay electrode layers 32a, 32b: First and second underlay electrode layers 34: Plating layer 34a: First plating layer 34b: Second plating layer 34a1, 34b1: First and second lower plating layers 34a2, 34b2: First and second upper plating layers 40, 42: Interface region 40a: First interface region 40b: Second interface region 42a: Third interface region 42b: Fourth interface region x: Height direction y: Width direction z: Length direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of dielectric layers and a plurality of internal electrode layers; an external electrode provided on the outer surface of the laminate and electrically connected to the plurality of internal electrode layers in the portion where the plurality of internal electrode layers are exposed in the laminate; wherein the internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers exposed on different surfaces of the laminate; the external electrode has a first external electrode electrically connected to the first internal electrode layer and a second external electrode electrically connected to the second internal electrode layer; the internal electrode layers are mainly composed of Ni; and interface regions containing at least one oxide from Zn, Fe, Sb, In, Mn, Ge, Sn, Mo, W, Ga, Cr, V are arranged near the interface between the first internal electrode layer and the dielectric layer, and near the interface between the second internal electrode layer and the dielectric layer.

2. The multilayer ceramic capacitor according to claim 1, wherein the first interface region is arranged on both sides of the first internal electrode layer.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the second interface region is arranged on both sides of the second internal electrode layer.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the thickness of the first interface region is 0.5 nm or more and 20 nm or less.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the thickness of the second interface region is 0.5 nm or more and 20 nm or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the thickness of the first internal electrode layer and the second internal electrode layer is 1.2 μm or less.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the thickness of the dielectric layer is 1.2 μm or less.

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