Josephson d-latch

Abstract

Josephson junction based data latch devices and methods for their use are described herein. An example Josephson junction based data latch device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. Each loop of the plurality of superconducting loops is electrically coupled and is configured to shift or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses. A readout line is coupled to the plurality of superconducting loops. A plurality of data and control lines are coupled to the plurality of superconducting loops. Each line is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops. The plurality of signals includes a data signal, an enable control signal, and a read control signal.

Description

JOSEPHSON D-LATCH FIELD OF THE DISCLOSURE

[0001] This application relates to superconducting circuits. In particular, this application discloses a D-latch circuit implemented using a plurality of superconducting Josephson junctions and related circuitry. In such scenarios, the implementations may use single-flux quantum (SFQ) pulses to store state information. BACKGROUND

[0002] Conventional digital circuits make use of complementary metal-oxide semiconductor (CMOS) technology to provide digital logic functionality. Recent developments have provided a more power efficient, higher-bandwidth, and denser solution: superconducting digital (SCD) technology, including pulse conservative logic (PCL), which makes use of Josephson single flux quantum (SFQ) pulses, while retaining compatibility with existing electronic design automation (EDA) tools.

[0003] However, there exists a need to reproduce all functions of a standard CMOS gate library in PCL in order to achieve feature parity, including a D-latch to retain state information in certain operating contexts. SUMMARY

[0004] The embodiments herein efficiently utilize Josephson junctions to implement a D-latch using a single latch in PCL. The conventional CMOS design of a D-Latch uses a primary-secondary (master-slave) configuration, but the embodiments herein may include a single latch plus an OR gate that suppresses glitches in the output.

[0005] The embodiments herein relate to an implementation of a D-latch in PCL- based SCD circuits. Such a D-latch utilizes superconducting Josephson junctions and related circuitry as well as single-flux quantum (SFQ) pulses stored in loops to retain state information.

[0006] In a first aspect, a Josephson junction based data latch device is provided. The Josephson junction based data latch device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. Each loop of the plurality of superconducting loops is electrically coupled. Each loop of the plurality of superconducting loops is configured to shift or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses. The Josephson junction based data latch device also includes a readout line coupled to the plurality of superconducting loops.

[0007] The Josephson junction based data latch device also includes a plurality of data and control lines coupled to the plurality of superconducting loops. Each line of the plurality of data and control lines is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops. The plurality of signals includes a data signal, an enable control signal, and a read control signal.

[0008] In a second aspect, a shift register system is provided. The shift register system includes a plurality of Josephson junction based data latch devices. Each Josephson junction based data latch device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. Each loop of the plurality of superconducting loops is electrically coupled. Each loop of the plurality of superconducting loops is configured to shift or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses. Each Josephson junction based data latch device also includes a readout line coupled to the plurality of superconducting loops. Each Josephson junction based data latch device also includes a plurality of data and control lines coupled to the plurality of superconducting loops. Each line of the plurality of data and control lines is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops. The plurality of signals includes a data signal, an enable control signal, and a read control signal. The plurality of Josephson junction based data latch devices are serially connected via a plurality of wave-pipelined Josephson transmission lines.

[0009] In a third aspect, a method for storing digital information in a Josephson junction based data latch device is provided. The method includes providing, to a plurality of superconducting loops, a combination of a plurality of signals and single flux quantum (SFQ) pulses. Each superconducting loop includes at least one Josephson junction. Each loop of the plurality of superconducting loops is electrically coupled. The plurality of signals include a data signal, an enable control signal, and a read control signal. A plurality of data and control lines are coupled to the plurality of superconducting loops. Each line of the plurality of data and control lines is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops. The method also includes, in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops. The method further includes transmitting, via a readout line coupled to the plurality of superconducting loops, an output signal.BRIEF DESCRIPTION OF THE FIGURES

[0010] The above, as well as additional features, will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

[0011] Figure 1 illustrates an overview of a PCL-based D-latch device, in accordance with example embodiments.

[0012] Figure 2 illustrates a schematic diagram of a Josephson junction based data latch device 200, in accordance with example embodiments.

[0013] Figure 3A illustrates a circuit diagram of a Josephson junction based data latch device, in accordance with example embodiments.

[0014] Figure 3B illustrates a circuit diagram of a Josephson junction based data latch device, in accordance with example embodiments.

[0015] Figure 3C illustrates a circuit diagram of a Josephson junction based data latch device, in accordance with example embodiments.

[0016] Figure 4A illustrates an initial flux biasing method, in accordance with example embodiments.

[0017] Figure 4B illustrates an initial flux biasing method, in accordance with example embodiments.

[0018] Figure 5A illustrates a signal sequence, in accordance with example embodiments.

[0019] Figure 5B illustrates a single flux quantum shifting sequence, in accordance with example embodiments.

[0020] Figure 6A illustrates a signal sequence, in accordance with example embodiments.

[0021] Figure 6B illustrates a single flux quantum shifting sequence, in accordance with example embodiments.

[0022] Figure 7A illustrates a signal sequence, in accordance with example embodiments.

[0023] Figure 7B illustrates a single flux quantum shifting sequence, in accordance with example embodiments.

[0024] Figure 8 illustrates results of a waveform simulation, in accordance with example embodiments.

[0025] Figure 9 illustrates a schematic of an enabled shift register device, in accordance with example embodiments.

[0026] Figure 10 illustrates results of a waveform simulation, in accordance with example embodiments.

[0027] Figure 11 illustrates a graph of an inverted enable signal, in accordance with example embodiments.

[0028] Figure 12 illustrates a method for storing digital information in a Josephson junction based data latch device, in accordance with example embodiments.

[0029] All the figures are schematic, not necessarily to scale, and generally only show parts that are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested. DETAILED DESCRIPTION

[0030] Various examples of systems, devices, and / or methods are described herein with reference to the accompanying drawings. Any embodiment, implementation, and / or feature described herein as being an example is not necessarily to be construed as preferred or advantageous over any other embodiment, implementation, and / or feature unless stated as such. Thus, other embodiments, implementations, and / or features may be utilized, and other changes may be made without departing from the scope of the subject matter presented herein.

[0031] Accordingly, the examples described herein are not meant to be limiting. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations.

[0032] Further, unless the context suggests otherwise, the features illustrated in each of the figures may be used in combination with one another. Thus, the figures should be generally viewed as component aspects of one or more overall embodiments, with the understanding that not all illustrated features are necessary for each embodiment.

[0033] Additionally, any enumeration of elements, blocks, or steps in this specification or the claims is for purposes of clarity. Thus, such enumeration should not be interpreted to require or imply that these elements, blocks, or steps adhere to a particular arrangement or are carried out in a particular order.

[0034] Moreover, terms such as “substantially” or “about” that may be used herein are meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including, for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those skilled in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.

[0035] Further, terms such as “A coupled to B,” “A electrically coupled to B,” “A connected to B,” “A electrically connected to B” etc., do not necessarily mean that items A and B are directly coupled to one another. For example, a first component electrically coupled to a second component is interpreted to mean that the components are either directly coupled (e.g., via a conductor) or coupled to one another via one or more resistors, capacitors, inductors, and / or other active or passive components.

[0036] The potential of superconducting digital technology as a beyond-CMOS technology derives from high energy efficiency, high computational density, and high interconnect bandwidth. The technology is based on the single-flux-quantum (SFQ) pulse, which is fast, low power, and low-dispersion / low-loss on superconductor transmission lines. Example embodiments involve various combinations of fabrication materials, density, power / clock distribution, logic and memory design, packaging, interfaces, and architecture. D-Latch Logic

[0037] The latch is a fundamental element in digital circuit design that retains the state of the input signal after the input is removed. This feature is beneficial for various purposes, such as data storage from one clock cycle to the next, synchronization, and control logic.

[0038] Implementation of the D-latch in PCL-based SCD circuits is distinct from other types of latches since the signals are represented using single flux quantum (SFQ) pulses. Instead of a conventional (as in CMOS) primary-secondary (master-slave) configuration, a single gate can be used. However, in some situations, the simplest design suffers from glitches producing spurious output whenever the enable signal has a value of one. The embodiments herein describe an area efficient latch implementation that suppresses such glitches using an auxiliary read signal.

[0039] An example D-latch involves an enable (E) input and becomes “transparent,” with the input conveyed to the output, when E is asserted. When E is low (or has a value of zero), the D-latch stores this state for an arbitrary time until it is overwritten again by asserting E.

[0040] Figure 1 illustrates an overview of a PCL-based D-latch device 100. Figure 1 also depicts the D-latch device 100 configured to receive a plurality of signals, including a data signal 102 D, an enable control signal 104A E, and a read (or strobe) control signal 106 S. The D-latch device 100 of Figure 1 is also configured to provide an output signal 108 Q.

[0041] As noted above, in order to suppress glitches in the output of the latch, an auxiliary read control signal may be used. This auxiliary signal corresponds with the readcontrol signal 106, and in some embodiments may be the result of an OR operation between the data signal 102 and a result of a NOT operation on the enable control signal 104B, as illustrated in Figure 1 with OR gate 110.

[0042] In some embodiments, the data signal 102 may be delayed, for example by Josephson transmission line (JTL) 112, between the data signal source and the latch circuit itself.

[0043] Some or all of the aforementioned components in Figure 1 may be consolidated into a single unit, such as latch unit 114, for simplicity in circuit design. Example Josephson Junction Based Data Latch Devices

[0044] Figure 2 illustrates a schematic diagram of a Josephson junction based data latch device 200, in accordance with example embodiments, which may be configured to operate as a D-latch as described above. The Josephson junction based data latch device 200 includes a plurality of superconducting loops 202. Each superconducting loop (e.g., superconducting loop 202a, 202b, 202c, or 202d) includes at least one Josephson junction (e.g., Josephson junction 204a, 204b, and / or 204c). In such scenarios, the plurality of superconducting loops 202 are electrically coupled to one another.

[0045] As illustrated in Figure 2, the plurality of superconducting loops 202 could be electrically coupled in a sequential (i.e. series) arrangement. In some examples, the sequential arrangement can include four superconducting loops (e.g., superconducting loops 202a, 202b, 202c, and 202d). In such scenarios, each superconducting loop of the plurality of superconducting loops 202 has one or two adjacent loops. As an example, superconducting loop 202a has one adjacent loop (superconducting loop 202b), superconducting loop 202b has two adjacent loops (superconducting loop 202a and superconducting loop 202c), superconducting loop 202c has two adjacent loops (superconducting loop 202b and superconducting loop 202d), and superconducting loop 202d has one adjacent loop (superconducting loop 202c). It will be understood that other arrangements of the superconducting loops 202 are possible and contemplated in relation to the present disclosure.

[0046] The Josephson junction based data latch device 200 also includes a plurality of data and control lines 210 coupled to the plurality of superconducting loops 202. In some embodiments, the Josephson junction based data latch device 200 may be coupled to an AC current-bias source. In some embodiments, the AC current-bias source may be a capacitor, which in some embodiments may be coupled to a resonant clock-power distribution network. In some embodiments, each line of the plurality of data and control lines 210 could include aJosephson transmission line, at least one inductor, and / or a resistor connected between the Josephson transmission line and a corresponding superconducting loop of the plurality of superconducting loops.

[0047] The plurality of superconducting loops 202 are configured to shift or annihilate magnetic flux quanta (e.g., SFQ 220a or SFQ 220b) in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses. In some embodiments, the signals include a data signal, an enable control signal, and a read (or strobe) control signal.

[0048] In some embodiments, the signals could be provided to the superconducting loops 202 by way of the data and control lines 210. In the embodiment illustrated in Figure 2, the signals are provided by a data line 212, an enable control line 214, and / or a read control line 216. These control lines correspond to the data signal 102, an enable control signal 104A, and read control signal 106 illustrated in Figure 1.

[0049] In some embodiments, the data signal is configured to be transmitted to a first loop and a second loop of the plurality of superconducting loops, the enable control signal is configured to be transmitted to a second loop and a third loop of the plurality of superconducting loops, and the read control signal is configured to be transmitted to a third loop and a fourth loop of the plurality of superconducting loops.

[0050] In some embodiments, the plurality of superconducting loops 202 are configured to shift a magnetic flux quanta (e.g., SFQ 220a) from an initial superconducting loop (e.g., superconducting loop 202c) to an adjacent loop (e.g., superconducting loop 202b) in response to a SFQ pulse and / or signal applied to the initial superconducting loop. In some embodiments, this shifting may be based on the presence and orientation of magnetic flux quanta in the plurality of superconducting loops.

[0051] In some embodiments, a magnetic flux quanta is shifted from an initial superconducting loop to an adjacent loop in a first direction along the sequential arrangement in response to a positive SFQ pulse polarity. In some embodiments, a magnetic flux quanta is shifted from an initial superconducting loop to an adjacent loop in a second direction along the sequential arrangement in response to a negative SFQ pulse polarity.

[0052] In some embodiments, a readout line 230 may be coupled to the plurality of superconducting loops. In response to the shifting of SFQ between superconducting loops 202 and the signals, an output signal may be transmitted via the readout line 230.

[0053] The operation of the data latch device may involve shifting a stored single- flux-quantum (SFQ) between superconducting loops separated by Josephson junctions inresponse to signals provided to the superconducting loops via the data and control lines as discussed above. The shifting mechanism is discussed below.

[0054] The principle of operation is based on magnetic flux quantization and energy conservation of the circuit. Flux is quantized in superconducting loops according to ,where is number of flux quantasustained (or “trapped”) in the loop. AJosephson junction connected to a superconducting loop will trigger if that does not result in an increment in the circuit energy which is given by the equationwhere is the inductance of the superconducting wires. For instance, if the Josephson junction is connected to two superconducting loops with no initial flux biasing, triggering this junction will store two flux quanta in the two loops, significantly increasing the circuit energy. However, if only one of the loops has a stored flux due to initial biasing, triggering the Josephson junction will move the flux quantum from the current loop to the next one. Thus, the overall energy remains constant. In other words, if the current of a stored SFQ interferes constructively with the current associated with an input signal (e.g. a data or control signal as described herein) in any Josephson junction, then the critical current of that Josephson junction will be exceeded. This has the effect of moving the stored SFQ to the adjacent loop. Otherwise, the signal will be dissipated (or annihilated) across the coupling resistor with no change in the state. This is visually depicted in Table 1 below.

[0055] As shown in Table 1, by applying a signal and depending on the presence of SFQs in the superconducting loops, SFQs may be shifted between loops and / or annihilated, which may thus cause an output signal to be transmitted via the readout line.

[0056] An alternate principle of operation is based on current through the Josephson junctions. If the signal current interferes constructively with the stored flux current the Josephson junction will trigger, moving the flux through the Josephson junction. The resistors connected to the input may absorb the voltage signal in cases where the Josephson junctions do not trigger.

[0057] The signal timing is particularly important to the cell functionality. To ensure correct timing, the enable control signal should arrive at the data latch device before the other signals. In other words, a transition edge of the enable control signal may be configured to arrive along a corresponding control line at a time prior to any other control signal of the plurality of signals involved in a single data latch operation. This may be accomplished byassigning incrementing AC clock phase assignment of the signals. For instance, the enable control signal may be configured to arrive at the data latch device at least one clock cycle prior to the other signals.

[0058] Using the above methods, logical operations may be performed by manipulating the signals, including data latch operations as described above.

[0059] Figure 3A illustrates a circuit 300 of an embodiment of the Josephson junction based data latch device 200 of Figure 2. The circuit 300 consists of Josephson transmission line (JTL) stages along the data and control lines 310A. The current sources (with arrows) represent AC bias, which allows both positive and negative SFQ pulses to propagate at different times in the clock cycle. As noted above, the AC bias may be a capacitor, which in some embodiments may be coupled to a resonant clock-power distribution network Resistors couple the inputs to the internals of the cell. Each junction-resistor pair is a decision-making element; if the signal current adds with the same polarity to the current of the SFQ in a superconducting loop as seen by the junction, the signal will trigger the junction to produce an SFQ pulse and move the stored pulse to the adjacent superconducting loop. Otherwise, the signal voltage may be lost across the resistor. In some embodiments, similar behavior can be achieved by replacing any or all of these coupling resistors with additional Josephson junctions. The pulsed voltage sources (represented as circles with dots) represent SFQ sources to produce the initial state. The initial state shown corresponds to the zero state, but other initial states could be used. Additionally, a readout line 330A is coupled to the superconducting loops 302A that may transmit an output signal Q.

[0060] As illustrated in Figure 3A, in some embodiments, the data signal is configured to be transmitted to a first loop and a second loop of the plurality of superconducting loops. The data signal may be configured to shift a magnetic flux quantum from the first loop to the second loop and from the second loop to the first loop based on the presence of magnetic flux quanta in the plurality of superconducting loops.

[0061] In some embodiments, the enable control signal is configured to be transmitted to a second loop and a third loop of the plurality of superconducting loops. The enable control signal may be configured to shift a magnetic flux quantum from the second loop to the third loop and from the third loop to the second loop based on the presence of magnetic flux quanta in the plurality of superconducting loops.

[0062] In some embodiments, the read control signal is configured to be transmitted to a third loop and a fourth loop of the plurality of superconducting loops. The read control signal may be configured to shift a magnetic flux quantum from the third loop to the fourthloop and from the fourth loop to the third loop based on the presence of magnetic flux quanta in the plurality of superconducting loops.

[0063] Figure 3B illustrates a circuit 350 of another embodiment of the Josephson junction based data latch device 200 of Figure 2. While such an embodiment operates according to the same principles as the devices illustrates in Figure 2 and 3A, it may be configured in a slightly different manner, with different inductances at different points in the circuit. However, the behavior of the circuit 350 with regards to input and output signals is the same as the prior embodiments.

[0064] Figure 3C illustrates a circuit 380 of another embodiment of the Josephson junction based data latch device 200 of Figure 2. While such an embodiment operates according to the same principles as the devices illustrates in Figure 2, 3A, and 3B, it may be configured in a slightly different manner, with different inductances at different points in the circuit. Additionally, one of the superconducting loops in the circuit 380 is initialized with and configured to make use of half a magnetic flux quantum and the read control line 316C is positioned to be coupled to a fourth superconducting loop. Additionally, Figure 3C depicts a superconducting loop coupled to other superconducting loop(s) in a parallel configuration (as opposed to a series / sequential configuration. Thus, in some embodiments, at least two of the loops of the plurality of superconducting loops are electrically coupled in a parallel arrangement. However, as before, the behavior of the circuit 380 with regards to input and output signals is the same as the prior embodiments.

[0065] In use, setting the initial state may not necessarily use pulsed voltage sources as depicted in Figures 3A, 3B, and 3C. In some embodiments, magnetic coupling provided by way of a feed line may be used to set the initial state.

[0066] In some embodiments, an initial flux biasing may be used to set up the internalstate, where denotes a single flux quantum (SFQ), corresponding to a 2 phase rotation ofa Josephson junction. In some embodiments, the initial flux bias is set using the circuit shown in Figure 4A. The current in the feed line 410 is ramped up until the current I in the feed line410 satisfies the equation / , where M is mutual coupling (i.e. the mutual inductancebetween the top and bottom inductors illustrated in Figure 4A), to store an SFQ in the loop.

[0067] Figure 4B depicts an alternative flux biasing method that may be used in someembodiments. In this alternative, the feed line 460 maintains a currentbefore theloop transitions into a superconducting state (i.e., where the temperature T > the critical temperature ) and the temperature T is then gradually reduced to achieve thesuperconducting state. The circuit initializes to the ground state with no net flux. However, this state can be understood as a superposition of the applied flux and a virtual flux in the loop in the opposite direction, as also illustrated in Figure 4B. Then, the current in the feed line is switched off, which traps a single flux quantum in the loop. This application and removal of the flux in the feed line can be described as a “bait and switch.”

[0068] Put another way, the data latch device 200 may include at least one magnetically coupled feed line. In such scenarios, the plurality of superconducting loops 202 are configured to provide an initial flux state in response to a two-step flux initialization process. The two-step flux initialization process may include: 1) while cooling down the Josephson junction based data latch device, providing an initialization signal via the at least one magnetically coupled feed line; and 2) upon reaching a superconducting critical temperature of the Josephson junction based data latch device, turning off the initialization signal such that an exact integral number of SFQ are stored in one or more of the superconducting loops.

[0069] Figure 5A depicts a signal sequence 500, which represents changes in the control and output signals associated with the data latch device 200. In this and the following examples, D represents the data signal, E represents the enable control signal, S represents the read control signal, and Q represents the output signal.

[0070] Figure 5B depicts an SFQ shifting sequence 550 within the superconducting loops 202 of the data latch device 200, in accordance with example embodiments. The shifting sequence 550 is associated with the signal sequence 500 of Figure 5A. Figures 5A- 8B make use of circuit 300 depicted in Figure 3A. The numbers within the circles represent the time t, which corresponds to the time within the circles shown in Figure 5A.

[0071] Prior to the actions described in Figures 5A, 5B, or any of the following drawings, the data latch device 200 may have its “zero-state” set according to an initial flux biasing process as described above in relation to Figures 4A and 4B.

[0072] Example operations are illustrated in Figures 5A and 5B as a time sequence of the propagating input signals. If the current of a stored SFQ interferes constructively with the current associated with an input signal (e.g. a data or control signal as described herein) in any Josephson junction, then the critical current of that Josephson junction will be exceeded. This has the effect of moving the stored SFQ to the adjacent loop. Otherwise, the signal will be dissipated (or annihilated) across the coupling resistor with no change in the state. In other words, each loop of the plurality of superconducting loops is configured to shift or annihilatemagnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses.

[0073] As shown in Figures 5A and 5B, at time t = 1, the enable control signal E arrives before the other two inputs. The read signal S is the logical OR of the data signal D and inverted enable !E signals, as described previously. The flux bias configuration starts in the initial state (i.e., zero state) of the latch, with single flux quanta in the two rightmost loops. When the enable control signal E arrives at t = 1, current associated with E constructively interferes with the stored SFQ and triggers the middle Josephson junction (junction 204b in the example of Figure 2). This action shifts the stored SFQ to the left as shown at t = 2 in Figure 5B, allowing the read control signal S to trigger the right-most Josephson junction (junction 204c in the example of Figure 2), which indicates the SET state (i.e., one state) of the latch.

[0074] As also illustrated in Figures 5A and 5B, further input signals result in stored SFQ moving across the superconducting loops, with a variety of results. This enables the D- latch operations write 1 (from t = 1 to t = 4) and read 1 (from t = 8 to t = 9). Despite not having an enable control signal or data signal active at t = 8, the latch still outputs a value of 1, retaining the state from the previous write operation.

[0075] Note that enable temporarily puts the cell in to a one state when enable is active, even if the data is zero. This means the cell passes pulses whenever the enable is active. This would result in glitching (i.e. incorrect outputs) without the OR gate on the read control signal S as discussed previously.

[0076] As described previously, the operating principle involves addition of currents in the Josephson junctions (e.g., Josephson junctions 204a, 204b, and 204c): the SFQ will move one superconducting loop to the left if a positive signal current adds constructively to the stored SFQ, which is a persistent current in the loop. The SFQ will move one superconducting loop to the right if a negative signal current adds to negative current in the stored SFQ. The currents of SFQ stored in adjacent loops cancel in the shared Josephson junctions, so that two SFQs do not occupy a shared loop at the same time. The Q output signal may be generated in a case where the S junction switches and moves the stored pulse between loops.

[0077] Figure 6A depicts a signal sequence 600, which represents changes in the control and output signals associated with the data latch device 200. Figure 6B depicts an SFQ shifting sequence 650 within the superconducting loops 202 of the data latch device200, in accordance with example embodiments. As noted above, this example makes use of circuit 300 depicted in Figure 3A.

[0078] As illustrated in Figures 6A and 6B, input signals result in stored SFQ moving across the superconducting loops, with a variety of results. This enables the D-latch operations write 0 (from t = 11 to t = 14) and read 0 (from t = 15 to t = 16). As shown, the latch is set to output a value of 0.

[0079] Figure 7A depicts a signal sequence 700, which represents changes in the control and output signals associated with the data latch device 200. Figure 7B depicts an SFQ shifting sequence 750 within the superconducting loops 202 of the data latch device 200, in accordance with example embodiments. As noted above, this example makes use of circuit 300 depicted in Figure 3A.

[0080] As illustrated in Figures 7A and 7B, input signals result in stored SFQ moving across the superconducting loops, with a variety of results. Note that, as depicted, the output signal Q remains at 0, demonstrating latch behavior from the previous operations depicted in Figures 5A-6B.

[0081] Figure 8 illustrates results 800 of a simulation of the circuit of Figure 3A using WRSpice software. The input waveforms correspond to those of Figures 5A-7B, but with each input pulse repeated. The results otherwise correspond to Figures 5A-7B and its accompanying description.

[0082] Figure 9 illustrates a schematic of an example enabled shift register device 900. Such a device is analogous to a CMOS-implemented pipeline, but as illustrated in Figure 9 the output Q of each latch device (e.g. a latch unit 114 as in Figure 1) is connected to the input of the following latch with an explicit cycle delay, realized using wave-pipelined Josephson transmission lines. In some embodiments, the signals E and !E may be broadcast to all the latches in the device.

[0083] As shown in the example of Figure 9, latch device 902A is coupled to latch device 902B via a combinational logic cloud 904, which may implement the cycle delay mentioned above. The numbers represent the phase angles of the wave-pipelined Josephson transmission lines. As shown, this may be repeated for however many latches are desired to be in the shift register device 900. As noted above, Figure 9 depicts an example shift register device. The combinational logic cloud 904 may represent different types of combinational logic, and thus other configurations are possible in other embodiments.

[0084] In other words, Figure 9 depicts an embodiment of a shift register system. The shift register system includes a plurality of Josephson junction based data latch devices. Theplurality of Josephson junction based data latch devices are serially connected via a plurality of wave-pipelined Josephson transmission lines. Each Josephson junction based data latch device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. Each loop of the plurality of superconducting loops is electrically coupled. Each loop of the plurality of superconducting loops is configured to shift or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses. Each Josephson junction based data latch device also includes a readout line coupled to the plurality of superconducting loops. Each Josephson junction based data latch device also includes a plurality of data and control lines coupled to the plurality of superconducting loops. Each line is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops. The plurality of signals includes a data signal, an enable control signal, and a read control signal.

[0085] Figure 10 illustrates results 1000 of a simulation of an example three-stage enabled shift register (e.g. enabled shift register device 900 of Figure 9) using WRSpice software. Correct operation of the shift register may be verified from the state of each latch at a given time as indicated by a vertical column of numbers.

[0086] As described above, the read control signal may in some embodiments be the result of an OR operation between the data signal and a NOT (or inverted) enable control signal, as illustrated in Figure 1 with OR gate 110. An example is illustrated in Figure 11, showing an enable signal E and its counterpart inverted enable signal !E in graph 1100. However, the inverted signal may be configured to arrive one clock cycle before E goes to a value of one. This may be done to ensure proper data communication in the aforementioned circuits in the case where the OR gate is implemented. Example Methods

[0087] Figure 12 illustrates a method 1200, in accordance with example embodiments. The method 1200 includes a process for storing digital information in a Josephson junction based data latch device (e.g., data latch device 200 as illustrated and described in relation to Figure 2). The method 1200 may occur with any valid initial state (i.e., zero state or one state) of the superconducting loops of the data latch device.

[0088] The method 1200 includes, at block 1202, providing, to a plurality of superconducting loops (e.g., superconducting loops 202), a combination of a plurality of signals and single flux quantum (SFQ) pulses. Each superconducting loop comprises at least one Josephson junction (e.g., Josephson junctions 204a, 204b, and 204c). Each loop of theplurality of superconducting loops is electrically coupled. The plurality of signals includes a data signal, an enable control signal, and a read control signal. A plurality of data and control lines are coupled to the plurality of superconducting loops. Each line is configured to provide at least one of the plurality of signals to at least a portion of the plurality of superconducting loops.

[0089] The method 1200 includes, at block 1204, in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta (e.g., SFQ 220a and / or 220b) in one or more of the superconducting loops.

[0090] In some embodiments, the method 1200 may include transmitting, via a readout line coupled to the plurality of superconducting loops, an output signal.

[0091] In some embodiments, the plurality of superconducting loops are electrically coupled in a sequential arrangement, and each superconducting loop of the plurality of superconducting loops has one or two adjacent loops.

[0092] In some embodiments, the plurality of superconducting loops are configured to shift a magnetic flux quanta from an initial superconducting loop to an adjacent loop in response to a SFQ pulse applied to the initial superconducting loop based on the presence of magnetic flux quanta in the plurality of superconducting loops.

[0093] In some embodiments, a first and second magnetic flux quantum are stored in each of a third superconducting loop and a fourth superconducting loop.

[0094] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes receiving, via an control line coupled to a first and second superconducting loop, a transition edge of the enable control signal. In some embodiments, a transition edge may be a rising edge or a trailing edge. In some embodiments, a positive SFQ pulse may result in a rising edge, and in some embodiments a negative SFQ pulse may result in a trailing edge.

[0095] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes, in response to receiving the transition edge of the enable control signal, shifting the first magnetic flux quantum from the third superconducting loop to the first superconducting loop.

[0096] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes receiving, via an control line coupled to the third superconducting loop and a fourth superconducting loop, a transition edge of the read control signal.

[0097] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes, in response to receiving the transition edge of the read control signal, shifting the second magnetic flux quantum from the fourth superconducting loop to the third superconducting loop.

[0098] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes outputting a transition edge of an output signal to the readout line.

[0099] In some embodiments, a third and fourth magnetic flux quantum are stored in each of a second superconducting loop and a third superconducting loop. In some embodiments, the third and fourth magnetic flux quantum may be, but do not have to be, identical to the first and second magnetic flux quantum as resulting from some of the above- described method embodiments.

[0100] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes receiving, via an control line coupled to a first superconducting loop and the second superconducting loop, a transition edge of the data signal.

[0101] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes, in response to receiving the transition edge of the data signal, shifting the third magnetic flux quantum from the second superconducting loop to the first superconducting loop.

[0102] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes receiving, via an control line coupled to the second and the third superconducting loop, a transition edge of the enable control signal.

[0103] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes receiving, via an control line coupled to the third superconducting loop and a fourth superconducting loop, a transition edge of the read control signal.

[0104] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes, in response to receiving the transition edge of the read control signal, shifting the fourth magnetic flux quantum from the third superconducting loop to the fourth superconducting loop.

[0105] In some embodiments, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops includes outputting a transition edge of an output signal to the readout line.Enumerated Example Embodiments

[0106] Embodiments of the present disclosure may thus relate to one of the enumerated example embodiments (EEEs) listed below.

[0107] EEE 1 includes a Josephson junction based data latch device comprising: a plurality of superconducting loops, wherein each superconducting loop comprises at least one Josephson junction, wherein each loop of the plurality of superconducting loops is electrically coupled, and wherein the plurality of superconducting loops are configured to shift or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses; a readout line coupled to the plurality of superconducting loops; and a plurality of data and control lines coupled to the plurality of superconducting loops, wherein each line is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops, wherein the plurality of signals comprises: a data signal; an enable control signal; and a read control signal.

[0108] EEE 2 includes the Josephson junction based data latch device of EE1, wherein the data latch device is coupled to an AC current-bias source, and wherein each line of the plurality of data and control lines comprises: a Josephson transmission line; at least one inductor; and a resistor connected between the Josephson transmission line and a corresponding superconducting loop of the plurality of superconducting loops.

[0109] EEE 3 includes the Josephson junction based data latch device of either EEE 1 or EEE 2, wherein: the data signal is configured to be transmitted to a first and second loop of the plurality of superconducting loops; the enable control signal is configured to be transmitted to the second loop and a third loop of the plurality of superconducting loops; and the read control signal is configured to be transmitted to the third loop and a fourth loop of the plurality of superconducting loops.

[0110] EEE 4 includes the Josephson junction based data latch device of EEE 3, wherein the read control signal comprises the result of an OR operation between the data signal and a result of a NOT operation on the enable control signal.

[0111] EEE 5 includes the Josephson junction based data latch device of EEE 3, wherein a transition edge of the enable control signal is configured to arrive along a corresponding control line at a time prior to any other control signal of the plurality of signals involved in a single data latch operation.

[0112] EEE 6 includes the Josephson junction based data latch device of any of EEEs 1-5, wherein the plurality of superconducting loops is electrically coupled in a sequential arrangement, wherein each superconducting loop of the plurality of superconducting loops has one or two adjacent loops.

[0113] EEE 7 includes the Josephson junction based data latch device of EEE 6, wherein the plurality of superconducting loops are configured to shift a magnetic flux quanta from an initial superconducting loop to an adjacent loop in response to a SFQ pulse applied to the initial superconducting loop and based on the presence of magnetic flux quanta in the plurality of superconducting loops.

[0114] EEE 8 includes the Josephson junction based data latch device of EEE 6, wherein the magnetic flux quanta is shifted from an initial superconducting loop to an adjacent loop in a first direction along the sequential arrangement in response to a positive SFQ pulse polarity and based on the presence and orientation of magnetic flux quanta in the plurality of superconducting loops, and wherein the magnetic flux quanta is shifted from an initial superconducting loop to an adjacent loop in a second direction along the sequential arrangement in response to a negative SFQ pulse polarity and based on the presence and orientation of magnetic flux quanta in the plurality of superconducting loops.

[0115] EEE 9 includes the Josephson junction based data latch device of either EEE 7 or EEE 8, wherein: the data signal is configured to be transmitted to a first and second loop of the plurality of superconducting loops, and wherein the data signal is configured to shift a magnetic flux quantum from the first loop to the second loop and from the second loop to the first loop based on the presence of magnetic flux quanta in the plurality of superconducting loops; the enable control signal is configured to be transmitted to the second loop and a third loop of the plurality of superconducting loops, and wherein the enable control signal is configured to shift a magnetic flux quantum from the second loop to the third loop andfrom the third loop to the second loop based on the presence of magnetic flux quanta in the plurality of superconducting loops; and the read control signal is configured to be transmitted to the third and a fourth loop of the plurality of superconducting loops, and wherein the read control signal is configured to shift a magnetic flux quantum from the third loop to the fourth loop and from the fourth loop to the third loop based on the presence of magnetic flux quanta in the plurality of superconducting loops.

[0116] EEE 10 includes the Josephson junction based data latch device of any of EEEs 1-9, further comprising at least one magnetically coupled feed line, wherein the plurality of superconducting loops are further configured to provide an initial flux state in response to a two-step flux initialization process, wherein the two-step flux initialization process comprises: while cooling down the Josephson junction based data latch device, providing an initialization signal via the at least one magnetically coupled feed line; and upon reaching a superconducting critical temperature of the Josephson junction based data latch device, turning off the initialization signal such that an exact integral number of SFQ are stored in the plurality of superconducting loops.

[0117] EEE 11 includes a shift register system comprising: a plurality of Josephson junction based data latch devices, wherein the plurality of Josephson junction based data latch devices are serially connected via a plurality of wave-pipelined Josephson transmission lines, and wherein each device comprises: a plurality of superconducting loops, wherein each superconducting loop comprises at least one Josephson junction, wherein each loop of the plurality of superconducting loops is electrically coupled, and wherein each loop of the plurality of superconducting loops is configured to shift or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses; a readout line coupled to the plurality of superconducting loops; and a plurality of data and control lines coupled to the plurality of superconducting loops, wherein each line is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops, wherein the plurality of signals comprises: a data signal;an enable control signal; and a read control signal.

[0118] EEE 12 includes a method for storing digital information in a Josephson junction based data latch device, the method comprising: providing, to a plurality of superconducting loops, a combination of a plurality of signals and single flux quantum (SFQ) pulses, wherein each superconducting loop comprises at least one Josephson junction, wherein each loop of the plurality of superconducting loops is electrically coupled, wherein the plurality of signals comprises a data signal, an enable control signal, and a read control signal, wherein a plurality of data and control lines are coupled to the plurality of superconducting loops, wherein each line is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops; and in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops.

[0119] EEE 13 includes the method of EEE 12, wherein the plurality of superconducting loops is electrically coupled in a sequential arrangement, wherein each superconducting loop of the plurality of superconducting loops has one or two adjacent loops, and wherein the plurality of superconducting loops are configured to shift a magnetic flux quanta from an initial superconducting loop to an adjacent loop in response to a SFQ pulse applied to the initial superconducting loop based on the presence of magnetic flux quanta in the plurality of superconducting loops.

[0120] EEE 14 includes the method of EEE 13, wherein a first and second magnetic flux quantum are stored in each of a third superconducting loop and a fourth superconducting loop, and wherein in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops comprises: receiving, via an control line coupled to a second superconducting loop and the third superconducting loop, a transition edge of the enable control signal; in response to receiving the transition edge of the enable control signal, shifting the first magnetic flux quantum from the third superconducting loop to the second superconducting loop; receiving, via an control line coupled to the third superconducting loop and a fourth superconducting loop, a transition edge of the read control signal;in response to receiving the transition edge of the read control signal, shifting the second magnetic flux quantum from the fourth superconducting loop to the third superconducting loop; and outputting a transition edge of an output signal to a readout line.

[0121] EEE 15 includes the method of EEE 13, wherein a third and fourth magnetic flux quantum are stored in each of a second superconducting loop and a third superconducting loop, and wherein in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops comprises: receiving, via an control line coupled to a first superconducting loop and the second superconducting loop, a transition edge of the data signal; in response to receiving the transition edge of the data signal, shifting the third magnetic flux quantum from the second superconducting loop to the first superconducting loop; receiving, via an control line coupled to the second superconducting loop and the third superconducting loop, a transition edge of the enable control signal; receiving, via an control line coupled to the third superconducting loop and a fourth superconducting loop, a transition edge of the read control signal; in response to receiving the transition edge of the read control signal, shifting the fourth magnetic flux quantum from the third superconducting loop to the fourth superconducting loop; and outputting a transition edge of an output signal to a readout line.

[0122] In the following EEEs, the numbered magnetic flux quanta may be, but do not have to be, identical to the first and second (and / or third and fourth) magnetic flux quantum as resulting from some of the above-described method EEEs. For example, the seventh and eighth magnetic flux quantum may be identical to the first and second magnetic flux quantum, but they may also be newly-initialized or otherwise different magnetic flux quantum.

[0123] EEE 16 includes the method of any of EEEs 13-15, wherein a fifth and sixth magnetic flux quantum are stored in each of a first superconducting loop and a fourth superconducting loop, and wherein in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops comprises:receiving, via an control line coupled to a third superconducting loop and the fourth superconducting loop, a transition edge of the read control signal; in response to receiving the transition edge of the read control signal, shifting the sixth magnetic flux quantum from the fourth superconducting loop to the third superconducting loop; outputting a transition edge of an output signal to a readout line; receiving, via an control line coupled to a third superconducting loop and the fourth superconducting loop, a further transition edge of the read control signal; in response to receiving the further transition edge of the read control signal, shifting the sixth magnetic flux quantum from the third superconducting loop to the fourth superconducting loop; and outputting a further transition edge of the output signal to the readout line.

[0124] EEE 17 includes the method of any of EEEs 13-16, wherein a seventh and eighth magnetic flux quantum are stored in each of a second superconducting loop and a fourth superconducting loop, and wherein in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops comprises: receiving, via an control line coupled to the second superconducting loop and a third superconducting loop, a transition edge of the enable control signal; receiving, via an control line coupled to the second superconducting loop and a third superconducting loop, a further transition edge of the enable control signal; in response to receiving the further transition edge of the enable control signal, shifting the seventh magnetic flux quantum from the second superconducting loop to a third superconducting loop; receiving, via an control line coupled to the third superconducting loop and the fourth superconducting loop, a transition edge of the read control signal; and receiving, via an control line coupled to the third superconducting loop and the fourth superconducting loop, a further transition edge of the read control signal.

[0125] EEE 18 includes the method of any of EEEs 13-17, wherein a ninth and tenth magnetic flux quantum are stored in each of a third superconducting loop and a fourth superconducting loop, and wherein in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops comprises:receiving, via an control line coupled to the third superconducting loop and the fourth superconducting loop, a transition edge of the read control signal; receiving, via an control line coupled to a first superconducting loop and a second superconducting loop, a transition edge of the data signal; receiving, via an control line coupled to the third superconducting loop and the fourth superconducting loop, a further transition edge of the read control signal; and receiving, via an control line coupled to the first superconducting loop and the second superconducting loop, a further transition edge of the data signal.

[0126] EEE 19 includes the method of EEE 13, wherein: the data signal is configured to be transmitted to a first and second loop of the plurality of superconducting loops; the enable control signal is configured to be transmitted to the second loop and a third loop of the plurality of superconducting loops; and the read control signal is configured to be transmitted to the third loop and a fourth loop of the plurality of superconducting loops.

[0127] EEE 20 includes the method of EEE 13, wherein the read control signal comprises the result of an OR operation between the data signal and a result of a NOT operation on the enable control signal.

[0128] EEE 21 includes the method of EEE 13, wherein a transition edge of the enable control signal is configured to arrive along a corresponding control line at a time prior to any other control signal of the plurality of signals involved in a single data latch operation.

[0129] EEE 22 includes the method of EEE 12, further comprising transmitting, via a readout line coupled to the plurality of superconducting loops, an output signal. Conclusion

[0130] The present disclosure is not to be limited in terms of the particular embodiments described in this application, which are intended as illustrations of various aspects. Many modifications and variations can be made without departing from its scope, as will be apparent to those skilled in the art. Functionally equivalent methods and apparatuses within the scope of the disclosure, in addition to those described herein, will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations are intended to fall within the scope of the appended claims.

[0131] The above detailed description describes various features and operations of the disclosed systems, devices, and methods with reference to the accompanying figures. The example embodiments described herein and in the figures are not meant to be limiting. Otherembodiments can be utilized, and other changes can be made, without departing from the scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations.

[0132] With respect to any or all of the message flow diagrams, scenarios, and flow charts in the figures and as discussed herein, each step, block, operation, and / or communication can represent a processing of information and / or a transmission of information in accordance with example embodiments. Alternative embodiments are included within the scope of these example embodiments. In these alternative embodiments, for example, operations described as method steps, blocks, transmissions, communications, requests, responses, and / or messages can be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved. Further, more or fewer blocks and / or operations can be used with any of the message flow diagrams, scenarios, and flow charts discussed herein, and these message flow diagrams, scenarios, and flow charts can be combined with one another, in part or in whole.

[0133] A step, block, or operation that represents a processing of information can correspond to circuitry that can be configured to perform the specific logical functions of a herein-described method or technique. Alternatively or additionally, a step or block that represents a processing of information can correspond to a module, a segment, or a portion of program code (including related data). The program code can include one or more instructions executable by a processor for implementing specific logical operations or actions in the method or technique. The program code and / or related data can be stored on any type of computer-readable medium such as a storage device including RAM, a disk drive, a solid state drive, or another storage medium.

[0134] The computer-readable medium can also include non-transitory computer- readable media such as computer-readable media that store data for short periods of time like register memory and processor cache. The computer-readable media can further include non- transitory computer-readable media that store program code and / or data for longer periods of time. Thus, the computer-readable media may include secondary or persistent long term storage, like ROM, optical or magnetic disks, solid state drives, compact-disc read-only memory (CD-ROM), for example. The computer-readable media can also be any othervolatile or non-volatile storage systems. A computer-readable medium can be considered a computer-readable storage medium, for example, or a tangible storage device.

[0135] Moreover, a step, block, or operation that represents one or more information transmissions can correspond to information transmissions between software and / or hardware modules in the same physical device. However, other information transmissions can be between software modules and / or hardware modules in different physical devices.

[0136] The particular arrangements shown in the figures should not be viewed as limiting. It should be understood that other embodiments can include more or less of each element shown in a given figure. Further, some of the illustrated elements can be combined or omitted. Yet further, an example embodiment can include elements that are not illustrated in the figures.

[0137] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purpose of illustration and are not intended to be limiting, with the true scope being indicated by the following claims.

Claims

CLAIMS What is claimed is:

1. A Josephson junction based data latch device comprising: a plurality of superconducting loops, wherein each superconducting loop comprises at least one Josephson junction, wherein each loop of the plurality of superconducting loops is electrically coupled, and wherein the plurality of superconducting loops are configured to shift or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses; a readout line coupled to the plurality of superconducting loops; and a plurality of data and control lines coupled to the plurality of superconducting loops, wherein each line is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops, wherein the plurality of signals comprises: a data signal; an enable control signal; and a read control signal.

2. The Josephson junction based data latch device of claim 1, wherein the data latch device is coupled to an AC current-bias source, and wherein each line of the plurality of data and control lines comprises: a Josephson transmission line; at least one inductor; and a resistor connected between the Josephson transmission line and a corresponding superconducting loop of the plurality of superconducting loops.

3. The Josephson junction based data latch device of claim 1, wherein the plurality of superconducting loops is electrically coupled in a sequential arrangement, wherein each superconducting loop of the plurality of superconducting loops has one or two adjacent loops.

4. The Josephson junction based data latch device of claim 3, wherein the magnetic flux quanta is shifted from an initial superconducting loop to an adjacent loop in a first direction along the sequential arrangement in response to a positive SFQ pulse polarity and based on the presence and orientation of magnetic flux quanta in the plurality ofsuperconducting loops, and wherein the magnetic flux quanta is shifted from an initial superconducting loop to an adjacent loop in a second direction along the sequential arrangement in response to a negative SFQ pulse polarity and based on the presence and orientation of magnetic flux quanta in the plurality of superconducting loops.

5. The Josephson junction based data latch device of claim 3, wherein: the data signal is configured to be transmitted to a first and second loop of the plurality of superconducting loops, and wherein the data signal is configured to shift a magnetic flux quantum from the first loop to the second loop and from the second loop to the first loop based on the presence of magnetic flux quanta in the plurality of superconducting loops; the enable control signal is configured to be transmitted to the second loop and a third loop of the plurality of superconducting loops, and wherein the enable control signal is configured to shift a magnetic flux quantum from the second loop to the third loop and from the third loop to the second loop based on the presence of magnetic flux quanta in the plurality of superconducting loops; and the read control signal is configured to be transmitted to the third and a fourth loop of the plurality of superconducting loops, and wherein the read control signal is configured to shift a magnetic flux quantum from the third loop to the fourth loop and from the fourth loop to the third loop based on the presence of magnetic flux quanta in the plurality of superconducting loops.

6. The Josephson junction based data latch device of claim 1, further comprising at least one magnetically coupled feed line, wherein the plurality of superconducting loops are further configured to provide an initial flux state in response to a two-step flux initialization process, wherein the two-step flux initialization process comprises: while cooling down the Josephson junction based data latch device, providing an initialization signal via the at least one magnetically coupled feed line; and upon reaching a superconducting critical temperature of the Josephson junction based data latch device, turning off the initialization signal such that an exact integral number of SFQ are stored in the plurality of superconducting loops.

7. A shift register system comprising: a plurality of Josephson junction based data latch devices, wherein the plurality of Josephson junction based data latch devices are serially connected via a plurality of wave- pipelined Josephson transmission lines, and wherein each device comprises: a plurality of superconducting loops, wherein each superconducting loop comprises at least one Josephson junction, wherein each loop of the plurality of superconducting loops is electrically coupled, and wherein each loop of the plurality of superconducting loops is configured to shift or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of signals and single flux quantum (SFQ) pulses; a readout line coupled to the plurality of superconducting loops; and a plurality of data and control lines coupled to the plurality of superconducting loops, wherein each line is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops, wherein the plurality of signals comprises: a data signal; an enable control signal; and a read control signal.

8. A method for storing digital information in a Josephson junction based data latch device, the method comprising: providing, to a plurality of superconducting loops, a combination of a plurality of signals and single flux quantum (SFQ) pulses, wherein each superconducting loop comprises at least one Josephson junction, wherein each loop of the plurality of superconducting loops is electrically coupled, wherein the plurality of signals comprises a data signal, an enable control signal, and a read control signal, wherein a plurality of data and control lines are coupled to the plurality of superconducting loops, wherein each line is configured to provide at least one of a plurality of signals to at least a portion of the plurality of superconducting loops; and in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops.

9. The method of claim 8, further comprising: transmitting, via a readout line coupled to the plurality of superconducting loops, an output signal.

10. The method of claim 8, wherein the plurality of superconducting loops is electrically coupled in a sequential arrangement, wherein each superconducting loop of the plurality of superconducting loops has one or two adjacent loops, and wherein the plurality of superconducting loops are configured to shift a magnetic flux quanta from an initial superconducting loop to an adjacent loop in response to a SFQ pulse applied to the initial superconducting loop and based on the presence of magnetic flux quanta in the plurality of superconducting loops.

11. The method of claim 10, wherein a first and second magnetic flux quantum are stored in each of a third superconducting loop and a fourth superconducting loop, and wherein in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops comprises: receiving, via an control line coupled to a second superconducting loop and the third superconducting loop, a transition edge of the enable control signal; in response to receiving the transition edge of the enable control signal, shifting the first magnetic flux quantum from the third superconducting loop to the second superconducting loop; receiving, via an control line coupled to the third superconducting loop and a fourth superconducting loop, a transition edge of the read control signal; in response to receiving the transition edge of the read control signal, shifting the second magnetic flux quantum from the fourth superconducting loop to the third superconducting loop; and outputting a transition edge of an output signal to a readout line.

12. The method of claim 10, wherein a third and fourth magnetic flux quantum are stored in each of a second superconducting loop and a third superconducting loop, and wherein in response to the combination of signals and SFQ pulses, shifting or annihilating magnetic flux quanta in one or more of the superconducting loops comprises: receiving, via an control line coupled to a first superconducting loop and the second superconducting loop, a transition edge of the data signal;in response to receiving the transition edge of the data signal, shifting the third magnetic flux quantum from the second superconducting loop to the first superconducting loop; receiving, via an control line coupled to the second superconducting loop and the third superconducting loop, a transition edge of the enable control signal; receiving, via an control line coupled to the third superconducting loop and a fourth superconducting loop, a transition edge of the read control signal; in response to receiving the transition edge of the read control signal, shifting the fourth magnetic flux quantum from the third superconducting loop to the fourth superconducting loop; and outputting a transition edge of an output signal to a readout line.

13. The method of claim 8, wherein: the data signal is configured to be transmitted to a first and second loop of the plurality of superconducting loops; the enable control signal is configured to be transmitted to the second loop and a third loop of the plurality of superconducting loops; and the read control signal is configured to be transmitted to the third loop and a fourth loop of the plurality of superconducting loops.

14. The method of claim 8, wherein the read control signal comprises the result of an OR operation between the data signal and a result of a NOT operation on the enable control signal.

15. The method of claim 8, wherein a transition edge of the enable control signal is configured to arrive along a corresponding control line at a time prior to any other control signal of the plurality of signals involved in a single data latch operation.

Images