A selective ETCH stop layer for capacitor etch

Abstract

A method for etching features in a stack is provided. A stack has one or more layers of a silicon oxide containing layer and one or more layers of a silicon nitride containing layer above a selective etch stop layer, wherein the selective etch stop layer is above a substrate. At least one feature is etched in the one or more layers of a silicon oxide containing layer and one or more layers of a silicon nitride containing layer with a cryogenic dry etch to the selective etch stop layer, wherein the cryogenic dry etch provides a substrate support maintained at a temperature of no more than 0º C. The selective etch stop layer is opened.

Description

A SELECTIVE ETCH STOP LAYER FOR CAPACITOR ETCH CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63 / 698,262, filed September 24, 2024, which is incorporated herein by reference for all purposes.BACKGROUND

[0002] The disclosure relates to a method of forming semiconductor devices on a semiconductor wafer.

[0003] In forming semiconductor devices, etch layers may be etched to form memory holes or lines, or other semiconductor features. Some semiconductor devices may be formed by etching a single stack of silicon dioxide also known as silicon oxide (SiCb), for example, to form a capacitor in dynamic access random memory (DRAM). Other semiconductor devices may be formed by etching stacks of bilayers of alternating silicon dioxide (oxide) and silicon nitride (nitride) (ONON), or alternating silicon dioxide and polysilicon (OPOP). Other stacks of alternating layers may be etched. Some of the stacks of alternating layers may have one of the layers of the alternating layers that is silicon oxide. Some alternating layers may be alternating trilayers. Such stacks may be used in memory applications and three dimensional “not and” gates (3D NAND). These stacks tend to require a relatively high aspect ratio (HAR) etching of the dielectrics. For high aspect ratio etches, examples of desired etch characteristics are high etch selectivity to the mask (such as an amorphous carbon mask), low sidewall etching with straight profiles, and high etch rate at the etch front. Some high aspect ratio etches result in tapered features that are much wider at the top than the bottom. Such features may increase device failure or limit device density, device performance, and device depth.

[0004] The background description provided here is for the purpose of generally presenting the context of the disclosure. Information described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0005] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method for etching features in a stack is provided. A stack has one or more layers of a silicon oxide containing layer and one or more layers of a silicon nitride containing layer above a selective etch stop layer, wherein the selective etch stop layer is above a substrate. At least one feature is etched in the one or more layers of a silicon oxide containing layer and one or more layers of a silicon nitride containing layer with a cryogenic dry etch to the selective etch stop layer, wherein the cryogenic dry etch provides a substrate support maintained at a temperature of no more than0° C. The selective etch stop layer is opened.

[0006] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0008] FIG. 1 is a high level flow chart of processes used in some embodiments.

[0009] FIGS. 2A-I are schematic cross-sectional views of a stack processed according to some embodiments.

[0010] FIG. 3 is a schematic cross-sectional view of a stack processed without a selective etch stop.

[0011] FIGS. 4A-C are schematic cross-sectional views of a stack processed according to some embodiments.

[0012] FIG. 5 is a schematic view of an etch chamber that may be used in some embodiments.

[0013] FIG. 6 is a schematic view of a computer system that may be used in practicing some embodiments.

[0014] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and / or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.

[0016] Dry development of high aspect ratio contacts requires strict control of the tapering angle of the sidewall. Various methods try to limit lateral critical dimension (CD) differences between the top and bottom parts of the etched structures. With the recent development ofDRAM memory having smaller-sized higher aspect ratio features. In case the profile (difference between the top and bottom CDs) increases, subsequent steps of device manufacturing will be atrisk that will impact device performance. In the current technology, reactive ion etching of high aspect ratio structures relies on sidewall deposition to protect against CD lateral erosion. A delicate balance between etching and sidewall deposition is especially difficult to maintain for high aspect ratio features. As a result, high aspect ratio dry development is limited to thinner structures and requires significant complex development to enable a thick stack to be etched.

[0017] Embodiments described herein provide an in-situ process for providing high aspect ratio features etched in a stack in order to provide structures, such as capacitors. To facilitate understanding, FIG. 1 is a high level flow chart that may be used in some embodiments. A stack is provided (step 104). In some embodiments, the stack is placed on a substrate support in a process chamber.

[0018] FIG. 2A is a schematic cross-sectional view of a stack 204 that may be processed in some embodiments. The figures are not to scale in order to better illustrate various features. In some embodiments, the stack 204 comprises a substrate 208 with at least one electrical contact 210. In some embodiments, the electrical contact 210 may be a metal contact. In some embodiments, the substrate 208 comprises silicon oxide (SiC ). In some embodiments, the electrical contact 210 is an electrically conductive metal, such as tungsten. An etch stop layer 211 is over the substrate 208. A first mold layer 212 is above the etch stop layer 211. In some embodiments, the first mold layer 212 comprises SiCh. A first hold layer 216 is above the first mold layer 212. In some embodiments, the first hold layer 216 comprises silicon nitride (SiN). In some embodiments, a second mold layer 220 is above the first hold layer 216. In some embodiments, the second mold layer 220 comprises SiCK In some embodiments, a second hold layer 224 is above the second mold layer 220. In some embodiments, the second hold layer 224 comprises SiN. In some embodiments, a third mold layer 228 is above the second hold layer 224. In some embodiments, the third mold layer 228 comprises S1O2. In some embodiments, a third hold layer 232 is above the third mold layer 228. In some embodiments, the third hold layer 232 comprises SiN. A patterned mask 236 is above the third hold layer 232. The patterned mask 236 may have one or more patterned features 240. In various embodiments, one or more additional layers may be between various layers.

[0019] The stack 204 is etched to the etch stop layer 211 (step 108). In some embodiments, the etch is a cryogenic dry etch. In some embodiments, the cryogenic dry etch cools a substrate support that supports the stack to a temperature of no more than 0° C. An etch gas is provided. In some embodiments, the etch gas may comprise a fluorine source and a hydrofluorocarbon. In some embodiments, the fluorine source is hydrogen fluoride (HF) gas. In some embodiments, the hydrofluorocarbon comprises at least one of difluoromethane (CH2F2) and fluoromethane(CH F). In some embodiments, the etch gas is formed into a plasma. In some embodiments, an excitation power is provided to transform the etch gas into the plasma. The excitation power may be provided at various frequencies. In various embodiments, the excitation power is provided at frequencies of at least one of 13.56 megahertz (MHz), 60 MHz, 27 MHz, 2 MHz, 1 MHz, and 400 kilohertz (kHz). The excitation power may be sinusoidal (radio frequency (RF)) or non-sinusoidal. In some embodiments, the excitation power is pulsed. In some embodiments, the excitation power is continuous. In some embodiments, a voltage is applied to accelerate ions from the plasma to the stack and provide a more directional etch. The ions etch the stack 204 and etch some of the mask 236 to the etch stop layer 211.

[0020] FIG. 2B is a schematic cross-sectional view of a stack 204 after the stack 204 has been etched to the etch stop layer forming etch features 244. FIG. 2C is an enlarged view of region IIC shown in FIG. 2B. In this embodiment, the etch stop layer comprises a first etch stop layer 211a and a second etch stop layer 211b. In this embodiment, the first etch stop layer 211a is a selective etch stop. In the specification and claims, the selective etch stop is an etch stop that allows for a selective etch of silicon oxide and silicon nitride with respect to the selective etch stop at an etch selectivity ratio of greater than 5:1. In some embodiments, silicon oxide and silicon nitride may be selectively etched with respect to the selective etch stop at a ratio of greater than 10:1. In some embodiments, the selective etch stop is a metal containing etch stop. In some embodiments, the metal containing etch stop comprises at least one of tungsten (W), titanium (Ti), and aluminum, such as aluminum oxide (AI2O3). In some embodiments, the selective etch stop comprises silicon carbide (SiC). In some embodiments, the second etch stop layer 21 lb is a silicon nitride containing layer, such as at least one of silicon nitride (SiN), silicon carbonitride, (SiCN), and silicon boron nitride (SiBN). The etch highly selectively etches the stack with respect to the first etch stop layer 211a.

[0021] The first etch stop layer 211a is opened (step 112). In some embodiments, the first etch stop layer is opened (step 112) after the etching of the stack to the etch stop (step 108) is completed. In some embodiments, the opening of the first etch stop layer 21 la comprises at least one of a wet etch and a dry etch. FIG. 2D is a schematic cross-sectional view of the stack 204 after the first etch stop layer 21 la has been opened.

[0022] The second etch stop layer 211b is opened (step 116). The opening of the second etch stop layer 211b may be a wet etch or a soft dry etch. If the stack does not have a second etch stop layer 21 lb, then the process does not have an opening of the second etch stop layer (step 116). FIG. 2E is a schematic cross-sectional view of the stack 204 after the second etch stoplayer 211b has been opened. In some embodiments, the opening of the second etch stop layer 211b etches some of the SiO substrate 208, as shown.

[0023] The features are filled (step 120). In some embodiments, the features 244 are at least partially filled with a ceramic material (e.g., TiN) that is to hold the shape for the future device. In some embodiments, the filler may be a single material to form unitary capacitor electrodes. In some embodiments, two or more layers of materials may fill the features forming more complex combinations of dielectric sleeves around an electrically conductive capacitor electrode. FIG. 2F is a schematic cross-sectional view of the stack 204 after the features 244 (shown in FIG. 2E) have been filled with an electrically conductive material to form capacitor structures 248.

[0024] In some embodiments, the first etch stop layer 211a is exposed (step 124). In some embodiments, the first mold layer 212, the second mold layer 220, and the third mold layer 228 are removed in order to expose the first etch stop layer 211a. In some embodiments, the exposing the first etch stop layer 211a selectively etches silicon oxide with respect to silicon nitride. In some embodiments, a wet etch is used. In some embodiments, a dry etch at non- cryogenic temperatures is used. FIG. 2G is a schematic cross-sectional view of the stack 204 after the first mold layer 212, the second mold layer 220, and the third mold layer, shown in FIG. 2B are removed in order to expose the first etch stop layer 211a.

[0025] In some embodiments, the exposed first etch stop layer 21 la is removed (step 128). In some embodiments, a wet etch is used to remove the exposed first etch stop layer 211a. If the first etch stop layer 211a is electrically conductive, the removal of the exposed first etch stop layer 211a removes an electrical conductor between the capacitor structures 248. FIG. 2H is a schematic cross-sectional view of the stack after the exposed first etch stop layer 211a, shown in FIG. 2F, is removed.

[0026] In some embodiments, the second etch stop layer 211b is removed via selective etch. In some embodiments, the second etch stop layer 211b is not removed or only partially removed.

[0027] Additional processes may be performed on the stack 204, such as the removal of the mask 236. FIG. 21 is a schematic cross-sectional view of the stack after some of the additional processes, such as removal of the mask 236 (shown in FIG. 2B), are completed.

[0028] A feature of using a cryogenic dry etch to etch the stack 204 is that a cryogenic dry etch is able to nonselectively etch silicon oxide and silicon nitride layers, so that the SiO2 and SiN layers are etched at a fast rate. However, if a silicon nitride containing layer is used as an etch stop, such a cryogenic dry etch of the first mold layer 212 would punch through a silicon nitride containing etch stop and then etch into the silicon oxide substrate 208 adjacent to the electrical contact 210 causing damage. FIG. 3 is an enlarged view of part of a stack 304 withonly a SiN etch stop layer 311 and without a selective etch layer. A feature 344 is etched into the stack through a first mold layer 312, and the SiN etch stop layer 311 has been punched through causing an irregular etch of the substrate 308 adjacent to a contact 310. The feature formed by the punch through does not provide a contact on the side of contact 310. Providing a first etch stop layer 21 la of a selective etch material prevents the cryogenic dry etch of the stack from punching through the first etch stop layer 211a, protecting the substrate 208. The first etch stop layer 211a may be opened with a wet etch that will not damage or etch the substrate 208. This is important for devices that rely on precise connectivity between etched mold layers. Experiments have found that a first etch stop layer 21 la of tungsten was not significantly etched by cryogenic etching of SiCF and SiN layers to form the features.

[0029] If a second etch stop layer 211b is provided, then the second etch stop layer 211b may be used to protect the electrical contact 210 when opening the first etch stop layer 21 lb. A soft etch may be used to open the second etch stop layer 211b. Since the second etch stop layer 21 lb is thin, the opening may be controlled to provide a more controlled etch of the SiCh substrate 208.

[0030] FIG. 4A is a cross-sectional enlarged view of part of a stack 404 with a first mold layer of SiC and a single selective etch stop layer 411 over a substrate 408 with a contact 410 after a feature 444 has been etched into the stack 404 used in some embodiments where only a selective etch stop layer 211 is provided. In these embodiments, the stack 404 does not have a second etch stop layer. In some embodiments, the selective etch stop 411 comprises at least one of SiC and metal.

[0031] FIG. 4B is a cross-sectional enlarged view of the stack 404 after the etch stop layer 411 has been opened. By making the etch stop layer 411 from the same material as the contact 410, the etch stop layer 411 and the contact 410 may be uniformly etched as shown. In some embodiments, the etch stop layer 411 is a different material than the contact 410 but has similar etch properties when the etch stop opening process is provided so that the etch stop layer 411 and the contact 410 are uniformly etched.

[0032] FIG. 4C is a cross-sectional enlarged view of the stack after the features have been filled to form an electrode 448. The electrode 448 has a good contact with the top and sides of the contact 410.

[0033] Since a second etch stop layer is not provided, one less deposition process and one less opening process are needed. As a result, the process is simplified, and throughput may be increased.

[0034] Some embodiments provide an etch depth of greater than 1 micron. In some embodiments, the etch depth is in the range of 0.5 microns to 1.3 microns.

[0035] FIG. 5 is a schematic view of an etch reactor system 500 that may be used to etch the features in some embodiments. In some embodiments, an etch reactor system 500 comprises a gas distribution plate 506 providing a gas inlet and an electrostatic chuck (ESC) 508, within an etch (or process) chamber 509, enclosed by a chamber wall 552. Within the etch chamber 509, a stack 504 is positioned over the ESC 508 that is used as a substrate support. The ESC 508 may provide a bias from the ESC source 548. An etch gas source 510 is connected to the etch chamber 509 through the gas distribution plate 506. An ESC temperature controller 550 is connected to the ESC 508. A radio frequency (RF) source 530 provides RF power to a lower electrode and / or an upper electrode, which in this embodiment are the ESC 508 and the gas distribution plate 506, respectively. In some embodiments, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally, 2 MHz, and 27 MHz power sources make up the RF source 530 and the ESC source 548. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generators may be in separate RF sources or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. Other arrangements of RF sources and electrodes may be used in other embodiments. A controller 535 is controllably connected to the RF source 530, the ESC source 548, an exhaust pump 520, and the etch gas source 510. An example of such an etch chamber is the Vantex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0036] FIG. 6 is a high level block diagram showing a computer system 600, which is suitable for implementing the controller 535 used in embodiments. The computer system 600 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 600 includes one or more processors 602 and further can include an electronic display device 604 (for displaying graphics, text, and other data), a main memory 606 (e.g., random access memory (RAM)), storage device 608 (e.g., hard disk drive), removable storage device 610 (e.g., optical disk drive), user interface devices 612 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 614 (e.g., wireless network interface). The communications interface 614 allows software and data to be transferred between the computer system 600 and external devices via a link. The system may also include acommunications infrastructure 616 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices / modules are connected.

[0037] Information transferred via communications interface 614 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 614, via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and / or other communications channels. With such a communications interface 614, it is contemplated that the one or more processors 602 might receive information from a network or might output information to the network in the course of performing the abovedescribed method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.

[0038] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that is executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

[0039] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, that fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C. Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMSWhat is claimed is:

1. A method for etching features in a stack, comprising: a) providing a stack with one or more layers of a silicon oxide containing layer and one or more layers of a silicon nitride containing layer above a selective etch stop layer, wherein the selective etch stop layer is above a substrate; b) etching at least one feature in the one or more layers of a silicon oxide containing layer and one or more layers of a silicon nitride containing layer with a cryogenic dry etch to the selective etch stop layer, wherein the cryogenic dry etch provides a substrate support maintained at a temperature of no more than 0° C; and c) opening the selective etch stop layer.

2. The method, as recited in claim 1, further comprising; after c, d) filling the features; e) removing some of the at least one of a silicon oxide containing layers or silicon nitride containing layers to expose at least some of the selective etch stop layer; and f) removing the exposed selective etch stop layer.

3. The method, as recited in claim 2, wherein the filling the features fills at least partially fills the features with an electrically conductive material.

4. The method, as recited in claim 3, wherein the electrically conductive material is electrically conductive metal.

5. The method, as recited in claim 2, wherein the stack further comprises a silicon nitride containing etch stop layer under the selective etch stop layer.

6. The method, as recited in claim 5, further comprising: opening the silicon nitride containing etch stop layer after step c and before step d; and removing at least some of the silicon nitride containing etch stop layer after step f.

7. The method, as recited in claim 5, wherein the silicon nitride containing layer comprises at least one of SiN, SiCN, and SiBN.

8. The method, as recited in claim 1, wherein the selective etch stop layer comprises at least one of SiC, W, Ti, and aluminum.

9. The method, as recited in claim 1, wherein the substrate comprises at least one of a silicon oxide containing layer and a silicon nitride containing layer.

10. The method, as recited in claim 9, wherein the substrate further comprises a metal contact.

11. The method, as recited in claim 1, wherein the cryogenic dry etch selectively etches the one or more layers of a silicon oxide containing layer and one or more layers of a silicon nitride containing layer with respect to the selective etch stop layer at a ratio of at least 5:1.

12. The method, as recited in claim 1, wherein the cryogenic dry etch selectively etches the one or more layers of a silicon oxide containing layer and one or more layers of a silicon nitride containing layer with respect to the selective etch stop layer at a ratio of at least 10: 1.

13. The method, as recited in claim 1, wherein step c) opening the selective etch stop layer is provided after step b) etching at least one feature is completed.

14. The method, as recited in claim 1, wherein the stack further comprises a silicon nitride containing etch stop layer under the selective etch stop layer.

15. The method, as recited in claim 14, further comprising opening the silicon nitride containing etch stop layer after step c.

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