Semiconductor optical device

Abstract

This semiconductor optical device comprises a first region (151), a second region (152), a third region (153), a fourth region (154), and a fifth region (155), which are arranged in series in a waveguide direction. The first region (151) comprises a substrate (101), a first low refractive index layer (102) formed on the substrate (101), and an active layer (104) formed on the first low refractive index layer (102). A first semiconductor layer (106) and a second semiconductor layer (107) are formed so as to sandwich the active layer (104). The second region (152), the third region (153), and the fourth region (154) are provided with a compound core (112) configured from a compound semiconductor having a larger band gap than the active layer (104), with the compound core (112) being provided on the same plane as the active layer (104).

Description

Semiconductor optical device

[0001] The present invention relates to a semiconductor optical device.

[0002] In recent years, with the increase in communication capacity in a structural data center or the like, research on small and highly functional optical integrated circuits has been actively conducted. In miniaturizing an optical integrated circuit, silicon photonics technology, which fabricates a fine wire waveguide and a passive device by microfabrication of silicon (Si), is widely used. In the application of silicon photonics, there are advantages such as the material itself being inexpensive and the ability to utilize the microfabrication technology cultivated in the field of electronics technology. On the other hand, since silicon is an indirect transition material, a highly efficient light-emitting device has not been realized so far. Therefore, heterogeneous material integration with a direct transition material capable of realizing highly efficient light emission is required.

[0003] As a device integrating the above-mentioned heterogeneous materials, a hybrid device has been developed in which a III-V compound semiconductor, which is a direct transition material, is formed on an SOI (Si-on-insulator) substrate on which an Si waveguide or the like is formed, and a light-emitting device and an Si photonics device are integrated (see Non-Patent Document 1). In this technology, the light-emitting device typically uses an active layer composed of a compound semiconductor such as InGaAsP or InGaAlAs as a light-emitting layer.

[0004] Further, by disposing InP layers above and below the active layer, vertical optical confinement is realized due to the difference in their refractive indices. Further, by doping the InP layers above and below the active layer with n-type and p-type, respectively, carriers are injected into the active layer from the vertical direction, enabling current driving (vertical pin structure). In the vertical pin structure, in order to separate the electrode disposed above the active layer from the active layer, a thick p-type layer is formed above the active layer so that the light to be guided by the active layer is not affected by the electrode.

[0005] Incidentally, vertical PIN structures are also widely used in monolithic InP devices on InP substrates. In such monolithic devices, by placing layers of semiconductors with a larger band gap than the active layer (such as InP, InGaAsP, or InGaAlAs with a different composition from the active layer) on either side of the active layer, an embedded heterostructure that confines light in the left-right direction can be created. In this configuration, for example, by making the semiconductor layers on either side of the active layer semi-insulating, a structure with low current leakage can be created (see Non-Patent Literature 1).

[0006] Furthermore, by placing semiconductor layers with a larger band gap than the active layer (such as InP, InGaAsP, or InGaAlAs, which have different compositions from the active layer) before and after the active layer (in the direction of the waveguide), it can also be used as a waveguide with less light absorption relative to the oscillation wavelength.

[0007] To fabricate such planar heterostructures relative to the active layer, a crystal regrowth technique is used, in which a stacked structure is formed on an InP substrate by crystal growth, a portion of the stacked structure is removed by selective etching, and another semiconductor is newly grown.

[0008] On the other hand, when fabricating vertical PIN structures by hybrid integration, it is difficult to fabricate such planar heterostructures. This is because when Si and InP-based semiconductors are hybridized and then exposed to high temperatures, thermal stress is generated due to the differences in their physical properties, causing crystal defects in the InP-based semiconductor. Therefore, crystal growth (typical process temperature: 600°C), which is a high-temperature process, is generally not performed after hybrid integration.

[0009] One possible solution to the aforementioned problems in hybrid integration is to perform hybrid integration after regrowth on an InP substrate. However, this method requires micron-scale waveguide structures to be formed on both the InP and Si substrates before integration, thus necessitating precise positioning technology. For this reason, in hybrid integrated light-emitting devices, planar heterostructures are generally not employed on the III-V compound semiconductor side; instead, the device structure is fabricated exclusively by heterostructures in the stacking direction and etching.

[0010] Due to these structural limitations, hybrid devices with a typical vertical PIN structure face challenges in the process of converting modes from the active layer to the Si waveguide. Tapered structures are widely used for mode conversion from a portion of a light-emitting device made of III-V semiconductors to the Si waveguide. According to the structure described in Non-Patent Document 1, light generated from the active layer is coupled to the Si waveguide via a tapered structure fabricated by processing the same stacked structure as the active layer.

[0011] However, if the same material as the active layer is used in the waveguide region, light absorption is unavoidable unless carriers are injected, and energy efficiency cannot be increased. Furthermore, in the tapered region, the p-type InP layer above the active layer is removed, so the structure is not suitable for carrier injection. Even if one were to retain the p-type semiconductor layer above the tapered region, the thickness of the InP-based semiconductor layer is typically around 2 μm, and the aspect ratio is too high for the tapered tip, which is typically less than 100 nm wide, making processing itself difficult.

[0012] T. Kikuchi et al., "III-V gain region / Si waveguide hybrid lasers with InP-based two-storied ridge structure by direct bonding technology", Japanese Journal of Applied Physics, vol. 61, no. 5, 052002, 2022.

[0013] As described above, in conventional technology, when mode conversion is performed to a Si waveguide in an optical semiconductor, there is a waveguide region made of the same material as the active layer, and due to the resulting optical loss, it is not easy to improve energy efficiency.

[0014] This invention was made to solve the above-mentioned problems and aims to improve the energy efficiency when performing mode conversion of optical semiconductors to Si waveguides.

[0015] The semiconductor optical device according to the present invention comprises a first region, a second region, a third region, a fourth region, and a fifth region formed continuously in the waveguide direction, and the entirety of the first region, the second region, the third region, the fourth region, and the fifth region comprises a low refractive index layer formed on a substrate, the first region comprises an active layer formed on the low refractive index layer and a cap layer formed on the active layer with a larger band gap than the active layer, and the second region, the third region, and the fourth region comprises a compound core formed on the substrate continuously with respect to the active layer and the cap layer, with a larger band gap than the active layer In the first, second, third, and fourth regions, a first semiconductor layer and a second semiconductor layer are formed on the substrate so as to sandwich the active layer and the cap layer, and have a band gap larger than that of the active layer. In the first, second, and third regions, a rib portion is formed above the cap layer and the compound core, along the active layer and the compound core, and has a band gap larger than that of the active layer. In the third, fourth, and fifth regions, a Si-based core is embedded in the low refractive index layer, and in the third and fourth regions, a Si-based core is formed along the active layer and the compound core.

[0016] As described above, the present invention makes it possible to improve the energy efficiency when performing mode conversion of an optical semiconductor to a Si waveguide.

[0017] Figure 1A is a cross-sectional view showing the configuration of a semiconductor optical device according to Embodiment 1. Figure 1B is a plan view showing the configuration of a semiconductor optical device according to Embodiment 1. Figure 2A is a cross-sectional view showing a partial configuration of a semiconductor optical device according to Embodiment 1. Figure 2B is a cross-sectional view showing a partial configuration of a semiconductor optical device according to Embodiment 1. Figure 2C is a cross-sectional view showing a partial configuration of a semiconductor optical device according to Embodiment 1. Figure 2D is a cross-sectional view showing a partial configuration of a semiconductor optical device according to Embodiment 1. Figure 2E is a cross-sectional view showing a partial configuration of a semiconductor optical device according to Embodiment 1. Figure 3A is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3B is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3C is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3D is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3E is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3F is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3G is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3H is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3I is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3J is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3K is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention.Figure 3L is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3M is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3N is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3O is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3P is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3Q is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 3R is a cross-sectional view showing the state of a semiconductor optical device in an intermediate step for explaining the manufacturing method of a semiconductor optical device according to Embodiment 1 of the present invention. Figure 4 is a cross-sectional view showing a part of the configuration of a semiconductor optical device according to Embodiment 2. Figure 5 is a cross-sectional view showing the configuration of a semiconductor optical device according to Embodiment 3. Figure 6A is a cross-sectional view showing the configuration of a semiconductor optical device according to Embodiment 4. Figure 6B is a plan view showing the configuration of a semiconductor optical device according to Embodiment 4. Figure 7 is a cross-sectional view showing a partial configuration of a semiconductor optical device according to Embodiment 5. Figure 8 is a cross-sectional view showing a partial configuration of a semiconductor optical device according to Embodiment 6. Figure 9A is a distribution showing the results of mode calculation by film mode matching for each cross-section of a semiconductor optical device according to an embodiment. Figure 9B is a distribution showing the results of mode calculation by film mode matching for each cross-section of a semiconductor optical device according to an embodiment. Figure 9C is a distribution showing the results of mode calculation by film mode matching for each cross-section of a semiconductor optical device according to an embodiment. Figure 9D is a distribution showing the results of mode calculation by film mode matching for each cross-section of a semiconductor optical device according to an embodiment. Figure 9E is a distribution showing the results of mode calculation by film mode matching for each cross-section of a semiconductor optical device according to an embodiment.

[0018] The following describes a semiconductor optical device according to an embodiment of the present invention.

[0019] [Embodiment 1] First, a semiconductor optical device according to Embodiment 1 of the present invention will be described with reference to Figures 1A, 1B, 2A, 2B, 2C, 2D, and 2E. This semiconductor optical device comprises a first region 151, a second region 152, a third region 153, a fourth region 154, and a fifth region 155 arranged in series in the waveguide direction.

[0020] Figure 2A shows a cross-section of the plane perpendicular to the waveguide direction in the first region 151. Figure 2B shows a cross-section of the plane perpendicular to the waveguide direction in the second region 152. Figure 2C shows a cross-section of the plane perpendicular to the waveguide direction in the third region 153. Figure 2D shows a cross-section of the plane perpendicular to the waveguide direction in the fourth region 154. Figure 2E shows a cross-section of the plane perpendicular to the waveguide direction in the fifth region 155.

[0021] The first region 151 comprises a substrate 101, a first low refractive index layer 102 formed thereon, and an active layer 104 formed thereon. The substrate 101 can be, for example, a Si substrate. The first low refractive index layer 102 can be, for example, SiO2, SiO x It can be composed of materials such as SiN. The active layer 104 can be composed of, for example, InGaAsP, InGaAs, and InGaAlAs. Furthermore, the active layer 104 can be a multiple quantum well (MQW) structure in which the compositions of the compound semiconductors described above are varied and stacked.

[0022] Furthermore, a first semiconductor layer 106 and a second semiconductor layer 107 are formed so as to sandwich the active layer 104. The first semiconductor layer 106 and the second semiconductor layer 107 can be made of, for example, InP. Alternatively, the first semiconductor layer 106 and the second semiconductor layer 107 can be made of InGaAsP and InGaAlAs, which have a larger band gap than the active layer 104.

[0023] The device also includes a contact layer 103 formed on the first low refractive index layer 102 and a buffer layer 121 formed on the contact layer 103. The active layer 104, the first semiconductor layer 106, and the second semiconductor layer 107 are formed on the buffer layer 121. The contact layer 103 is formed over the entire area of ​​the first region 151, the second region 152, the third region 153, the fourth region 154, and the fifth region 155. The contact layer 103 can be made of, for example, n-type InP, InGaAsP, or InGaAs. The buffer layer 121 can be made of n-type InP.

[0024] Furthermore, a cap layer 105 is formed on the active layer 104, and the stacked structure of the active layer 104 and the cap layer 105 is sandwiched between the first semiconductor layer 106 and the second semiconductor layer 107. The cap layer 105 can be made of, for example, p-type InP.

[0025] Furthermore, an etch-stop layer 122 is provided on the first semiconductor layer 106, the cap layer 105, and the second semiconductor layer 107, and a rib portion 108 is provided on the etch-stop layer 122. The etch-stop layer 122 can be made of InGaAsP, InGaAlAs, etc. The rib portion 108 can be made of p-type InP, InGaAsP, InGaAs. In addition, the rib portion 108 can be made of a laminated structure of InP, InGaAsP, InGaAs, etc. as appropriate for purposes such as reducing electrical resistance.

[0026] Furthermore, the width of the rib portion 108 on the active layer 104 side can be smaller than that of the active layer 104. For example, the width of the rib portion 108 on the active layer 104 side can be 500 nm or less. In this example, a second low refractive index layer 109 is formed on the etch stop layer 122 so as to fill both sides of the rib portion 108. The second low refractive index layer 109 is, for example, SiO2, SiO x It can be made of materials such as SiN or benzocyclobutene (BCB). Furthermore, the first electrode 110 is connected to the contact layer 103, and the second electrode 111 is connected to the rib portion 108.

[0027] The second region 152, the third region 153, and the fourth region 154 are located on the same plane as the active layer 104 and contain a compound core 112 made of a compound semiconductor with a larger band gap than the active layer 104. The compound core 112 is formed continuously with respect to the active layer 104 in the waveguide direction. In addition, the first semiconductor layer 106 and the second semiconductor layer 107 are formed in the second region 152, the third region 153, and the fourth region 154, sandwiching the compound core 112 continuously from the location of the active layer 104.

[0028] Furthermore, the rib portion 108 is formed above the active layer 104 and the compound core 112, extending from the first region 151 to the second region 152 and the third region 153. In the second region 152 and the third region 153, a rib-type waveguide is formed by the rib portion 108, which consists of the first semiconductor layer 106 and the second semiconductor layer 107 as slabs.

[0029] The buffer layer 121 is formed from the first region 151 to the second region 152, the third region 153, and the fourth region 154. The etch stop layer 122 is also formed from the first region 151 to the second region 152, the third region 153, and the fourth region 154. In the second region 152 and the third region 153, the second low refractive index layer 109 is formed to fill both sides of the rib portion 108. The rib portion 108 is not formed in the fourth region 154.

[0030] Furthermore, the Si-based waveguide is configured with Si-based cores 113 embedded in the first low refractive index layer 102 of the third region 153, the fourth region 154, and the fifth region 155.

[0031] In the third region 153, a compound core 112 (rib portion 108) is positioned above the Si-based core 113, along the Si-based core 113. The distance between the Si-based core 113 and the compound core 112 in the thickness direction is set to a range in which the rib-type waveguide and the Si-based waveguide can be optically coupled.

[0032] Furthermore, in the third region 153, the rib portion 108 has a tapered portion whose width gradually decreases from the side of the second region 152 to the side of the fourth region 154.

[0033] Furthermore, in the third region 153, the Si-based core 113 has a tapered portion whose width gradually decreases from the fourth region 154 side to the second region 152 side.

[0034] Furthermore, in the fourth region 154, there is no rib portion 108, and the widths of the first semiconductor layer 106 and the second semiconductor layer 107 gradually decrease from the third region 153 side to the fifth region 155 side toward the compound core 112 side.

[0035] The following describes the change in the waveguide direction. In the second region 152, the third region 153, and the fourth region 154, a compound core 112 is formed instead of the active layer 104 and the capping layer 105 (Figure 2B). By constructing the compound core 112 from a material with a larger band gap than the active layer 104, the rib-type waveguide consisting of the first semiconductor layer 106, the compound core 112, the second semiconductor layer 107, and the rib portion 108 can be made into a low optical-loss waveguide without injecting carriers into the compound core 112.

[0036] To fabricate the structure described above, the regrowth technique described later can be used, and it is process-efficient to simultaneously regrow the first semiconductor layer 106, the compound core 112, and the second semiconductor layer 107 to form a semiconductor with the same composition. There are no restrictions on the conductivity type of the compound core 112, but by using a non-doped or non-conductive type, a low-loss waveguide can be made while suppressing leakage current.

[0037] In the third region 153, a Si-based core 113 is formed in the first low refractive index layer 102 below the region where the rib portion 108 is formed, constituting a Si-based waveguide. As the waveguide direction progresses, the width of the rib portion 108 narrows while the width of the Si-based core 113 widens (Figure 2C). This configuration allows for the adiabatic transfer of light modes from the rib-type waveguide to the Si-based waveguide by suppressing reflection and scattering.

[0038] In the fourth region 154, the rib portion 108 has disappeared, and a waveguide consisting of a Si-based waveguide formed by the Si-based core 113, and a contact layer 103, a first semiconductor layer 106, a second semiconductor layer 107, and a compound core 112 has been formed (Figure 2D). As the waveguide direction progresses from this region, the widths of the first semiconductor layer 106 and the second semiconductor layer 107 are narrowed, allowing the optical modes to be adiabatically transferred to the Si-based waveguide formed by the Si-based core 113. In the fifth region 155, all semiconductor layers above the contact layer 103 have disappeared, and the optical modes have transitioned to the Si-based waveguide formed by the Si-based core 113 (Figure 2E).

[0039] Next, a method for manufacturing a semiconductor optical device according to Embodiment 1 will be described with reference to Figures 3A to 3R. Figures 3A, 3D, 3G, 3I, 3J, 3L, 3N, 3P, and 3R show cross-sections of the first region 151. Figures 3B, 3E, 3H, 3K, 3M, and 3O show cross-sections of the fourth region 154. Figures 3C, 3F, and 3Q show cross-sections of the third region 153.

[0040] First, as shown in Figures 3A, 3B, and 3C, a Si-based waveguide is formed, comprising a Si-based core 113 embedded in a first low-refractive-index layer 102. For example, after forming the Si-based core 113 by processing the surface Si layer of an SOI substrate, a first low-refractive-index layer 102 is formed by depositing a dielectric or the like, consisting of an embedded insulating layer and a deposited layer. Subsequently, the surface of the first low-refractive-index layer 102 is planarized by CMP or the like. As the material for the Si-based core 113, in addition to single-crystal silicon, hydrogenated amorphous silicon and the like can be used. Furthermore, the cross-sectional shape of the Si-based core 113 can be rib-shaped.

[0041] Next, as shown in Figures 3D, 3E, and 3F, a contact layer 103 is formed on the first low refractive index layer 102. Here, for example, a well-known wafer bonding technique can be used.

[0042] Next, by selective growth using the selective growth mask 201, as shown in FIGS. 3G and 3H, a buffer layer 121, an active layer 104, and a cap layer 105 are continuously formed on the exposed contact layer 103 in the same growth apparatus. These can be formed by growth using well-known metalorganic vapor phase epitaxy or molecular beam epitaxy methods. The total thickness of the entire semiconductor layer fabricated in the above process is formed to be, for example, 150 to 350 nm referring to Reference 1.

[0043] Next, as shown in FIG. 3I, the cap layer 105 and the active layer 104 are patterned by an etching technique using a selective growth mask 201a made of an inorganic material formed by lithography technology, so that a stripe structure composed of the cap layer 105 and the active layer 104 is formed in the first region 151, and the buffer layers 121 on both sides thereof are exposed. The width of the active layer 104 in plan view is formed to be, for example, 800 nm. Also, in forming the stripe shape of the active layer 104, the buffer layers 121 are exposed without using a mask in the second region 152 to the fifth region 155.

[0044] In the description so far, the procedure of forming the contact layer 103 on the first low refractive index layer 102 and performing crystal growth thereon has been shown. However, after forming (transferring) a stacked structure including the active layer 104 grown on another substrate made of InP in advance on the first low refractive index layer 102, patterning is performed by an etching technique using a mask (not shown) made of an inorganic material (for example, silicon oxide) formed by a known lithography technique, so that the buffer layer 121 may be exposed.

[0045] Next, using the selective growth mask 201a as a selective growth mask, the first semiconductor layer 106 and the second semiconductor layer 107 are formed by regrowing non-doped InP or semi-insulating InP on the exposed buffer layer 121, as shown in FIG. 3J. The growth of this InP can be carried out by well-known metalorganic vapor phase epitaxy or molecular beam epitaxy methods. Also, at this time, by simultaneously growing a semiconductor such as InP in the second region 152, it becomes possible to form a low light absorption waveguide, which is a feature of the embodiment, in the waveguide direction (FIG. 3K).

[0046] In the process of forming an InP crystal by the method as described above, it is usually exposed to a high temperature of about 600°C. In such a situation, with the temperature change from room temperature, in a structure where different materials are integrated, thermal strain occurs due to the difference in the coefficient of thermal expansion between the materials. For example, when silicon (coefficient of thermal expansion 2.62) is used for the substrate 101, the difference in the coefficient of thermal expansion from InP (coefficient of thermal expansion 4.6) and the thermal strain due to the temperature change from room temperature to 600°C are usually not acceptable, and a large number of defects are generated in the InP. For the above reasons, it is known as common technical knowledge that crystal growth after direct bonding of InP and Si is difficult. However, as shown in Reference 2, in the case of a thin film structure where the thickness of the growing semiconductor layer is limited to 430 nm or less, InP can elastically deform without generating dislocations, enabling high-quality crystal growth.

[0047] Next, as shown in FIGS. 3L and 3M, an etch stop layer 122 made of p-type InGaAsP is formed on the first semiconductor layer 106, the cap layer 105, and the second semiconductor layer 107.

[0048] Next, as shown in FIGS. 3N and 3O, a selective growth mask 201b having an opening in a predetermined region is formed on the etch stop layer 122. The selective growth mask 201b is formed, for example, in a state of surrounding the periphery of the active layer 104 whose shape in plan view is rectangular. For example, in plan view, the selective growth mask 201b is formed in a state where the active layer 104 is disposed at the center of the opening. [[ID= IO]]

[0049] Next, by selective growth using the selective growth mask 201b, p-type InP is grown on the etch stop layer 122 exposed in the opening to form an InP layer. Subsequently, p-type InGaAs or InGaAsP or a stacked structure thereof is grown on the InP layer. These stacked structures are formed, for example, to a thickness of about 1500 nm. Here, the width of the opening in the plane direction of the substrate 101 can be, for example, about 1 μm to 200 μm. The stacked structure becomes the rib portion 108.

[0050] As described above, by using the selective growth mask 201b, the laminated structure is formed over a smaller area in plan view, thus preventing the generation of large residual stresses compared to when this layer is formed over the entire area of ​​the etch stop layer 122. The growth of the laminated structure is carried out using methods such as metal-organic vapor deposition or molecular beam epitaxy, similar to the semiconductor layers described above. As is well known, these growth methods involve high process temperatures.

[0051] In high-temperature processing such as crystal growth described above, stress is generated due to the difference in thermal expansion coefficients between the silicon substrate 101 and the InP, InGaAsP, and InGaAs that constitute the laminated structure.

[0052] When the laminated structure grows thicker and stress is generated as described above, elastic stress relaxation alone may not be sufficient, and stress relaxation may occur in the laminated structure through the formation of cracks. When cracks are formed in the laminated structure in this way, it can cause damage to the thinly formed active layer 104.

[0053] In contrast, as described above, by limiting the area in which the laminated structure is formed using the selective growth mask 201b, elastic stress relaxation in the planar direction of the substrate 101 becomes possible, and the occurrence of cracks in the active layer 104 region can be suppressed. Thus, by forming a laminated structure using the selective growth mask 201b, it becomes possible to fabricate a thick InP-based layer structure on silicon by crystal growth, which is normally difficult.

[0054] Next, the laminated structure is patterned using known lithography and etching techniques to form a rib structure consisting of rib portions 108 in the cross-section of the first region 151, as shown in Figures 3P and 3Q, and to form tapered portions of the rib portions 108 in the cross-sections of the second region 152 and the third region 153. For example, the rib portions 108 can be formed by patterning using wet etching, which selectively etches the laminated structure with respect to the etch stop layer 122. In the fourth region 154 and the fifth region 155, all of the rib portions 108 are removed. After this, the selective growth mask 201 and the selective growth mask 201b are removed.

[0055] Next, the excess semiconductor layer in the fifth region 155 is removed by patterning using known lithography and etching techniques, exposing the first low refractive index layer 102. In this process, by etching a portion of the semiconductor layer in the fourth region 154, adiabatic mode conversion between the fourth region 154 and the fifth region 155 can be achieved.

[0056] Next, as shown in Figure 3R (Figures 2A, 2B, 2C, 2D, and 2E), a second low refractive index layer 109 is formed. For example, a photosensitive BCB is applied to form a coating film, and this coating film is patterned using known lithography techniques to form the second low refractive index layer 109 in the desired region. After forming the second low refractive index layer 109 in this manner, the first electrode 110 and the second electrode 111 are formed. These electrodes can be formed, for example, by a well-known lift-off method.

[0057] The manufacturing method described above enables mode conversion without causing light absorption by the material throughout the entire waveguide, making it possible to integrate highly efficient semiconductor optical devices.

[0058] [Embodiment 2] Next, a semiconductor optical device according to Embodiment 2 of the present invention will be described with reference to Figure 4. Figure 4 shows a cross-section of the first region 151.

[0059] In Embodiment 2, unlike Embodiment 1, the first and second semiconductor layers sandwiching the active layer 104a and cap layer 105a are not formed. In Embodiment 2, the refractive index difference between the rib portion 108 and the surrounding area is utilized to shift the guided mode to the rib portion 108 side. With this configuration, the center of the guided light mode is located at the active layer 104a and cap layer 105a in the region where the rib portion 108 is formed, which is the same as when the first and second semiconductor layers are formed.

[0060] [Embodiment 3] Next, a semiconductor optical device according to Embodiment 3 of the present invention will be described with reference to Figure 5. In Embodiment 3, the Si-based core 113 is formed up to the second region 152 and the first region 151, and the Si-based waveguide made of the Si-based core 113 is arranged up to the region below the active layer 104. More adiabatic mode conversion is possible without creating discontinuities caused by the presence or absence of the Si-based waveguide in the area from the second region 152 to the third region 153. By appropriately designing the cross-sectional shape of the Si-based core 113 in the first region 151, the optical confinement to the active layer 104 can also be appropriately changed. The cross-sectional shape of the Si-based core 113 is channel-shaped, but it can be rib-shaped.

[0061] Furthermore, a resonator can be formed by creating a diffraction grating near the extended Si-based core 113, and the first region 151 can be used as a DFB laser or DBR laser. The diffraction grating can be formed by processing the upper or side portion of the Si-based core 113 by dry etching or the like, based on the refractive index difference between the Si-based core 113 material and the surrounding first low refractive index layer 102.

[0062] [Embodiment 4] Next, a semiconductor optical device according to Embodiment 4 of the present invention will be described with reference to Figures 6A and 6B. In Embodiment 4, in the third region 153, the first semiconductor layer 106a and the second semiconductor layer 107a are processed into a tapered shape, and in the fourth region 154, the first semiconductor layer 106a, the compound core 112, and the second semiconductor layer 107a are absent (disappeared). The widths of the first semiconductor layer 106a and the second semiconductor layer 107a gradually decrease from the second region 152 to the fourth region 154. This configuration makes it possible to further simplify the tapered structure in the rib-type waveguide and to shorten the total tapered length. This structure can be combined with Embodiments 2 and 3.

[0063] [Embodiment 5] Next, a semiconductor optical device according to Embodiment 5 of the present invention will be described with reference to Figure 7. Figure 7 shows a cross-section of the first region 151. In Embodiment 5, a diffraction grating 123 is formed on the etch stop layer 122. The diffraction grating 123 is formed by processing the area near the rib portion 108 of the etch stop layer 122 by etching or the like. The irregularities of the diffraction grating 123 are arranged from the front to the back of the page in Figure 7.

[0064] The diffraction grating 123 is coupled to the mode field near the active layer 104, and the first region 151 can be configured as a DFB laser or a DBR laser. For example, after forming the rib portion 108 as described using Figures 3P and 3Q, an etching mask is formed by lithography or the like, and the etch stop layer 122 is formed by patterning with selective etching using this etching mask. Furthermore, not limited to the etch stop layer 122, for example, in the process of forming the rib portion 108, irregularities can be formed on the upper part of the rib portion 108 to create a diffraction grating. This structure can be combined with embodiments 2, 3, and 4.

[0065] [Embodiment 6] Next, a semiconductor optical device according to Embodiment 6 of the present invention will be described with reference to Figure 8. Figure 8 shows a cross-section of the first region 151. In Embodiment 6, the etch stop layer 122 is not used. For example, a selective growth mask having an opening in a predetermined region is formed on the first semiconductor layer 106, the cap layer 105, and the second semiconductor layer 107, and an InP layer and p-type InGaAs or InGaAsP or a stacked structure thereof are formed on the first semiconductor layer 106, the cap layer 105, and the second semiconductor layer 107 exposed at the opening by selective growth using the selective growth mask. After this, the stacked structure is patterned by dry etching to form the rib portion 108. This structure can be combined with Embodiments 2, 3, 4, and 5.

[0066] Next, the results of mode calculations using the film mode matching method for the cross-sections of each region in the semiconductor optical device according to the embodiment are shown in Figures 9A, 9B, 9C, 9D, and 9E. The width of the rib portion 108 was set to 400 nm. The thickness of the first semiconductor layer 106 and the second semiconductor layer 107 was set to 350 nm, and the thickness of the active layer 104 was set to 100 nm. The etch stop layer was omitted for simplicity.

[0067] The cross-sectional dimensions of the Si-based core 113 were set to a width of 440 nm and a thickness of 220 nm, which is a structure commonly used in silicon photonics. The thickness of the first low refractive index layer 102 between the Si-based core 113 and the contact layer 103 was set to 50 nm. The refractive index of the active layer 104 was set to 3.4, assuming InGaAsP, InGaAlAs, etc. The refractive index of the first semiconductor layer 106 and the second semiconductor layer 107 was set to 3.169, assuming InP. The refractive index of each low refractive index layer was set to 1.45, assuming SiO2, and the refractive index of the Si-based core 113 was set to 3.5, assuming Si.

[0068] Figure 9A shows the calculated mode field of the cross-section of the first region 151. Figure 9B shows the calculated mode field of the cross-section of the first region 151 in Embodiment 2. Figure 9C shows the calculated mode field of the second region 152 in Embodiments 1 and 2.

[0069] In both cases, it can be seen that waveguide modes exist around the ribs defined by the rib portion 108. Furthermore, the optical confinement in the active layer 104 was 31.3% in Embodiment 1 and 37.0% in Embodiment 2. Figure 9D shows the calculated mode field of the fourth region 154 in Embodiments 1 and 2. In the fourth region 154, it can be seen that the Si-based waveguide by the Si-based core 113 functions as a waveguide due to lateral confinement. In the fifth region 155, it can be seen that the modes have transitioned to the Si-based waveguide.

[0070] Next, we will discuss the mode conversion between each cross-section. The boundary between the first region 151 and the second region 152 is formed by a butt joint due to crystal growth, resulting in losses due to discontinuities in equivalent refractive index and mode shape. The coupling efficiency of the first region 151 and the second region 152, calculated by the film mode matching method, is sufficiently high at 96.0% in the case of Embodiment 1 and 96.7% in the case of Embodiment 2, indicating that it can function as a waveguide.

[0071] Furthermore, when forming the stripe shape of the active layer 104 and the cap layer 105, a tapered shape can be created in which the width changes by approximately 0.1 to 5 μm in a plan view in the waveguide direction. By providing such a short taper, the shortness of the tapered portion itself, as well as the diffusion of carriers into the tapered portion and its transparency, can be suppressed due to material absorption, while enabling adiabatic mode conversion.

[0072] In this embodiment, all regions other than the first region 151 are formed of a material transparent to light of the band gap wavelength of the active layer, and precise microfabrication can be easily performed by appropriately combining lithography and dry etching. Therefore, mode conversion between each region from the second region 152 to the fifth region 155 can be performed adiabatically by appropriately providing a tapered shape during etching.

[0073] Another feature of this structure is that it can increase the efficiency of the light source itself. As long as a typical vertical PIN structure is used, a semiconductor layer is required above or below the active layer 104. Since the refractive index difference between InP and InGaAsP or InGaAlAs is not very large, it is not possible to achieve high optical confinement in the active layer 104. For this reason, it was necessary to increase the length of the active layer 104 in the waveguide direction in order to obtain laser oscillation. While such lasers can produce high optical output, they have the problem of not being able to create low-energy-consumption light sources because the threshold current becomes large.

[0074] On the other hand, in this embodiment, a semiconductor layer with a thickness of, for example, 350 nm or less can be used in the laser region (first region 151), and a low refractive index layer can be placed nearby, which allows for a larger optical confinement coefficient in the active layer 104. This makes it possible to reduce the volume of the active layer 104, and thus lower the threshold voltage of the light source itself.

[0075] As described above, according to the embodiments of the present invention, the energy efficiency when performing mode conversion of an optical semiconductor to a Si waveguide can be increased.

[0076] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be implemented within the technical concept of the present invention by those with ordinary skill in the art.

[0077] [Reference 1] Patent No. 7410276 [Reference 2] T. Fujii et al., "Epitaxial growth of InP to bury directly bonded thin active layer on SiO2 / Si substrate for fabricating distributed feedback lasers on silicon", IET Optoelectron, vol. 9, no. 4, pp. 151-157, 2015.

[0078] 101...Substrate, 102...First low refractive index layer, 103...Contact layer, 104...Active layer, 105...Cap layer, 106...First semiconductor layer, 107...Second semiconductor layer, 108...Rib portion, 109...Second low refractive index layer, 110...First electrode, 111...Second electrode, 112...Compound core, 113...Si-based core, 121...Buffer layer, 122...Etch stop layer, 151...First region, 152...Second region, 153...Third region, 154...Fourth region, 155...Fifth region.

Claims

1. A first, second, third, fourth, and fifth region formed continuously in the waveguide direction, wherein the entirety of the first, second, third, fourth, and fifth regions is provided with a low refractive index layer formed on a substrate, the first region comprises an active layer formed on the low refractive index layer and a cap layer formed on the active layer having a larger band gap than the active layer, the second, third, and fourth regions comprises a compound core formed on the substrate continuously with respect to the active layer and the cap layer, having a larger band gap than the active layer, the first, second, third, and fourth regions are provided with a first semiconductor layer and a second semiconductor layer formed on the substrate so as to sandwich the active layer and the cap layer, having a larger band gap than the active layer, and above the cap layer and the compound core, the first, second, and third regions are provided with a rib portion formed along the active layer and the compound core, having a larger band gap than the active layer. A semiconductor optical device comprising a Si-based core embedded in the low refractive index layer in the third, fourth, and fifth regions, and formed along the active layer and the compound core in the third and fourth regions.

2. A semiconductor optical device according to claim 1, wherein in the third region, the rib portion has a tapered portion whose width gradually decreases from the side of the second region to the side of the fourth region, and in the third region, the Si-based core has a tapered portion whose width gradually decreases from the side of the fourth region to the side of the second region.

3. A semiconductor optical device according to claim 1 or 2, wherein in the fourth region, the widths of the first semiconductor layer and the second semiconductor layer gradually decrease from the third region to the fifth region.

4. A semiconductor optical device according to claim 1 or 2, wherein in the third region, the widths of the first semiconductor layer and the second semiconductor layer gradually decrease from the second region to the fourth region.

Images