Power conversion device

Abstract

A power conversion device according to an embodiment of the present invention comprises: a voltage detection circuit that has one end connected to the drain of a power semiconductor element and detects a reference voltage with which it is possible to identify a voltage corresponding to an element current of the power semiconductor element; and a switching element that has the drain connected to the gate of the power semiconductor element and has the gate electrically connected to the voltage detection circuit. The switching element is turned on when the voltage corresponding to the element current exceeds a second threshold that is less than or equal to a first threshold for short-circuit determination.

Description

Power conversion device

[0001] The present invention relates to a power conversion device.

[0002] Conventionally, in a power conversion device that converts DC power and AC power, a technique for protecting a power semiconductor element such as a power switching element included in such a power conversion device from an overcurrent generated by a short circuit of the power semiconductor element is known. For example, Patent Document 1 listed below discloses a protection device that performs the following operations with the problem of suppressing heat generation during a short circuit of a switching element while ensuring normal operation during noise generation. That is, when an overcurrent (large current) is detected, the gate voltage is lowered below the normal value, and then, when a short circuit of the switching element is detected, the gate voltage is further lowered, and when a short circuit is not detected, the gate voltage is raised to the normal value. A protection device is disclosed.

[0003] Japanese Patent Application Laid-Open No. 2015-012755

[0004] However, the power conversion device according to the above-described conventional technology requires a semiconductor regulator (protection drive circuit) that controls the gate voltage applied to the gate of the switching element when an overcurrent is detected, separately from the drive circuit used when no overcurrent is detected. Therefore, the above-described conventional technology has a problem that the circuit scale becomes large.

[0005] In one aspect, the present invention has been made in view of such circumstances, and an object thereof is to provide a power conversion device that can protect a power semiconductor element from a large current, a short-circuit current, etc. by suppressing the number of parts.

[0006] To solve the above-mentioned problems, a power conversion device according to one aspect of the present invention comprises: a power semiconductor element; a voltage detection circuit, one end of which is connected to the drain or collector of the power semiconductor element, which detects a reference voltage capable of identifying a voltage corresponding to the element current of the power semiconductor element; an overcurrent determination circuit, which outputs an overcurrent suppression signal when the voltage corresponding to the element current identified by the reference voltage detected by the voltage detection circuit exceeds a predetermined first threshold; a driving element, which, upon receiving the overcurrent suppression signal from the overcurrent determination circuit, interrupts the gate voltage or base current of the power semiconductor element; and a switching element, the drain or collector of which is connected to the gate or base of the power semiconductor element, and the gate or base of which is electrically connected to the voltage detection circuit, wherein the switching element is configured to turn on when the voltage corresponding to the element current exceeds a predetermined second threshold less than or equal to the first threshold, thereby reducing the gate voltage or base current of the power semiconductor element.

[0007] According to the present invention, it is possible to provide a power conversion device that can protect power semiconductor elements from high currents, short-circuit currents, and the like while reducing the number of components.

[0008] This is a block diagram showing an example of the schematic configuration of a power converter according to the embodiment. It shows an example of the configuration of the control circuit section of the power converter illustrated in Figure 1. Regarding the voltage detection circuit according to the embodiment, a different configuration example from that shown in Figure 2 is shown. Regarding the driving elements and the like according to the embodiment, a different configuration example from that shown in Figure 2 is shown. An example of an operation time chart for the power converter according to the embodiment when a short circuit occurs in the power semiconductor element is shown. An example of an operation time chart for the power converter according to the embodiment when a large current flows without a short circuit occurring in the power semiconductor element is shown. An example of an operation time chart for the power converter according to the embodiment when neither a short-circuit current nor a large current flows through the power semiconductor element is shown.

[0009] Hereinafter, an embodiment relating to one aspect of the present invention (hereinafter also referred to as "this embodiment") will be described based on the drawings. However, this embodiment described below is merely illustrative in all respects of the present invention. Needless to say, various improvements and modifications can be made without departing from the scope of the present invention. In other words, in carrying out the present invention, specific configurations according to the embodiment may be appropriately adopted.

[0010] §1 Overall schematic diagram 1 of the power converter is a block diagram showing an example of the schematic configuration of the power converter (power converter M) according to this embodiment. The power converter M is used, for example, in an inverter for driving automobiles, and performs power conversion between a motor (not shown, for example, a three-phase motor) which is an electrical load and a drive source, and a power supply 1. Figure 1 illustrates a power converter M that includes one phase of power semiconductor elements 8A and 8B, and control circuits 3A and 3B that control the on and off states of the power semiconductor elements 8A and 8B, respectively. However, it is not essential for the power converter M to include one phase of power semiconductor elements 8 and control circuits 3. The power converter M may include multiple phases of power semiconductor elements 8 and control circuits 3, for example, three phases. In this embodiment, when there is no need to particularly distinguish between the power semiconductor elements 8A and 8B, they may simply be referred to as "power semiconductor element 8". Similarly, when there is no need to distinguish between control circuit sections 3A and 3B, they may simply be referred to as "control circuit section 3".

[0011] The power converter M illustrated in Figure 1 comprises a power supply 1, a smoothing capacitor 2, power semiconductor elements 8A and 8B, and control circuit sections 3A and 3B. However, the power converter M may also include components other than those illustrated in Figure 1 (electronic components), such as a current sensor for current detection.

[0012] Power source 1 is a DC power source, which is implemented by, for example, a battery (a rechargeable battery such as a lithium-ion battery or nickel-metal hydride battery) and supplies DC power. Power source 1 may also be implemented by rectifying a commercial power source.

[0013] The smoothing capacitor 2 is provided for the purpose of smoothing the power input to the power converter M, and is implemented by, for example, a film capacitor or an aluminum electrolytic capacitor. The smoothing capacitor 2 can also be considered as an element that smooths the output voltage of the power supply 1 and supplies it to the power semiconductor elements 8A and 8B, which are the upper and lower arm elements for one phase of the three-phase motor.

[0014] The power semiconductor element 8 is a power switching element, a so-called power element. Figure 1 shows an example in which the power semiconductor element 8 is realized using only one MOSFET (Metal Oxide Semiconductor Field Effect Transistor) chip, but it is not essential to realize the power semiconductor element 8 with a single MOSFET chip. The power semiconductor element 8 may be realized, for example, by a parallel connection of an IGBT (Insulated Gate Bipolar Transistor) and a diode. Furthermore, the power semiconductor element 8 may be realized using multiple chips, or for example, by connecting multiple types of chips in parallel. The power semiconductor element 8 may be realized using a switching element that comprises a pair of main terminals (input / output terminals) and a control terminal that controls the current (element current) flowing between the pair of main terminals, and switches between the pair of main terminals in response to an electrical signal applied to the control terminal. In this embodiment, an example in which the power semiconductor element 8 is realized using a MOSFET will be described, that is, an example in which the source and drain are a pair of main terminals, the gate is a control terminal, and the drain-source current (element current) is controlled by the gate voltage. When the power semiconductor device 8 is realized using a bipolar transistor, the source, drain, and gate in the following description can be read as emitter, collector, and base, respectively. Similarly, the gate voltage in the following description can be read as base current.

[0015] The control circuit unit 3 controls the on / off state (turn-on, turn-off) of the power semiconductor element 8. For example, the control circuit unit 3 receives (acquires) an on / off control signal from an external device or circuit to control the on / off state of the power semiconductor element 8. The control circuit unit 3 controls the on / off state of the power semiconductor element 8 according to the received on / off control signal. Furthermore, if the control circuit unit 3 detects an abnormality in the power converter M, for example, if it detects a short circuit in the power semiconductor element 8, it outputs an alarm signal to notify the power converter M of the abnormality. In addition to controlling the on / off state of the power semiconductor element 8, the control circuit unit 3 also performs processing to protect the power semiconductor element 8 from overcurrents caused by short circuits, etc.

[0016] In this embodiment, the power converter M (particularly the control circuit unit 3) determines that an overcurrent has flowed through the power semiconductor element 8 when the drain-source voltage (voltage MV corresponding to the element current) of the power semiconductor element 8 exceeds a predetermined first threshold FT. Upon determining that an overcurrent has flowed through the power semiconductor element 8, the power converter M executes an overcurrent suppression process. In the overcurrent suppression process, the power converter M protects the power semiconductor element 8 from overcurrent by interrupting the gate voltage applied to the gate of the power semiconductor element 8. For example, when the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the first threshold FT, the power converter M stops applying the gate voltage to the gate of the power semiconductor element 8 and sets the gate voltage to zero or a predetermined negative voltage.

[0017] In the following explanation, the situation of "a short-circuit current flowing through the power semiconductor element 8" will be described as an example of the situation of "an overcurrent flowing through the power semiconductor element 8," that is, a short-circuit current will be described as an example of an overcurrent. In other words, in the following, the situation of "a short circuit occurring in the power semiconductor element 8" will be described as an example of the situation of "an overcurrent flowing through the power semiconductor element 8." However, the situation of "an overcurrent flowing through the power semiconductor element 8" is not limited to the situation of "a short circuit occurring in the power semiconductor element 8." This is because an overcurrent (large current) may flow through the power semiconductor element 8 transiently even in cases other than "a short circuit occurring in the power semiconductor element 8." Therefore, the power converter M may determine, in addition to (or instead of) "whether or not a short-circuit current flowed through the power semiconductor element 8," whether or not "an overcurrent flowed through the power semiconductor element 8 transiently."

[0018] The power converter M (particularly the control circuit unit 3) does not perform overcurrent suppression processing if the voltage MV corresponding to the element current is less than the first threshold FT. However, if the voltage MV corresponding to the element current exceeds a predetermined second threshold ST which is less than or equal to the first threshold FT, the power converter M determines that a large current (overcurrent), such as noise current, has flowed through the power semiconductor element 8. When the power converter M determines that a large current has flowed through the power semiconductor element 8, it performs main current suppression processing. In the main current suppression processing, the power converter M suppresses the element current (large current) flowing through the power semiconductor element 8 by reducing the gate voltage applied to the gate of the power semiconductor element 8, thereby protecting the power semiconductor element 8 from large currents. In this embodiment, "reducing the gate voltage applied to the gate of the power semiconductor element 8" is also referred to as "suppression of the gate voltage of the power semiconductor element 8".

[0019] In particular, the power converter M includes a voltage detection circuit 5 that detects a reference voltage RV capable of identifying the voltage MV corresponding to the element current, and a switching element (gate voltage suppression semiconductor element 20) that turns on and off according to the reference voltage RV. The drain (or collector) of the gate voltage suppression semiconductor element 20 is connected to the gate of the power semiconductor element 8, and the gate (or base) of the gate voltage suppression semiconductor element 20 is electrically connected to the voltage detection circuit 5. The gate voltage suppression semiconductor element 20 is configured to turn on when the voltage MV corresponding to the element current exceeds a second threshold ST, thereby reducing the gate voltage of the power semiconductor element 8. The power converter M can reduce the gate voltage of the power semiconductor element 8 when the voltage MV corresponding to the element current exceeds the second threshold ST by using the gate voltage suppression semiconductor element 20, which turns on and off according to the reference voltage RV capable of identifying the voltage MV corresponding to the element current. In other words, the power converter M can protect the power semiconductor element 8 from high currents by directly controlling the gate voltage of the power semiconductor element 8 in accordance with the reference voltage RV. To put it another way, the power converter M does not require a semiconductor regulator to control the gate voltage of the power semiconductor element 8 when a high current is detected, and can protect the power semiconductor element 8 from high currents using a switching element (gate voltage suppression semiconductor element 20). Therefore, the power converter M according to this embodiment can protect the power semiconductor element 8 from high currents, short-circuit currents, etc., while keeping the number of components low. We have now described the general outline of the power converter M. Next, we will explain the details of the control circuit section 3 of the power converter M, using Figures 2 to 7. Figure 2 shows an example of the configuration of the control circuit section 3 of the power converter M.

[0020] §2 Example of Control Circuit Configuration The control circuit 3 illustrated in Figure 1 includes a short-circuit detection circuit 4, a voltage detection circuit 5, a drive element 6, and a main current suppression circuit 7. However, the control circuit 3 may also include other circuits and elements. For example, the control circuit 3 may include a circuit that receives on / off control signals from external devices and circuits. The control circuit 3 may also include circuits and elements that output the alarm signals mentioned above.

[0021] The short-circuit detection circuit 4 is an example of the "overcurrent detection circuit" of the present invention and can be implemented, for example, by a comparator. The short-circuit detection circuit 4 determines whether or not an overcurrent has flowed through the power semiconductor element 8. In this embodiment, the short-circuit detection circuit 4 determines whether or not a short circuit has occurred in the power semiconductor element 8, or in other words, whether or not a short-circuit current is flowing through the power semiconductor element 8. When the short-circuit detection circuit 4 determines that a short circuit has occurred (an overcurrent has flowed) in the power semiconductor element 8, it outputs a short-circuit occurrence signal SCS. The short-circuit occurrence signal SCS is an example of the "overcurrent suppression signal" of the present invention and is a signal indicating that an overcurrent has flowed through the power semiconductor element 8 (in this embodiment, a short circuit has occurred). When the short-circuit detection circuit 4 determines that a short circuit has occurred in the power semiconductor element 8, it outputs the short-circuit occurrence signal SCS to, for example, the drive element 6.

[0022] For example, the short-circuit detection circuit 4 determines whether the drain-source voltage (voltage MV corresponding to the element current) of the power semiconductor element 8 exceeds a first threshold FT. If the voltage MV corresponding to the element current exceeds the first threshold FT, it determines that a short circuit has occurred in the power semiconductor element 8. In this embodiment, the short-circuit detection circuit 4 uses a reference voltage RV detected by the voltage detection circuit 5 to determine whether the voltage MV corresponding to the element current specified by the reference voltage RV exceeds the first threshold FT. In the example shown in Figure 2, the short-circuit detection circuit 4 takes the reference voltage RV(b) detected by the voltage detection circuit 5 as input and determines that if the reference voltage RV(b) exceeds the corresponding first threshold CFT corresponding to the first threshold FT, the voltage MV corresponding to the element current exceeds the first threshold FT. In other words, the short-circuit detection circuit 4 determines that a short circuit has occurred in the power semiconductor element 8 if the reference voltage RV(b) exceeds the corresponding first threshold CFT. When the short-circuit detection circuit 4 determines that a short circuit has occurred in the power semiconductor element 8, it outputs a short-circuit detection signal SCS to the drive element 6, instructing the drive circuit 62 to stop applying the gate voltage and the protection circuit 61 to shut off the gate voltage. As a result, the power semiconductor element 8 is turned off, and the power converter M (especially the control circuit 3) can protect the power semiconductor element 8 from failure due to short-circuit current.

[0023] The voltage detection circuit 5 is an example of the "voltage detection circuit" of the present invention, and as illustrated in Figure 1, one end is connected to the drain of the power semiconductor element 8, and it detects a reference voltage RV that can identify the voltage MV corresponding to the element current of the power semiconductor element 8. In the example shown in Figure 2, the voltage detection circuit 5 includes a voltage detection current adjustment resistor 11, voltage divider resistors 12 and 13, and a voltage detection diode element 19. One end of the voltage detection current adjustment resistor 11 is connected to the turn-on output terminal (drive terminal) of the drive element 6, and the other end is connected to node A in Figure 2. Node A is connected to the drain of the power semiconductor element 8 via the voltage detection diode element 19. That is, one end of the voltage detection diode element 19 is connected to the drain of the power semiconductor element 8, and the other end is connected to node A. Node A is also connected to the turn-on output terminal of the drive element 6 via the voltage detection current adjustment resistor 11. Furthermore, node A is connected to node B via the voltage divider resistor 13, and is also connected to the suppression time adjustment capacitor 21 of the main current suppression circuit 7.

[0024] Node B, illustrated in Figure 2, is connected to the input terminal of the short-circuit detection circuit 4 and is also connected to Node A via the voltage divider resistor 13. Node B is also connected to the source of the power semiconductor element 8 via the voltage divider resistor 12. If a negative voltage is used as the gate voltage when the power semiconductor element 8 is turned off, Node B may be connected to a terminal connected to a negative power supply via the voltage divider resistor 12, rather than to the source of the power semiconductor element 8.

[0025] When the drain-source voltage of the power semiconductor element 8 (voltage MV corresponding to the element current) is high, the reference voltage RV(a) between node A and the source of the power semiconductor element 8 rises, and the reference voltage RV(b), obtained by dividing the reference voltage RV(a) with the voltage divider resistors 12 and 13, also rises. The reference voltage RV(b) is the voltage between node B in Figure 2 and the source of the power semiconductor element 8. In other words, the reference voltage RV(a) and the reference voltage RV(b) are voltages that can specify the voltage MV corresponding to the element current. In this embodiment, when there is no need to particularly distinguish between the reference voltages RV(a) and RV(b), they may simply be referred to as "reference voltage RV".

[0026] Although Figure 2 shows an example where the voltage detection circuit 5 includes one voltage detection diode element 19, it is not essential that the voltage detection circuit 5 includes only one voltage detection diode element 19. The voltage detection circuit 5 may include multiple voltage detection diode elements 19 connected in series with each other, from the viewpoint of ensuring voltage withstand capability. Similarly, in the voltage detection circuit 5, resistors may be connected in parallel or in series with the voltage detection diode elements 19. Also, in the example shown in Figure 2, the short-circuit detection circuit 4 receives a reference voltage RV(b) obtained by dividing the reference voltage RV(a) with voltage divider resistors 12 and 13, but it is not essential that the voltage detection circuit 5 includes voltage divider resistors 12 and 13. The short-circuit detection circuit 4 may receive reference voltage RV(a) instead of reference voltage RV(b), and the short-circuit detection circuit 4 may use reference voltage RV(a) instead of reference voltage RV(b) to determine whether the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the first threshold FT. The voltage detection circuit 5 only needs to be able to detect a reference voltage RV at one end that can identify the voltage MV corresponding to the element current, and it is sufficient that it can detect either reference voltage RV(a) or reference voltage RV(b) as the reference voltage RV. The short-circuit detection circuit 4 then uses the reference voltage RV detected by the voltage detection circuit 5 to determine whether the voltage MV corresponding to the element current exceeds the first threshold FT. In other words, the short-circuit detection circuit 4 uses either reference voltage RV(a) or reference voltage RV(b) to determine whether the voltage MV corresponding to the element current exceeds the first threshold FT. The short-circuit detection circuit 4 determines that a short circuit has occurred in the power semiconductor element 8 if the voltage MV corresponding to the element current specified by the reference voltage RV(a) or reference voltage RV(b) exceeds the first threshold FT. Furthermore, as will be described in detail later, the main current suppression circuit 7 controls the gate voltage of the power semiconductor element 8 in accordance with the reference voltage RV detected by the voltage detection circuit 5, thereby suppressing the element current of the power semiconductor element 8 from becoming excessive.In other words, the power converter M uses a reference voltage RV (reference voltage RV(a) or reference voltage RV(b)) that can identify the voltage MV corresponding to the element current to suppress the large current flowing through the power semiconductor element 8 and protect the power semiconductor element 8 from short-circuit current.

[0027] When the drive element 6 receives a short-circuit signal SCS from the short-circuit detection circuit 4, it performs overcurrent suppression processing, for example, by interrupting the gate voltage applied to the gate of the power semiconductor element 8. If the drive element 6 does not receive a short-circuit signal SCS from the short-circuit detection circuit 4, it performs normal on / off control (normal turn-on / turn-off control), for example, by controlling the on / off state of the power semiconductor element 8 according to an on / off control signal. In the example shown in Figure 2, the drive element 6 includes a protection circuit section 61 and a drive circuit section 62.

[0028] When the protection circuit unit 61 receives a short-circuit signal SCS, it performs overcurrent suppression processing. For example, as overcurrent suppression processing, the protection circuit unit 61 interrupts the gate voltage applied to the gate of the power semiconductor element 8 (in other words, stops the application of gate voltage to the gate of the power semiconductor element 8), and sets the gate voltage to zero. In the example shown in Figure 2, the protection circuit unit 61 includes an output terminal (drive terminal) for short-circuit interruption and a short-circuit interruption gate resistor 16. It is desirable to use a short-circuit interruption gate resistor 16 with a larger resistance value than the turn-off gate resistor 15, which will be described later. By making the resistance value of the short-circuit interruption gate resistor 16 larger than the resistance value of the turn-off gate resistor 15, it is possible to prevent a large surge voltage from being generated and causing the power semiconductor element 8 to fail when an extremely large short-circuit current is interrupted. However, in cases where surge voltage is not a problem, the drive circuit unit 62 may perform the overcurrent suppression processing instead of the protection circuit unit 61. For example, the control circuit unit 3 does not necessarily have to include a protection circuit unit 61. In that case, the drive circuit unit 62 may perform overcurrent suppression processing when it receives a short-circuit occurrence signal SCS from the short-circuit detection circuit 4.

[0029] The drive circuit 62 performs on / off control under normal conditions (i.e., when the short-circuit detection circuit 4 determines that "no short circuit has occurred in the power semiconductor element 8"). In other words, the drive circuit 62 controls the on / off state of the power semiconductor element 8 while the short-circuit detection circuit 4 is not outputting a short-circuit signal SCS. In this embodiment, the drive circuit 62 controls the on / off state of the power semiconductor element 8 according to on / off control signals received from external devices and circuits of the control circuit 3. For example, the drive circuit 62 includes a semiconductor switching element, and controls the gate voltage applied to the gate of the power semiconductor element 8 by turning the switching element on and off according to the on / off control signal. In the example shown in Figure 2, the drive circuit 62 includes a turn-on output terminal, a turn-on gate resistor 14, a turn-off output terminal, and a turn-off gate resistor 15. The drive circuit 62, in accordance with the on / off control signal, applies a voltage to the gate of the power semiconductor element 8 via the turn-on gate resistor 14 to turn on the power semiconductor element 8, or removes charge from the gate of the power semiconductor element 8 via the turn-off gate resistor 15 to turn off the power semiconductor element 8.

[0030] Figure 2 shows an example in which the drive circuit 62 separately includes a circuit for turning on the power semiconductor element 8 (a turn-on output terminal and a turn-on gate resistor 14) and a circuit for turning it off (a turn-off output terminal and a turn-off gate resistor 15). However, in the drive circuit 62, the circuit for turning on the power semiconductor element 8 and the circuit for turning it off may be configured as a single unit, or for example, both may be realized by the same single circuit. For example, the turn-on output terminal and the turn-off output terminal may be realized by a single terminal. Furthermore, it is not essential for the drive circuit 62 to include a turn-on gate resistor 14 and a turn-off gate resistor 15. The turn-on output terminal and the turn-off output terminal of the drive circuit 62 may be connected to the gate of the power semiconductor element 8 without going through the turn-on gate resistor 14 and the turn-off gate resistor 15. In addition, the drive circuit 62 may include electronic components other than those exemplified in Figure 2, such as capacitors.

[0031] The main current suppression circuit 7 protects the power semiconductor element 8 from high currents. In this embodiment, it protects the power semiconductor element 8 from high currents by reducing the gate voltage applied to the gate of the power semiconductor element 8, thereby suppressing the element current of the power semiconductor element 8. In other words, the main current suppression circuit 7 protects the power semiconductor element 8 from high currents by suppressing the gate voltage of the power semiconductor element 8, thereby suppressing the element current (high current) flowing through the power semiconductor element 8. In the example shown in Figure 2, the main current suppression circuit 7 includes a gate voltage suppression resistor 17, a gate voltage suppression time adjustment resistor 18, a gate voltage suppression semiconductor element 20, and suppression time adjustment capacitors 21 and 22. The gate voltage suppression semiconductor element 20 is an example of the "switching element" of the present invention, and is realized by, for example, a MOSFET. The suppression time adjustment capacitor 21 is an example of the "capacitor" of the present invention.

[0032] One end of the suppression time adjustment capacitor 21 is connected to the voltage detection circuit 5 (node ​​A of the voltage detection circuit 5), and the other end is connected to the gate voltage suppression semiconductor element 20, and more specifically, to the gate of the gate voltage suppression semiconductor element 20. In other words, the gate of the gate voltage suppression semiconductor element 20 is electrically connected to the voltage detection circuit 5, and in the example shown in Figure 2, it is connected to node A of the voltage detection circuit 5 via the suppression time adjustment capacitor 21. Furthermore, the drain of the gate voltage suppression semiconductor element 20 is connected to the gate of the power semiconductor element 8, and in the example shown in Figure 2, it is connected to the gate of the power semiconductor element 8 via the gate voltage suppression resistor 17. In addition, the source of the gate voltage suppression semiconductor element 20 is connected to the source of the power semiconductor element 8. The gate voltage suppression time adjustment resistor 18 and the suppression time adjustment capacitor 22 each have one end connected between the suppression time adjustment capacitor 21 and the gate of the gate voltage suppression semiconductor element 20, and the other end connected to the source of the power semiconductor element 8. One end of the gate voltage suppression resistor 17 is connected to the drain of the gate voltage suppression semiconductor element 20, and the other end is connected between the drive terminals of the drive element 6 (output terminal for turn-on, output terminal for turn-off, and output terminal for short-circuit interruption) and the gate of the power semiconductor element 8.

[0033] The configuration of the main current suppression circuit 7 described above can be rephrased as follows, centering on node C as illustrated in Figure 2. That is, node C is connected to node A of the voltage detection circuit 5 via a suppression time adjustment capacitor 21. Node C is also connected to the gate of the gate voltage suppression semiconductor element 20. Furthermore, node C is connected to the source of the power semiconductor element 8 via a gate voltage suppression time adjustment resistor 18, and also to the source of the power semiconductor element 8 via a suppression time adjustment capacitor 22. If a negative voltage is used as the gate voltage when the power semiconductor element 8 is turned off, node C may be connected to a terminal connected to a negative power supply via the gate voltage suppression time adjustment resistor 18 or the suppression time adjustment capacitor 22, rather than to the source of the power semiconductor element 8.

[0034] In the example shown in Figure 2, the suppression time adjustment capacitors 21 and 22 are charged according to the reference voltage RV(a) between node A of the voltage detection circuit 5 and the source of the power semiconductor element 8. The voltage Vc between node C and the source of the power semiconductor element 8 is determined by the suppression time adjustment capacitors 21 and 22 and the gate voltage suppression time adjustment resistor 18. The time for which the gate voltage suppression semiconductor element 20 is turned on (on-state duration OSD) is determined by this voltage Vc. When the gate voltage suppression semiconductor element 20 is turned on, the gate voltage applied to the gate of the power semiconductor element 8 decreases, and along with the decrease in the gate voltage of the power semiconductor element 8, the element current of the power semiconductor element 8 also decreases, that is, the large current flowing through the power semiconductor element 8 decreases.

[0035] Specifically, the gate voltage suppression semiconductor element 20 is configured to turn on when the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds a second threshold ST, thereby reducing the gate voltage of the power semiconductor element 8. For example, the threshold voltage TV of the gate voltage suppression semiconductor element 20 is predetermined so that the gate voltage suppression semiconductor element 20 turns on when the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the second threshold ST. That is, as described above, the voltage Vc between node C and the source of the power semiconductor element 8 fluctuates according to a reference voltage RV (reference voltage RV(a) in the example shown in Figure 2), and the reference voltage RV is a voltage that can identify the voltage MV (drain-source voltage) corresponding to the element current of the power semiconductor element 8. Therefore, the threshold voltage TV of the gate voltage suppression semiconductor element 20 is predetermined so that when the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the second threshold ST, the gate voltage suppression semiconductor element 20 turns on by the voltage Vc that fluctuates according to the voltage MV. Therefore, when the voltage Vc exceeds the threshold voltage TV, the gate voltage suppression semiconductor element 20 turns on, reducing the gate voltage of the power semiconductor element 8 and thereby reducing the large current flowing through the power semiconductor element 8.

[0036] Furthermore, since the second threshold ST is set to be less than or equal to the first threshold FT, the gate voltage of the power semiconductor element 8 is not cut off simply because the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the second threshold ST, and the drive element 6 (drive circuit 62) outputs the normal gate voltage. When the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the second threshold ST, it turns ON and reduces the normal gate voltage output from the drive circuit 62.

[0037] As described above, the voltage Vc between node C and the source of the power semiconductor element 8 fluctuates according to the reference voltage RV (in the example shown in Figure 2, reference voltage RV(a)) detected by the voltage detection circuit 5. That is, if the reference voltage RV rises, the voltage Vc also rises, and if the reference voltage RV falls, the voltage Vc also falls. The on / off state of the gate voltage suppression semiconductor element 20 is determined by the voltage Vc; in other words, the gate voltage suppression semiconductor element 20 turns on and off according to the reference voltage RV. In this embodiment, the gate voltage suppression semiconductor element 20 turns on and off according to the reference voltage RV, or in other words, controls the gate voltage applied to the gate of the power semiconductor element 8 according to the reference voltage RV. Specifically, the gate voltage suppression semiconductor element 20 turns on when the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the second threshold ST, and reduces the gate voltage of the power semiconductor element 8.

[0038] Therefore, the power converter M can reduce the gate voltage of the power semiconductor element 8 when the voltage MV corresponding to the element current exceeds a second threshold ST, by using a gate voltage suppression semiconductor element 20 that turns on and off according to a reference voltage RV. In particular, the gate voltage suppression semiconductor element 20, which turns on when the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the second threshold ST (i.e., when a large current is generated) and reduces the gate voltage of the power semiconductor element 8, turns on and off according to the reference voltage RV. Therefore, compared to the case where the on / off of the gate voltage suppression semiconductor element 20 is controlled using a small voltage (for example, the gate voltage applied from the driving element 6 to the gate of the power semiconductor element 8), the power converter M achieves the following effects. That is, the power converter M can use a sufficiently high reference voltage RV to control the on / off of the gate voltage suppression semiconductor element 20, and can control the gate voltage suppression semiconductor element 20 accurately and effectively using such reference voltage RV. In particular, the power converter M can use the high-voltage reference voltage RV used for short-circuit detection to suppress the element current (main current) of the power semiconductor element 8 when a large current is generated, and can directly control the gate voltage of the power semiconductor element 8 in accordance with the high-voltage reference voltage RV.

[0039] The gate voltage suppression semiconductor element 20 turns off when the voltage MV corresponding to the element current of the power semiconductor element 8 falls below the second threshold ST. For example, when the voltage Vc falls below the threshold voltage TV of the gate voltage suppression semiconductor element 20, the gate voltage suppression semiconductor element 20 turns off. As described above, the drive element 6 does not cut off the gate voltage if the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the second threshold ST, and instead outputs the normal gate voltage. Therefore, when the gate voltage suppression semiconductor element 20 turns off, the gate voltage suppression semiconductor element 20 is applied to the gate of the power semiconductor element 8. In other words, when the voltage MV corresponding to the element current of the power semiconductor element 8 falls below the second threshold ST, the gate voltage suppression semiconductor element 20 turns off, and the gate voltage of the power semiconductor element 8 returns to the value it was when the voltage MV corresponding to the element current was below the second threshold ST (the normal gate voltage).

[0040] In this embodiment, the time (period) from when the gate voltage suppression semiconductor element 20 turns ON until it returns to the OFF state is referred to as the "ON state duration OSD". In the power conversion device M (particularly the control circuit unit 3), a suppression time adjustment capacitor 21 is inserted between the gate of the gate voltage suppression semiconductor element 20 and the voltage detection circuit 5 (node ​​A of the voltage detection circuit 5). The ON state duration OSD is adjusted by the capacitance of the suppression time adjustment capacitor 21; in other words, the capacitance of the suppression time adjustment capacitor 21 is predetermined in order to set the ON state duration OSD to a desired time (period). In the example shown in Figure 2, the ON state duration OSD is adjusted by the capacitance of the suppression time adjustment capacitor 21, the resistance value of the gate voltage suppression time adjustment resistor 18, and the capacitance of the suppression time adjustment capacitor 22. The gate voltage suppression semiconductor element 20 returns to the off state after a predetermined on-state duration OSD has elapsed, so that the power converter M can minimize power loss associated with false detections, such as when it falsely detects a large current. Furthermore, the power converter M can adjust the on-state duration OSD by adjusting the capacitance of the suppression time adjustment capacitor 22 without using components such as timers, meaning that the on-state duration OSD can be adjusted with a simple configuration while preventing an increase in circuit size.

[0041] As described above, the ON state duration OSD is adjusted by the capacitance of the suppression time adjustment capacitor 21. For example, the ON state duration OSD may be adjusted as follows: The ON state duration OSD may be adjusted to be longer than or equal to the maximum time required from the point when the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the second threshold ST until the point when the voltage MV corresponding to the element current exceeds the first threshold FT. In other words, the ON state duration OSD may be adjusted so that the short-circuit determination circuit 4 can determine whether a short circuit has occurred in the power semiconductor element 8 while the gate voltage suppression semiconductor element 20 is in the ON state. By adjusting the ON state duration OSD to such a time, the power converter M can determine whether a short circuit has occurred in the power semiconductor element 8 while the gate voltage suppression semiconductor element 20 is in the ON state and suppressing the element current (large current) of the power semiconductor element 8. In other words, the power converter M can perform the short-circuit detection described above while the gate voltage suppression semiconductor element 20 is in the ON state (in other words, while suppressing the element current of the power semiconductor element 8). For example, the power converter M can reduce turn-off losses when it determines that a short circuit has occurred in the power semiconductor element 8 and performs overcurrent suppression processing.

[0042] The ON state duration OSD may be further adjusted such that "the gate voltage suppression semiconductor element 20 returns to the OFF state between the time the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the first threshold FT and the drive element 6 starts interrupting the gate voltage of the power semiconductor element 8, and the time the interruption is completed." In other words, the ON state duration OSD may be adjusted such that "the gate voltage suppression semiconductor element 20 returns to the OFF state during the interruption of the gate voltage by the protection circuit 61." By adjusting the ON state duration OSD to such a time, the power converter M can slow down the gate voltage interruption speed and reduce surge voltage.

[0043] So far, an example has been described in which the main current suppression circuit 7 includes a gate voltage suppression time adjustment resistor 18, suppression time adjustment capacitors 21 and 22 to adjust the on-state duration OSD of the gate voltage suppression semiconductor element 20. However, for the main current suppression circuit 7, it is not essential to connect each of the gate voltage suppression time adjustment resistor 18, suppression time adjustment capacitors 21 and 22 to the gate voltage suppression semiconductor element 20 as illustrated in FIG. 2 in order to adjust the on-state duration OSD. The main current suppression circuit 7 may adjust the on-state duration OSD, for example, without using the suppression time adjustment capacitor 22. Similarly, the main current suppression circuit 7 may adjust the on-state duration OSD without using the gate voltage suppression time adjustment resistor 18. Further, the main current suppression circuit 7 may further include at least one of a resistor and a capacitor in addition to the gate voltage suppression time adjustment resistor 18, suppression time adjustment capacitors 21 and 22. The main current suppression circuit 7 may include at least one of a resistor and a capacitor connected in series or in parallel to at least one of the gate voltage suppression time adjustment resistor 18, gate voltage suppression semiconductor element 20, and suppression time adjustment capacitors 21 and 22.

[0044] Also, it is not essential to realize the gate voltage suppression semiconductor element 20 by a MOSFET. The gate voltage suppression semiconductor element 20 may be realized, for example, by a power transistor or by using an element such as an IGBT. When the gate voltage suppression semiconductor element 20 is realized by using a bipolar transistor, the source, drain, and gate of the gate voltage suppression semiconductor element 20 can be respectively read as the emitter, collector, and base. Similarly, the gate voltage of the gate voltage suppression semiconductor element 20 can be read as the base current.

[0045] Furthermore, it is not essential that the main current suppression circuit 7 includes a gate voltage suppression resistor 17; the drain of the gate voltage suppression semiconductor element 20 may be directly connected to the gate of the power semiconductor element 8. Alternatively, the main current suppression circuit 7 may use a diode (for example, a Zener diode for voltage clamping) instead of the gate voltage suppression resistor 17.

[0046] In the main current suppression circuit 7, the suppression time adjustment capacitor 21 is discharged when the reference voltage RV decreases in accordance with the decrease in the voltage MV corresponding to the element current of the power semiconductor element 8. For example, when the power semiconductor element 8 is turned off by the drive element 6, the reference voltage RV also decreases, and the suppression time adjustment capacitor 21 is discharged. Since the power semiconductor element 8 repeatedly turns on and off periodically, the suppression time adjustment capacitor 21, which was charged when the power semiconductor element 8 was turned on, will be discharged at the timing when the power semiconductor element 8 turns off in the next cycle after that turn-on. Therefore, the power converter M can make the on-state duration OSD when the power semiconductor element 8 is turned on in a certain period and the on-state duration OSD when the power semiconductor element 8 is turned on in the next period after that period to be the same. As described above, the power converter M is used, for example, in an inverter for driving automobiles. Therefore, for example, when the power converter M operates continuously as an inverter (periodically repeating the control of turning the power semiconductor element 8 on and off), the power converter M can use the same ON state duration OSD for multiple cycles.

[0047] In particular, in the example shown in FIG. 2, node A is connected to the output terminal for turning on the drive element 6 via the voltage detection and current adjustment resistor 11. Therefore, the suppression time adjustment capacitors 21 and 22 are discharged when the power semiconductor element 8 turns off, that is, when no gate voltage is applied from the output terminal for turning on the drive element 6 to the gate of the power semiconductor element 8. In other words, the suppression time adjustment capacitors 21 and 22 charged when the power semiconductor element 8 turns on are discharged when the next turn-off occurs after such a turn-on. Therefore, when the power conversion device M turns on the power semiconductor element 8 in the next cycle, the suppression time adjustment capacitors 21 and 22 can be operated with the same waveform as when the power semiconductor element 8 was turned on in the previous cycle.

[0048] (Consideration of Voltage Detection Circuit) In the present embodiment, the voltage detection circuit included in the power conversion device M only needs to be one that can detect a reference voltage RV at one end connected to the drain of the power semiconductor element 8 and capable of specifying a voltage MV corresponding to the element current of the power semiconductor element 8, and does not necessarily need to have the configuration illustrated in FIG. 2. Hereinafter, with reference to FIG. 3, a voltage detection circuit according to the present embodiment having a configuration different from the configuration illustrated in FIG. 2 will be described.

[0049] Instead of the control circuit unit 3 illustrated in FIG. 2, the power conversion device M may include the control circuit unit 3' illustrated in FIG. 3. The control circuit unit 3' is the same as the control circuit unit 3 except that it includes a voltage detection circuit 5' instead of the voltage detection circuit 5 illustrated in FIG. 2. Therefore, hereinafter, among the configurations included in the control circuit unit 3' (the short-circuit determination circuit 4, the voltage detection circuit 5', the drive element 6, and the main current suppression circuit 7), the description of the configurations other than the voltage detection circuit 5' will be omitted as appropriate.

[0050] Voltage detection circuit 5' is an example of the "voltage detection circuit" of the present invention, and as illustrated in Figure 3, one end is connected to the drain of the power semiconductor element 8, and it detects a reference voltage RV that can identify the voltage MV corresponding to the element current of the power semiconductor element 8. However, voltage detection circuit 5' differs from voltage detection circuit 5, which detects a reference voltage RV(b) as the reference voltage RV, in that it detects a reference voltage RV(b') as the reference voltage RV. The reference voltage RV(b') is the voltage between node B' in Figure 3 and the source of the power semiconductor element 8.

[0051] Specifically, the voltage detection circuit 5' illustrated in Figure 3 includes a short-circuit detection current source 43, voltage divider resistors 31 and 32, a voltage detection diode element 38, and a short-circuit detection time adjustment capacitor 42. In the voltage detection circuit 5', when current is supplied from the short-circuit detection current source 43, the short-circuit detection time adjustment capacitor 42 is charged, and the reference voltage RV(a') between node A' and the source of the power semiconductor element 8 rises. The voltage detection circuit 5' detects a reference voltage RV(b') obtained by adjusting the reference voltage RV(a') with the voltage divider resistor 32 or the like.

[0052] In the control circuit 3', the voltage Vc between node C and the source of the power semiconductor element 8 fluctuates according to the reference voltage RV, similar to the control circuit 3 illustrated in Figure 2. However, in the control circuit 3', the voltage Vc fluctuates according to the reference voltage RV(a'). Except for this point, the main current suppression circuit 7 of the control circuit 3' is the same as the main current suppression circuit 7 of the control circuit 3.

[0053] Furthermore, the short-circuit detection circuit 4 in the control circuit unit 3' takes a reference voltage RV as input and determines whether the voltage MV corresponding to the element current exceeds a first threshold FT, that is, whether a short circuit has occurred in the power semiconductor element 8, just as in the short-circuit detection circuit 4 of the control circuit unit 3. However, in the control circuit unit 3', the short-circuit detection circuit 4 takes a reference voltage RV(b') detected by the voltage detection circuit 5' as input and makes the determination. The reference voltage RV(a') and reference voltage RV(b') are, respectively, voltages that can specify the voltage MV corresponding to the element current, just as in the reference voltage RV(a) and reference voltage RV(b).

[0054] In the example shown in Figure 3, node A' is connected to the drain of the power semiconductor element 8 via a voltage detection diode element 38. That is, one end of the voltage detection diode element 38 is connected to the drain of the power semiconductor element 8, and the other end is connected to node A'. Furthermore, node A' is connected to node B', and in the illustrated example, it is connected to node B' via a voltage divider resistor 31. In addition, node A' is connected to the short-circuit detection current source 43 and the suppression time adjustment capacitor 21 of the main current suppression circuit 7.

[0055] Node B' is connected to node A' via voltage divider resistor 31, and also to the source of the power semiconductor element 8 via voltage divider resistor 32. One end of the short-circuit detection time adjustment capacitor 42 is connected between voltage divider resistor 32 and the source of the power semiconductor element 8, and the other end is connected between voltage divider resistor 31 and node A'.

[0056] As explained above, the control circuit 3' is the same as the control circuit 3, except that the voltage detection circuit 5' detects a reference voltage RV(b') instead of a reference voltage RV(b) as a reference voltage RV. Therefore, the power converter M including the control circuit 3' can perform the same processing as the power converter M including the control circuit 3, and can achieve the same effects as the power converter M including the control circuit 3.

[0057] Furthermore, in the control circuit section 3', the short-circuit detection circuit 4 includes the following circuit in addition to the configuration illustrated in Figure 2. Specifically, the short-circuit detection circuit 4 includes a circuit (not shown) for dischargering the short-circuit detection time adjustment capacitor 42 while the gate voltage of the power semiconductor element 8 is off. With this circuit, in addition to the short-circuit detection time adjustment capacitor 42, the suppression time adjustment capacitors 21 and 22 can also be discharged.

[0058] Just as it was not essential for the voltage detection circuit 5 to include the voltage divider resistors 12 and 13, the voltage detection circuit 5' does not need to include the voltage divider resistors 31 and 32. In the example shown in Figure 3, the short-circuit detection circuit 4 is input with reference voltage RV(b'), but the short-circuit detection circuit 4 may also be input with reference voltage RV(a'). In other words, the short-circuit detection circuit 4 may use the reference voltage RV(a') to determine whether the voltage MV corresponding to the element current of the power semiconductor element 8 exceeds the first threshold FT.

[0059] (Consideration of the driving element) In this embodiment, the driving element provided in the power converter M only needs to interrupt the gate voltage of the power semiconductor element 8 when it receives a short-circuit detection signal SCS from the short-circuit detection circuit 4, and does not need to have the configuration illustrated in Figure 2. The driving element according to this embodiment, which has a configuration different from the one illustrated in Figure 2, will be described below with reference to Figure 4.

[0060] The power converter M may include a control circuit 3'' as illustrated in Figure 4 instead of the control circuit 3 illustrated in Figure 2. The control circuit 3'' includes a drive element 6'' instead of the drive element 6 illustrated in Figure 2, and the drive element 6'' includes a terminal for an active mirror clamp (active mirror clamp terminal). The "active mirror clamp terminal" provided by the drive element 6'' is an example of the "clamp terminal" of the present invention. The main current suppression circuit 7'' is connected to the active mirror clamp terminal, and specifically, the gate of the gate voltage suppression semiconductor element 20 is connected to the active mirror clamp terminal of the drive element 6''. Except for these points, it is the same as the control circuit 3. Therefore, in the following, among the configurations provided by the control circuit 3'' (short circuit determination circuit 4, voltage detection circuit 5, drive element 6'', and main current suppression circuit 7''), the configurations other than the drive element 6'' and the main current suppression circuit 7'' will be omitted from explanation as appropriate.

[0061] The drive element 6'', like the drive element 6, is equipped with an output terminal for turn-on, an output terminal for turn-off, and an output terminal for short-circuit interruption. However, in addition to these output terminals, the drive element 6'' is further equipped with an active Miller clamp terminal. The active Miller clamp is a function to prevent the power semiconductor element 8 from being erroneously turned on. For example, in elements that constitute two arms (semiconductor elements) connected in series with each other, such as the power semiconductor elements 8A and 8B illustrated in Figure 1, if one arm is turned on while the other arm is turned off, the following situation may occur. That is, current may flow out from the gate due to the parasitic capacitance of the semiconductor element, and a voltage may be induced in the gate resistance, causing the gate-source voltage to rise and resulting in an erroneous turn-on. The active Miller clamp circuit is a circuit that prevents such a situation from occurring. That is, the active Miller clamp circuit is a circuit that connects the gate and source with low resistance using a MOSFET or the like near the gate of the semiconductor element so that a gate voltage is not erroneously induced when the semiconductor element is turned off. The active mirror clamp terminal of the driving element 6'' is a terminal for clamping the gate voltage of the power semiconductor element 8, and is a terminal that applies an ON signal to the MOSFET of the active mirror clamp circuit. In the example shown in Figure 4, the active mirror clamp terminal of the driving element 6'' applies an ON signal to the main current suppression circuit 7'' which operates as an active mirror clamp circuit.

[0062] In the example shown in Figure 4, the active mirror clamp terminal of the driving element 6'' is connected to node C'' of the main current suppression circuit 7'', and in the main current suppression circuit 7'', node C'' is connected to the gate voltage suppression semiconductor element 20. In particular, in the illustrated example, node C'' is connected to the gate of the gate voltage suppression semiconductor element 20. That is, in the control circuit section 3'', the active mirror clamp terminal of the driving element 6'' is connected to the gate of the gate voltage suppression semiconductor element 20. Furthermore, node C'' is connected to node A of the voltage detection circuit 5 via a suppression time adjustment capacitor 21. In addition, node C'' is connected to the source of the power semiconductor element 8 via a gate voltage suppression time adjustment resistor 18, and is also connected to the source of the power semiconductor element 8 via a suppression time adjustment capacitor 22. Between the active mirror clamp terminal of the driving element 6'' and node C'' of the main current suppression circuit 7'', (A) an active mirror clamp resistor 64 and (B) an active mirror clamp diode element 65 and an active mirror clamp capacitor 66 connected in series are connected in parallel.

[0063] The main current suppression circuit 7'' (especially the gate voltage suppression semiconductor element 20) operates similarly to the main current suppression circuit 7 in the control circuit unit 3 as a "circuit that suppresses the large current (element current of the power semiconductor element 8) flowing through the power semiconductor element 8 when a large current is generated." In addition, in the control circuit unit 3'', the gate voltage suppression semiconductor element 20 is connected to the active mirror clamp terminal of the driving element 6'', thereby forming an active mirror clamp circuit. In other words, the main current suppression circuit 7'' also operates as an active mirror clamp circuit. Therefore, the control circuit unit 3'' can reduce (reduce) the number of components compared to a configuration that provides an active mirror clamp circuit separately from the "circuit that suppresses the large current flowing through the power semiconductor element 8 when a large current is generated."

[0064] In the control circuit section 3'', the active mirror clamp resistor 64 is provided to adjust the voltage applied to the gate of the gate voltage suppression semiconductor element 20. For example, the active mirror clamp resistor 64 is provided to adjust the voltage applied from the active mirror clamp terminal to the gate of the gate voltage suppression semiconductor element 20. However, it is not essential for the control circuit section 3'' to include the active mirror clamp resistor 64. For example, if it is not necessary to adjust the voltage applied from the active mirror clamp terminal to the gate of the gate voltage suppression semiconductor element 20, the control circuit section 3'' may not include the active mirror clamp resistor 64.

[0065] In the control circuit section 3'', the diode element 65 for active mirror clamping and the capacitor 66 for active mirror clamping are provided to ensure that the main current suppression circuit 7'' operates properly as an active mirror clamping circuit. As described above, the power semiconductor element 8 repeatedly switches on and off periodically. When the power semiconductor element 8 is turned on, the suppression time adjustment capacitor 22 of the main current suppression circuit 7'' is charged. Therefore, in order for the main current suppression circuit 7'' to operate properly as an active mirror clamping circuit, it is desirable to rapidly discharge the suppression time adjustment capacitor 22 at the timing when the power semiconductor element 8 turns off, following the on-state. Accordingly, the control circuit section 3'' uses the diode element 65 and the capacitor 66 for active mirror clamping to rapidly discharge the suppression time adjustment capacitor 22 at the timing when the power semiconductor element 8 turns off. However, it is not essential for the control circuit section 3'' to include the diode element 65 and the capacitor 66 for active mirror clamping. For example, if it is not necessary to rapidly discharge the suppression time adjustment capacitor 22 at the timing when the power semiconductor element 8 turns off, the control circuit unit 3'' does not need to include the active mirror clamp diode element 65 and the active mirror clamp capacitor 66. Alternatively, the control circuit unit 3'' may include another configuration for rapidly discharging the suppression time adjustment capacitor 22 at the timing when the power semiconductor element 8 turns off, instead of the active mirror clamp diode element 65 and the active mirror clamp capacitor 66.

[0066] Furthermore, if a negative voltage is used as the gate voltage when the power semiconductor element 8 is turned off, one end of each of the gate voltage suppression time adjustment resistor 18, the gate voltage suppression semiconductor element 20, and the suppression time adjustment capacitor 22 may be connected to a terminal connected to a negative power supply (a negative voltage power supply potential) instead of the source terminal of the power semiconductor element 8. With this configuration, the control circuit unit 3'' can appropriately discharge the suppression time adjustment capacitor 22 at the timing when the power semiconductor element 8 is turned off.

[0067] As explained above, the control circuit section 3'' is the same as the control circuit section 3, except that the driving element 6'' is equipped with an active mirror clamp terminal, and the gate of the gate voltage suppression semiconductor element 20 is connected to the active mirror clamp terminal in addition to the voltage detection circuit 5 (node ​​A of the voltage detection circuit 5).

[0068] §3 Operation Example (Processing and Operation of Power Converter in Case of Short Circuit in Power Semiconductor) Figure 5 shows an example of an operation time chart when an overcurrent (short-circuit current in this embodiment) flows through the power semiconductor element 8 in the power converter M (a short circuit occurs), and in particular illustrates the changes over time of the drain-source voltage (voltage MV corresponding to the element current) of the power semiconductor element 8.

[0069] When a short circuit occurs in the power semiconductor element 8, a gate voltage is applied to the gate of the power semiconductor element 8 (indicated as "Gate voltage application start" in the figure), and even though element current begins to flow, both the drain-source voltage and the gate-source voltage of the power semiconductor element 8 remain high. As a result, the reference voltage RV(a) between node A and the source of the power semiconductor element 8 rises, and the reference voltage RV(b), obtained by dividing the reference voltage RV(a) with the voltage divider resistors 12 and 13, also rises. As the reference voltage RV(a) rises, the voltage Vc between node C and the source of the power semiconductor element 8 also rises, while the suppression time adjustment capacitors 21 and 22 are charged. Note that the voltage Vc does not have to change only in response to the reference voltage RV(a). For example, the voltage Vc may change via the parasitic capacitance of the gate voltage suppression semiconductor element 20 at the timing when the gate voltage is applied to the gate of the power semiconductor element 8.

[0070] When the voltage Vc between node C and the source of the power semiconductor element 8 rises and the voltage Vc exceeds the threshold voltage TV of the gate voltage suppression semiconductor element 20, the gate voltage suppression semiconductor element 20 turns on (indicated as "gate voltage suppression start" in the figure), and the gate voltage applied to the gate of the power semiconductor element 8 decreases. As a result, the element current of the power semiconductor element 8 is reduced, that is, the element current of the power semiconductor element 8 is suppressed. By reducing the element current of the power semiconductor element 8, the energy released when a short circuit occurs in the power semiconductor element 8 can be suppressed.

[0071] As described above, when the gate voltage suppression semiconductor element 20 is turned on, the gate voltage of the power semiconductor element 8 decreases. However, if a short circuit occurs in the power semiconductor element 8, the voltage MV corresponding to the element current of the power semiconductor element 8 remains high. In the example shown in Figure 5, after "gate voltage suppression starts" (the gate voltage suppression semiconductor element 20 is turned on), both the drain-source voltage of the power semiconductor element 8 and the element current of the power semiconductor element 8 decrease slightly, but neither decreases sufficiently. Therefore, even after the gate voltage suppression semiconductor element 20 is turned on, the reference voltage RV(a) continues to rise, and the reference voltage RV(b), obtained by dividing the reference voltage RV(a) with the voltage divider resistors 12 and 13, also increases in proportion to the reference voltage RV(a). Then, when the reference voltage RV(b) exceeds the corresponding first threshold CFT, the short-circuit detection circuit 4 determines that the drain-source voltage (voltage MV corresponding to the element current) of the power semiconductor element 8 exceeds the first threshold FT, that is, it determines that a short circuit has occurred in the power semiconductor element 8. Having determined that a short circuit has occurred in the power semiconductor element 8, the short-circuit detection circuit 4 outputs a short-circuit occurrence signal SCS to the drive element 6 (particularly the protection circuit section 61). Upon receiving the short-circuit occurrence signal SCS, the protection circuit section 61 cuts off the gate voltage applied to the gate of the power semiconductor element 8 (indicated as "Short-circuit cutoff start at the protection circuit section" in the figure). As a result, the drain-source voltage (voltage MV corresponding to the element current) of the power semiconductor element 8 decreases towards the off state and is then completely cut off.

[0072] In particular, at the time the protection circuit 61 cuts off the gate voltage of the power semiconductor element 8, the gate voltage suppression semiconductor element 20 is in the ON state. In other words, the gate voltage of the power semiconductor element 8 is reduced by the gate voltage suppression semiconductor element 20. Therefore, the power converter M can cut off the gate voltage of the power semiconductor element 8 when its gate voltage is low, thereby reducing turn-off losses during short-circuit interruption.

[0073] Furthermore, the ON state duration OSD is pre-adjusted so that the gate voltage suppression semiconductor element 20 turns off after the protection circuit unit 61 starts interrupting the gate voltage of the power semiconductor element 8. Specifically, the capacitance of the suppression time adjustment capacitor 21 is pre-determined so that after the protection circuit unit 61 starts interrupting the gate voltage of the power semiconductor element 8, the voltage Vc between node C and the source of the power semiconductor element 8 becomes less than the threshold voltage TV of the gate voltage suppression semiconductor element 20. By setting the timing for the gate voltage suppression semiconductor element 20 to return to the OFF state to after the gate voltage interruption starts, the power converter M can slow down the gate voltage interruption speed and reduce surge voltage. By setting the timing for the gate voltage suppression semiconductor element 20 to return to the OFF state to after the gate voltage interruption starts, the power converter M can prevent the gate voltage from being interrupted at high speed via the gate voltage suppression semiconductor element 20 during a short circuit interruption, thereby suppressing excessive surge voltage.

[0074] (Processing and operation of the power converter when only a large current flows and no short-circuit current flows) Figure 6 shows an example of an operation time chart in the power converter M when a large current flows (a large current is generated) without an overcurrent flowing (in this embodiment, no short-circuit current flows) through the power semiconductor element 8. In particular, Figure 6 illustrates the changes over time of the drain-source voltage (voltage MV corresponding to the element current) of the power semiconductor element 8 when a large current flows without a short circuit occurring.

[0075] When a large current flows through the power semiconductor element 8 (including when noise is applied to the power semiconductor element 8), a gate voltage is applied to the gate of the power semiconductor element 8 (indicated as "gate voltage application start" in the figure), and even when element current begins to flow, neither the drain-source voltage nor the gate-source voltage of the power semiconductor element 8 drops sufficiently. Therefore, the reference voltage RV(a) between node A and the source of the power semiconductor element 8 rises, and the voltage Vc between node C and the source of the power semiconductor element 8 also rises. When the voltage Vc exceeds the threshold voltage TV of the gate voltage suppression semiconductor element 20, the gate voltage suppression semiconductor element 20 turns on (indicated as "gate voltage suppression start" in the figure), and the gate voltage applied to the gate of the power semiconductor element 8 drops. However, since the reference voltage RV(a) does not rise as much as when a short circuit occurs in the power semiconductor element 8, the reference voltage RV(b) also does not rise, and the reference voltage RV(b) does not exceed the corresponding first threshold CFT. As the suppression time adjustment capacitor 21 charges, the voltage Vc between node C and the source of the power semiconductor element 8 decreases. When the voltage Vc falls below the threshold voltage TV of the gate voltage suppression semiconductor element 20, the gate voltage suppression semiconductor element 20 turns off (indicated as "gate voltage suppression ends" in the figure), and the gate voltage applied to the gate of the power semiconductor element 8 returns to the voltage that is not suppressed by the gate voltage suppression semiconductor element 20. In other words, when the gate voltage suppression semiconductor element 20 turns off, the gate voltage of the power semiconductor element 8 returns to the value it had when the voltage MV corresponding to the element current was less than the second threshold ST, or in other words, it returns to the "normal gate voltage". Then, the drive element 6 (especially the drive circuit 62) performs the normal turn-off operation (indicated as "normal turn-off" in the figure). Therefore, the power converter M can protect the power semiconductor element 8 from high currents, and the gate voltage suppression semiconductor element 20 returns to the off state after a predetermined on-state duration OSD has elapsed, thereby suppressing the deterioration of losses in the case where a short circuit did not occur in the power semiconductor element 8.

[0076] (Processing and operation of the power converter when neither short-circuit current nor high current flows) Figure 7 shows an example of an operation time chart in the power converter M when neither overcurrent (short-circuit current in this embodiment) nor high current flows through the power semiconductor element 8 (neither a short circuit nor a high current occurred). In particular, Figure 7 illustrates the changes over time of the drain-source voltage (voltage MV corresponding to the element current) of the power semiconductor element 8 when neither short-circuit current nor high current flows.

[0077] When neither short-circuit current nor large current flows, a gate voltage is applied to the gate of the power semiconductor element 8 (indicated as "Gate voltage application start" in the figure), and when element current begins to flow, both the drain-source voltage and the gate-source voltage of the power semiconductor element 8 rise. However, the drain-source voltage of the power semiconductor element 8 (voltage MV corresponding to the element current) remains within the range of the rated voltage and is sufficiently low for both the first threshold FT and the second threshold ST. The current flowing through the voltage detection current adjustment resistor 11 flows to the power semiconductor element 8 via the voltage detection diode element 19, and the reference voltage RV(a) between node A and the source of the power semiconductor element 8 does not rise much. In line with the fact that the reference voltage RV(a) does not rise, the reference voltage RV(b), obtained by dividing the reference voltage RV(a) with the voltage divider resistors 12 and 13, and the voltage Vc between node C and the source of the power semiconductor element 8 also do not rise. Therefore, the voltage Vc never exceeds the threshold voltage TV of the gate voltage suppression semiconductor element 20, and the gate voltage suppression semiconductor element 20 never turns on. As a result, the gate voltage applied to the gate of the power semiconductor element 8 is not suppressed, and the power semiconductor element 8 operates with normal turn-on and turn-off (indicated as "normal turn-off" in the figure).

[0078] [Features] As described above, the power converter M according to this embodiment comprises a power semiconductor element 8, a voltage detection circuit 5 (or a voltage detection circuit 5'), a short-circuit detection circuit 4, a drive element 6 (or a drive element 6''), and a gate voltage suppression semiconductor element 20 (switching element). One end of the voltage detection circuit 5 (5') is connected to the drain of the power semiconductor element 8 and detects a reference voltage RV that can identify the voltage MV corresponding to the element current of the power semiconductor element 8. When the power semiconductor element 8 is realized using a bipolar transistor such as an IGBT, one end of the voltage detection circuit 5 (5') is connected to the collector of the power semiconductor element 8 and detects a reference voltage RV that can identify the voltage MV corresponding to the element current of the power semiconductor element 8. The short-circuit detection circuit 4 (overcurrent detection circuit) outputs a short-circuit generation signal SCS (overcurrent suppression signal) when the voltage MV corresponding to the element current identified by the reference voltage RV detected by the voltage detection circuit 5 (5') exceeds a predetermined first threshold FT. When the driving element 6 (6'') receives a short-circuit signal SCS from the short-circuit detection circuit 4, it cuts off the gate voltage of the power semiconductor element 8. When the power semiconductor element 8 is implemented using a bipolar transistor, the driving element 6 (6'') cuts off the base current of the power semiconductor element 8 when it receives a short-circuit signal SCS from the short-circuit detection circuit 4. The gate voltage suppression semiconductor element 20 has its drain or collector connected to the gate of the power semiconductor element 8, and its gate or base is electrically connected to the voltage detection circuit 5. The gate voltage suppression semiconductor element 20 is configured to turn on when the voltage MV corresponding to the element current exceeds a predetermined second threshold ST which is less than or equal to the first threshold FT, thereby reducing the gate voltage of the power semiconductor element 8. When the power semiconductor element 8 is implemented using a bipolar transistor, the gate voltage suppression semiconductor element 20 has its drain or collector connected to the base of the power semiconductor element 8, and its gate or base is electrically connected to the voltage detection circuit 5. When the power semiconductor element 8 is realized using a bipolar transistor, the gate voltage suppression semiconductor element 20 is configured to turn on when the voltage MV corresponding to the element current exceeds a predetermined second threshold ST which is less than or equal to the first threshold FT, thereby reducing the base current of the power semiconductor element 8.

[0079] According to this configuration, the power converter M includes a gate voltage suppression semiconductor element 20 that turns on and off in accordance with a reference voltage RV that can identify the voltage MV corresponding to the element current. The drain of the gate voltage suppression semiconductor element 20 is connected to the gate of the power semiconductor element 8, and the gate of the gate voltage suppression semiconductor element 20 is electrically connected to a voltage detection circuit 5 (5') that detects the reference voltage RV. The gate voltage suppression semiconductor element 20 is configured to turn on when the voltage MV corresponding to the element current exceeds a second threshold ST, thereby reducing the gate voltage of the power semiconductor element 8. The power converter M can reduce the gate voltage of the power semiconductor element 8 when the voltage MV corresponding to the element current exceeds the second threshold ST by using the gate voltage suppression semiconductor element 20 that turns on and off in accordance with a reference voltage RV that can identify the voltage MV corresponding to the element current. In other words, the power converter M can directly control the gate voltage of the power semiconductor element 8 in accordance with the reference voltage RV and protect the power semiconductor element 8 from large currents. In other words, the power converter M does not require a semiconductor regulator to control the gate voltage of the power semiconductor element 8 when a large current is detected, and can protect the power semiconductor element 8 from large currents using a switching element (gate voltage suppression semiconductor element 20). Therefore, the power converter M according to this embodiment can protect the power semiconductor element 8 from large currents, short-circuit currents, etc., while reducing the number of components.

[0080] §4 Modifications While embodiments of the present invention have been described in detail above, the descriptions above are merely illustrative of the present invention in all respects. It goes without saying that various improvements or modifications can be made without departing from the scope of the present invention. For example, the following modifications are possible. In the following, the same reference numerals are used for components similar to those in the above embodiments, and explanations of similar points are omitted as appropriate. The following modifications can be combined as appropriate.

[0081] 4...Short circuit detection circuit (overcurrent detection circuit), 5, 5'...Voltage detection circuit, 6, 6''...Drive element, 8...Power semiconductor element, 20...Gate voltage suppression semiconductor element (switching element), 21...Suppression time adjustment capacitor (capacitor), FT...First threshold, M...Power converter, MV...Voltage corresponding to the element current of the power semiconductor element, OSD...On state duration, RV...Reference voltage, SCS...Short circuit generation signal (overcurrent suppression signal), ST...Second threshold

Claims

1. A power converter comprising: a power semiconductor element; a voltage detection circuit having one end connected to the drain or collector of the power semiconductor element and detecting a reference voltage capable of identifying a voltage corresponding to the element current of the power semiconductor element; an overcurrent determination circuit that outputs an overcurrent suppression signal when the voltage corresponding to the element current identified by the reference voltage detected by the voltage detection circuit exceeds a predetermined first threshold; a driving element that interrupts the gate voltage or base current of the power semiconductor element when it receives the overcurrent suppression signal from the overcurrent determination circuit; and a switching element having its drain or collector connected to the gate or base of the power semiconductor element, and its gate or base electrically connected to the voltage detection circuit, wherein the switching element is configured to turn on when the voltage corresponding to the element current exceeds a predetermined second threshold less than or equal to the first threshold, thereby reducing the gate voltage or base current of the power semiconductor element.

2. When the voltage corresponding to the element current falls below the second threshold, the switching element turns off, and the gate voltage or base current of the power semiconductor element returns to the value it had when the voltage corresponding to the element current was below the second threshold; a capacitor is inserted between the gate or base of the switching element and the voltage detection circuit, which is charged according to the reference voltage; and the duration of the on state from when the switching element turns on to when it returns to the off state is adjusted by the capacitance of the capacitor, as described in claim 1.

3. The power conversion device according to claim 2, wherein the ON state duration is adjusted to be at least the maximum time required from the point in time when the voltage corresponding to the element current exceeds the second threshold to the point in time when the voltage corresponding to the element current further exceeds the first threshold.

4. The power conversion device according to claim 3, wherein the ON state duration is further adjusted such that the switching element returns to the OFF state between the time the voltage corresponding to the element current exceeds the first threshold and the drive element starts interrupting the gate voltage or base current of the power semiconductor element, and the time the interruption is completed.

5. The capacitor is discharged as the reference voltage decreases in accordance with the decrease in the voltage corresponding to the element current, according to any one of claims 2 to 4.

6. The power conversion device according to any one of claims 1 to 4, wherein the driving element is provided with a clamping terminal for clamping the gate voltage or base current of the power semiconductor element, and the gate or base of the switching element is connected to the clamping terminal, thereby the switching element constituting a clamping circuit.

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