Substrate processing method, etching apparatus, and electronic device

Abstract

The present invention provides a substrate processing method for processing the shape of an IGZO film, an etching apparatus, and an electronic device.　The substrate processing method includes: a step for preparing a substrate which has a base material, a core that is formed on the base material and has a line-and-space shape extending in a first direction, an IGZO film that covers the base material and the core, and a carbon film that is formed on the IGZO film and has a line-and-space shape extending in a second direction orthogonal to the first direction; and a step for generating plasma of an etching gas using a mixed gas of CH4 and H2 as the etching gas, and removing the IGZO film that is exposed from an opening of the carbon film by means of reactive ion etching.

Description

Substrate processing method, etching apparatus, and electronic device

[0001] This disclosure relates to a substrate processing method, an etching apparatus, and an electronic device.

[0002] Patent Document 1 discloses a method for forming a semiconductor device having a linear gate structure on the side wall of a linear dielectric structure.

[0003] U.S. Patent Application Publication No. 2022 / 0416088

[0004] In one aspect, this disclosure provides a substrate processing method, etching apparatus, and electronic device for processing the shape of an IGZO film.

[0005] To solve the above problems, according to one embodiment, a step of preparing a substrate having a base material, a core formed on the base material and having a line-and-space shape extending in a first direction, an IGZO film covering the base material and the core, and a carbon film formed on the IGZO film and having a line-and-space shape extending in a second direction perpendicular to the first direction, and using CH as the etching gas ４ and H ２ A substrate processing method is provided, comprising the steps of generating an etching gas plasma using a mixed gas and removing the IGZO film exposed from the opening of the carbon film by reactive ion etching.

[0006] In one aspect, this disclosure can provide a substrate processing method, etching apparatus, and electronic device for processing the shape of an IGZO film.

[0007] An example flowchart showing a substrate processing method for forming an electronic device. An example diagram illustrating a prepared substrate. An example diagram illustrating a prepared substrate. An example diagram illustrating a substrate after a core has been formed. An example diagram illustrating a substrate after a core has been formed. An example diagram illustrating a substrate after an IGZO film has been formed. An example diagram illustrating a substrate after an IGZO film has been formed. An example diagram illustrating a substrate after an SOC film has been formed. An example diagram illustrating a substrate after an SOC film has been formed. An example diagram illustrating a substrate after a hard mask layer has been formed. An example diagram illustrating a substrate after a hard mask layer has been formed. An example diagram illustrating a substrate after development treatment. An example diagram illustrating a substrate after development treatment. An example diagram illustrating a substrate after etching of the SOC film. An example diagram illustrating a substrate after etching of the SOC film. An example diagram illustrating a substrate after peeling off the IGZO film. An example diagram illustrating a substrate after peeling off the IGZO film. An example diagram illustrating a substrate after peeling off the IGZO film. An example diagram illustrating a substrate after ashing of the SOC film. An example of a diagram illustrating the substrate after ashing of the SOC film. An example of a diagram illustrating the substrate after ashing of the SOC film. An example of a diagram illustrating the substrate after forming an insulating film. An example of a diagram illustrating the substrate after forming an insulating film. An example of a diagram illustrating the substrate after forming an insulating film. An example of a diagram illustrating the substrate after forming a metal film. An example of a diagram illustrating the substrate after forming a metal film. An example of a diagram illustrating the substrate after etching of a metal film. An example of a diagram illustrating the substrate after etching of a metal film. An example of a diagram illustrating the substrate after etching of a metal film. An example of a diagram illustrating the substrate after etching of a metal film. An example of a diagram illustrating the substrate after etching of a metal film. An example of a diagram illustrating the substrate after etching of a metal film. An example of a diagram illustrating the substrate after etching of a metal film. An example of a diagram illustrating the substrate after etching of a metal film. An example of a diagram illustrating the substrate after channel separation. An example of a diagram illustrating the substrate after channel separation. An example of a graph showing the relationship between the etching gas and the etching rates of the IGZO film and core. An example of a graph showing the etching selectivity of the IGZO film for the core material. An example of a schematic diagram illustrating the temperature dependence of the IGZO film in reactive ion etching. An example of a schematic diagram illustrating the temperature dependence of reactive ion etching of IGZO films.An example of a graph showing the relationship between DC bias voltage and core damage. An example of a figure showing the relationship between the composition ratio of the IGZO film and high-frequency power HF. A graph showing an example of etching rate in citrate cleaning. An example of a graph explaining the etching control in citrate cleaning. An example of a block diagram showing substrate processing system 700. An example of a figure for explaining an example configuration of a capacitively coupled plasma processing apparatus (reactive ion etching apparatus).

[0008] The following describes embodiments for implementing this disclosure with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0009] [Method for Forming Electronic Devices] An example of a substrate processing method for forming electronic devices on a substrate W will be explained using Figures 1 to 15C. In Figures 2A to 15C, one horizontal direction will be referred to as the X direction (second direction), another horizontal direction perpendicular to the X direction will be referred to as the Y direction (first direction), and the height direction will be referred to as the Z direction.

[0010] Figure 1 is an example of a flowchart showing a substrate processing method for forming an electronic device. Here, the channel structure of a vertical channel transistor is formed as the electronic device. Vertical channel transistors are used, for example, in DRAMs. Furthermore, the explanation assumes that high-mobility IGZO (a semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O)) is used as the channel material for the electronic device.

[0011] In step S101, the substrate W is prepared. Figures 2A and 2B are examples of diagrams illustrating the prepared substrate W, where Figure 2A is an example of a schematic diagram of the substrate W viewed from above, and Figure 2B is an example of a schematic cross-sectional diagram cut at position B1-B1.

[0012] The substrate W comprises a base material 500, a core material layer 510, and mask structure layers (611-613).

[0013] The substrate 500 may be made of, for example, silicon (Si). Furthermore, circuits or the like that which are connected to electronic devices may be formed on the substrate 500.

[0014] A core material layer 510 is formed on the substrate 500. The core material layer 510 is made of a material for forming a core 511 (see Figures 3A to 3B, etc., described later) on which an IGZO film 520 is formed on the side walls.

[0015] On the core material layer 510, a mask structure layer is formed by sequentially stacking an SOC (spin-on carbon) film 611, an SOG (spin-on glass) film 612, and a resist film 613. The mask structure layer (611-613) is used to pattern the core material layer 510 and form the core 511. A line-and-space pattern is formed on the resist film 613 by exposure and development processes. Here, the resist film 613 has a line-and-space pattern extending in the Y direction. In other words, in the X direction, the resist film 613 has alternating line portions (the actual parts of the resist film 613) and space portions (the openings of the resist film 613).

[0016] In step S102, the mask structure layer (611-613) is used as a mask and the core 511 is etched down to the core 511 to form a line-and-space (L / S) shaped core 511. Figures 3A-3B are examples of diagrams illustrating the substrate W after the core 511 has been formed. Figure 3A is an example of a schematic diagram of the substrate W viewed from above, and Figure 3B is an example of a schematic cross-sectional diagram cut at position B2-B2.

[0017] Here, the core material layer 510 is etched using the mask structure layers (611 to 613) as a mask to form the core 511. That is, by etching the SOG film 612 using the resist film 613 in which a line-and-space shaped pattern is formed as a mask, an opening pattern is formed in the SOG film 612. Further, by etching the SOC film 611 using the SOG film 612 in which the opening pattern is formed as a mask, an opening pattern is formed in the SOC film 611. Finally, by etching the core material layer 510 using the SOC film 611 in which the opening pattern is formed as a mask, a line-and-space shaped pattern is formed in the core material layer 510. As a result, the core 511 having a line-and-space shape extending in the Y direction is formed. In other words, in the X direction, the core 511 has the line portions (the real parts of the core 511) and the space portions (the openings of the core 511) repeating alternately.

[0018] For the core material layer 510 (core 511), any one of, for example, SiN, SiON, SiCN, SiOCN, etc. can be used. It is preferable to use silicon nitride (SiNx) having high etching resistance in the process of etching the IGZO film 520 described later (see step S109) for the core material layer 510 (core 511).

[0019] For the etching of the core material layer 510, a fluorocarbon-based gas can be used as the etching gas. The fluorocarbon-based gas can be, for example, any one of gases such as C ４ F ８ , C ４ F ６ , C ３ F ８ , CH ２ F ２ , CHF ３ , etc. The etching gas may be added with an appropriate amount of gases such as O ２ , N ２ , Ar, He, etc.

[0020] The shape of the core 511 is a line and space shape, and the CD (critical dimension) value of the line portion, the CD value of the space portion, the height of the core 511, and the aspect ratio of the line portion are respectively Line CD = 10 to 30 nm Space CD = 20 to 50 nm Core height = 50 to 150 nm Line Aspect Ratio = 3 to 15 It is preferably within the range of

[0021] After forming the core 511 by etching the core material layer 510, the mask structure layer (SOC film 611, SOG film 612, resist film 613) is removed. Further, after forming the core 511 by etching the core material layer 510, cleaning treatments such as DHF cleaning, APM cleaning, and DIW cleaning are performed to remove fluorine residues and particles on the surface.

[0022] In step S103, an IGZO film 520 is formed. FIGS. 4A to 4B are examples of diagrams for explaining the substrate W after the IGZO film 520 is formed. FIG. 4A is an example of a schematic diagram of the substrate W viewed from above, and FIG. 4B is an example of a cross-sectional schematic diagram cut at the B3 - B3 position.

[0023] Here, an ALD (Atomic layer deposition) film-forming apparatus is used to form the IGZO film 520 on the substrate W. As a result, as shown in FIGS. 4A to 4B, the IGZO film 520 is formed on the upper surface and sidewalls of the line portion (core 511) and the bottom surface of the space portion (the upper surface of the exposed base material 500). The IGZO film 520 forms a channel of the electronic device by being elementally separated by a process described later.

[0024] The film thickness of the IGZO film 520 is preferably, for example, within the range of 1 to 10 nm. The composition ratio of the IGZO film 520 is preferably, for example, any one of In:Ga:Zn = 1:1:1, 1:1:2, 1:2:1, 2:1:1, 1:2:2, 2:1:2, 2:2:1, etc. Note that a trace amount of a Sn or Al precursor may be added during ALD film formation to form a Sn or Al-doped IGZO film 520.

[0025] In step S104, the SOC film 620 is formed. Figures 5A to 5B are examples of diagrams illustrating the substrate W after the SOC film 620 has been formed. Figure 5A is an example of a schematic diagram of the substrate W viewed from above, and Figure 5B is an example of a schematic cross-sectional diagram cut at position B4-B4.

[0026] Here, a spin coating method is used to form an SOC film 620 on the substrate W. This embeds the SOC film 620 on the space areas (recesses between cores 511) and line areas (cores 511). Furthermore, by using the spin coating method, the SOC film 620 can be formed on the IGZO film 520 in a void-free and well-adhering manner. Before forming the SOC film 620 on the substrate W, water washing or APM washing may be performed.

[0027] After embedding the SOC film 620, the surface of the SOC film 620 may extend approximately 10 to 50 nm beyond the surface (upper surface) of the IGZO film 520 formed on the upper surface of the core 511. That is, the film thickness of the SOC film 620 formed above the core 511 may be in the range of 10 to 50 nm.

[0028] In step S104, the carbon film (SOC film 620) was described as being embedded in the substrate W using a spin coating method, but the method is not limited to this, and a configuration in which the carbon film is embedded in the substrate W using a CVD method is also possible.

[0029] In step S105, a hard mask layer 630 is formed. Figures 6A to 6B are examples of diagrams illustrating the substrate W after the hard mask layer 630 has been formed. Figure 6A is an example of a schematic diagram of the substrate W viewed from above, and Figure 6B is an example of a schematic cross-sectional diagram cut at position B5-B5.

[0030] Here, the SOC film 620 formed in step S104 is used as a mask in the etching process of the IGZO film 520 (see step S109), which will be described later. The SOC film 620 is prone to pattern collapse due to the collapse of the line portions, making it difficult to form a thick film. Also, since the SOC film 620 formed on the core 511 is thin, there is a risk of insufficient etching resistance in the etching process of the IGZO film 520 (see step S109), which will be described later. For this reason, it is preferable to form a hard mask layer 630 on the SOC film 620. For example, a silicon oxide film (SiOx) can be used as the hard mask layer 630. The hard mask layer 630 may be completely consumed and removed during the etching process of the IGZO film 520 (see step S109), which will be described later. Furthermore, after the etching process of the IGZO film 520 described later (see step S109), the hard mask layer 630 may be removed by a CF plasma that suppresses damage to the core 511 (for example, SiN). Also, the hard mask layer 630 formed in step S105 may be omitted (see dashed arrow in Figure 1).

[0031] In step S106, a mask structure layer (641-643) is formed. Here, a mask structure layer is formed by sequentially stacking an SOC (spin-on carbon) film 641, an SOG (spin-on glass) film 642, and a resist film 643 on the substrate W.

[0032] In step S107, exposure and development processes are performed. Figures 7A to 7C are examples of diagrams illustrating the substrate W after the development process. Figure 7A is an example of a schematic diagram of the substrate W viewed from above. Figure 7B is an example of a schematic cross-sectional diagram cut at position B6-B6. Figure 7C is an example of a schematic cross-sectional diagram cut at position C6-C6.

[0033] By applying exposure and development processes, a line-and-space pattern is formed on the resist film 643. Here, the line-and-space pattern formed on the resist film 643 is formed in a direction perpendicular to the line-and-space shape of the core 511 that extends in the Y direction. That is, the resist film 643 has a line-and-space pattern that extends in the X direction. In other words, in the Y direction, the resist film 643 consists of alternating line portions (the actual parts of the resist film 643) and space portions (the openings of the resist film 643).

[0034] The resist film 613 has a line-and-space shape, and the CD values ​​of the line portion and the space portion are preferably within the ranges of Line CD = 10 to 30 nm and Space CD = 10 to 30 nm, respectively.

[0035] In step S108, the mask structure layers (641-643) are used as a mask to etch down to the SOC film 620, thereby forming an opening pattern up to the SOC film 620. In other words, in step S108, a line-and-space (L / S) shaped SOC film 620 is formed that is perpendicular to the line-and-space (L / S) shaped core 511. Figures 8A-8C are examples of diagrams illustrating the substrate W after etching of the SOC film 620. Figure 8A is an example of a schematic diagram of the substrate W viewed from above. Figure 8B is an example of a schematic cross-sectional diagram cut at position B7-B7. Figure 8C is an example of a schematic cross-sectional diagram cut at position C7-C7.

[0036] Here, an opening pattern is formed on the SOG film 642 by etching the SOG film 642 using the resist film 643, on which a line-and-space pattern is formed, as a mask. Furthermore, an opening pattern is formed on the SOC film 641 by etching the SOC film 641 using the SOG film 642, on which the opening pattern is formed, as a mask. Finally, the hard mask layer 630 and the SOC film 620 are etched using the SOC film 641, on which the opening pattern is formed, as a mask. As a result, an SOC film 620 having a line-and-space (L / S) shape extending in the direction perpendicular to the core 511 (X direction) is formed on the core 511, which has a line-and-space (L / S) shape extending in the Y direction. In other words, in the Y direction, the SOC film 620 has alternating line portions (the actual parts of the SOC film 620) and space portions (the openings of the SOC film 620).

[0037] At position B7-B7 shown in Figure 8B, this is the line portion where the SOC film 620 is formed, and the IGZO film 520 is covered by the SOC film 620. On the other hand, at position C7-C7 shown in Figure 8C, this is the space portion that is the opening of the SOC film 620, and the IGZO film 520 is exposed.

[0038] Specifically, by the process from step S101 to step S108, a substrate W is prepared having a base material 500, a core 511 formed on the base material 500 and having a line-and-space shape extending in a first direction (Y direction), an IGZO film 520 covering the base material 500 and the core 511, and an SOC film (carbon film) 620 formed on the IGZO film 520 and having a line-and-space shape extending in a second direction (X direction) perpendicular to the first direction (Y direction).

[0039] In step S109, the IGZO film 520 exposed from the opening of the SOC film 620 is peeled off. Figures 9A to 9C are examples of diagrams illustrating the substrate W after the IGZO film 520 has been peeled off. Figure 9A is an example of a schematic diagram of the substrate W viewed from above, Figure 9B is an example of a schematic cross-sectional diagram cut at position B8-B8, and Figure 9C is an example of a schematic cross-sectional diagram cut at position C8-C8.

[0040] Here, the substrate W is anisotropically etched using reactive ion etching (RIE) technology, leaving the IGZO film 520 covered with the SOC film 641, while completely removing the IGZO film 520 not covered with the SOC film 641 (the IGZO film 520 exposed from the openings in the SOC film 620). Here, the IGZO film 520 formed on the upper surface of the core 511 and the upper surface of the substrate 500 is removed by reactive ion etching. Furthermore, the IGZO film 520 formed on the sidewall of the core 511 is removed by etching from top to bottom while suppressing wear of the core 511, by using an etching gas with a high etching selectivity ratio for the IGZO film 520 relative to the core 511 (e.g., SiN).

[0041] The etching gas is CH ４ and H ２ A mixed gas of CH can be used. ４ and H ２ Flow ratio (CH ４ : H ２ The ratio is preferably in the range of 1:2 to 1:10. The substrate temperature is preferably in the range of 60°C to 200°C. Furthermore, for high aspect ratio reactive ion etching, the pressure is preferably in the range of 1 to 20 mT.

[0042] The power of the high-frequency power (HF) used for plasma generation may be appropriately changed depending on the composition ratio of the IGZO. For example, if In:Ga:Zn = 1:1:1, it may be 600W. For example, if In:Ga:Zn = 1:2:1, it may be 1200W.

[0043] Furthermore, the power of the high-frequency bias power LF applied to the lower electrode on the mounting table on which the substrate W is placed is preferably kept low in order to suppress damage to the core 511 (for example, SiN). Also, the absolute value of the negative DC bias voltage applied to the lower electrode on the mounting table on which the substrate W is placed is preferably in the range of 20 to 400 V.

[0044] Furthermore, the substrate processing apparatus (plasma etching apparatus) for reactive ion etching may have a lower two-frequency configuration in which high-frequency power HF for plasma generation and high-frequency power LF for bias are supplied to the lower electrode provided on the mounting stage on which the substrate W is placed, or it may have an upper and lower two-frequency configuration in which high-frequency power LF for bias is supplied to the lower electrode provided on the mounting stage on which the substrate W is placed, and high-frequency power HF for plasma generation is supplied to the upper electrode facing the lower electrode. In addition, the substrate processing apparatus (plasma etching apparatus) may have opposing upper and lower electrodes and may be an apparatus that generates capacitively coupled plasma (CCP) between the electrodes to perform etching on the substrate W, or an apparatus that generates inductively coupled plasma (ICP) to perform etching on the substrate W, or an apparatus with other configurations.

[0045] At position B8-B8 shown in Figure 9B, the IGZO film 520 is covered by the SOC film 620 and remains without being removed by etching. On the other hand, at position C8-C8 shown in Figure 9C, the IGZO film 520 is peeled off (removed), exposing the core 511 and substrate 500.

[0046] In other words, the substrate W has a first region and a second region extending in a second direction (X direction) perpendicular to a first direction (Y direction). The first region is the region where the resist film 643 is formed (Figure 7B, position B6-B6). The second region is the region where an opening in the resist film 643 is formed (Figure 7C, position C6-C6). The first region is also the region where the SOC film 620 is formed (Figure 8B, position B7-B7). The second region is the region where an opening in the SOC film 620 is formed (Figure 8C, position C7-C7). The first region is also the region where the IGZO film 520 is formed (Figure 9B, position B8-B8). The second region is the region where the IGZO film 520 has been removed (Figure 9C, position C8-C8).

[0047] In step S110, citric acid cleaning is performed. Next, in step S111, the SOC film 620 is ashed. Figures 10A to 10C are examples of diagrams illustrating the substrate W after ashing of the SOC film 620. Figure 10A is an example of a schematic diagram of the substrate W viewed from above. Figure 10B is an example of a schematic cross-sectional diagram cut at position B9-B9. Figure 10C is an example of a schematic cross-sectional diagram cut at position C9-C9.

[0048] At this point, after the IGZO film 520 is peeled off, IGZO residue and / or deposits may adhere to the surface of the core 511. The substrate W is then cleaned using an aqueous solution of citric acid in a single-wafer washing machine or a batch washing machine. The concentration of citric acid is preferably in the range of 0.01 to 20 wt% (weight percent). Furthermore, at 5 wt%, the etching rate becomes saturated (see Figure 21 described later), so a concentration of citric acid in the range of 0.01 to 5 wt% is more preferable.

[0049] Citric acid etches only the IGZO, without etching the SOC film 620. Therefore, it removes IGZO residue and / or deposits from the surface of the core 511, and etches the IGZO film 520, which is located beneath the SOC film 620, from the sidewall side. It is preferable to keep the recess formed by etching the IGZO film 520 from the sidewall side to within 2 nm. Also, due to the high aspect ratio, a longer washing time is preferable to allow sufficient replacement of the chemical solution at the bottom of the recess. For this reason, in order to suitably remove IGZO residue and / or deposits from the surface of the core 511 while suppressing etching of the IGZO film 520 located beneath the SOC film 620 from the sidewall side, it is more preferable that the concentration of citric acid be in the range of 0.01 to 0.2 wt%.

[0050] Furthermore, the citric acid washing can be performed at room temperature. After the citric acid washing, the SOC film 620 is ashed.

[0051] At the position B9-B9 shown in Figure 10B, the SOC film 620 is removed by ashing, leaving the IGZO film 520. On the other hand, at the position C9-C9 shown in Figure 10C, the IGZO film 520 is peeled off (removed), exposing the core 511 and substrate 500.

[0052] Although the explanation described the procedure as performing citric acid cleaning (S110) followed by ashing (S111) of the SOC film 620, it is not limited to this. As shown by the dashed line in Figure 1, the SOC film 620 may also be ashed (S110A) followed by citric acid cleaning (S111A).

[0053] In this case, the aspect ratio of the recess can be reduced, allowing for sufficient replacement of the chemical solution at the bottom, thereby improving cleaning performance. On the other hand, the thickness of the IGZO film 520, which forms the channel, also becomes thinner. For this reason, in a configuration in which the SOC film 620 is ashed (S110A) first and then citric acid cleaning (S111A) is performed, it is preferable to increase the thickness of the IGZO film 520 formed in step S103 beforehand. By increasing the thickness of the IGZO film 520 in advance, taking into account the reduction in film thickness due to citric acid cleaning (S111A), the thickness of the IGZO film 520 after citric acid cleaning (S111A) can be set to the desired thickness.

[0054] In step S112, an insulating film 530 is formed. Figures 11A to 11C are examples of diagrams illustrating the substrate W after the insulating film 530 has been formed. Figure 11A is an example of a schematic diagram of the substrate W viewed from above. Figure 11B is an example of a schematic cross-sectional diagram cut at position B10-B10. Figure 11C is an example of a schematic cross-sectional diagram cut at position C10-C10.

[0055] Here, an insulating film 530 is formed on the substrate W using an ALD (Atomic Layer Deposition) film deposition apparatus. As a result, as shown in Figures 11A to 11C, the insulating film 530 is formed on the upper surface and side walls of the line portion and on the bottom surface of the space portion. The insulating film 530 can be any of the following: silicon oxide (SiOx), aluminum oxide (AlOx), hafnium oxide (HfOx), etc. The thickness of the insulating film 530 is preferably in the range of 2 to 10 nm.

[0056] At the position B10-B10 shown in Figure 11B, the IGZO film 520 and insulating film 530 are present on the upper surface and side walls of the line portion and on the bottom surface of the space portion. On the other hand, at the position C10-C10 shown in Figure 11C, the insulating film 530 is present on the upper surface and side walls of the line portion and on the bottom surface of the space portion.

[0057] In step S113, a metal film 540 is formed. Figures 12A to 12C are examples of diagrams illustrating the substrate W after the metal film 540 has been formed. Figure 12A is an example of a schematic diagram of the substrate W viewed from above. Figure 12B is an example of a schematic cross-sectional diagram cut at position B11-B11. Figure 12C is an example of a schematic cross-sectional diagram cut at position C11-C11.

[0058] Here, a metal film 540 is formed on the substrate W using an ALD (Atomic Layer Deposition) film deposition apparatus. As a result, as shown in Figures 12A to 12C, the metal film 540 is formed on the top surface and side walls of the line portion and the bottom surface of the space portion. The metal film 540 can be made of any of the following materials: titanium nitride (TiN), molybdenum (Mo), tungsten (W), etc. The thickness of the metal film 540 is preferably in the range of 2 to 10 nm. The metal film 540 is a film used as word line metal in electronic devices.

[0059] At the position B11-B11 shown in Figure 12B, the IGZO film 520, insulating film 530, and metal film 540 are present on the upper surface and side walls of the line portion and on the bottom surface of the space portion. On the other hand, at the position C11-C11 shown in Figure 12C, the insulating film 530 and metal film 540 are present on the upper surface and side walls of the line portion and on the bottom surface of the space portion.

[0060] In step S114, the metal film 540 is anisotropically etched. Figures 13A to 13C are examples of diagrams illustrating the substrate W after etching of the metal film 540. Figure 13A is an example of a schematic diagram of the substrate W viewed from above. Figure 13B is an example of a schematic cross-sectional diagram cut at position B12-B12. Figure 13C is an example of a schematic cross-sectional diagram cut at position C12-C12.

[0061] Here, the metal film 540 formed on the upper surface of the line portion and the bottom surface of the space portion is removed by etching using anisotropic etching. Specifically, an etching gas plasma is generated, and a negative bias voltage is applied to the mounting stage on which the substrate W is placed, thereby drawing the ions generated by the plasma into the substrate W and performing anisotropic etching. When the metal film 540 is titanium nitride (TiN) or tungsten (W), Cl is used as the etching gas. ２ Plasma etching is performed using a mixed gas of Ar. Alternatively, BCl is used as the etching gas. ３ , O ２ , N ２ The following may be added. If the metal film 540 is molybdenum (Mo), CF is used as the etching gas. ２ Plasma etching is performed using a mixed gas of Ar. Furthermore, NF is used as the etching gas. ３ SF ６ The following may be added:

[0062] In step S115, the insulating film 530 is anisotropically etched. Figures 14A to 14C are examples of diagrams illustrating the substrate W after etching of the metal film 540. Figure 14A is an example of a schematic diagram of the substrate W viewed from above. Figure 14B is an example of a schematic cross-sectional diagram cut at position B13-B13. Figure 14C is an example of a schematic cross-sectional diagram cut at position C13-C13.

[0063] Here, the insulating film 530 formed on the upper surface of the line portion and the bottom surface of the space portion is removed by etching using anisotropic etching. Specifically, an etching gas plasma is generated, and a negative bias voltage is applied to the mounting stage on which the substrate W is placed, thereby drawing ions generated by the plasma into the substrate W and performing anisotropic etching. When the insulating film 530 is a silicon oxide film (SiOx), CF is used as the etching gas. ４ Plasma etching is performed using a mixed gas of and Ar. When the insulating film 530 is an aluminum oxide film (AlOx) or a hafnium oxide film (HfOx), Cl is used as the etching gas. ２ Plasma etching is performed using a mixed gas of Ar. Alternatively, BCl is used as the etching gas. ３ The following may be added:

[0064] Specifically, by the process from step S101 to step S115, a substrate W is prepared having a base material 500, a core 511 formed on the base material 500 and having a line-and-space shape extending in a first direction (Y direction), an IGZO film 520 covering the base material 500 and the core 511 in a first region extending in a second direction (X direction) perpendicular to the first direction (Y direction), an insulating film 530 formed on the IGZO film 520 formed on the side wall of the core 511, and a metal film 540 formed on the insulating film 530 formed on the side wall of the core 511.

[0065] In step S116, the IGZO film 520 that will form the channel is etched. Figures 15A to 15C are examples of diagrams illustrating the substrate W after channel separation. Figure 15A is an example of a schematic diagram of the substrate W viewed from above. Figure 15B is an example of a schematic cross-sectional diagram cut at position B14-B14. Figure 15C is an example of a schematic cross-sectional diagram cut at position C14-C14.

[0066] Here, by etching the substrate W using reactive ion etching (RIE) technology, the IGZO film 520 covered with the insulating film 530 and the metal film 540 is left intact, while all exposed IGZO film 520 is peeled off (removed). This removes the IGZO film 520 formed on the upper surface of the line portion and the bottom surface of the space portion, while leaving the IGZO film 520 formed on the side surface of the line portion. This cuts the IGZO film 520 connected in the X direction, separating the IGZO film 520 formed on the side surface of the line portion (core 511).

[0067] The process may be carried out under the same conditions as the etching process of the IGZO film 520 in step S109. That is, the etching gas is CH ４ and H ２ A mixed gas of CH can be used. ４ and H ２ Flow ratio (CH ４ : H ２ The ratio is preferably in the range of 1:2 to 1:10. The substrate temperature is preferably in the range of 60°C to 200°C. Furthermore, for high aspect ratio reactive ion etching, the pressure is preferably in the range of 1 to 20 mT.

[0068] The power of the high-frequency power (HF) used for plasma generation may be appropriately changed depending on the composition ratio of the IGZO. For example, if In:Ga:Zn = 1:1:1, it may be 600W. For example, if In:Ga:Zn = 1:2:1, it may be 1200W.

[0069] Furthermore, the power of the high-frequency bias power LF applied to the lower electrode on the mounting table on which the substrate W is placed is preferably kept low in order to suppress damage to the core 511 (for example, SiN). Also, the absolute value of the negative DC bias voltage applied to the lower electrode on the mounting table on which the substrate W is placed is preferably in the range of 20 to 400 V.

[0070] CH ４ and H ２ Flow ratio (CH ４ : H ２ The ratio of hydrogen to hydrogen (H) is more preferably within the range of 1:2 to 1:4. This prevents hydrogen (H) which may induce oxygen vacancies in the insulating film 530 (SiOx, AlOx, HfOx, etc.). ２ The amount of ( ) can be reduced. Also, it is preferable to minimize the etching time so that the thin IGZO film 520 can be removed. In addition, it is preferable to reduce the pressure and increase the power of the high-frequency power HF for plasma generation as needed. This makes it possible to increase the etching rate of the IGZO film 520.

[0071] Note that hydrogen (H ２ If it is not possible to use the above method, the IGZO film 520 formed on the upper surface of the line portion and the bottom surface of the space portion may be removed using argon sputtering.

[0072] In step S117, citric acid cleaning is performed.

[0073] The process may be carried out under the same conditions as the citric acid cleaning process in step S110. The process in step S117 may also be omitted (see the dashed arrow in Figure 1). That is, the substrate W is cleaned using an aqueous solution of citric acid in a single-wafer washing machine or a batch washing machine. The concentration of citric acid is preferably in the range of 0.01 to 20 wt%. Furthermore, since the etching rate saturates at 5 wt%, the concentration of citric acid is more preferably in the range of 0.01 to 5 wt%. In addition, it is preferable to keep the etched areas formed by etching from the sidewall side of the IGZO film 520 to within 2 nm.

[0074] Furthermore, the formation of the insulating film 530 and the metal film 540 on the side walls of the line portion narrows the Space CD. As a result, the aspect ratio of the space portion becomes even higher. This may cause inclination in the line portion. For this reason, it is preferable to dry the moisture after citric acid washing using a supercritical drying apparatus or the like that using a supercritical fluid.

[0075] With the above steps completed, the substrate processing shown in Figure 1 is finished. This results in the formation of an electronic device comprising a substrate 500, a core 511 formed on the substrate 500 and having a line-and-space shape extending in a first direction (Y direction), an IGZO film 520 provided on the sidewall of the core 511 in a first region extending in a second direction (X direction) perpendicular to the first direction (Y direction), an insulating film 530 formed on the sidewall of the core 511, and a metal film 540 formed on the sidewall of the core 511.

[0076] In vertical channel transistors, when high-mobility IGZO is used as the channel material, it is difficult to perform vertical processing with a high aspect ratio on the IGZO, and thus difficult to isolate the channel elements.

[0077] In contrast, as shown in Figures 1 to 15C, according to the substrate processing method of this embodiment, the IGZO film 520 in the Y direction is separated in step S109, and the IGZO film 520 in the X direction is separated in step S116, thereby enabling channel separation and the formation of vertical channels of IGZO.

[0078] [Reactive ion etching of IGZO film 520] Next, the reactive ion etching of the IGZO film 520 (see S109 and S116) will be explained using Figures 16 to 20.

[0079] Figure 16 is an example of a graph showing the relationship between the etching gas and the etching rates of the IGZO film 520 and core 511. Here, CH is used as the etching gas. ４ / H ２ And HBr and Cl ２ The cases using Ar and are shown. The etching rate of the IGZO film 520 is shown in a shaded bar graph, and the etching rate (damage rate) of the core 511 (SiNx) is shown in a blank bar graph.

[0080] As shown in Figure 16, CH is used as the etching gas. ４ / H ２ By using this method, the IGZO film 520 can be selectively etched while suppressing damage to the core 511 (SiNx).

[0081] Figure 17 is an example of a graph showing the etching selectivity of the IGZO film 520 over the core material 511. Here, CH is used as the etching gas. ４ / H ２ The following shows the case where silicon nitride (SiNx) and silicon oxide (SiOx) are used as the material for core 511.

[0082] As shown in Figure 17, CH is used as the etching gas. ４ / H ２ This demonstrates that by using silicon nitride (SiNx) as the material for the core 511, the IGZO film 520 can be selectively etched.

[0083] Figures 18A to 18B are examples of schematic diagrams illustrating the temperature dependence of the IGZO film 520 during reactive ion etching.

[0084] Here, the line-and-space core 511 has a high aspect ratio structure. For this reason, it is preferable to set the pressure low so that the reaction products are discharged from the recess. Specifically, it is preferable to set the pressure to 1 to 20 mT.

[0085] Furthermore, as shown in Figure 18A, in the low temperature range (below 60°C), CH ４ / H ２ CHx deposits 525 are generated from the plasma and deposited on the IGZO film 520, thereby suppressing etching of the IGZO film 520.

[0086] In contrast, as shown in Figure 18B, at high temperatures (60°C or higher), the deposit 525 can be suppressed, and the IGZO film 520 can be suitably etched.

[0087] Figure 19 is an example graph showing the relationship between DC bias voltage and core 551 damage. The horizontal axis represents the absolute value of the negative DC bias voltage, and the vertical axis represents the damage rate of core 551 (SiNx). When core 551 is damaged, the upper corners wear down and become rounded, and the CD value at the top of core 551 increases. In Figure 19, the increase in top CD of core 511 is shown as damage.

[0088] As shown in Figure 19, damage to the core 511 increases when the absolute value of the negative DC bias voltage exceeds 400V. For this reason, it is preferable to keep the absolute value of the negative DC bias voltage below 400V. Furthermore, in order to draw ions into the substrate W by reactive ion etching, it is preferable to keep the absolute value of the negative DC bias voltage above 20V. That is, it is preferable that the absolute value of the negative DC bias voltage be within the range of 20 to 400V.

[0089] Figure 20 is an example of a diagram showing the relationship between the composition ratio of the IGZO film 520 and the high-frequency power HF. The horizontal axis of the table shows the composition ratio (In:Ga:Zn) of the IGZO film 520. The vertical axis of the table shows the power [W] of the high-frequency power HF used for plasma generation. Furthermore, after etching the IGZO film 520, a circle indicates no residue, a triangle indicates some residue, and an X indicates a lot of residue.

[0090] As shown in Figure 20, the amount of residue on the IGZO film 520 increases with a composition ratio that contains a high amount of gallium (Ga). In contrast, by increasing the power of the high-frequency power HF used for plasma generation, the IGZO film 520 can be removed without residue. Also, CH4 is used as the etching gas. ４ / H ２ By using this method, even for IGZO films 520 with different composition ratios, the IGZO film 520 can be removed without residue by adjusting the power of the high-frequency power HF used for plasma generation.

[0091] [Residue Removal Treatment of IGZO Film 520] Next, the citric acid washing (see S110, S111A, S117) to remove residue from the IGZO film 520 will be explained using Figures 21 to 22.

[0092] Figure 21 is a graph showing an example of etching rates in citric acid cleaning. The horizontal axis represents the concentration of citric acid in wt% (weight percentage). The vertical axis represents the etching rate. Here, the etching rates of IGZO film 520, core 511 (SiN), and SOC film 620 are shown.

[0093] As shown in Figure 21, citric acid cleaning can selectively etch the IGZO film 520 from the core 511 (SiN) and the SOC film 620. In other words, citric acid cleaning can suitably remove the residue of the IGZO film 520 while suppressing damage to the core 511 (SiN) and the SOC film 620.

[0094] Figure 22 is an example of a graph illustrating the control of etching depth in citric acid cleaning. The horizontal axis shows the concentration of citric acid in wt% (weight percent). The left vertical axis shows the etching rate of the IGZO film 520. The right vertical axis shows the processing time (cleaning time) for citric acid cleaning when the etching depth is 1 nm and 2 nm.

[0095] In the IGZO film 520 covered with the SOC film 620, recesses are formed in the IGZO film 520 by etching from the sidewall side by citric acid washing. As shown in Figure 22, by lowering the concentration of citric acid in the citric acid washing, the processing time for citric acid washing until a predetermined acceptable depth of recess is formed can be extended. By extending the processing time for citric acid washing, depth loading can be controlled, and residues accumulated on the bottom surface of the recesses can be suitably removed. For this reason, it is more preferable that the concentration of citric acid be in the range of 0.01 to 0.2 wt%.

[0096] [Substrate Processing System] Next, an example of a substrate processing system will be explained using Figure 23. Figure 23 is an example of a block diagram showing a substrate processing system 700.

[0097] The substrate processing system 700 includes an ALD film deposition apparatus 710, a reactive ion etching apparatus 720, a cleaning apparatus 730, a supercritical drying apparatus 740, and a control unit 750.

[0098] The ALD film deposition apparatus 710 deposits the IGZO film 520 (see S103).

[0099] The reactive ion etching apparatus 720 removes the IGZO film 520 (see S109, S116).

[0100] The cleaning device 730 removes the residue from the IGZO film 520 by citric acid cleaning (see S110, S111A, S117).

[0101] The supercritical drying apparatus 740 dries the water after citric acid washing using a supercritical fluid (see S117).

[0102] The control unit 750 controls each of the devices (710 to 740).

[0103] [Etching apparatus] Next, an example of a reactive ion etching apparatus 720 will be explained using Figure 24.

[0104] [Reactive Ion Etching Apparatus 720] Next, an example of the configuration of the reactive ion etching apparatus 720 will be explained using a capacitively coupled plasma processing apparatus (reactive ion etching apparatus) 1 as an example. Figure 24 is an example of a diagram used to explain an example of the configuration of a capacitively coupled plasma processing apparatus (reactive ion etching apparatus) 1.

[0105] The plasma processing system includes a capacitively coupled plasma processing apparatus 1 and a control unit 2. The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a shower head 13. The substrate support unit 11 is located inside the plasma processing chamber 10. The shower head 13 is located above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the side walls 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space 10s, and at least one gas outlet for discharging gas from the plasma processing space 10s. The plasma processing chamber 10 is grounded. The shower head 13 and the substrate support portion 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0106] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a plan view. The substrate W is placed on the central region 111a of the main body portion 111, and the ring assembly 112 is placed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also called the substrate support surface for supporting the substrate W, and the annular region 111b is also called the ring support surface for supporting the ring assembly 112.

[0107] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is placed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic chuck electrode 1111b placed within the ceramic member 1111a. The electrostatic chuck electrode 1111b is also called a clamping electrode. In one embodiment, the electrostatic chuck electrode 1111b is electrically connected or coupled to a chuck power supply. The chuck power supply may be a DC power supply or an AC power supply. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Furthermore, other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have an annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or it may be placed on both the electrostatic chuck 1111 and the annular insulating member. In addition, at least one bias electrode, which is electrically connected or coupled to the power supply 31 and / or power supply 32 described later, may be placed inside the ceramic member 1111a. In this case, at least one bias electrode functions as a lower electrode. Also, the conductive member of the base 1110 and the bias electrode inside the ceramic member 1111a may function as multiple lower electrodes. In one embodiment, the first voltage generation unit 32a, which functions as a voltage pulse generation unit described later, is electrically connected or coupled to the bias electrode inside the ceramic member 1111a, and the first RF generation unit 31a, described later, is electrically connected or coupled to the conductive member of the base 1110. Furthermore, the electrostatic chuck electrode 1111b may function as a lower electrode. Therefore, the substrate support portion 11 includes at least one lower electrode.

[0108] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one covering ring. The edge rings are formed of a conductive or insulating material, and the covering rings are formed of an insulating material.

[0109] The substrate support section 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate W to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are arranged within the ceramic member 1111a of the electrostatic chuck 1111. The substrate support section 11 may also include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0110] The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlet ports 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s through the plurality of gas inlet ports 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas introduction unit may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the side wall 10a.

[0111] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas to the shower head 13 from a corresponding gas source 21 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include one or more flow modulation devices that modulate or pulse the flow rate of at least one processing gas.

[0112] The power supply system 30 includes a power supply 31 that is electrically connected to or coupled to the plasma processing chamber 10. In one embodiment, the power supply 31 is electrically connected to or coupled to the plasma processing chamber 10 via at least one impedance matcher. The impedance matcher may be a mechanically controlled matcher or an electronically controlled matcher. The power supply 31 is configured to supply at least one RF (Radio Frequency) signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the power supply 31 can function as at least part of a plasma generation unit configured to generate plasma from one or more processing gases in the plasma processing chamber 10. In addition, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, and ionic components in the formed plasma can be drawn into the substrate W.

[0113] The power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode and is configured to generate a source RF signal (source RF power) to generate plasma in the plasma processing space 10s. In one embodiment, the first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matcher. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate a plurality of source RF signals having different frequencies. One or more generated source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0114] The second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode and is configured to generate a bias RF signal (bias RF power). In one embodiment, the second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode via at least one impedance matcher. When the first RF generation unit 31a is electrically connected to or coupled to a lower electrode, the second RF generation unit 31b may be electrically connected to or coupled to the same lower electrode, or it may be electrically connected to or coupled to a different lower electrode. The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0115] The power supply system 30 may also include a power supply 32 that is electrically connected to or coupled to the plasma processing chamber 10. The power supply 32 includes a first voltage generation unit 32a and a second voltage generation unit 32b. In one embodiment, the first voltage generation unit 32a is electrically connected to or coupled to at least one lower electrode and is configured to generate a first voltage signal. The generated first voltage signal is applied to at least one lower electrode. In one embodiment, the second voltage generation unit 32b is electrically connected to or coupled to at least one upper electrode and is configured to generate a second voltage signal. The generated second voltage signal is applied to at least one upper electrode.

[0116] In various embodiments, the first and / or second voltage signals may be pulsed. In this case, the first voltage generation unit 32a and / or the second voltage generation unit 32b function as voltage pulse generation units configured to generate a sequence of voltage pulses. Thus, the sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. In one embodiment, the sequence of voltage pulses has a plurality of cycles, each cycle including a burst of voltage pulses in a first period and a constant reference voltage in a second period. That is, in the sequence of voltage pulses, the burst of voltage pulses is repeated. The absolute value of the voltage level of the voltage pulse is greater than the absolute value of the voltage level of the reference voltage. The voltage pulse may have an arbitrary waveform having a rectangle, trapezoid, triangle, or a combination thereof, and the arbitrary waveform may change over time. The voltage pulse may have positive polarity or negative polarity. The sequence of voltage pulses may also include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. The first and second voltage generation units 32a and 32b may be provided in addition to the power supply 31, and the first voltage generation unit 32a may be provided in place of the second RF generation unit 31b.

[0117] The exhaust system 40 may be connected to, for example, a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0118] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 may be configured to control the elements of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 is implemented, for example, by a computer 2a. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The functions realized by the processing unit 2a1 described herein may be implemented in a circuit or processing circuit, including a general-purpose processor, an application-specific processor, integrated circuits, ASICs (Application Specific Integrated Circuits), a CPU (Central Processing Unit), a conventional circuit, and / or a combination thereof, programmed to realize the described functions. The processor is considered to be a circuit or processing circuit, including transistors and other circuits. The processor may be a programmed processor that executes a program stored in the storage unit 2a2. This program may be pre-stored in the storage unit 2a2 or retrieved via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or it may be a communication line connected to the communication interface 2a3. The storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).In this disclosure, circuits, units, and means are hardware programmed to perform or configured to perform the functions described. Such hardware may be any hardware described in this disclosure, or any hardware known to be programmed to perform or execute the functions described. If such hardware is a processor that is considered to be a type of circuit, such circuit, means, or unit is a combination of hardware and software used to constitute such hardware and / or processor.

[0119] In this description, the plasma processing apparatus (reactive ion etching apparatus) 1 was explained using an etching apparatus as an example, which has opposing upper and lower electrodes and generates capacitively coupled plasma (CCP) between the electrodes to perform etching on the substrate W. The configuration of the etching apparatus is not limited to this, and other etching apparatuses, such as an etching apparatus that generates inductively coupled plasma (ICP) to perform etching on the substrate W, may also be used.

[0120] Although the substrate processing method has been described above, this disclosure is not limited to the embodiments described above, and various modifications and improvements are possible within the scope of the gist of this disclosure as described in the claims.

[0121] Furthermore, this application claims priority based on Japanese Patent Application No. 2024-172745, filed on October 1, 2024, and the entire contents of these Japanese Patent Applications are incorporated herein by reference.

[0122] 500 Substrate 510 Core material layer 511 Core 520 IGZO film 530 Insulating film 540 Metal film 611, 641 SOC film 612, 642 SOG film 613, 643 Resist film 620 SOC film 630 Hard mask layer W Substrate

Claims

1. A step of preparing a substrate having a base material, a core formed on the base material having a line-and-space shape extending in a first direction, an IGZO film covering the base material and the core, and a carbon film formed on the IGZO film having a line-and-space shape extending in a second direction perpendicular to the first direction, and using CH as the etching gas. ４ and H ２ A substrate processing method comprising the steps of generating an etching gas plasma using a mixed gas and removing the IGZO film exposed from the opening of the carbon film by reactive ion etching.

2. The substrate processing method according to claim 1, further comprising: a step of performing citric acid cleaning after the step of removing the IGZO film; and a step of ashing the carbon film after the step of performing citric acid cleaning.

3. The substrate processing method according to claim 1, further comprising: a step of ashing the carbon film after the step of removing the IGZO film; and a step of performing citric acid cleaning after the step of ashing the carbon film.

4. The substrate processing method according to claim 1, wherein the core is composed of silicon nitride.

5. The step of removing the IGZO film is CH ４ and H ２ The substrate processing method according to claim 1, wherein the flow rate ratio is in the range of 1:2 to 1:

10.

6. The substrate processing method according to claim 1, wherein the step of removing the IGZO film is performed at a pressure in the range of 1 to 10 mT.

7. The substrate processing method according to claim 1, wherein the step of removing the IGZO film is performed when the temperature of the substrate is in the range of 60 to 200°C.

8. The substrate processing method according to claim 1, wherein the step of removing the IGZO film is performed in which the absolute value of the negative bias voltage is in the range of 20 to 400 V.

9. The substrate processing method according to claim 2 or claim 3, wherein the step of performing the citric acid cleaning is in which the citric acid concentration is in the range of 0.01 to 0.2 wt%.

10. A step of preparing a substrate having a base material, a core formed on the base material and having a line-and-space shape extending in a first direction, an IGZO film covering the base material and the core in a first region extending in a second direction perpendicular to the first direction, an insulating film formed on the IGZO film formed on the side wall of the core, and a metal film formed on the insulating film formed on the side wall of the core, wherein CH is used as the etching gas. ４ and H ２ A substrate processing method comprising the steps of generating an etching gas plasma using a mixed gas and removing the exposed IGZO film by reactive ion etching.

11. The substrate processing method according to claim 10, further comprising the step of performing citric acid cleaning after the step of removing the IGZO film.

12. A step of preparing a substrate having a base material, a core formed on the base material and having a line-and-space shape extending in a first direction, an IGZO film covering the base material and the core, and a carbon film formed on the IGZO film and having a line-and-space shape extending in a second direction orthogonal to the first direction, and using CH as a first etching gas ４ and H ２ to generate a plasma of the first etching gas and remove the exposed IGZO film from the opening of the carbon film by reactive ion etching; a step of ashing the carbon film; a step of forming an insulating film; a step of forming a metal film; a step of etching the metal film by anisotropic etching; a step of etching the insulating film by anisotropic etching; and using CH as a second etching gas ４ and H ２ to generate a plasma of the second etching gas and further remove the exposed IGZO film by reactive ion etching. A substrate processing method 13. The substrate processing method according to claim 12, further comprising a first cleaning step of performing citric acid cleaning after the first removal step and before the step of ashing the carbon film.

14. The substrate processing method according to claim 12, further comprising a first cleaning step of performing citric acid cleaning after the step of ashing the carbon film and before the step of forming the insulating film.

15. A substrate processing method according to any one of claims 12 to 14, further comprising a second cleaning step of performing citric acid cleaning after the second removal step.

16. A plasma processing chamber, a substrate support section provided within the plasma processing chamber for supporting a substrate, a gas supply section for supplying a processing gas, a plasma generation section for generating plasma of the processing gas, and a control section, wherein the control section provides a step of preparing a substrate having a substrate, a core formed on the substrate and having a line-and-space shape extending in a first direction, an IGZO film covering the substrate and the core, and a carbon film formed on the IGZO film and having a line-and-space shape extending in a second direction perpendicular to the first direction, and using CH as the etching gas. ４ and H ２ An etching apparatus configured to perform the steps of generating an etching gas plasma using a mixed gas and removing the IGZO film exposed from the opening of the carbon film by reactive ion etching.

17. An electronic device comprising: a substrate; a core formed on the substrate and having a line-and-space shape extending in a first direction; an IGZO film provided on the side wall of the core in a first region extending in a second direction perpendicular to the first direction; an insulating film formed on the side wall of the core; and a metal film formed on the side wall of the core.

Images