Display apparatus and driving method therefor

Abstract

The present application provides a display apparatus and a driving method therefor. The display apparatus comprises a display panel and a driving circuit. The display panel comprises a plurality of partitions divided along a scanning direction. The driving circuit is used to generate a sweep signal, input the sweep signal into pixel units, and sequentially control pixel units of each partition to perform data writing and light emission within a driving period of one image frame. The driving period of the pixel units comprises a data writing stage and a light emission stage, and the light emission stage comprises a plurality of pulse periods of the sweep signal. The present application can alleviate flickering problems of a display panel when displaying low-grayscale images.

Description

Display device and its driving method Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] In traditional MLED display panels, the light-emitting time of each pixel unit is concentrated in the latter half of the driving cycle of a single frame, and the sweep signal has only one pulse cycle within that driving cycle. Therefore, when displaying low grayscale images, the light-emitting time of a traditional MLED display panel may be less than 10%, resulting in noticeable flickering. This flickering not only affects the viewing experience but may also cause visual fatigue.

[0003] Therefore, how to effectively improve the flicker problem when displaying low grayscale images while maintaining the advantages of MLED display panels has become an urgent technical problem to be solved in the current MLED display technology field. Invention Overview

[0004] Embodiments of this application provide a display device and its driving method, which aim to improve the flickering problem of the display panel when displaying low grayscale images.

[0005] An embodiment of this application provides a display device, comprising: a display panel, the display panel including N partitions divided along a scanning direction, each partition including M rows of pixel units, each pixel unit including a pixel circuit and a light-emitting device, where N and M are both positive integers; and a driving circuit electrically connected to the pixel units, the driving circuit being configured to generate a ramp signal, input the ramp signal to the pixel units, and sequentially control the pixel units of each of the N partitions to perform data writing and light emission within a driving cycle of one frame; wherein the ramp signal includes multiple pulse cycles within a driving cycle of one frame, the driving cycle of the pixel units of each partition includes a data writing phase and a light emission phase, the data writing phase preceding the light emission phase, and the light emission phase including multiple pulse cycles of the ramp signal.

[0006] Embodiments of this application also provide a driving method for a display device. The display panel of the display device includes N partitions divided along a scanning direction. Each partition includes M rows of pixel units. Each pixel unit includes a pixel circuit and a light-emitting device. N and M are both positive integers. The driving method includes: generating a ramp signal, the ramp signal including multiple pulse cycles within a driving cycle of one frame; inputting the ramp signal to multiple pixel units; and sequentially controlling the pixel units of each of the N partitions to perform data writing and light emission within a driving cycle of one frame. The driving cycle of the pixel units of each partition includes a data writing phase and a light emission phase, the data writing phase preceding the light emission phase, and the light emission phase including multiple pulse cycles of the ramp signal. Beneficial effects

[0007] The embodiments of this application divide the display panel into N partitions along the scanning direction, and sequentially control the pixel units of each of these N partitions to write data and emit light within the driving cycle of one frame. Simultaneously, a ramp signal containing multiple pulse cycles within the driving cycle of one frame is used to control the light emission time of the pixel units, achieving distributed light emission time. Compared with traditional global synchronous light emission, the scheme of this application includes multiple sub-light emission stages within the driving cycle of one frame, with each sub-light emission stage corresponding to one pulse cycle of the ramp signal, thereby enabling each pixel unit to emit light multiple times within the driving cycle of one frame. This partitioned multi-pulse driving method allows the pixel units in each partition to emit light multiple times within one frame cycle, instead of emitting light only once. This distributed light emission method makes the light emission of the entire display panel more uniform in time. Therefore, even in low grayscale images, the light emission time can be evenly distributed throughout the driving cycle, effectively improving the flicker problem.

[0008] Furthermore, the embodiments of this application effectively eliminate the problem of uneven screen display caused by inconsistent transistor characteristics by compensating the threshold voltages of the second and seventh transistors, thereby further improving the display quality.

[0009] Furthermore, the embodiments of this application introduce a Vdd compensation technique, which makes the current Ids of the seventh transistor unrelated to Vdd, thereby effectively reducing the impact of power supply voltage fluctuations on the display effect and improving the stability of the display. Attached Figure Description

[0010] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application.

[0011] Figure 2 is a schematic diagram of the first technical solution of the display device and driving method provided in the embodiments of this application.

[0012] Figure 3 is a second schematic diagram of the technical solution of the display device and its driving method provided in the embodiments of this application.

[0013] Figure 4 is a circuit diagram of a first embodiment of a pixel unit in a multi-zone display device provided in this application.

[0014] Figure 5 is a waveform diagram of the signal of the pixel unit shown in Figure 4.

[0015] Figure 6 is a circuit diagram of a second embodiment of a pixel unit in a multi-zone display device provided in this application.

[0016] Figure 7 is a circuit diagram of a third embodiment of a pixel unit in a multi-zone display device provided in this application.

[0017] Figure 8 is a waveform diagram of the signal of the pixel unit shown in Figure 7.

[0018] Figure 9 is a waveform diagram of the signal of a pixel unit in a single-zone display device provided in an embodiment of this application. Embodiments of the present invention

[0019] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0020] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0021] The embodiments of this application can be combined with each other.

[0022] Referring to Figure 1, the display device provided in the embodiments of this application may be, for example, a Micro-LED display device. Of course, the display device may also be a Mini-LED display device or an OLED display device. The embodiments of this application are described using a Micro-LED display device.

[0023] The display device includes a source drive circuit, a gate drive circuit, a timing controller, a light-emitting controller, a power management chip, a substrate, data lines (DATA), scan lines (SCAN), power lines (VDD, VSS), light-emitting control signal lines (EM), a pixel array, a packaging layer, a polarizer, and a color filter.

[0024] The substrate can be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel array is composed of multiple pixel units PX arranged in rows and columns. Each pixel unit PX includes a light-emitting device and a driving circuit. The driving circuit includes TFT devices, which control the brightness of each light-emitting device in the display device. TFT devices include low-temperature polycrystalline silicon (LTPS) and metal oxide TFTs. The TFT devices can employ a dual-gate structure. The light-emitting devices are electrically connected to the TFT devices. The light-emitting devices include a light-emitting layer, an electron transport layer, a hole transport layer, a cathode, and an anode. Each gate driving unit in the gate driving circuit controls a row of pixel units PX. The gate driving unit controls the TFT devices to select the pixel units PX. Each gate driving unit mainly consists of thin-film transistors (TFTs) and capacitors. The source driving circuit provides data signals to the pixel units PX. The timing controller receives externally input image data and synchronization signals, generating the signals required by the gate driving circuit and the source driving circuit. The power management chip provides the necessary operating voltage to various parts of the display device.

[0025] In addition, the display device of this application can also integrate an embedded touch circuit, which is electrically connected to the display driving circuit, and uses time-division multiplexing to realize touch function and display function.

[0026] This application provides a display device including a display panel and a driving circuit. The driving circuit includes at least one of the above-mentioned source driving circuit, gate driving circuit, timing controller, light-emitting controller, and power management chip. As shown in Figure 1.

[0027] Referring to Figures 2 and 3, the display panel includes N partitions divided along the scanning direction SD. Each partition includes M rows of pixel units, and each pixel unit includes pixel circuitry and a light-emitting device (LED). N and M are both positive integers.

[0028] The driving circuit is electrically connected to the pixel unit. The driving circuit is used to generate a slope signal Sweep and input the slope signal Sweep to the pixel unit. It also controls the pixel unit of each of the N partitions to write data and emit light sequentially within the driving cycle of one frame.

[0029] The Sweep signal in a frame includes multiple pulse cycles. The driving cycle of each pixel unit in each partition includes a data writing phase and a light emission phase. The data writing phase precedes the light emission phase in time. The light emission phase includes multiple pulse cycles of the Sweep signal, as shown in Figures 5, 8 and 9.

[0030] The Sweep output terminal of the driving circuit is electrically connected to multiple pixel units of the display panel. The driving circuit is used to generate the Sweep signal and provide the Sweep signal to multiple pixel units through the Sweep output terminal.

[0031] Referring to Figure 4, the pixel circuit of the pixel unit in the J-th partition includes a pulse width modulation (PWM) module and a pulse amplitude modulation (PAM) module. The PWM module and the PAM module are electrically connected, and the PAM module is electrically connected to the light-emitting device (LED). The Sweep input terminal of the PWM module is electrically connected to the Sweep output terminal of the driving circuit. Here, J is a positive integer.

[0032] The pulse width modulation (PWM) module is used to control the light emission time of the LED light-emitting device, and the pulse amplitude modulation (PAM) module is used to control the light emission current of the LED light-emitting device.

[0033] The pulse width modulation module (PWM) includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1.

[0034] The pixel circuit also includes a first light emission control signal EM1 input terminal, a first power supply signal Vdd input terminal, a scan signal S(J) input terminal, a first data signal Data-PWM input terminal, and a ramp signal Sweep input terminal.

[0035] The gate of the first transistor T1 is electrically connected to the input terminal of the first light-emitting control signal EM1.

[0036] The gate of the second transistor T2 is electrically connected to the second node B, and one of the source and drain of the second transistor T2 is electrically connected to one of the source and drain of the first transistor T1.

[0037] The gate of the third transistor T3 is electrically connected to the input terminal of the first light emission control signal EM1. One of the source and drain of the third transistor T3 is electrically connected to the other of the source and drain of the second transistor T2. The other of the source and drain of the third transistor T3 is electrically connected to the input terminal of the first power supply signal Vdd.

[0038] The gate of the fourth transistor T4 is electrically connected to the input terminal of the scan signal S(J), one of the source and drain of the fourth transistor T4 is electrically connected to the second node B, and the other of the source and drain of the fourth transistor T4 is electrically connected to one of the source and drain of the second transistor T2.

[0039] The gate of the fifth transistor T5 is electrically connected to the input terminal of the scan signal S(J), one of the source and drain of the fifth transistor T5 is electrically connected to the input terminal of the first data signal Data-PWM, and the other of the source and drain of the fifth transistor T5 is electrically connected to the other of the source and drain of the second transistor T2.

[0040] One end of the first capacitor C1 is electrically connected to the second node B, and the other end of the first capacitor C1 is electrically connected to the input terminal of the ramp signal Sweep.

[0041] The pulse amplitude modulation module (PAM) includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a second capacitor C2.

[0042] The pixel circuit also includes a second light emission control signal EM2 input terminal, a constant current source signal CCG input terminal or a second data signal Data-PAM input terminal, and a second power supply signal Vss input terminal.

[0043] The gate of the sixth transistor T6 is electrically connected to the input terminal of the first light emission control signal EM1, and one of the source and drain of the sixth transistor T6 is electrically connected to the input terminal of the first power supply signal Vdd.

[0044] The gate of the seventh transistor T7 is electrically connected to the first node A, and one of the source and drain of the seventh transistor T7 is electrically connected to the other of the source and drain of the sixth transistor T6.

[0045] The gate of the eighth transistor T8 is electrically connected to the input terminal of the second light emission control signal EM2 or the input terminal of the scan signal S(J). One of the sources and drains of the eighth transistor T8 is electrically connected to the input terminal of the constant current source signal CCG or the input terminal of the second data signal Data-PAM. The other of the sources and drains of the eighth transistor T8 is electrically connected to one of the sources and drains of the seventh transistor T7.

[0046] The gate of the ninth transistor T9 is electrically connected to the input terminal of the second light emission control signal EM2 or the input terminal of the scan signal S(J). One of the source and drain of the ninth transistor T9 is electrically connected to the first node A. The other of the source and drain of the ninth transistor T9 is electrically connected to the other of the source and drain of the seventh transistor T7.

[0047] The gate of the tenth transistor T10 is electrically connected to the input terminal of the first light-emitting control signal EM1 or the fourth node D. One of the source and drain of the tenth transistor T10 is electrically connected to the other of the source and drain of the seventh transistor T7. The other of the source and drain of the tenth transistor T10 is electrically connected to the anode of the light-emitting device LED.

[0048] The gate of the eleventh transistor T11 is electrically connected to the input terminal of the second light-emitting control signal EM2. One of the source and drain of the eleventh transistor T11 is electrically connected to the anode of the light-emitting device LED. The other of the source and drain of the eleventh transistor T11 is electrically connected to the input terminal of the second power supply signal Vss.

[0049] One end of the second capacitor C2 is electrically connected to the first node A, and the other end is electrically connected to the input terminal of the first power signal Vdd.

[0050] Referring to Figures 4 and 5, the driving circuit is used to write the first data signal Data-PWM to the second node B of the pulse width modulation module PWM during the data writing stage, and to write the constant current source signal CCG to the first node A of the pulse amplitude modulation module PAM. The threshold voltage Vth1 of the second transistor T2 is compensated to V(data-pwm)+Vth1, and the threshold voltage Vth2 of the seventh transistor T7 is compensated to Vccg+Vth2.

[0051] During the light-emitting phase, the input terminal of the first light-emitting control signal EM1 receives a low-level first light-emitting control signal EM1, the sixth transistor T6 and the tenth transistor T10 are turned on, and the light-emitting device LED emits light. The voltage of the second node B decreases as the voltage of the Sweep signal decreases. When the voltage of the second node B V(data-pwm)+Vth1-V△sweep(t)-Vdd < the threshold voltage Vth1 of the second transistor T2, the second transistor T2 is turned on, the first power supply signal Vdd is written to the first node A, the seventh transistor T7 is turned off, and the light-emitting device LED stops emitting light.

[0052] During the light emission stage, the voltage of the first node A is Vccg + Vth2, and the voltage of the second node B is V(data-pwm) + Vth1.

[0053] During the light-emitting stage, the current Ids of the seventh transistor T7 is Ids = K*(Vccg-Vref)^2, where K is a constant.

[0054] The driving circuit generates a first light-emitting control signal EM1 and a second light-emitting control signal EM2. The first light-emitting control signal EM1 is high during the data writing phase and low during the light-emitting phase, and the second light-emitting control signal EM2 is low during the data writing phase and high during the light-emitting phase; or the first light-emitting control signal EM1 is low during the data writing phase and high during the light-emitting phase, and the second light-emitting control signal EM2 is high during the data writing phase and low during the light-emitting phase.

[0055] The driving circuit is used to sequentially provide M scan signals S(J) to the M rows of pixel units in the J-th partition. The scan signal S(J) is low during the data writing phase of the pixel unit in the partition and high during the light emission phase; or the scan signal S(J) is high during the data writing phase of the pixel unit in the partition and low during the light emission phase.

[0056] Embodiments of this application also provide a driving method for a display device, the driving method including:

[0057] A slope signal called Sweep is generated, which consists of multiple pulse cycles within the driving cycle of one frame.

[0058] The sweep signal Sweep is input to multiple pixel units; and

[0059] Within the driving cycle of one frame, the pixel units of each of the N partitions are sequentially controlled to write data and emit light;

[0060] The driving cycle of each pixel unit in each partition includes a data writing phase and a light emission phase. The data writing phase precedes the light emission phase, and the light emission phase includes multiple pulse cycles of the Sweep signal.

[0061] The driving method also includes:

[0062] During the data writing phase, the first data signal Data-PWM is written to the second node B of the PWM module of the pixel circuit, and the constant current source signal CCG is written to the first node A of the PAM module of the pixel circuit.

[0063] Among them, the threshold voltage Vth1 of the second transistor T2 is compensated to V(data-pwm)+Vth1, and the threshold voltage Vth2 of the seventh transistor T7 is compensated to Vccg+Vth2.

[0064] The driving method also includes:

[0065] During the luminescence stage:

[0066] When the input terminal of the first light-emitting control signal EM1 receives a low-level first light-emitting control signal EM1, the sixth transistor T6 and the tenth transistor T10 are turned on, and the light-emitting device LED emits light.

[0067] The voltage of the second node B decreases as the voltage of the Sweep signal decreases. When the voltage of the second node B, V(data-pwm)+Vth1-V△sweep(t)-Vdd, is less than the threshold voltage Vth1 of the second transistor T2, the second transistor T2 is turned on, the first power supply signal Vdd is written to the first node A, the seventh transistor T7 is turned off, and the light-emitting device LED stops emitting light.

[0068] The driving method also includes:

[0069] A first light-emitting control signal EM1 and a second light-emitting control signal EM2 are generated. The first light-emitting control signal EM1 is high during the data writing phase and low during the light-emitting phase, and the second light-emitting control signal EM2 is low during the data writing phase and high during the light-emitting phase; or the first light-emitting control signal EM1 is low during the data writing phase and high during the light-emitting phase, and the second light-emitting control signal EM2 is high during the data writing phase and low during the light-emitting phase.

[0070] The driving method also includes:

[0071] During the data writing phase, M scan signals S(J) are sequentially provided to the M rows of pixel units in the J-th partition. The scan signal S(J) is low during the data writing phase and high during the light emission phase; or the scan signal S(J) is high during the data writing phase and low during the light emission phase. Here, J is a positive integer.

[0072] During the light emission stage, the voltage of the first node A is Vccg + Vth2, and the voltage of the second node B is V(data-pwm) + Vth1.

[0073] Example 1

[0074] The micro-light-emitting diode display panel of the present application includes a plurality of pixel units, which are distributed in N partitions along the scanning direction SD of the micro-light-emitting diode display panel, and each partition includes M rows of pixel units.

[0075] Each pixel unit includes a pixel circuit and a light-emitting device (LED). In this embodiment, the pixel circuit adopts a structure of 11 transistors (T1-T11) and 2 capacitors (C1, C2). This pixel circuit, in conjunction with the constant current source signal CCG and the timing shown in Figure 5, enables multi-zone, multi-pulse operation.

[0076] For each pixel unit, the driving cycle of a frame includes a data writing phase and a light emission phase. The data writing phase precedes the light emission phase. During the data writing phase, the scan signals S(J) transmitted by the M scan lines in the J-th partition are sequentially low-level signals, the first light emission control signal EM1 is high-level, the second light emission control signal EM2 is low-level, and the sweep signal Sweep is high-level. The light emission phase includes multiple sub-light emission phases. In the first sub-light emission phase, the sweep signal Sweep is a signal with a linearly decreasing voltage; in the second and subsequent sub-light emission phases, the sweep signal Sweep is first high-level and then changes to a signal with a linearly decreasing voltage. Here, J is a positive integer less than or equal to N.

[0077] In the pixel circuit of the embodiments of this application, all transistors are P-type transistors, although these transistors can also be N-type transistors.

[0078] Referring to Figure 4, the pixel circuit of this embodiment includes:

[0079] The first transistor T1 has its gate electrically connected to the input terminal of the first light emission control signal EM1, and its source electrically connected to the input terminal of the first power supply signal Vdd.

[0080] The gate of the second transistor T2 is electrically connected to the second node B, and its source is electrically connected to the drain of the first transistor T1.

[0081] The gate of the third transistor T3 is electrically connected to the input terminal of the first light-emitting control signal EM1, the source is electrically connected to the drain of the second transistor T2, and the drain is electrically connected to the input terminal of the first power supply signal Vdd.

[0082] The fourth transistor T4 has its gate electrically connected to the input terminal of the scan signal S(J), its source electrically connected to the second node B, and its drain electrically connected to the source of the second transistor T2.

[0083] The fifth transistor T5 has its gate electrically connected to the input terminal of the scan signal S(J), its source electrically connected to the input terminal of the first data signal Data-PWM, and its drain electrically connected to the drain of the second transistor T2.

[0084] The sixth transistor T6 has its gate electrically connected to the input terminal of the first light emission control signal EM1, and its source electrically connected to the input terminal of the first power supply signal Vdd.

[0085] The seventh transistor T7 has its gate electrically connected to the first node A and its source electrically connected to the drain of the sixth transistor T6.

[0086] The gate of the eighth transistor T8 is electrically connected to the input terminal of the second light-emitting control signal EM2, the source is electrically connected to the input terminal of the constant current source signal CCG, and the drain is electrically connected to the source of the seventh transistor T7.

[0087] The ninth transistor T9 has its gate electrically connected to the input terminal of the second light-emitting control signal EM2, its source electrically connected to the first node A, and its drain electrically connected to the drain of the seventh transistor T7.

[0088] The gate of the tenth transistor T10 is electrically connected to the input terminal of the first light-emitting control signal EM1, the source is electrically connected to the drain of the seventh transistor T7, and the drain is electrically connected to the anode of the light-emitting device LED.

[0089] The eleventh transistor T11, whose gate is electrically connected to the input terminal of the second light emission control signal EM2, source is electrically connected to the anode of the light emitting device LED, and drain is electrically connected to the input terminal of the second power supply signal Vss;

[0090] The first capacitor C1, one end of which is electrically connected to the first node A and the other end is electrically connected to the input terminal of the first power supply signal Vdd;

[0091] The second capacitor C2, one end of which is electrically connected to the second node B and the other end is electrically connected to the input terminal of the ramp signal Sweep.

[0092] Referring to Table 1, Figure 4, and Figure 5, the specific working process of the display device in this embodiment is as follows:

[0093] Data writing stage:

[0094] Data signals are written and compensated for each row of pixel units in sequence. In this stage, the first data signal Data-PWM is written to the second node B of the pixel circuit, and the threshold voltage Vth1 of the second transistor T2 in the diode mode is compensated to V(data-pwm)+Vth1. The voltage of the constant current source signal CCG is written to the first node A, and the threshold voltage Vth2 of the seventh transistor T7 in the diode mode is compensated to Vccg+Vth2. After writing the data, the voltages of the second node B and the first node A are stored by the first capacitor C1 and the second capacitor C2 respectively. Each row of pixel units is sequentially controlled by the scan signal S(J) for data writing and compensation.

[0095] Light emission stage:

[0096] The first light emission control signal EM1 is at a low level, enabling the sixth transistor T6 and the tenth transistor T10 to turn on. The voltage of the first node A is Vccg+Vth2-Vdd<Vth2, the seventh transistor T7 turns on, and the light emitting device LED starts to emit light. The light emission current of the seventh transistor T7 is K*(Vccg+Vth2-Vdd-Vth2)^2 = K*(Vccg-Vdd)^2. The voltage of the second node B decreases as the voltage of the ramp signal Sweep decreases. When the voltage of the second node B, Vdata+Vth1-V△sweep(t)-Vdd<Vth1, the second transistor T2 turns on, the first power supply signal Vdd is written to the first node A, the seventh transistor T7 turns off, and the light emitting device LED stops emitting light.

[0097] During the light-emitting phase, the voltage of the first node A is Vccg + Vth2 or V(data - pam) + Vth2, and the voltage of the second node B is coupled to Vdata + Vth1 by the ramp signal Sweep. This comparison and emission process is repeated multiple times to achieve multi-pulse light emission. In other words, the light-emitting phase of the LED device within one frame's driving cycle includes multiple sub-light-emitting phases, each corresponding to one pulse cycle of the ramp signal Sweep.

[0098] Table 1

[0099] Transistor / Node Data Writing Stage Light Emission Stage T1 Off On T2 Off Off → On T3 Off On T4 Switch T5 Switch T6 Off On T7 On On T8 Switch T9 Switch T10 Off On T11 Switch AVccg+Vth2Vccg+Vth2→VddBV(data-pwm)+Vth1V(data-pwm)+Vth1-V △sweep(t)

[0100] Referring to Figures 5 and 6, in the display device provided in the embodiments of this application, the pulse amplitude modulation module (PAM) further includes a twelfth transistor T12 and a thirteenth transistor T13.

[0101] The pixel circuit also includes a reference voltage signal Vref input.

[0102] The gate of the twelfth transistor T12 is electrically connected to the input terminal of the second light emission control signal EM2 or the scan signal S(J). One of the sources and drains of the twelfth transistor T12 is electrically connected to the input terminal of the reference voltage signal Vref. The other of the sources and drains of the twelfth transistor T12 is electrically connected to the third node C.

[0103] The gate of the thirteenth transistor T13 is electrically connected to the input terminal of the first light-emitting control signal EM1. One of the source and drain of the thirteenth transistor T13 is electrically connected to the input terminal of the first power supply signal Vdd. The other of the source and drain of the thirteenth transistor T13 is electrically connected to the third node C.

[0104] During the data writing phase, the driving circuit is also used to write the reference voltage signal Vref to the third node C.

[0105] During the light-emitting stage, the first light-emitting control signal EM1 input terminal receives the low-level first light-emitting control signal EM1, the thirteenth transistor T13 turns on, the voltage of the third node C changes from Vref to Vdd and is coupled to the first node A, the seventh transistor T7 turns off, and the light-emitting device LED stops emitting light.

[0106] The driving method also includes:

[0107] During the data writing phase, the reference voltage signal Vref is written to the third node C.

[0108] During the luminescence stage:

[0109] When the first light-emitting control signal EM1 input terminal receives the low-level first light-emitting control signal EM1, the thirteenth transistor T13 turns on, causing the voltage of the third node C to change from Vref to Vdd and couple to the first node A. The seventh transistor T7 turns off, and the light-emitting device LED stops emitting light.

[0110] Example 2

[0111] Example 2 is similar to Example 1, except that it adds a Vdd compensation function. Specifically, the pixel circuit in this example uses a structure of 13 transistors and 2 capacitors. Compared to Example 1, it adds a twelfth transistor T12 and a thirteenth transistor T13 to achieve Vdd compensation.

[0112] Referring to Figure 6, the pixel circuit in this embodiment is improved upon that in embodiment 1 by adding the following:

[0113] The twelfth transistor T12 has its gate electrically connected to the input terminal of the second light emission control signal EM2, its source electrically connected to the input terminal of the reference voltage signal Vref, and its drain electrically connected to the third node C.

[0114] The thirteenth transistor T13 has its gate electrically connected to the input terminal of the first light-emitting control signal EM1, its source electrically connected to the input terminal of the first power supply signal Vdd, and its drain electrically connected to the third node C.

[0115] In this structure, the luminous current of the seventh transistor T7 is K*(Vccg+Vth2+Vdd-Vref-Vdd-Vth2)^2=k*(Vccg-Vref)^2, achieving compensation for Vdd. Specifically, when the first luminous control signal EM1 turns on the thirteenth transistor T13, the voltage at the third node C changes from the reference voltage Vref to Vdd, causing the voltage at the first node A to change from Vccg+Vth2 to Vccg+Vth2+Vdd-Vref. Therefore, the current of the seventh transistor T7 is Ids=K*(Vg-Vs-Vth)^2=K*(Vccg+Vth2+Vdd-Vref-Vdd-Vth2)^2=K*(Vccg-Vref)^2. This process achieves Vdd compensation, making the luminous current Ids independent of Vdd.

[0116] Referring to Table 2, Figure 5, and Figure 6, the specific workflow of the display device in this embodiment is as follows:

[0117] Data writing phase:

[0118] The pixel units in each row are sequentially written with data signals and compensated. At this stage, the first data signal Data-PWM is written to the second node B of the pixel circuit, and the threshold voltage Vth1 of the second transistor T2 in the diode mode is compensated to V(data-pwm)+Vth1. The voltage of the constant current source signal CCG is written to the first node A, and the threshold voltage Vth2 of the seventh transistor T7 in the diode mode is compensated to Vccg+Vth2. After writing the data, the voltages of the second node B and the first node A are stored through the first capacitor C1 and the second capacitor C2 respectively. The pixel units in each row are sequentially controlled by the scan signal S(J) for data writing and compensation.

[0119] In the light-emitting stage, the first light-emitting control signal EM1 is at a low level, and the voltage of the third node C changes from Vref to Vdd and is coupled to the first node A, causing the voltage of the first node A to change from Vccg+Vth2 to Vccg+Vth2+Vdd-Vref. The voltage of the first node A is Vccg+Vth2-Vdd<Vth2, and the seventh transistor T7 is turned on, and the light-emitting device LED starts to emit light. The light-emitting current of the seventh transistor T7 is Ids=K*(Vg-Vs-Vth2)^2=K*(Vccg+Vth2+Vdd-Vref-Vdd-Vth2)^2=K*(Vccg-Vref)^2, and this process realizes Vdd compensation. During the light emission of the light-emitting device LED, the voltage of the second node B decreases as the voltage of the ramp signal Sweep decreases. When the voltage of the second node B, Vdata+Vth1-V△sweep(t)-Vdd<Vth1, the second transistor T2 is turned on, and the first power supply signal Vdd is written to the first node A, and the seventh transistor T7 is turned off, and the light-emitting device LED stops emitting light.

[0120] Table 2

[0121] Transistor / NodeData Writing StageLight-Emitting StageT1OffOnT2OffOff→OnT3OffOnT4OnOffT5OnOffT6OffOnT7OnOnT8OnOffT9OnOffT10OffOnT11OnOffT12OnOffT13OffOnAVccg+Vth2Vccg+Vth2+Vdd-Vref→VddBV(data-pwm)+Vth1V(data-pwm)+Vth1-V△sweep(t)CVrefVdd

[0122] Referring to FIGS. 7 and 8, in the display device provided in the embodiment of the present application, the pulse amplitude modulation module PAM further includes a fourteenth transistor T14 and a third capacitor C3.

[0123] The gate of the fourteenth transistor T14 is electrically connected to the input terminal of the second light emission control signal EM2. One of the sources and drains of the fourteenth transistor T14 is electrically connected to the input terminal of the second power supply signal Vss. The other of the sources and drains of the fourteenth transistor T14 is electrically connected to the fourth node D.

[0124] One end of the third capacitor C3 is electrically connected to the fourth node D, and the other end is electrically connected to the input terminal of the first power signal Vdd.

[0125] During the data writing phase, the driving circuit is also used to write the reference voltage signal Vref to the third node C and the second power supply signal Vss to the fourth node D.

[0126] During the luminescence stage:

[0127] The voltage at the fourth node D is the voltage of the second power supply signal Vss, the tenth transistor T10 is turned on, and the light-emitting device LED emits light.

[0128] The voltage of the second node B decreases as the voltage of the Sweep signal decreases. When the voltage of the second node B, V(data-pwm)+Vth1-V△sweep(t)-Vdd, is less than the threshold voltage Vth1 of the second transistor T2, the second transistor T2 is turned on, the first power supply signal Vdd is written to the fourth node D, the tenth transistor T10 is turned off, and the light-emitting device LED stops emitting light.

[0129] During the light emission stage, the voltage of the first node A is V(data-pam)+Vth2, and the voltage of the second node B is V(data-pwm)+Vth1.

[0130] During the light-emitting stage, the current Ids of the seventh transistor T7 is Ids = K * (V(data-pam) - Vref)^2, where K is a constant.

[0131] The driving method also includes:

[0132] During the data writing phase, a reference voltage signal Vref is written to the third node C, and a second power supply signal Vss is written to the fourth node D.

[0133] During the light-emitting phase, the voltage of the fourth node D is the voltage of the second power supply signal Vss, the tenth transistor T10 is turned on, and the light-emitting device LED emits light; the voltage of the second node B decreases as the voltage of the Sweep signal decreases. When the voltage of the second node B V(data-pwm)+Vth1-V△sweep(t)-Vdd < the threshold voltage Vth1 of the second transistor T2, the second transistor T2 is turned on, the first power supply signal Vdd is written to the fourth node D, the tenth transistor T10 is turned off, and the light-emitting device LED stops emitting light.

[0134] During the light emission stage, the voltage of the first node A is Vccg+Vth2 or V(data-pam)+Vth2, and the voltage of the second node B is V(data-pwm)+Vth1.

[0135] Example 3

[0136] Example 3 is similar to Example 2, except that Example 3 proposes a pixel circuit with a structure of 14 transistors and 3 capacitors, which realizes Vth / Vdd compensation.

[0137] Referring to Figure 7, the pixel circuit of the display device in this embodiment is improved based on that in embodiment 2 by adding the following:

[0138] The fourteenth transistor T14 has its gate electrically connected to the input terminal of the second light emission control signal EM2, its source electrically connected to the input terminal of the second power supply signal Vss, and its drain electrically connected to the fourth node D.

[0139] The third capacitor C3 has one end electrically connected to the fourth node D and the other end electrically connected to the input terminal of the first power signal Vdd.

[0140] Meanwhile, the gate of the tenth transistor T10 is changed to be electrically connected to the fourth node D, and the source of the eighth transistor T8 is changed to be electrically connected to the input terminal of the second data signal Data-PAM.

[0141] Referring to Table 3, Figure 7, and Figure 8, the specific workflow of the display device in this embodiment is as follows:

[0142] Data writing phase:

[0143] The voltage V(data-pwm) of the first data signal Data-PWM is written to the second node B, compensating the threshold voltage Vth1 of the second transistor T2 in diode mode to V(data-pwm) + Vth1. The voltage Vdata of the second data signal Data-PAM is written to the first node A, compensating the threshold voltage Vth2 of the seventh transistor T7 in diode mode to V(data-pam) + Vth2. The reference voltage signal Vref is written to the third node C, and the second power supply signal Vss is written to the fourth node D. After writing the data, the voltages of the second node B, the first node A, and the fourth node D are stored through the first capacitor C1, the second capacitor C2, and the third capacitor C3, respectively.

[0144] Luminescence stage:

[0145] The first light emission control signal EM1 is at a low level, the thirteenth transistor T13 is turned on, the voltage of the third node C changes from Vref to Vdd and is coupled to the first node A. The voltage of the first node A changes from V(data - pam)+Vth2 to V(data - pam)+Vth2+Vdd - Vref. The voltage of the fourth node D remains at the voltage of the second power supply signal Vss, the tenth transistor T10 remains on, the voltage of the first node A is V(data - pam)+Vth2 - Vdd<Vth2, the seventh transistor T7 is turned on, and the light - emitting device LED starts to emit light. The light - emitting current of the seventh transistor T7 is K*(V(data - pam)+Vth2+Vdd - Vref - Vdd - Vth2)^2 = K*(V(data - pam)-Vref)^2, achieving Vdd compensation. During the light - emitting process, the voltage of the second node B decreases as the voltage of the ramp signal Sweep decreases. When the voltage of the second node B, V(data - pwm)+Vth1 - V△sweep(t)-Vdd<Vth1, the second transistor T2 is turned on, the first power supply signal Vdd is written to the fourth node D, and the tenth transistor T10 is turned off, and the light - emitting device LED stops emitting light.

[0146] When data is written to the pixel units in other partitions, the voltages of the first node A and the third node C of the pixel units in this partition (the J - th partition) remain unchanged, and the voltage of the second node B is coupled by the ramp signal Sweep to V(data - pwm)+Vth1, and the comparison light - emission is repeated. This comparison light - emission is performed multiple times to achieve multi - pulse light - emission.

[0147] Table 3

[0148] Transistor / NodeData Writing StageLight - Emitting StageT1OffOnT2Switch→OnT3OffOnT4SwitchT5SwitchT6OffOnT7SwitchT8OnOnT9SwitchT10OffOn→OffT11SwitchT12SwitchT13OffOnT14SwitchAV(data - pam)+Vth2V(data - pam)+Vth2+Vdd - VrefBV(data - pwm)+Vth1V(data - pwm)+Vth1 - V△sweep(t)CVrefVddDVssVss→Vdd

[0149] Because the input terminal of the first power signal Vdd experiences different loads depending on the content displayed on the screen, it may exhibit some instability and voltage drop. In this embodiment, since one plate of the third capacitor C3 is connected to the input terminal of the first power signal Vdd, fluctuations in the first power signal Vdd are coupled to the gate of the tenth transistor T10. This ensures that the difference between the gate voltage Vg and the source voltage Vs of the tenth transistor T10 remains relatively stable, thereby offsetting the influence of fluctuations in the first power signal Vdd and guaranteeing the stability of the current (current formula: Ids=K*(Vg-Vs-Vth)^2).

[0150] Through the above technical solutions, the embodiments of this application realize multi-zone multi-pulse light emission, effectively improving the flickering problem that occurs when the micro light-emitting diode display panel displays low grayscale images, and improving the uniformity and stability of the display through various compensation mechanisms.

[0151] The technical solution of the embodiments of this application can be applied to multi-segment single-slope wave signal multi-pulse emission, as shown in Figures 5 and 8, and can also be applied to single-segment single-slope wave signal multi-pulse emission, as shown in Figure 9. The emission stage includes multiple sub-emission stages. In the data writing stage, the second emission control signal EM2 is a low-level signal. In the first sub-emission stage of the emission stage, the second emission control signal EM2 is a high-level signal. In the second and subsequent sub-emission stages, the second emission control signal EM2 is first a low-level signal and then a high-level signal. That is, before or during each sub-emission stage, the low-level second emission control signal EM2 is used to reset each row of pixel units. The slope signal Sweep is a signal with a linearly decreasing voltage; in the second and subsequent sub-emission stages, the slope signal Sweep is first a high-level signal and then becomes a signal with a linearly decreasing voltage. Single-segment refers to a micro-LED display panel that is not divided into multiple zones; single-slope signal refers to a single slope signal output terminal that is electrically connected to all pixel units of the entire micro-LED display panel; multi-pulse refers to the slope signal having multiple sub-emission stages in the emission phase of each frame's drive cycle, with each sub-emission stage being one comparison emission time. The number of pulses can be customized from one to multiple as needed.

[0152] The embodiments of this application divide the display panel into N partitions along the scanning direction SD, and sequentially control the pixel units of each of these N partitions to write data and emit light within the driving cycle of one frame. Simultaneously, a ramp signal containing multiple pulse cycles within the driving cycle of one frame is used to control the light emission time of the pixel units, achieving distributed light emission time. Compared with traditional global synchronous light emission, the scheme of this application includes multiple sub-light emission stages within the driving cycle of one frame, with each sub-light emission stage corresponding to one pulse cycle of the ramp signal, thereby enabling each pixel unit to emit light multiple times within the driving cycle of one frame. This partitioned multi-pulse driving method allows the pixel units in each partition to emit light multiple times within one frame cycle, instead of emitting light only once. This distributed light emission method makes the light emission of the entire display panel more uniform in time. Therefore, even in low grayscale images, the light emission time can be evenly distributed throughout the driving cycle, effectively improving the flicker problem.

[0153] Furthermore, the embodiments of this application effectively eliminate the problem of uneven screen display caused by inconsistent transistor characteristics by compensating the threshold voltages of the second transistor T2 and the seventh transistor T7, thereby further improving the display quality.

[0154] Furthermore, the embodiments of this application introduce a Vdd compensation technique, which makes the current Ids of the seventh transistor T7 independent of Vdd, thereby effectively reducing the impact of power supply voltage fluctuations on the display effect and improving the stability of the display.

[0155] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, comprising: The display panel includes N partitions divided along the scanning direction (SD), each partition includes M rows of pixel units, and each pixel unit includes pixel circuitry and a light-emitting device (LED), where N and M are both positive integers; as well as A driving circuit is electrically connected to the pixel unit. The driving circuit is used to generate a sweep signal and input the sweep signal to the pixel unit. It also sequentially controls the pixel unit of each of the N partitions to perform data writing and light emission within the driving cycle of one frame. The sweep signal comprises multiple pulse cycles within the driving cycle of one frame. The driving cycle of each pixel unit in the partition includes a data writing phase and a light emission phase. The data writing phase precedes the light emission phase. The light emission phase includes multiple pulse cycles of the sweep signal.

2. The display device according to claim 1, wherein The sweep signal output terminal of the driving circuit is electrically connected to a plurality of pixel units of the display panel. The driving circuit is used to generate the sweep signal and provide the sweep signal to the plurality of pixel units through the sweep signal output terminal. The pixel circuit includes a pulse width modulation module (PWM) and a pulse amplitude modulation module (PAM). The PWM module is electrically connected to the PAM module, and the PAM module is electrically connected to the light-emitting device (LED). The sweep signal input terminal of the PWM module is electrically connected to the sweep signal output terminal of the driving circuit.

3. The display device of claim 2, wherein, The pulse width modulation (PWM) module includes: The first transistor (T1) has its gate electrically connected to the input terminal of the first light-emitting control signal (EM1); The second transistor (T2) has its gate electrically connected to the second node (B), and one of the source and drain of the second transistor (T2) is electrically connected to one of the source and drain of the first transistor (T1). The third transistor (T3) has its gate electrically connected to the input terminal of the first light emission control signal (EM1), one of the source and drain of the third transistor (T3) is electrically connected to the other of the source and drain of the second transistor (T2), and the other of the source and drain of the third transistor (T3) is electrically connected to the input terminal of the first power supply signal (Vdd). The fourth transistor (T4) has its gate electrically connected to the input terminal of the scan signal S (J), one of the source and drain of the fourth transistor (T4) is electrically connected to the second node (B), and the other of the source and drain of the fourth transistor (T4) is electrically connected to one of the source and drain of the second transistor (T2). A fifth transistor (T5), wherein the gate of the fifth transistor (T5) is electrically connected to the input terminal of the scan signal S(J), one of the source and drain of the fifth transistor (T5) is electrically connected to the input terminal of the first data signal (Data-PWM), and the other of the source and drain of the fifth transistor (T5) is electrically connected to the other of the source and drain of the second transistor (T2); and A first capacitor (C1) is connected at one end to the second node (B) and at the other end to the input terminal of the slope signal (Sweep). Where J is a positive integer.

4. The display device according to claim 2, wherein The pulse amplitude modulation module (PAM) includes: The sixth transistor (T6) has its gate electrically connected to the first light emission control signal (EM1) input terminal, and one of the source and drain of the sixth transistor (T6) is electrically connected to the first power supply signal (Vdd) input terminal. The seventh transistor (T7) has its gate electrically connected to the first node (A), and one of the source and drain of the seventh transistor (T7) is electrically connected to the other of the source and drain of the sixth transistor (T6). The eighth transistor (T8) has its gate electrically connected to the input terminal of the second light emission control signal (EM2) or the input terminal of the scan signal S(J), and one of the source and drain of the eighth transistor (T8) is electrically connected to the input terminal of the constant current source signal (CCG) or the input terminal of the second data signal (Data-PAM). The other of the source and drain of the eighth transistor (T8) is electrically connected to one of the source and drain of the seventh transistor (T7). The ninth transistor (T9) has its gate electrically connected to the input terminal of the second light emission control signal (EM2) or the input terminal of the scan signal S (J), and one of the source and drain of the ninth transistor (T9) is electrically connected to the first node (A), and the other of the source and drain of the ninth transistor (T9) is electrically connected to the other of the source and drain of the seventh transistor (T7). The tenth transistor (T10) has its gate electrically connected to the input terminal of the first light-emitting control signal (EM1) or the fourth node (D), one of the source and drain of the tenth transistor (T10) is electrically connected to the other of the source and drain of the seventh transistor (T7), and the other of the source and drain of the tenth transistor (T10) is electrically connected to the anode of the light-emitting device (LED). The eleventh transistor (T11), wherein the gate of the eleventh transistor (T11) is electrically connected to the input terminal of the second light-emitting control signal (EM2), one of the source and drain of the eleventh transistor (T11) is electrically connected to the anode of the light-emitting device (LED), and the other of the source and drain of the eleventh transistor (T11) is electrically connected to the input terminal of the second power supply signal (Vss); and The second capacitor (C2) has one end electrically connected to the first node (A) and the other end electrically connected to the first power signal (Vdd) input terminal.

5. The display device of claim 4, wherein, The pulse amplitude modulation module (PAM) also includes: A twelfth transistor (T12), wherein the gate of the twelfth transistor (T12) is electrically connected to the input terminal of the second light emission control signal (EM2) or the scan signal S(J); one of the source and drain of the twelfth transistor (T12) is electrically connected to the input terminal of the reference voltage signal (Vref); and the other of the source and drain of the twelfth transistor (T12) is electrically connected to the third node (C); and The thirteenth transistor (T13) has its gate electrically connected to the input terminal of the first light emission control signal (EM1), one of the source and drain of the thirteenth transistor (T13) electrically connected to the input terminal of the first power supply signal (Vdd), and the other of the source and drain of the thirteenth transistor (T13) electrically connected to the third node (C).

6. The display device of claim 5, wherein, During the light-emitting phase, the current of the seventh transistor (T7) is Ids = K*(Vccg-Vref)^2 or Ids = K*(V(data-pam)-Vref)^2, where K is a constant.

7. The display device according to claim 4, wherein The pulse amplitude modulation module (PAM) also includes: The fourteenth transistor (T14), wherein the gate of the fourteenth transistor (T14) is electrically connected to the input terminal of the second light emission control signal (EM2), one of the source and drain of the fourteenth transistor (T14) is electrically connected to the input terminal of the second power supply signal (Vss), and the other of the source and drain of the fourteenth transistor (T14) is electrically connected to the fourth node (D); and The third capacitor (C3) has one end electrically connected to the fourth node (D) and the other end electrically connected to the first power signal (Vdd) input terminal.

8. The display device according to claim 2, wherein The driving circuit is used to write a first data signal (Data-PWM) to the second node (B) of the pulse width modulation module (PWM) and to write a constant current source signal (CCG) to the first node (A) of the pulse amplitude modulation module (PAM) during the data writing phase. The threshold voltage Vth1 of the second transistor (T2) is compensated to V(data-pwm) + Vth1, and the threshold voltage Vth2 of the seventh transistor (T7) is compensated to Vccg + Vth2.

9. The display device of claim 8, wherein, During the light-emitting stage: When the first light-emitting control signal (EM1) input terminal receives a low-level first light-emitting control signal (EM1), the sixth transistor (T6) and the tenth transistor (T10) are turned on, and the light-emitting device (LED) emits light; When the voltage of the second node (B) V(data-pwm)+Vth1-V△sweep(t)-Vdd < the threshold voltage Vth1 of the second transistor (T2), the second transistor (T2) is turned on, the first power supply signal (Vdd) is written to the first node (A), the seventh transistor (T7) is turned off, and the light-emitting device (LED) stops emitting light.

10. The display device of claim 8, wherein, During the data writing phase, the driving circuit is also used to write a reference voltage signal (Vref) to the third node (C); or During the data writing phase, the driving circuit is also used to write a reference voltage signal (Vref) to the third node (C) and a second power supply signal (Vss) to the fourth node (D).

11. The display device of claim 10, wherein, During the light-emitting stage: When the first light-emitting control signal (EM1) input terminal receives a low-level first light-emitting control signal (EM1), the thirteenth transistor (T13) turns on, the voltage of the third node (C) changes from Vref to Vdd and is coupled to the first node (A), the seventh transistor (T7) turns off, and the light-emitting device (LED) stops emitting light.

12. The display device of claim 11, wherein, During the light-emitting stage: The voltage at the fourth node (D) is the voltage of the second power supply signal (Vss), the tenth transistor (T10) is turned on, and the light-emitting device (LED) emits light; When the voltage of the second node (B) V(data-pwm)+Vth1-V△sweep(t)-Vdd < the threshold voltage Vth1 of the second transistor (T2), the second transistor (T2) is turned on, the first power supply signal (Vdd) is written to the fourth node (D), the tenth transistor (T10) is turned off, and the light-emitting device (LED) stops emitting light.

13. The display device of claim 8, wherein, During the light emission stage, the voltage of the first node (A) is Vccg+Vth2 or V(data-pam)+Vth2, and the voltage of the second node (B) is V(data-pwm)+Vth1.

14. A driving method of a display device, wherein, The display panel of the display device includes N partitions divided along the scanning direction (SD), each partition including M rows of pixel units, each pixel unit including pixel circuitry and a light-emitting device (LED), where N and M are both positive integers, and the driving method includes: A sweep signal is generated, which includes multiple pulse cycles within the driving cycle of one frame. Input the sweep signal to the plurality of said pixel units; and Within the driving cycle of one frame, the pixel units of each of the N partitions are sequentially controlled to write data and emit light; The driving cycle of the pixel unit of each partition includes a data writing phase and a light emission phase, wherein the data writing phase precedes the light emission phase, and the light emission phase includes multiple pulse cycles of the sweep signal.

15. The driving method according to claim 14, wherein The driving method further includes: During the data writing phase, a first data signal (Data-PWM) is written to the second node (B) of the pulse width modulation module (PWM) of the pixel circuit, and a constant current source signal (CCG) is written to the first node (A) of the pulse amplitude modulation module (PAM) of the pixel circuit. Among them, the threshold voltage Vth1 of the second transistor (T2) is compensated to V(data-pwm)+Vth1, and the threshold voltage Vth2 of the seventh transistor (T7) is compensated to Vccg+Vth2.

16. The driving method according to claim 15, wherein The driving method further includes: During the light-emitting stage: When the first light-emitting control signal (EM1) input terminal receives a low-level first light-emitting control signal (EM1), the sixth transistor (T6) and the tenth transistor (T10) are turned on, and the light-emitting device (LED) emits light; When the voltage of the second node (B) V(data-pwm)+Vth1-V△sweep(t)-Vdd < the threshold voltage Vth1 of the second transistor (T2), the second transistor (T2) is turned on, the first power supply signal (Vdd) is written to the first node (A), the seventh transistor (T7) is turned off, and the light-emitting device (LED) stops emitting light.

17. The driving method according to claim 15, wherein The driving method further includes: During the data writing phase, a reference voltage signal (Vref) is written to the third node (C); or During the data writing phase, a reference voltage signal (Vref) is written to the third node (C), and a second power supply signal (Vss) is written to the fourth node (D).

18. The driving method according to claim 17, wherein The driving method further includes: During the light-emitting stage: When the first light-emitting control signal (EM1) input terminal receives a low-level first light-emitting control signal (EM1), the thirteenth transistor (T13) turns on, causing the voltage of the third node (C) to change from Vref to Vdd and be coupled to the first node (A), the seventh transistor (T7) turns off, and the light-emitting device (LED) stops emitting light.

19. The driving method according to claim 18, wherein The driving method further includes: During the light-emitting stage: The voltage at the fourth node (D) is the voltage of the second power supply signal (Vss), the tenth transistor (T10) is turned on, and the light-emitting device (LED) emits light; When the voltage of the second node (B) V(data-pwm)+Vth1-V△sweep(t)-Vdd < the threshold voltage Vth1 of the second transistor (T2), the second transistor (T2) is turned on, the first power supply signal (Vdd) is written to the fourth node (D), the tenth transistor (T10) is turned off, and the light-emitting device (LED) stops emitting light.

20. The driving method according to claim 15, wherein During the light emission stage, the voltage of the first node (A) is Vccg+Vth2 or V(data-pam)+Vth2, and the voltage of the second node (B) is V(data-pwm)+Vth1.

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