Memory, operation method for memory, and memory device

Abstract

A memory (10), an operation method for the memory (10), and a memory device. The memory (10) comprises: a plurality of memory banks, a plurality of error detection circuits (100), and an error address generation circuit (200). Each memory bank comprises a plurality of data storage blocks and an ECC storage block. Each error detection circuit (100) is configured to respectively read stored data and check data from a memory bank, and generate a corresponding error detection signal (UCE_flag) on the basis of the stored data and the check data. The error address generation circuit (200) is configured to receive a plurality of error detection signals (UCE_flag) from the plurality of error detection circuits (100), and when any error detection signal (UCE_flag) is at an invalid level, store address information corresponding to an error that does not meet the condition. In this way, on-chip ECC can be used to pre-identify an error occurring in the memory (10). When identifying an on-chip ECC uncorrectable error, an error detection signal (UCE_flag) is generated to timely record the error address information, thereby facilitating subsequent error correction and improving the correctness rate of the memory (10).

Description

A memory, a method of operating the memory, and a storage device.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411455976.8, filed on October 18, 2024, entitled "A memory, a method of operating the memory and a storage device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a memory, a method of operating the memory, and a storage device. Background Technology

[0004] In the semiconductor industry, memory chips such as Dynamic Random Access Memory (DRAM) consist of a memory cell composed of a transistor and a capacitor. DRAM performs data writing operations by storing charge in the capacitor of the memory cell, and data reading operations by reading the charge from the capacitor of the memory cell. With the development of semiconductor technology, the integration density of DRAM is becoming increasingly higher, and the number of errors is also increasing. In some cases, error correction functions can be performed using ECC encoding and / or decoding circuits to correct erroneous bits. Summary of the Invention

[0005] This disclosure provides a memory, a method for operating the memory, and a storage device.

[0006] According to some embodiments of this disclosure, a first aspect of this disclosure provides a memory, including: a plurality of storage repositories, each repository including a plurality of data storage blocks and an ECC storage block; a plurality of error detection circuits corresponding one-to-one with the plurality of storage repositories; each error detection circuit is configured to read stored data and verification data from the plurality of data storage blocks and the ECC storage block of the corresponding repository, and generate a corresponding error detection signal based on the stored data and the verification data, wherein the error detection signal is used to indicate whether the stored data and / or the verification data of the corresponding repository has encountered a conditional error; an error address generation circuit is configured to receive the plurality of error detection signals from the plurality of error detection circuits, and when any of the error detection signals is at an invalid level, store the address information corresponding to the conditional error; wherein the address information includes: error row address information and error column address information.

[0007] In some embodiments, the error address generation circuit is further configured to generate and store error identification information when any of the error detection signals is at an invalid level; wherein the error identification information is used to indicate whether the stored data and / or check data corresponding to the stored address information has encountered an error that does not meet the conditions.

[0008] In some embodiments, the error detection circuit includes: a first detection circuit configured to receive the stored data and the verification data, and compare a checksum generated based on the stored data with the verification data to generate a comparison result; and a first judgment circuit configured to receive the comparison result and determine whether a condition is met, and generate an error detection signal at an invalid level when the comparison result meets the condition, and generate an error detection signal at an valid level when the comparison result does not meet the condition.

[0009] In some embodiments, the error address generation circuit includes: a merging circuit configured to receive multiple error detection signals corresponding to multiple repositories, merge them to generate a total error detection signal, wherein if any one of the error detection signals is at an invalid level, the generated total error detection signal is at an invalid level; a row address generation circuit configured to receive the multiple error detection signals and the total error detection signal, and when any one of the error detection signals is at an invalid level, output the row address information of the corresponding repository as error row address information, and store the error row address information in response to the total error detection signal at an invalid level; and a column address generation circuit configured to store the error column address information corresponding to errors that do not meet the conditions in response to the total error detection signal at an invalid level.

[0010] In some embodiments, the row address generation circuit includes: a plurality of row address latching circuits, each corresponding to one of the plurality of repositories, each row address latching circuit being configured to latch the row address information corresponding to the activation signal in response to the activation signal of the corresponding repository; a row address selection circuit being configured to receive a plurality of error detection signals and a plurality of row address information latched by the plurality of row address latching circuits, and to output the corresponding row address information as error row address information when any of the error detection signals is at an invalid level; and a row address storage circuit being configured to store the error row address information in response to the error detection signal being at an invalid level.

[0011] In some embodiments, the column address generation circuit includes: a column address latch circuit configured to input column address information corresponding to a read signal into a buffer in response to a read signal, and to output the column address information corresponding to the read signal as error column address information from the buffer in response to a read delay signal; wherein the read delay signal is a delayed signal of the read signal; and a column address storage circuit configured to store the error column address information into a corresponding mode register in response to the error detection total signal at an invalid level.

[0012] In some embodiments, the row address storage circuit includes: N serially connected row address storage sub-circuits; a first row address storage sub-circuit configured to store received erroneous row address information when the total error detection signal after N-1 first delays is at an invalid level; an i-th row address storage sub-circuit configured to receive and store the erroneous row address information stored by the (i-1)-th row address storage sub-circuit when the total error detection signal after Ni first delays is at an invalid level; and an N-th row address storage sub-circuit configured to receive and store the erroneous row address information stored by the (N-1)-th row address storage sub-circuit when the total error detection signal is at an invalid level; wherein, the first delay is a plurality of clock cycles, N is greater than or equal to 2, and i is greater than 1 and... The column address storage circuit comprises: N serially connected column address storage sub-circuits; the first column address storage sub-circuit is configured to store the received error row and column address information when the total error detection signal after performing N-1 second delays is at an invalid level; the j-th column address storage sub-circuit is configured to receive and store the error column address information stored by the (j-1)-th column address storage sub-circuit when the total error detection signal after performing Nj second delays is at an invalid level; the N-th column address storage sub-circuit is configured to receive and store the error column address information stored by the (N-1)-th column address storage sub-circuit when the total error detection signal is at an invalid level; wherein, the second delay is a number of clock cycles, and j is a positive integer greater than 1 and less than N.

[0013] According to some embodiments of this disclosure, a second aspect of this disclosure also provides a method for operating a memory, the memory including a plurality of repositories, each repository including a plurality of data storage blocks and an ECC storage block, the method comprising: receiving stored data and verification data read from the plurality of data storage blocks and the ECC storage block of any repository respectively, and generating a corresponding error detection signal based on the stored data and the verification data; wherein the error detection signal is used to indicate whether the stored data and / or the verification data of the corresponding repository has encountered a conditional error; receiving the error detection signal, and storing address information corresponding to the conditional error when the error detection signal is at an invalid level; wherein the address information includes: error row address information and error column address information.

[0014] In some embodiments, when the error detection signal is at an invalid level, error identification information is generated and stored, wherein the error identification information is used to indicate whether the stored data and / or check data corresponding to the stored address information has encountered an error that does not meet the conditions.

[0015] In some embodiments, before receiving the storage data and verification data read from the plurality of data storage blocks and the ECC storage block of the corresponding repository, the method further includes: in response to an activation signal, receiving and latching the row address information of the repository corresponding to the activation signal; and in response to a read signal, receiving and inputting the column address information corresponding to the read signal into a buffer.

[0016] In some embodiments, generating a corresponding error detection signal based on the stored data and the verification data includes: generating a checksum based on the stored data, comparing the checksum with the verification data, and generating a comparison result; receiving the comparison result and determining whether it meets the conditions, and generating the error detection signal at an invalid level when the comparison result meets the conditions, and generating the error detection signal at an valid level when the comparison result does not meet the conditions.

[0017] In some embodiments, receiving the error detection signal and storing the address information corresponding to the error that does not meet the conditions when the error detection signal is at an invalid level includes: receiving multiple error detection signals corresponding to multiple repositories, merging them to generate a total error detection signal, wherein when any error detection signal is at an invalid level, an invalid level error detection signal is generated; selecting the received address information in response to the multiple error detection signals to generate error row address information and error column address information; and storing the error row address information and the error column address information in response to the total error detection signal.

[0018] In some embodiments, the step of selecting received address information in response to a plurality of error detection signals to generate error row address information and error column address information includes: receiving a plurality of error detection signals and a plurality of row address information corresponding to a plurality of repositories, and outputting the row address information of the corresponding repository as error row address information when any of the error detection signals is at an invalid level; and outputting the column address information corresponding to the read signal from the buffer as error column address information in response to a read delay signal, wherein the read delay signal is a delay signal of the read signal.

[0019] According to some embodiments of this disclosure, a third aspect of this disclosure also provides a storage device, including a plurality of memories as described in the first aspect, and a plurality of ECC chips; the error row address information and the error column address information in the memories are used to locate the data location where an error has occurred that does not meet the conditions, and the verification data stored in the ECC chips are used to detect and correct errors in the stored data and / or verification data corresponding to the error row address information and the error column address information.

[0020] This disclosure provides a memory, a method for operating the memory, and a storage device. The memory includes: multiple storage repositories and multiple ECC storage blocks; multiple error detection circuits configured to receive stored data read from corresponding storage repositories and verification data read from corresponding ECC storage blocks, and generate error detection signals, wherein the error detection signals indicate whether a conditional error has occurred in the stored data and / or verification data; and an error address generation circuit configured to receive address information and, in response to any error detection signal, store the address information corresponding to an error that does not meet the condition in a mode register. Thus, the error detection circuits can detect whether a conditional error has occurred in the storage repositories and / or ECC storage blocks, and the error address generation circuits can store the address information corresponding to the error that does not meet the condition in the mode register. In this way, on-chip ECC can be used to pre-identify errors occurring in the memory, and after identifying errors that cannot be corrected by the on-chip ECC, an error detection signal is generated to record the error address information in a timely manner, facilitating subsequent error correction and improving the accuracy of the memory. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure;

[0023] Figure 2 is a schematic diagram of the composition structure of an error detection circuit provided in an embodiment of this disclosure;

[0024] Figure 3 is a schematic diagram of the composition structure of an error address generation circuit provided in an embodiment of this disclosure;

[0025] Figure 4 is a schematic diagram of a data configuration of a mode register provided in an embodiment of this disclosure;

[0026] Figure 5 is a schematic diagram of the composition structure of a row address generation circuit provided in an embodiment of this disclosure;

[0027] Figure 6 is a circuit diagram of a row address generation circuit provided in an embodiment of this disclosure;

[0028] Figure 7 is a schematic diagram of the composition structure of a column address generation circuit provided in an embodiment of this disclosure;

[0029] Figure 8 is a circuit diagram of a column address generation circuit provided in an embodiment of this disclosure;

[0030] Figure 9 is a schematic diagram of the composition structure of a row address storage circuit and a column address storage circuit provided in an embodiment of this disclosure;

[0031] Figure 10 is a circuit diagram of a row address storage circuit and a column address storage circuit provided in an embodiment of this disclosure;

[0032] Figure 11 is a schematic flowchart of an operation method for a memory provided in an embodiment of this disclosure;

[0033] Figure 12 is a schematic diagram of another flow step of a memory operation method provided in an embodiment of this disclosure;

[0034] Figure 13 is a schematic diagram of another flow step of a memory operation method provided in an embodiment of this disclosure;

[0035] Figure 14 is a schematic diagram of another flow step of a memory operation method provided in an embodiment of this disclosure;

[0036] Figure 15 is a schematic diagram of another flow step of a memory operation method provided in an embodiment of this disclosure;

[0037] Figure 16 is a schematic diagram of another flow step of a memory operation method provided in an embodiment of this disclosure;

[0038] Figure 17 is a schematic diagram of the composition structure of a storage device provided in an embodiment of this disclosure. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0040] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0041] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.

[0042] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0043] As used in this disclosure, the term "module" means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0044] In current memory applications, error checking and correcting (ECC) technology can improve the stability and accuracy of stored data. ECC includes sideband ECC and on-die ECC. Sideband ECC uses an additional DRAM chip on the memory module to store ECC codes, and then implements error checking and correction in the controller via an additional ECC data bus. On-die ECC, on the other hand, is implemented within the DRAM chip, with an additional ECC storage area outside the main data storage area to store ECC check data. Because on-die ECC is integrated inside the chip, data can be directly corrected during calculation or transmission without additional processing or transmission, significantly reducing transmission latency and power consumption. However, on-die ECC can only detect and correct single-bit errors.

[0045] This disclosure provides a memory comprising: multiple storage repositories, each repository including multiple data storage blocks and an ECC storage block; multiple error detection circuits corresponding one-to-one with the multiple storage repositories; each error detection circuit is configured to read stored data and verification data from the multiple data storage blocks and the ECC storage block of the corresponding repository, and generate a corresponding error detection signal based on the stored data and verification data, wherein the error detection signal is used to indicate whether a condition-compliant error has occurred in the stored data and / or verification data of the corresponding repository; and an error address generation circuit configured to receive multiple error detection signals from the multiple error detection circuits, and when any error detection signal is at an invalid level, store the address information corresponding to the condition-compliant error in a mode register for storage; wherein the address signal information includes: error row address information and error column address information. Thus, using on-chip ECC, errors occurring in the memory can be pre-identified, and after identifying errors that cannot be corrected by the on-chip ECC, the error address information is recorded in a timely manner according to the indication of the generated error detection signal, facilitating subsequent error correction and improving the accuracy of the memory.

[0046] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0047] In one embodiment of this disclosure, referring to FIG1, a schematic diagram of the composition structure of a memory 10 provided in this embodiment is shown. As shown in FIG1, the memory 10 includes: a plurality of storage repositories, each repository including a plurality of data storage blocks and an ECC storage block; a plurality of error detection circuits 100, corresponding one-to-one with the plurality of storage repositories; each error detection circuit is configured to read stored data and verification data from the plurality of data storage blocks and ECC storage blocks of the corresponding repository, and generate a corresponding error detection signal based on the stored data and verification data, wherein the error detection signal is used to indicate whether the stored data and / or verification data of the corresponding repository has encountered a conditional error; an error address generation circuit 200 is configured to receive a plurality of error detection signals from the plurality of error detection circuits, and when any error detection signal is at an invalid level, store the address information corresponding to the conditional error in a mode register for storage; wherein the address signal information includes: error row address information and error column address information.

[0048] As shown in Figure 1, the memory 10 includes multiple storage banks, each of which includes multiple data storage blocks and ECC memory blocks (not shown in the figure). For DRAM, the multiple storage banks can be divided into multiple memory groups (BG) according to operational needs, and each memory group includes several storage banks (BA). For example, for a memory 10 with 32 storage banks, when the memory 10 is in X4 / X8 operation mode, the memory 10 can be divided into 8 memory groups, each of which includes 4 storage banks (as shown by the dashed box in the figure, a memory group can include 4 storage banks BA0, BA1, BA2, BA3). Each storage bank can be divided into multiple memory sections according to the layout, and each memory section includes multiple memory array tiles (MAT) and at least one ECC memory block (ECC mat). The memory blocks are used to store data, and the ECC memory blocks are used to store parity data. Each storage bank has a corresponding on-chip ECC calculation module, which is used to calculate the stored data read from the storage bank according to a preset algorithm. An error is indicated if the stored data read from the repository and the check data read from the ECC storage block do not match after calculation and comparison. If the error is 1 bit, the on-chip ECC can correct it. However, for errors of 2 bits or more, the on-chip ECC's check capability is insufficient for correction. It's important to understand that the on-chip ECC's check capability is determined by the number of bits in the checksum and the encoding method. For an on-chip ECC using Hamming code encoding, an N-bit checksum can be used to correct 1 bit of error in 2^N-1 bits of data. For example, with an 8-bit checksum, 2^8-1 = 255, meaning an 8-bit checksum can correct 1 bit of error in 255 bits of data. For 128 bits of data, 2^7-1 = 127 < 128 < 2^8-1, therefore an 8-bit ECC checksum is also required to achieve 1-bit verification and correction. For errors of 2 bits or more, if on-chip ECC is used for error correction, more check codes need to be set, the ECC encoding circuit will be more complex, and the ECC calculation module will occupy more memory space, which is not conducive to improving the integration of memory.

[0049] Specifically, when the error detection signal is at an active level, it indicates that the stored data and / or check data of the corresponding repository has encountered a conditional error, while when the error detection signal is at an inactive level, it indicates that the stored data and / or check data of the corresponding repository has encountered a conditional error.

[0050] Multiple error detection circuits 100 can be located in the peripheral area of ​​the memory repository. They are configured to receive stored data read from the corresponding memory repository and check data read from the corresponding ECC memory block. If the stored data and / or check data contain an on-chip ECC-correctable error (i.e., an error of 1 bit or less), it is considered a valid error, and the error detection circuit 100 generates a valid error detection signal. If the stored data and / or check data contain an on-chip ECC-uncorrectable error (i.e., an error of 2 bits or more), it is considered an invalid error, and the error detection circuit 100 generates an invalid error detection signal. The number of error detection circuits 100 can correspond one-to-one with the number of memory repositories, i.e., one error detection circuit 100 per repository. This achieves pre-identification of potential errors within the memory 10 using on-chip ECC. For valid errors, a valid error detection signal is generated; for invalid errors, an invalid error detection signal is generated. The invalid level can be high (logic 1), and the valid level can be low (logic 0). As shown in Figure 1, the error detection circuit 100 can be set in the outer area on the left or right side of the storage repository. It can receive the storage data read from the storage repository and the verification data read from the ECC storage block as quickly as possible, avoiding the misidentification of errors caused by data flipping on the long data bus and improving the accuracy of error identification.

[0051] The error address generation circuit 200, located in the middle region of the memory 10, is configured to receive address information and, in response to any error detection signal, store the address information corresponding to errors that do not meet the conditions in the mode register. This error address generation circuit 200 receives error detection signals generated by multiple error detection circuits 100. If any error detection signal is invalid (i.e., valid), indicating an uncorrectable on-chip ECC error in the memory 10, the error address generation circuit 200 stores the address information corresponding to the error. This ensures timely recording of the address information corresponding to pre-identified uncorrectable on-chip ECC errors, facilitating subsequent correction of the error by the memory controller based on the verification data stored in the external ECC chip, thus improving the memory's accuracy. Positioning the error address generation circuit 200 in the middle region of the memory 10 ensures consistent delays in the arrival of error detection signals from the storage bins on the left and right sides of the memory, preventing incorrect sampling.

[0052] In some embodiments, the address information corresponding to errors that do not meet the conditions is stored in a Reserved for Future Use (RUF) mode register. The memory controller can retrieve the address information corresponding to the error from the memory's mode register using a Mode Register Read (MRR) command or a Mode Register Set (MRS) command. In other embodiments, specific registers may be added to the memory to store the address information corresponding to detected errors that do not meet the conditions; no specific limitations are imposed here.

[0053] In some embodiments, as shown in FIG4, the error column address information further includes: error storage group information (BG<2:0>) and error storage repository information (BA<1:0>). Since the CA address carried in the read command includes storage group information, storage repository information and column address information, in this disclosure, the storage group information (BG<2:0>) and storage repository information (BA<1:0>) and column address information (CA<10:4>) are received, latched and stored together as column address information. In some other embodiments, the storage group information and storage repository information may also be processed separately based on error detection information, which is not specifically limited here.

[0054] In one embodiment of this disclosure, referring to Figures 2 and 4, the error address generation circuit 200 is further configured to generate and store error identification information UCE FLAG when any error detection signal is at an invalid level; wherein, the error identification information UCE FLAG is used to indicate whether the stored data and / or check data corresponding to the address information stored by the error address generation circuit 200 has encountered an error that does not meet the conditions.

[0055] Specifically, the error flag information UCE FLAG is used to mark whether the stored data and / or check data corresponding to the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit 200 have encountered an error that does not meet the conditions. The external memory controller will read the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit 200 through a read command (e.g., the mode register read command MRR). However, the memory controller does not know whether the read address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) is the error address information corresponding to an error that does not meet the conditions. Therefore, while the memory controller reads the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit, it also reads the corresponding error flag information UCE FLAG stored in the error address generation circuit 200. When the FLAG is at the first level, an error has occurred in the corresponding address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE). The memory controller, in conjunction with the check data within the ECC chip, performs error detection / correction. When the error flag FLAG is at the second level, no error has occurred in the corresponding address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE), and the memory controller does not need to perform error detection / correction. The first level can be high (logic 1), and the second level can be low (logic 0); no specific limitation is made here.

[0056] It should be noted that, as shown in Figure 4, each mode register can store 8 data bits (OP<7:0>), corresponding to 8 bits of address information or other information. Specifically, mode registers MR70-73 record NEW RA_UCE<16:0> / NEW CA_UCE<10:4> / NEW BG_UCE<2:0> / NEW BA_UCE<1:0> and mode registers MR74-77 record OLD RA_UCE<16:0> / OLD CA_UCE<10:4> / OLD BG_UCE<2:0> / OLD BA_UCE<1:0> indicates the two address information corresponding to the two reads of data that resulted in an error. NEW and OLD are only used to distinguish between the two address information; they can also be distinguished by (RA1_UCE<16:0> / CA1_UCE<10:4> / BG1_UCE<2:0> / BA1_UCE<1:0>) and (RA0_UCE<16:0> / CA0_UCE<10:4> / BG0_UCE<2:0> / BA0_UCE<1:0>), which is not limited here. In addition to the address information, mode registers MR70-73 and MR74-77 also record the corresponding error flag information UCE FLAG to indicate whether the stored data and check data corresponding to the address information stored in the corresponding mode register have encountered an error. In addition, mode register MR69 records the Serial Number is used to indicate the number of address information entries that have encountered ineligible errors stored in memory. For example, if memory can only store two address information entries that have encountered ineligible errors, then Serial Number = 2.

[0057] In one embodiment of this disclosure, referring to FIG2, a schematic diagram of the composition structure of an error detection circuit 100 provided in this embodiment is shown. As shown in FIG2, the error detection circuit 100 includes: a first detection circuit 101, configured to receive stored data OP<127:0> and check data ECC<7:0>, and compare the check code generated based on the stored data OP<127:0> with the check data ECC<7:0> to generate a comparison result Parity<7:0>; a first judgment circuit 102, configured to receive the comparison result Parity<7:0> and judge whether the comparison result meets the conditions, and generate an error detection signal UCE_flag at an invalid level when the comparison result meets the conditions, and generate an error detection signal UCE_flag at an valid level when the comparison result does not meet the conditions.

[0058] The first detection circuit 101 may include multiple XOR gates to receive stored data OP<127:0> read from the repository and check data ECC<7:0> read from the ECC storage block. It then compares the checksum generated based on the stored data OP<127:0> with the checksum ECC<7:0> to generate a comparison result Parity<7:0>. For example, assuming the stored data is 128 bits and the checksum is 8 bits, a 7-level XOR gate can be set to receive the stored data OP<127:0>, perform an XOR operation to generate an 8-bit checksum, and then compare the checksum ECC<7:0> with the checksum to generate the comparison result Parity<7:0>.

[0059] The first judgment circuit 102 receives the comparison result Parity<7:0> generated by the first detection circuit 101 and determines whether the comparison result meets the conditions. If the comparison result meets the conditions, it generates an invalid error detection signal UCE_flag; if the comparison result does not meet the conditions, it generates an active error detection signal UCE_flag. Specifically, it first determines whether the comparison result Parity<7:0> meets the first condition, which can be whether the comparison result Parity<7:0> is all 0 (= 00000000). If the comparison result Parity<7:0> is all 0, it indicates that the checksum calculated by the stored data OP<127:0> is consistent with the checksum ECC<7:0>, meaning that no error has occurred in the storage. In this case, an active error detection signal UCE_flag is generated. Otherwise, it indicates that the checksum calculated by the stored data OP<127:0> is inconsistent with the checksum ECC<7:0>, meaning that an error has occurred in the storage. Then, the first judgment circuit 102 continues to determine whether the comparison result Parity<7:0> meets the second condition. The second condition here could be that one bit in the 128-bit stored data OP<127:0> is faulty, or one bit in the 8-bit check data ECC<7:0> is faulty. Since these errors are all errors that can be corrected by the on-chip ECC, a valid error detection signal UCE_flag is generated. Otherwise, it indicates that two or more bits of the checksum and / or check data ECC generated by the stored data OP<127:0> are faulty, meaning that an error that cannot be corrected by the on-chip ECC has occurred in the stored data. In this case, an invalid error detection signal UCE_flag is generated.

[0060] The first judgment circuit 102 can be composed of multi-level logic circuit operations, such as NAND gates and XOR gates. The specific circuit of the first judgment circuit 102 corresponds one-to-one with the first condition and the second condition. Those skilled in the art should understand that when different ECC calculation encoding methods are used, the corresponding first condition and second condition will also be different; therefore, the implementation circuit of the first judgment circuit 102 will also be different. This disclosure does not limit the specific circuit of the first judgment circuit 102 in any way.

[0061] It's important to note a special case: when a 2-bit error occurs in the stored data and / or check data, but the combined encoding of multiple error locations still corresponds to a single error location, the on-chip ECC will consider a 1-bit error to have occurred in the stored data and / or check data, resulting in a missed detection of an ineligible error. To improve the probability of correct error identification, this situation can be avoided as much as possible by modifying the on-chip ECC's encoding matrix. This disclosure does not delve into the specific implementation of the on-chip ECC's encoding matrix.

[0062] In one embodiment of this disclosure, referring to Figures 3 and 4, a schematic diagram of the composition structure of an error address generation circuit 200 provided in this embodiment is shown. As shown in Figure 3, the error address generation circuit 200 includes: a merging circuit 201, configured to receive multiple error detection signals UCE_flag<31:0> corresponding to multiple repositories, and merge them to generate a total error detection signal UCE_flag_all, wherein if any error detection signal UCE_flag is at an invalid level, the generated total error detection signal UCE_flag_all is at an invalid level; and a row address generation circuit 202, configured to receive multiple error detection signals UCE_flag<31:0> and the total error detection signal UCE_flag_all. When any error detection signal UCE_flag is at an invalid level, the row address information RA of the corresponding repository is output as error row address information (RA_UCE), and the error row address information (RA_UCE) is stored in response to the invalid error detection total signal UCE_flag_all. The column address generation circuit 203 is configured to store the error column address information (CA_UCE / BG_UCE / BA_UCE) corresponding to the error that does not meet the conditions in response to the invalid error detection total signal UCE_flag_all.

[0063] Since each repository corresponds to an error detection circuit 100 and generates a corresponding error detection signal UCE_flag, as shown in Figure 1, when a memory 10 includes 32 repositories, 32 error detection signals UCE_flag<31:0> will be generated. To reduce the space occupied by the error address generation circuit 200 in the memory 10, a merging circuit 201 can be set up to receive multiple error detection signals UCE_flag<31:0> corresponding to multiple repositories and merge them to generate a total error detection signal UCE_flag_all. When any error detection signal UCE_flag is at an invalid level, that is, when any repository experiences an on-chip ECC uncorrectable error, the total error detection signal UCE_flag_all generated by the merging circuit 201 is also at an invalid level, which enables the subsequent row address generation circuit 202 and column address generation circuit 203 to store the row address information and column address information corresponding to the error respectively.

[0064] In some embodiments, the merging circuit 201 can be a multi-input OR gate. The input of the OR gate receives multiple error detection signals UCE_flag<31:0>, and the output of the OR gate outputs the total error detection signal UCE_flag_all.

[0065] The row address generation circuit 202 can select the received row address information RA in response to multiple error detection signals UCE_flag<31:0>, generate error row address information, and store it in the corresponding mode register in response to the error detection total signal UCE_flag_all; while the column address generation circuit 203 directly stores the corresponding error column address information in the corresponding mode register in response to the error detection total signal UCE_flag_all.

[0066] It is important to note that, according to the DRAM truth table, the row address information RA is obtained by decoding the command / address signal corresponding to the activation command, and the column address information CA is obtained by decoding the command / address signal corresponding to the read command. As for the error detection signal UCE_flag, it is generated by the error detection circuit 100 through logical operations after the memory 10 receives the read command. Therefore, it is necessary to select or delay the reading of the received address information RA / CA through multiple error detection signals UCE_flag<31:0> to ensure that the currently occurring error has an accurate correspondence with the stored error row address information and error column address information. Specifically, as shown in Figure 3, in the row address generation circuit 202, multiple error detection signals UCE_flag<31:0> are used to select from the multiple row address information RAs received in parallel. This avoids the occurrence of cross-read / write operations, i.e., when the memory 10 has not completed a read operation on one repository, it simultaneously performs an activation operation on another repository, causing the row address information RA corresponding to the next activation operation to be mistakenly sampled by the error address generation circuit 200 in response to the current total error detection signal UCE_flag_all. Since the column address information CA and the error detection signal UCE_flag are both generated based on the read command, their delays have a fixed correspondence. By delaying the reading of the corresponding column address information, the possibility of missampling is relatively small. Therefore, the received column address information CA can be directly used as the error column address information after a delay. For the mode register, as long as any error detection signal UCE_flag is at an invalid level, that is, any uncorrectable error of on-chip ECC has occurred in any storage device, the address information corresponding to the error will be stored in the mode register in response to the invalid error detection signal UCE_flag, so as to facilitate subsequent error location and correction.

[0067] In some embodiments, the column address generation circuit 203 may also adopt a design similar to that of the row address generation circuit 202. That is, the column address generation circuit 203 also selects the received column address information CA in response to multiple error detection signals UCE_flag<31:0>, generates error column address information, and stores it in the corresponding mode register in response to the error detection total signal UCE_flag_all. In one embodiment of this disclosure, referring to FIG5, a schematic diagram of the composition structure of a row address generation circuit 202 provided in this disclosure embodiment is shown. As shown in FIG4, the row address generation circuit 202 includes: multiple row address latch circuits 2021, corresponding one-to-one with multiple repositories, each row address latch circuit 2021 being configured to respond to the activation signal ACT of the corresponding repository. <31> Activation signal ACT <31> The corresponding row address information RA31 is latched; the row address selection circuit 2022 is configured to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 latched by multiple row address latching circuits 2021, and output the corresponding row address information RA as the error row address information RA_UCE when any error detection signal UCE_flag is at an invalid level; the row address storage circuit 2023 is configured to store the error row address information RA_UCE in response to the error detection total signal UCE_flag_all at an invalid level.

[0068] As mentioned earlier, since both the row address information RA and the activation signal ACT of the stored data are obtained by decoding the command / address signal corresponding to the activation signal ACT, in order to match the delay of the error detection signal UCE_flag, multiple row address latch circuits 2021 corresponding to multiple repositories can be set up. Each row address latch circuit 2021 is used to respond to the corresponding activation signal ACT. <31> The corresponding command / address signal is decoded to obtain the corresponding repository row address information RA31, which is then latched. The row address selection circuit 2022 is configured to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 latched by multiple row address latching circuits 2021, and output the corresponding row address information RA as error row address information RA_UCE when any error detection signal UCE_flag is at an invalid level. The row address selection circuit 2022 is used to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 latched by multiple row address latching circuits 2021, and selects to generate error row address information RA_UCE based on the multiple error detection signals UCE_flag<31:0>. For example, in the multiple error detection signals UCE_flag<31:0>, UCE_flag... <30> If the level is invalid, the corresponding row address information RA31 is output as the error row address information RA_UCE. When the error detection signal UCE_flag corresponding to any repository is invalid, it indicates that an uncorrectable on-chip ECC error has occurred in the repository. Therefore, the enabled row address selection circuit 2022 selects to generate the row address information corresponding to that repository, which is the error row address information RA_UCE. The row address storage circuit 2023 receives the error row address information RA_UCE generated by the row address selection circuit 2022 and, in response to the invalid error detection total signal UCE_flag_all, stores the error row address information RA_UCE in the corresponding mode register. It should be noted that, as shown in Figure 4, the mode register corresponding to the row address information can be a preset redundant mode register in the memory, such as mode registers MR70 to MR72, three mode registers used to store 17 bits of error row address information, with each mode register storing 8 bits.

[0069] In some embodiments, referring to FIG6, a circuit diagram of a row address generation circuit 202 provided in this disclosure is shown. As shown in FIG6, each row address latch circuit 2021 may include a set of latches. The data input terminal of each latch receives one bit of data from a set of row address signals RA<16:0> of the corresponding repository. The clock terminal of each latch receives an activation signal ACT31 of the corresponding repository (here, the set of latches included in the row address latch circuit 2021 corresponding to the 32nd repository is used as an example). In response to the activation signal ACT31, the corresponding repository BA is... <31> One bit of data in the corresponding row address information RA31<16:0> is latched. Therefore, the number of latches in the row address latch circuit 2021 can be set to be the same as the number of bits in the row address information RA<16:0> of the storage repository, and each bit of data in the row address information RA<16:0> is latched one by one.

[0070] As shown in Figure 6, the row address selection circuit 2022 receives multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 latched by multiple row address latching circuits 2021, and selects to generate error row address information RA_UCE based on the multiple error detection signals UCE_flag<31:0>. For example, in the multiple error detection signals UCE_flag<31:0>, UCE_flag... <30> If the level is invalid, the corresponding row address information RA31 will be output as error row address information RA_UCE. Referring again to Figure 6, the row address selection circuit 2022 may include a group (17) of selectors. Each selector's multiple (32) inputs are used to receive the same bit from the multiple (32) row address information RA31-RA0 latched by the multiple (32) row address latching circuits 2021. For example, the first selector MUX receives RA0... <0> …RA31 <0> The second selector MUX receives RA0 respectively. <1> …RA31 <1> Similarly, the control terminal of each selector MUX receives multiple error detection signals UCE_Flag<31:0> corresponding to multiple repositories. If any repository has an error that does not meet the conditions, i.e., an error that cannot be corrected by the on-chip ECC, then the error detection signal UCE_flag corresponding to that repository is at an invalid level (UCE_flag=1). Then, the selector is controlled to output 1 bit of row address information corresponding to that repository. Therefore, the set of (17 bits) row address information output by a set of selector MUXs included in the row address selection circuit 2022 is denoted as the error row address information RA_UCE<16:0>. Referring again to Figure 6, the row address storage circuit 2023 may include a set of 17 flip-flops. Each flip-flop's data input receives one bit from the error row address information RA_UCE<16:0>, and its clock input receives the error detection total signal UCE_flag_all. In response to the invalid error detection total signal UCE_flag_all, the flip-flop stores one bit of the error row address information RA_UCE<16:0> into the corresponding mode register. The set of 17 flip-flops in the row address storage circuit 2023 stores all 17 bits of the error row address information RA_UCE<16:0> in parallel into the corresponding mode registers. It is important to note that the number of flip-flops in a set corresponds to the number of bits in the mode register; every 8 flip-flops constitute one mode register. For example, if the error row address information RA_UCE<16:0> includes 17 bits, then 17 flip-flops are needed to form three 8-bit (capacity) mode registers to store it.For simplicity in the illustration, only one latch and one flip-flop are shown in the attached diagram. In the actual circuit, the memory includes 32 storage locations, the row address information RA includes 17 bits of data, the row address latch circuit 2021 may include 32 groups of latches, each group including 17 latches, corresponding to the 17 bits of data of the row address signal RA<16:0>, the row address selection circuit 2022 also includes 32 groups of selectors, each group including 17 selectors, corresponding to the 17 bits of data of the row address signal RA<16:0>, and the row address storage circuit 2023 may include 17 flip-flops, corresponding to the 17 bits of data of the error row address signal RA_UCE<16:0>.

[0071] In one embodiment of this disclosure, referring to FIG7, a schematic diagram of the composition structure of a column address generation circuit 203 provided in this embodiment is shown. As shown in FIG7, the column address generation circuit 203 includes: a column address latch circuit 2031, configured to input column address information corresponding to a read signal into a buffer in response to a read signal, and to output the column address information corresponding to the read signal as error column address information from the buffer in response to a read delay signal; wherein the read delay signal is a delayed signal of the read signal; and a column address storage circuit 2032, configured to store the error column address information into a corresponding mode register in response to an error detection total signal at an invalid level.

[0072] As mentioned earlier, since the column address information CA of the stored data is obtained by decoding the command / address signal corresponding to the read command, a column address latch circuit 2031 can be configured to decode the command / address signal in response to the read signal READ to obtain the corresponding column address information CA and input it into the buffer. In response to the read delay signal READ_DL, the column address information CA corresponding to the read signal READ is output from the buffer as the error column address information CA_UCE. It is understandable that during the DRAM data reading process, there is a delay from decoding the read signal READ from the command / address signal decoder to reading the stored data from the storage repository, and then transmitting the stored data to the data port. The read delay signal READ_DL is the read signal READ that matches these delays. For the error detection signal UCE_flag and the total error detection signal UCE_flag_all, these delays are also required. Therefore, the read delay signal READ_DL can be used as the output trigger signal of the column address latch circuit 2031, so that the error detection signal UCE_flag and the total error detection signal UCE_flag_all can be matched with the error column address information CA_UCE released from the column address latch circuit 2031. Therefore, the error column address information CA_UCE here does not need to be selected; it is simply the column address information CA received by the column address latch circuit 2031.

[0073] The column address storage circuit 2032 receives the error column address information CA_UCE output by the column address latch circuit 2031, and responds to the error detection total signal UCE_flag_all which is at an invalid level, storing the error column address information CA_UCE into the corresponding mode register.

[0074] In some embodiments, the error column address information CA_UCE<11:0> includes 7-bit column address information CA<10:4>, 3-bit memory group address information BG<2:0>, and 2-bit memory bank address information BA<1:0>. Therefore, redundant mode registers preset in the memory, such as MR72 to MR73 (two mode registers), can be used to store the 12-bit error column address information CA_UCE<12:0>. The error column address information CA_UCE<11:0> can share mode register MR72 with the error row address information RA_UCE<16:0>.

[0075] In some embodiments, referring to FIG8, a schematic diagram of a column address generation circuit 203 provided in an embodiment of the present disclosure is shown. As shown in FIG8, the column address latch circuit 2031 may include multiple first-in-first-out (FIFO) buffers. The data input terminal of the FIFO buffer receives column address information CA (not shown in the figure) generated by decoding the command / address signal corresponding to the read command. The input clock terminal receives the read signal READ, which is used to input the corresponding column address information CA into the FIFO buffer in response to the read signal READ. The output clock terminal receives the read delay signal READ_DL, which is used to output the error column address information CA_UCE<11:0> from the FIFO buffer in response to the read delay signal READ_DL. Since the delay from the read signal READ to the read delay signal READ_DL is affected by the column access strobe delay tAA, the memory 10 may receive the next read command during this delay, and the column address will change accordingly. In order to store the column address corresponding to each read command, a FIFO buffer can be set, and the depth of the FIFO buffer satisfies the following condition: depth = t(READ to READ_DL) / tccds. For example, the depth of the FIFO buffer can be set to 10. The number of FIFO buffers should match the number of bits in the error column address information CA_UCE<11:0>, which can be 12. Each FIFO buffer corresponds to receiving and outputting one bit of column address information.

[0076] The column address storage circuit 2032 may include multiple flip-flops. The data input of the flip-flops receives the error column address information CA_UCE<11:0>, and the clock input receives the error detection total signal UCE_flag_all. In response to the invalid error detection total signal UCE_flag_all, the circuit stores the error column address information CA_UCE<11:0> into the corresponding mode register. Similarly, the multiple flip-flops correspond to multiple bits in the mode register. For example, if the error column address information CA_UCE<11:0> includes 12 bits, then 12 flip-flops and two 8-bit (capacity) mode registers are needed to store it. For simplicity, only one flip-flop is shown in the attached diagram. In the actual circuit, the column address storage circuit 2032 may include 12 flip-flops, corresponding to the 12 bits of the error column address information CA_UCE<11:0>.

[0077] In one embodiment of this disclosure, referring to FIG9, a schematic diagram of the composition structure of a row address storage circuit 2023 and a column address storage circuit 2032 provided in this embodiment of the disclosure is shown. As shown in Figure 9, the row address storage circuit 2023 includes: N serially connected row address storage sub-circuits; the first row address storage sub-circuit 2023_1 is configured to store the received erroneous row address information when the error detection total signal UCE_flag_all_dn-1 after performing N-1 first delays is at an invalid level; the i-th row address storage sub-circuit 2023_i is configured to receive and store the erroneous row address information stored in the (i-1)-th row address storage sub-circuit 2023_i-1 when the error detection total signal UCE_flag_all_dn-i after performing Ni first delays is at an invalid level; the N-th row address storage sub-circuit 2023_N is configured to receive and store the erroneous row address information stored in the (N-1)-th row address storage sub-circuit 2023_N-1 when the error detection total signal UCE_flag_all is at an invalid level; wherein, the first delay is several The number of clock cycles is N, where N is greater than or equal to 2, and i is a positive integer greater than 1 and less than N. The first column address storage sub-circuit 2032_1 is configured to store the received error row and column address information when the error detection total signal UCE_flag_all_Dn-1 after performing N-1 second delays is at an invalid level. The j-th column address storage sub-circuit 2032_j is configured to receive and store the error column address information stored in the (j-1)-th column address storage sub-circuit 2032_j when the error detection total signal UCE_flag_all_Dn-j after performing Nj second delays is at an invalid level. The N-th column address storage sub-circuit 2032_N is configured to receive and store the error column address information stored in the (N-1)-th column address storage sub-circuit 2032_N when the error detection total signal UCE_flag_all is at an invalid level. The second delay is several clock cycles, and j is a positive integer greater than 1 and less than N.

[0078] In the row address storage circuit 2023, N serially connected row address storage sub-circuits can be configured. The first row address storage sub-circuit can respond to the invalid error detection total signal UCE_flag_all, storing the error row address information RA_UCE corresponding to the current error into the corresponding mode register. To distinguish between the previous error and the current error, the error detection total signal UCE_flag_all_dn-i received by the i-th row address storage sub-circuit 2023_i can be set to be delayed by several clock cycles compared to the error detection total signal UCE_flag_all_dn-i-1 received by the (i+1)-th row address storage sub-circuit 2023_i+1, where N is greater than or equal to 2. In this way, the error detection total signal used by each row address storage sub-circuit to respond to and store is different, and each is delayed by several clock cycles compared to the previous one. Thus, the address information corresponding to N errors is stored separately, and the storage device can read the address information corresponding to multiple errors through multiple rounds of mode register read commands and perform error correction.

[0079] In some embodiments, continuing to refer to FIG9, the row address storage circuit 2023 further includes: a first delay chain 2024; the first delay chain is configured to sequentially perform multiple first delays on the total error detection signal to generate multiple delayed total error detection signals, wherein the first delay is several clock cycles. Specifically, the first delay chain 2024 performs N-1 first delays on the received total error detection signal, generating and outputting a corresponding delayed total error detection signal each time. For example, the delayed total error detection signal generated by the first delay chain 2024 performing one first delay on the total error detection signal is sent to the (N-1)th row address storage sub-circuit, the delayed total error detection signal generated by performing two first delays on the total error detection signal is sent to the (N-2)th row address storage sub-circuit, and so on, with the delayed total error detection signal generated by performing N-1 first delays on the total error detection signal being sent to the first row address storage sub-circuit.

[0080] It should be noted that the first delay is executed N-1 times in sequence to ensure that the total error detection signal received by each row address storage sub-circuit is delayed by several clock cycles compared to the previous one. The specific number of clock cycles for the first delay can be adjusted according to the requirements of the buffer parameters in the delay chain, and no specific limit is made here.

[0081] In some embodiments, continuing to refer to FIG9, the column address storage circuit 2032 further includes: a second delay chain 2033; the second delay chain 2033 is configured to sequentially perform multiple second delays on the total error detection signal to generate multiple delayed total error detection signals, wherein the second delay is a number of clock cycles. Specifically, the second delay chain performs N-1 second delays on the received total error detection signal, generating and outputting a corresponding delayed total error detection signal each time. For example, the delayed total error detection signal generated by the second delay chain 2033 performing one second delay on the total error detection signal is sent to the (N-1)th column address storage sub-circuit, the delayed total error detection signal generated by performing two second delays on the total error detection signal is sent to the (N-2)th column address storage sub-circuit, and so on, with the delayed total error detection signal generated by performing N-1 second delays on the total error detection signal being sent to the first column address storage sub-circuit.

[0082] It should be noted that the second delay is executed N-1 times in sequence to ensure that the total error detection signal received by each column address storage sub-circuit is delayed by a certain number of clock cycles compared to the previous one. The specific number of clock cycles for the second delay can be adjusted according to the requirements of the buffer parameters in the delay chain. The second delay and the first delay can be set to the same number of clock cycles, and no specific limitation is made here.

[0083] In some embodiments, referring to FIG10, a circuit diagram of a row address storage circuit 2023 and a column address storage circuit 2032 provided in an embodiment of the present disclosure is shown. As shown in FIG10, the row address storage circuit 2023 may include two sets of serially connected flip-flops (a set of serially connected flip-flops can be used as a row address storage sub-circuit). Each set of flip-flops includes 17 parallel flip-flops. In the first set of flip-flops, the data input terminal of each flip-flop receives 17 bits of data of the error row address signal RA_UCE<16:0>, and the clock terminal receives the delayed signal of the error detection total signal UCE_flag_all. The output terminal of each flip-flop in the first set of flip-flops is connected to the data input terminal of a corresponding flip-flop in the second set of flip-flops. The clock terminal of each flip-flop in the second set of flip-flops receives the error detection total signal UCE_flag_all. The column address storage circuit 2032 may include two sets of serially connected flip-flops (each set of serially connected flip-flops can serve as a column address storage sub-circuit). Each set of flip-flops includes 12 parallel flip-flops. In the first set, the data input of each flip-flop receives 12 bits of the error column address signal CA_UCE<11:0>, and the clock input receives a delayed signal of the error detection total signal UCE_flag_all. The output of each flip-flop in the first set is connected to the data input of a corresponding flip-flop in the second set. The clock input of each flip-flop in the second set receives the error detection total signal UCE_flag_all. A row address storage circuit 2023 and a column address storage circuit 2032 with a depth of 2 (N=2) can store two sets of error address information (each set includes error row address information RA_UCE and error column address information CA_UCE). The storage device can read two invalid error messages using multiple mode register read commands, improving error correction efficiency.

[0084] It is important to note that when the row address storage circuit 2023 and the column address storage circuit 2032 each include N serially connected storage sub-circuits, at least one flip-flop is required. That is, at least one bit in the mode register is used to store N (as shown in Figure 4, the 8 flip-flops in the mode register MR69 are used to store the Serial Number). This records the number of error address information stored in the memory. In this way, the controller can determine how many error address information in the memory needs error correction by reading specific bits in the mode register. For example, mode register MR69 OP... <0> =0 indicates that there is one erroneous address in memory that does not meet the requirements and needs to be corrected. Mode register MR69 OP <0> =1 indicates that there are two incorrect address messages in the memory that do not meet the conditions and need to be corrected.

[0085] The memory 10 may also include a counting circuit for counting the total error detection signal UCE_flag_all, thereby recording the number of times the memory has encountered an error that does not meet the conditions. The controller can correct the error of the memory 10 by reading the value of the counting circuit.

[0086] This disclosure also provides an operation method for a memory, the memory including multiple repositories, each repository including multiple data storage blocks and ECC storage blocks, the operation method including: receiving stored data and verification data read from the multiple data storage blocks and ECC storage blocks of any repository respectively, and generating a corresponding error detection signal based on the stored data and verification data; wherein, the error detection signal is used to indicate whether a conditional error has occurred in the stored data and / or verification data of the corresponding repository; receiving the error detection signal, and storing the address information corresponding to the conditional error when the error detection signal is at an invalid level; wherein, the address information includes: error row address information and error column address information.

[0087] In one embodiment of this disclosure, referring to FIG11, a flowchart illustrating the operation steps of a memory method provided in this embodiment is shown. As shown in FIG11, the operation method includes the following steps:

[0088] Step S1: Receive storage data and verification data read from multiple data storage blocks and ECC storage blocks of any repository respectively, and generate corresponding error detection signals based on the storage data and verification data; wherein, the error detection signal is used to indicate whether the storage data and / or verification data of the corresponding repository have encountered an error that meets the conditions;

[0089] Step S2: Receive the error detection signal, and when the error detection signal is at an invalid level, store the address information corresponding to the error that does not meet the conditions; wherein, the address information includes: error row address information and error column address information.

[0090] In some embodiments, referring to Figures 1 and 11, the specific process of step S1 includes: each error detection circuit 100 receives storage data and verification data read from multiple data storage blocks and ECC storage blocks of the corresponding repository, and generates a corresponding error detection signal based on the storage data and verification data; wherein, if an error that meets the conditions occurs in the storage data and / or verification data, an error detection signal with an effective level is generated; otherwise, an error detection signal with an invalid level is generated.

[0091] In some embodiments, referring to Figures 1 and 11, step S2 specifically includes: the error address generation circuit 200 receives an error detection signal, and when the error detection signal is at an invalid level, stores the address information corresponding to the non-compliant error in the mode register. Specifically, the error address generation circuit 200 receives multiple error detection signals corresponding to multiple error detection circuits 100. If any error detection signal is at an invalid level, indicating that a non-compliant error has occurred in the stored data and / or verification data in the corresponding repository, the error address generation circuit 200 is enabled to store the address information corresponding to the non-compliant error in the mode register.

[0092] This allows for the detection of errors that meet certain criteria within the memory repository and / or ECC memory block, and the storage of address information corresponding to errors that do not meet the criteria into the mode register. Thus, on-chip ECC can pre-identify errors occurring in memory, and upon identifying errors that cannot be corrected by the on-chip ECC, the error address information can be recorded promptly, facilitating subsequent error correction and improving memory accuracy.

[0093] Referring to Figures 1, 4, and 12, this operation method, while performing step S2, also includes:

[0094] Step S3: When the error detection signal UCE_flag is at an invalid level, generate and store the error identification information UCE FLAG, wherein the error identification information UCE FLAG is used to indicate whether the stored data and / or check data corresponding to the stored address information has an error that does not meet the conditions.

[0095] Here, the error address generation circuit 200 is also configured to generate and store error identification information UCE FLAG when any error detection signal is at an invalid level. The error identification information UCE FLAG is used to mark whether the stored data and / or check data corresponding to the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit 200 have encountered an error that does not meet the conditions. The external memory controller reads the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit 200 using a read command (e.g., mode register read command MRR). However, the memory controller does not know whether the read address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) corresponds to an error address that does not meet the conditions. Therefore, while the memory controller reads the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit, it also reads the corresponding error identification information UCE stored in the error address generation circuit 200. The FLAG is also read. When the error flag information UCE FLAG is at the first level, the data of the corresponding address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) has an error that does not meet the conditions. The memory controller performs error detection / correction by combining the verification data in the ECC chip. When the error flag information UCE FLAG is at the second level, the data of the corresponding address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) has not an error that does not meet the conditions. The memory controller does not need to perform error detection / correction processing.

[0096] Referring to Figure 13, which illustrates another flow diagram of a memory operation method provided in an embodiment of this disclosure. As shown in Figure 11, before receiving storage data read from a corresponding repository and verification data read from the ECC storage block and generating an error detection signal, the operation method further includes:

[0097] Step S00: In response to the activation signal, receive the row address information of the repository corresponding to the activation signal and latch it;

[0098] Step S01: In response to the read signal, receive the column address information corresponding to the read signal and input it into the buffer.

[0099] In some embodiments, referring to Figures 4 and 13, the specific process of step S00 includes: a row address latching circuit 2021, used to latch the row address information RA of the repository obtained by decoding the command / address signal corresponding to the activation signal ACT in response to the activation signal ACT.

[0100] In some embodiments, referring to Figures 6 and 11, the specific process of step S01 includes: a column address latch circuit 2031, used to input the column address information CA of the repository obtained by decoding the command / address signal corresponding to the read signal READ into a buffer in response to the read signal READ.

[0101] Since the error detection signal is generated by performing logical operations on the stored data and / or check data by UCE_flag, in order to match the delay of the error detection signal UCE_flag, the address information needs to be latched first, and then the address information corresponding to the error needs to be generated according to the potential of the error detection signal UCE_flag.

[0102] Referring to Figure 14, a schematic diagram of another flow step of a memory operation method provided in this embodiment of the present disclosure is shown. As shown in Figure 14, step S1 of this operation method: generating a corresponding error detection signal based on stored data and verification data, specifically includes;

[0103] Step S11: Generate a check code based on the stored data, and compare the check code with the check data to generate a comparison result;

[0104] Step S12: Receive the comparison result and determine whether it meets the conditions. If the comparison result meets the conditions, generate an invalid error detection signal. If the comparison result does not meet the conditions, generate a valid error detection signal.

[0105] In some embodiments, in conjunction with Figures 2 and 14, the specific process of step S11 includes: the first detection circuit 101 receives the stored data OP<127:0> and the verification data ECC<7:0>, and compares the verification code generated according to the stored data OP<127:0> with the verification data ECC<7:0> to generate the comparison result Parity<7:0>.

[0106] In some embodiments, in conjunction with Figures 2 and 14, the specific process of step S12 includes: a first judgment circuit 102 receives the comparison result Parity<7:0> and determines whether it meets the conditions; when the comparison result meets the conditions, it generates an error detection signal UCE_flag at an invalid level; when the comparison result does not meet the conditions, it generates an error detection signal UCE_flag at an effective level. Specifically, it can first determine whether the comparison result Parity<7:0> meets the first condition. The first condition can be whether the comparison result Parity<7:0> is all 0 (=00000000). If the comparison result Parity<7:0> is all 0, it indicates that the checksum calculated by the stored data OP<127:0> is consistent with the checksum ECC<7:0>, that is, no error has occurred in the storage. In this case, an effective level error detection signal UCE_flag is generated. Otherwise, it indicates that the checksum calculated by the stored data OP<127:0> is inconsistent with the checksum ECC<7:0>, that is, an error has occurred in the storage. Then the first judgment circuit 102 continues to determine whether the comparison result Parity<7:0> meets the second condition. The second condition here could be that one bit in the 128-bit stored data OP<127:0> is faulty, or one bit in the 8-bit check data ECC<7:0> is faulty. Since these errors are all errors that can be corrected by the on-chip ECC, a valid error detection signal UCE_flag is generated. Otherwise, it indicates that two or more bits of the checksum and / or check data ECC generated by the stored data OP<127:0> are faulty, meaning that an error that cannot be corrected by the on-chip ECC has occurred in the stored data. In this case, an invalid error detection signal UCE_flag is generated.

[0107] Referring to Figure 15, a schematic diagram of another flow step of a memory operation method provided in an embodiment of the present disclosure is shown. As shown in Figure 15, step S2 of the operation method: receiving an error detection signal, and storing the address information corresponding to the error that does not meet the conditions when the error detection signal is at an invalid level, specifically includes;

[0108] Step S21: Receive multiple error detection signals corresponding to multiple repositories, merge them to generate a total error detection signal, wherein if any error detection signal is at an invalid level, an invalid level error detection signal is generated;

[0109] Step S22: In response to multiple error detection signals, select the received address information and generate error row address information and error column address information;

[0110] Step S23: In response to the overall error detection signal, store the error row address information and the error column address information.

[0111] In some embodiments, referring to Figures 3 and 15, step S21 specifically includes: a merging circuit 201, used to receive multiple error detection signals UCE_flag<31:0> corresponding to multiple repositories, and merge them to generate a total error detection signal UCE_flag_all. When any error detection signal UCE_flag is at an invalid level, that is, when any repository experiences an on-chip ECC uncorrectable error, the total error detection signal UCE_flag_all generated by the merging circuit 201 is also at an invalid level.

[0112] In some embodiments, in conjunction with Figures 3 and 15, the specific process of step S22 includes: row address generation circuit 202 and column address generation circuit 203, used to select the received address information RA / CA in response to multiple error detection signals UCE_flag<31:0>, and generate error row address information and error column address information.

[0113] In some embodiments, referring to Figures 3 and 15, step S23 specifically includes: row address generation circuit 202 and column address generation circuit 203, in response to the error detection total signal UCE_flag_all, storing the error row address information and error column address information into the corresponding mode registers respectively. For the mode registers, as long as any error detection signal UCE_flag is at an invalid level, that is, any uncorrectable on-chip ECC error has occurred in any storage device, the address information corresponding to the error is stored in the mode register in response to the invalid error detection total signal UCE_flag, facilitating subsequent error location and correction.

[0114] Referring to Figure 16, a schematic diagram of another flow step of a memory operation method provided in an embodiment of this disclosure is shown. As shown in Figure 16, step S22 of the operation method: selecting received address information in response to a plurality of error detection signals to generate error row address information and error column address information, specifically includes:

[0115] Step S221: Receive multiple error detection signals and multiple row address information corresponding to multiple repositories, and when any error detection signal is at an invalid level, output the row address information of the corresponding repository as error row address information;

[0116] Step S222: In response to the read delay signal, output the column address information corresponding to the read signal from the buffer as the error column address information, wherein the read delay signal is the delay signal of the read signal.

[0117] In some embodiments, referring to Figures 5 and 16, the specific process of step S221 includes: a row address selection circuit 2022, used to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 corresponding to multiple repositories, and selects to generate error row address information RA_UCE according to the multiple error detection signals UCE_flag<31:0> corresponding to multiple repositories. Wherein, if the error detection signal UCE_flag corresponding to any repository is at an invalid level, it indicates that an on-chip ECC uncorrectable error has occurred in the repository. Therefore, the row address selection circuit 2022 is enabled to select and generate the row address information corresponding to that repository, which is the error row address information RA_UCE.

[0118] In some embodiments, in conjunction with Figures 7 and 16, the specific process of step S222 includes: the column address latch circuit 2031, in response to the read delay signal READ_DL, outputs the column address information CA corresponding to the read signal READ from the buffer as the error column address information CA_UCE.

[0119] It should be noted that this embodiment can be implemented in conjunction with the memory provided in the previous embodiment. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment, and will not be repeated here to avoid repetition.

[0120] This disclosure also provides a storage device, including the memory as provided in the above embodiments, and a plurality of ECC chips, wherein the ECC chips correct errors in the memory that do not meet the conditions according to the address in the mode register in the memory.

[0121] In one embodiment of this disclosure, referring to FIG15, a schematic diagram of the composition structure of a storage device 20 provided in another embodiment of this disclosure is shown. As shown in FIG15, the storage device 20 includes: a plurality of memories 10 based on the above embodiments, and a plurality of ECC chips 30. Error row address information and error column address information in the memories 10 are used to locate the data location where an error has occurred. The verification data stored in the ECC chips 30 are used to detect and correct errors in the stored data and / or verification data corresponding to the error row address information and the error column address information.

[0122] Specifically, the memory controller can read the error flag information UCE FLAG and the corresponding address information RA / CA stored in each memory chip from the storage device through the mode register read command (MRR or MRS). It then determines whether the error flag information UCE FLAG in each memory chip marks that the corresponding memory chip has encountered an error that does not meet the conditions. Specifically, when the error flag information UCE FLAG is at the first level, it indicates that an error that does not meet the conditions has occurred in the corresponding memory chip 10. The memory controller obtains the stored address information and the check data in the ECC chip 30, and performs error detection / correction on the error that does not meet the conditions in the memory chip 10. At this time, the check data in the ECC chip 30 is only used to detect and correct errors in the specified memory chip 10, and there is no need to detect and correct errors in all memory chips 10, which greatly improves the error detection and correction capabilities. When the error flag information UCE FLAG is at the second level, no error that does not meet the conditions has occurred in the corresponding memory chip 10. The memory controller does not need to process the address information obtained from the corresponding memory chip 10, nor does it need to perform error detection and correction processing on its data.

[0123] Storage device 20 can be a Dual Inline Memory Module (DIMM), comprising multiple memory modules 10 and multiple ECC chips 30. For example, as shown in Figure 15, for the left and right sub-channels, each side includes 2 ECC chips and 8 DRAM chips. Here, the ECC chips are sideband ECCs. For sideband ECC using RS encoding mode, when the location of the error is uncertain, the error correction capability of the RS algorithm is half that of the parity bit. Therefore, two ECC chips can correct a 2-bit error in one DRAM chip (one ECC chip is used to determine the location, and one ECC chip is used for error correction). When the error location is determined, the error correction capability of the RS algorithm is equal to that of the parity bit; therefore, two ECC chips can correct a 2-bit error in two DRAM chips. This example uses a sub-channel comprising two ECC chips. The memory 10 in storage device 20 can pre-identify errors of 2 bits or more using the error detection circuit 100 and the error address generation circuit 200, and record the corresponding error location. The ECC chip 30 can then directly correct the error. Thus, while maintaining the structure of storage device 20, the error correction capability of the sideband ECC is doubled, improving the accuracy of the storage device. Those skilled in the art will understand that multiple ECC chips can be used in a sub-channel to improve error correction capability.

[0124] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A memory (10) characterized by, include: Multiple repositories, each of which includes multiple data storage blocks and ECC storage blocks; Multiple error detection circuits (100) correspond one-to-one with the multiple said repositories; Each of the error detection circuits (100) is configured to read stored data and verification data from the plurality of data storage blocks and the ECC storage block of the corresponding repository, respectively, and generate a corresponding error detection signal (UCE_flag) based on the stored data and the verification data, wherein the error detection signal (UCE_flag) is used to indicate whether the stored data and / or the verification data of the corresponding repository has encountered a conditional error; An error address generation circuit (200) is configured to receive multiple error detection signals (UCE_flag) from multiple error detection circuits (100), and to store the address information corresponding to an error that does not meet the conditions when any of the error detection signals (UCE_flag) is at an invalid level; wherein the address information includes: error column address information (RA_UCE) and error column address information (CA_UCE).

2. The memory (10) according to claim 1, characterized in that, The error address generation circuit (200) is further configured to generate and store error identification information (UCE FLAG) when any of the error detection signals (UCE_flag) is at an invalid level; wherein the error identification information (UCE FLAG) is used to indicate whether the stored data and / or check data corresponding to the stored address information has encountered an error that does not meet the conditions.

3. The memory (10) according to any one of claims 1-2, characterized in that, The error detection circuit (100) includes: The first detection circuit (101) is configured to receive the stored data and the verification data, and compare the verification code generated based on the stored data with the verification data to generate a comparison result; The first judgment circuit (102) is configured to receive the comparison result and determine whether the condition is met, and when the comparison result meets the condition, generate the error detection signal (UCE_flag) at an invalid level, and when the comparison result does not meet the condition, generate the error detection signal (UCE_flag) at an active level.

4. The memory (10) according to any one of claims 1 to 3, characterized in that The error address generation circuit (200) includes: The merging circuit (201) is configured to receive multiple error detection signals (UCE_flag) corresponding to multiple of the multiple repositories, merge them to generate a total error detection signal (UCE_flag_all), wherein if any one of the error detection signals (UCE_flag) is at an invalid level, the generated total error detection signal (UCE_flag_all) is at an invalid level; The row address generation circuit (202) is configured to receive a plurality of error detection signals (UCE_flag) and the error detection total signal (UCE_flag_all), and when any of the error detection signals (UCE_flag) is at an invalid level, output the row address information of the corresponding repository as error column address information (RA_UCE), and store the error column address information (RA_UCE) in response to the error detection total signal (UCE_flag_all) being at an invalid level; The column address generation circuit (203) is configured to store the error column address information (CA_UCE) corresponding to the error that does not meet the conditions in response to the error detection total signal (UCE_flag_all) which is at an invalid level.

5. The memory (10) according to claim 4, characterized in that The row address generation circuit (202) includes: Multiple row address latching circuits (2021) correspond one-to-one with multiple of the repositories, and each row address latching circuit (2021) is configured to latch the row address information corresponding to the activation signal in response to the activation signal of the corresponding repository; The row address selection circuit (2022) is configured to receive multiple error detection signals (UCE_flag) and multiple row address information latched by multiple row address latching circuits (2021), and output the corresponding row address information as error column address information (RA_UCE) when any of the error detection signals (UCE_flag) is at an invalid level; The row address storage circuit (2023) is configured to store the error column address information (RA_UCE) in response to the error detection total signal (UCE_flag_all) being at an invalid level.

6. The memory (10) according to claim 5, characterized by The column address generation circuit (203) includes: The column address latch circuit (2031) is configured to input the column address information corresponding to the read signal into a buffer in response to a read signal, and to output the column address information corresponding to the read signal as error column address information (CA_UCE) from the buffer in response to a read delay signal; wherein, the read delay signal is a delay signal of the read signal; The column address storage circuit (2032) is configured to store the error column address information (CA_UCE) into the corresponding mode register in response to the error detection total signal (UCE_flag_all) being at an invalid level.

7. The memory (10) according to claim 6, characterized by The row address storage circuit (2023) includes: N serially connected row address storage sub-circuits; The first row address storage sub-circuit (2023_1) is configured to store the received error column address information (RA_UCE) when the error detection total signal (UCE_flag_all) after performing N-1 first delays is at an invalid level; the i-th row address storage sub-circuit (2023_i) is configured to receive and store the error column address information (RA_UCE) stored by the (i-1)-th row address storage sub-circuit when the error detection total signal (UCE_flag_all) after performing Ni first delays is at an invalid level; the N-th row address storage sub-circuit (2023_N) is configured to receive and store the error column address information (RA_UCE) stored by the (N-1)-th row address storage sub-circuit when the error detection total signal (UCE_flag_all) is at an invalid level; wherein, the first delay is a number of clock cycles, N is greater than or equal to 2, and i is a positive integer greater than 1 and less than N; The column address storage circuit (2032) includes: N serially connected column address storage sub-circuits; The first column address storage sub-circuit (2032_1) is configured to store the received error row and column address information when the error detection total signal (UCE_flag_all) after performing N-1 second delays is at an invalid level; the j-th column address storage sub-circuit (2032_j) is configured to receive and store the error column address information (CA_UCE) stored by the (j-1)-th column address storage sub-circuit when the error detection total signal (UCE_flag_all) after performing Nj second delays is at an invalid level; the N-th column address storage sub-circuit (2032_N) is configured to receive and store the error column address information (CA_UCE) stored by the (N-1)-th column address storage sub-circuit when the error detection total signal (UCE_flag_all) is at an invalid level; wherein, the second delay is a number of clock cycles, and j is a positive integer greater than 1 and less than N.

8. A method of operating a memory, the memory comprising a plurality of banks, each of the banks comprising a plurality of data storage blocks and an ECC storage block, the method comprising: The operation method includes: The system receives storage data and verification data read from the plurality of data storage blocks and the ECC storage block of any of the aforementioned repositories, and generates a corresponding error detection signal based on the storage data and the verification data (S1); wherein the error detection signal is used to indicate whether the storage data and / or the verification data of the corresponding repository have encountered a conditional error. The error detection signal is received, and when the error detection signal is at an invalid level, the address information corresponding to the error that does not meet the conditions is stored (S2); wherein, the address information includes: error row address information and error column address information.

9. The operating method according to claim 8, characterized in that, When the error detection signal is at an invalid level, error identification information is generated and stored (S3); wherein, the error identification information is used to indicate whether the stored data and / or check data corresponding to the stored address information has an error that does not meet the conditions.

10. The method of operating according to any of claims 8-9, characterized in that, Before receiving the storage data and verification data read from the corresponding plurality of data storage blocks and the ECC storage block of the repository, respectively, the method further includes: In response to the activation signal, the row address information of the repository corresponding to the activation signal is received and latched (S00); In response to a read signal, the column address information corresponding to the read signal is received and input into the buffer (S01).

11. The method of operating according to any of claims 8-10, characterized in that, The step of generating a corresponding error detection signal based on the stored data and the verification data includes: A check code is generated based on the stored data, and the check code is compared with the check data to generate a comparison result (S11); The comparison result is received and it is determined whether the condition is met. If the comparison result meets the condition, the error detection signal at an invalid level is generated. If the comparison result does not meet the condition, the error detection signal at an valid level is generated (S12).

12. The method of claim 10, wherein, The step of receiving the error detection signal and storing the address information corresponding to the error that does not meet the conditions when the error detection signal is at an invalid level includes: Receive multiple error detection signals corresponding to multiple repositories, merge them to generate a total error detection signal, wherein if any error detection signal is at an invalid level, an invalid level error detection signal is generated (S21); In response to multiple error detection signals, the received address information is selected to generate error row address information and error column address information (S22); In response to the total error detection signal, the error row address information and the error column address information are stored (S23).

13. The method of operation of claim 12, wherein, The step of selecting from received address information in response to multiple error detection signals to generate error row address information and error column address information includes: Receive multiple error detection signals and multiple row address information corresponding to multiple repositories, and when any of the error detection signals is at an invalid level, output the row address information of the corresponding repository as error row address information (S221); In response to the read delay signal, the column address information corresponding to the read signal is output from the buffer as error column address information (S222); wherein the read delay signal is the delay signal of the read signal.

14. A storage device (20) comprising a plurality of memories (10) as described in any one of claims 1 to 7, and a plurality of ECC chips (30); The error row address information and the error column address information in the memory (10) are used to locate the data location where an error has occurred that does not meet the conditions. The verification data stored in the ECC chip (30) is used to detect and correct errors in the stored data and / or verification data corresponding to the error row address information and the error column address information.

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