Signal receiving device and method, mixed-signal test board, and tester

Abstract

A signal receiving device and method, a mixed-signal test board, and a tester. The signal receiving device comprises a main test unit and a sub-test unit. In the sub-test unit, an external clock chip outputs a sampling clock of a fixed frequency to an analog-to-digital conversion device; and a digital waveform collector receives an original waveform of the fixed frequency outputted by the analog-to-digital conversion device on the basis of the sampling clock, performs resampling processing on the original waveform, generates a reconstructed waveform of any required frequency, and sends the reconstructed waveform to a first communication module. In the main test unit, a second communication module receives the reconstructed waveform and sends same to a waveform receiving module, and the waveform receiving module stores the received reconstructed waveform in a storage module.

Description

Signal receiving device, method, mixed analog-to-digital test board and test machine

[0001] Related applications

[0002] This application claims priority to Chinese patent application filed on October 18, 2024, application number 202411457683.3, entitled “Signal Receiving Apparatus, Method, Analog-Digital Mixed Test Board and Tester”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor testing technology, and in particular to a signal receiving device, method, mixed analog-to-digital test board, and test machine. Background Technology

[0004] Semiconductor automated testing refers to the use of automated test equipment (ATE) to inspect various parameters of the device under test (DUT), eliminating defective products and controlling the quality of semiconductor devices before they leave the factory. In analog testing, especially high-speed analog testing, the test signals sent to the DUT often have very high requirements in terms of harmonics, signal-to-noise ratio, amplitude, and signal frequency. When implementing IQ (in-phase and quadrature) functionality, the test equipment needs to ensure IQ channel synchronization.

[0005] The existing test signal receiving scheme adjusts the sampling clock phase of the ADC (Analog-to-Digital Converter) in the IQ channel by changing the frequency of the clock signal output by the clock circuit, thereby synchronizing the IQ channels. This method of receiving test signals by adjusting the ADC sampling clock phase has complex control logic, is cumbersome to operate, and suffers from low testing efficiency.

[0006] There is currently no effective solution to the problems of complex control logic, cumbersome operation, and low testing efficiency in the output test signal methods of related technologies. Summary of the Invention

[0007] According to various embodiments of this application, a signal receiving device, method, mixed analog-to-digital test board, and test machine are provided.

[0008] A first aspect of this application provides a signal receiving device, comprising a main test unit and a sub-test unit, wherein:

[0009] The sub-test unit includes a digital waveform acquisition unit, a first communication module, and an external clock chip;

[0010] The external clock chip outputs a sampling clock at a fixed frequency to the analog-to-digital converter; the digital waveform acquisition device connects the analog-to-digital converter and the first communication module; the digital waveform acquisition device receives the original waveform at a fixed frequency output by the analog-to-digital converter according to the sampling clock, performs resampling processing on the original waveform, generates a reconstructed waveform of any desired frequency, and sends it to the first communication module.

[0011] The main test unit includes a second communication module, a waveform receiving module, and a storage module;

[0012] The second communication module connects the first communication module and the waveform receiving module, and receives the reconstructed waveform through the second communication module and sends it to the waveform receiving module; the waveform receiving module is connected to the storage module and stores the received reconstructed waveform in the storage module.

[0013] In one embodiment, the digital waveform acquisition device includes:

[0014] The synchronization control module is connected to the waveform data processing module and the analog-to-digital converter. It is used to receive the original waveform of a fixed frequency output by the analog-to-digital converter and send the original waveform to the waveform data processing module after receiving a trigger signal.

[0015] The waveform data processing module is connected to the first communication module, performs resampling processing on the original waveform, generates a reconstructed waveform of any required frequency, and sends it to the first communication module.

[0016] In one embodiment, the synchronization control module includes:

[0017] The synchronous receiving control module is connected to the acquisition signal processing module and two or more analog-to-digital converters. It receives the original waveforms output by each of the analog-to-digital converters and synchronously sends multiple original waveforms to the acquisition signal processing module after receiving a trigger signal.

[0018] The acquisition signal processing module is connected to the waveform data processing module and is used to synthesize the received multiple raw waveforms and output one raw waveform to the waveform data processing module.

[0019] In one embodiment, the waveform data processing module includes:

[0020] The calibration module, connected to the synchronization control module, is used to calibrate the received raw waveform and output the calibrated waveform data.

[0021] The digital resampling module, connected to the calibration module and the first communication module, is used to resample the calibrated waveform data, generate a reconstructed waveform of any desired frequency, and send it to the first communication module.

[0022] In one embodiment, the calibration module includes at least one of a DC (Direct Current) calibration module, an AC (Alternating Current) amplitude calibration module, and a low-pass filter module.

[0023] In one embodiment, the digital resampling module includes:

[0024] An input waveform data caching module is connected to the calibration module, the effective position calculation module, and the effective data caching module. It is used to cache the calibrated waveform data and send a start signal to the effective position calculation module when the number of cached data exceeds a set threshold. It also reads the effective data corresponding to the effective position from the cached data according to the received read enable signal and sends the read effective data to the effective data caching module for caching.

[0025] The effective position calculation module is connected to the effective coefficient generation module. After receiving the start signal, it calculates the effective position information according to the set step and initial phase, sends it to the effective coefficient generation module, and sends a read enable signal to the input waveform data buffer module.

[0026] The effective coefficient generation module is connected to the data calculation module and the effective data cache module. It is used to read coefficients from multiple pre-stored coefficients according to the effective position information, obtain effective coefficients and send them to the data calculation module, and send a data read enable signal to the effective data cache module.

[0027] The effective data caching module is connected to the data calculation module and is used to read the cached effective data and send it to the data calculation module according to the received data read enable signal.

[0028] The data calculation module is connected to the first communication module and is used to perform convolution calculation based on the received effective coefficients and effective data to obtain the reconstructed waveform and send it to the first communication module.

[0029] In one embodiment, the effective data caching module stores the effective data in parallel into consecutive internal cache units using a shifting method; and / or the effective coefficient generation module reads two adjacent sets of coefficients based on the integer position information of the effective position information, and calculates the effective coefficients by using a linear interpolation algorithm on the two sets of coefficients read based on the decimal position information of the effective position information.

[0030] In one embodiment, the data calculation module performs convolution calculations based on the received valid coefficients and valid data, including:

[0031] Wherein, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point, and DATA_IN represents the valid data corresponding to the valid position.

[0032] In one embodiment, the waveform receiving module includes:

[0033] A receiving control module, connected to the second communication module and the read / write control module, is used to receive the reconstructed waveform through the second communication module and send a write request instruction to the read / write control module;

[0034] The read / write control module is connected to the storage module and is used to store the reconstructed waveform into the storage module according to the write request instruction.

[0035] In one embodiment, the sub-test unit further includes a first service decoding module, which is connected to a host computer, the digital waveform acquisition device, and the external clock chip. The first service decoding module configures the parameters of the digital waveform acquisition device and the external clock chip according to instructions issued by the host computer; and / or

[0036] The main test unit also includes a second service decoding module, which is connected to the host computer and the waveform receiving module. The second service decoding module configures the parameters of the waveform receiving module according to the instructions issued by the host computer, and performs waveform reading operations on the storage module through the waveform receiving module.

[0037] A second aspect of this application provides a signal receiving method, comprising:

[0038] The external clock chip in the sub-test unit outputs a fixed-frequency sampling clock to the analog-to-digital converter.

[0039] The digital waveform acquisition unit in the sub-test unit receives the original waveform at a fixed frequency output by the analog-to-digital converter according to the sampling clock, performs resampling processing on the original waveform, generates a reconstructed waveform at any required frequency, and sends it to the first communication module in the sub-test unit.

[0040] The second communication module in the main test unit receives the reconstructed waveform sent by the first communication module and sends it to the waveform receiving module in the main test unit;

[0041] The waveform receiving module stores the received reconstructed waveform into the storage module in the main test unit.

[0042] A third aspect of this application provides a mixed-signal test board, including the signal receiving device described above.

[0043] The fourth aspect of this application provides a test machine, including a communication board, a backplane, and the aforementioned mixed analog-to-digital test board.

[0044] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the disclosed drawings without creative effort.

[0046] Figure 1 is a structural block diagram of a signal receiving device in one embodiment.

[0047] Figure 2 is a schematic diagram of the signal receiving device in one embodiment.

[0048] Figure 3 is a schematic diagram of the waveform data processing module in one embodiment.

[0049] Figure 4 is a schematic diagram of the principle of digital resampling in one embodiment.

[0050] Figure 5 is a flowchart of a signal receiving method in one embodiment. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0053] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0054] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0055] In one embodiment, as shown in FIG1, a signal receiving device is provided, including a sub-test unit 100 and a main test unit 200, wherein:

[0056] The sub-test unit 100 includes a digital waveform digitizer (DGT) 110, a first communication module 120, and an external clock chip 130. It may further include an analog-to-digital converter (ADC) 140. The external clock chip 130 outputs a fixed-frequency sampling clock to the ADC 140. The digital waveform digitizer 110 connects to the ADC 140 and the first communication module 120. The digital waveform digitizer 110 receives the original waveform at a fixed frequency output by the ADC 140 according to the sampling clock, resamples the original waveform, generates a reconstructed waveform of any desired frequency, and sends it to the first communication module 120. Furthermore, the external clock chip 130 can also connect to the digital waveform digitizer 110, outputting a fixed-frequency sampling clock to the digital waveform digitizer 110, which receives the waveform according to the sampling clock.

[0057] The main test unit 200 includes a second communication module 210, a waveform receiving module 220, and a storage module 230. The second communication module 210 is connected to the first communication module 120 and the waveform receiving module 220. The second communication module 210 receives the reconstructed waveform and sends it to the waveform receiving module 220. The waveform receiving module 220 is connected to the storage module 230 and stores the received reconstructed waveform in the storage module 230.

[0058] The main test unit 200 and the sub-test unit 100 can be used as the main test board and sub-test board of the test machine, respectively, or they can be designed as a single test board. Users can configure the parameters of the digital waveform acquisition unit 110 according to the actual scenario requirements, so that the digital waveform acquisition unit 110 resamples the original waveform and generates a reconstructed waveform of any frequency required by the user. The arbitrary frequency of the reconstructed waveform set by the user is less than or equal to the fixed frequency of the sampling clock. The external clock chip 130 can be a PLL (Phase Locked Loop) clock chip, and the storage module 230 can be a DDR (Double Data Rate) storage module composed of DDR4 chips. The first communication module 120 and the second communication module 210 can be gigabit (such as GTX) communication modules, or other types of communication modules. In actual applications, the modules within the main test unit 200 and the modules within the sub-test unit 100 can be interchanged as long as the functionality is satisfied; for example, the digital waveform acquisition unit 110 can be located within the main test unit 200.

[0059] After receiving the analog waveform output by the device under test (DUT), the analog-to-digital converter (ADC) 140 performs analog-to-digital conversion sampling on the analog waveform according to a fixed-frequency sampling clock, generating the original waveform and sending it to the digital waveform acquisition unit (DMU) 110. The DMU 110 processes the original waveform to generate a reconstructed waveform of any desired frequency. The DUT can be a semiconductor chip or other device. The number of ADCs 140 can be one or more. For example, for the IQ channels of a test machine, one or more ADCs 140 can be set for each channel to receive the analog waveform output by the DUT and perform analog-to-digital conversion based on the sampling clock.

[0060] As shown in Figure 2, the digital waveform acquisition unit 110 may include a synchronization control module 112 and a waveform data processing module 114. The synchronization control module 112 is connected to the waveform data processing module 114 and the analog-to-digital converter 140, and is used to receive the original waveform of a fixed frequency output by the analog-to-digital converter 140, and send the original waveform to the waveform data processing module 114 after receiving a trigger signal. The waveform data processing module 114 is connected to the first communication module 120, and performs resampling processing on the original waveform to generate a reconstructed waveform of arbitrary frequency and send it to the first communication module 120. Further, the sub-test unit 100 may also include a first service decoding module 150, which is connected to the host computer, the digital waveform acquisition unit 110 and the external clock chip 130, and configures the parameters of the digital waveform acquisition unit 110 and the external clock chip 130 according to the instructions issued by the host computer.

[0061] The digital waveform acquisition unit 110, the first communication module 120, and the first service decoding module 150 can be housed within an FPGA (Field-Programmable Gate Array), while the external clock chip 130 and the analog-to-digital converter 140 are located outside the FPGA. The PLL_CTRL port of the first service decoding module 150 is connected to the external clock chip 130 via an SPI (Serial Peripheral Interface) interface. Parameters are configured for the external clock chip 130 to output a fixed-frequency sampling clock to the analog-to-digital converter 140. This configuration can be either setting the external clock chip 130 to output the sampling clock at the maximum allowed frequency (e.g., 400MHz) or at other frequencies. The DTG_CTRL port of the first service decoding module 150 is connected to the synchronization control module 112 and the waveform data processing module 114 for parameter configuration.

[0062] Referring again to Figure 2, the synchronization control module 112 includes a synchronization receiving control module 1122 and a signal acquisition and processing module 1124. The synchronization receiving control module 1122 is connected to the signal acquisition and processing module 1124 and two or more analog-to-digital converters 140. It receives the raw waveforms output by each analog-to-digital converter 140 and synchronously sends multiple raw waveforms to the signal acquisition and processing module 1124 after receiving a trigger signal. The signal acquisition and processing module 1124 is connected to the waveform data processing module 114 and is used to synthesize the received multiple raw waveforms and output one raw waveform to the waveform data processing module 114.

[0063] Taking the test unit, including IQ channels, as an example, each channel is configured with two ADC chips. A signal processing module 1124, a waveform data processing module 114, a first communication module 120, and a second communication module 210 can be configured for each IQ channel. The synchronous reception control module 1122 receives the two raw waveforms from each channel via an LVDS (Low-Voltage Differential Signaling) interface and buffers them in an internal FIFO (First Input First Output) buffer. After receiving the trigger signal TRIG from the first service decoding module 150, the synchronous reception control module 1122 outputs the two raw waveforms from the same channel in the internal FIFO buffer to the corresponding signal processing module 1124. The signal processing module 1124 combines the two raw waveforms from the same channel into a single raw waveform and outputs it to the waveform data processing module 114. By combining two raw waveforms into a single I / Q channel raw waveform, the impact of noise can be reduced, and the SNR (Signal-to-Noise Ratio) can be improved. The waveform data processing module 114 performs digital signal processing (such as AC calibration, DC calibration, resampling control, and low-pass filtering) according to the instructions (e.g., DTG_Digital_CTRL_SIGNAL) issued by the first service decoding module 150, generating a reconstructed waveform of the required frequency and sending it to the first communication module 120. The first communication module 120 uses a GTX communication module to convert the 32-bit wide reconstructed waveform into a 64-bit wide reconstructed waveform before transmitting it to the second communication module 210, thereby improving communication bandwidth. The second communication module 210 uses a GTX communication module to convert the received 64-bit wide reconstructed waveform into a 32-bit wide reconstructed waveform and send it to the waveform receiving module 220.

[0064] Referring again to Figure 2, the four ADC chips for the I and Q channels have a fixed maximum sampling clock (400MHz). However, the user requires waveforms at any frequency. Therefore, the waveform data processing module 114 needs to resample the original waveform sampled at the fixed frequency. During resampling, the initial phase of the reconstructed waveform generated by the resampled waveform can be changed by setting the initial phase, thus achieving adjustable frequency and phase for the I and Q channels. The I and Q functions can be implemented using ordinary ADC chips, and the functions of the two non-I and Q channels can also be implemented without the need for an external clock chip 130 to adjust the sampling clock frequency, simplifying operation and improving testing efficiency.

[0065] Furthermore, the synchronous receiving control module 1122 also simultaneously acquires the original waveform output by the analog-to-digital converter 140 and the accompanying clock data_clk according to the sampling clock, ensuring the synchronization of the output sampling data. Again, taking the test machine including IQ dual channels as an example, the sampling clock input to the two ADC chips of each channel is provided by the external clock chip 130. Simultaneously, the external clock chip 130 also transmits the sampling clock to the synchronous receiving control module 1122. Therefore, the sampling clock input to the synchronous receiving control module 1122 is of the same source and frequency as the sampling clocks of the four ADC chips, allowing the synchronous receiving control module 1122 to simultaneously perform digital sampling on the four ADC chips using the input sampling clock.

[0066] Since the ADC chip outputs data using DDR dual-edge sampling, the synchronous receiving control module 1122 uses the sampling clock input from the external clock chip 130 to simultaneously sample the original waveforms output by the four ADC chips and their associated clock data_clk. Based on the sampling result of each ADC chip's associated clock data_clk, the dual-edge sampling result of the ADC data is determined. When the ADC's associated clock data_clk is high, the ADC data is sampled using odd-number sampling; otherwise, the ADC data is sampled using even-number sampling. After obtaining the sampling data results from the four ADC chips, the synchronous receiving control module 1122 arranges the four 16-bit sampled data into 64-bit data according to channel order and writes it into the cross-clock domain buffer FIFO using the input sampling clock as the write clock. After the cross-clock buffer FIFO is not empty, the synchronous receiving control module 1122 uses the system clock as the read clock to read the data from the buffer, completing the cross-clock domain conversion operation. After the cross-clock domain is converted to the system clock, the data synchronization control of the four ADC chips can still be maintained.

[0067] After receiving data from four ADCs based on the system clock, the synchronous receiving control module 1122 divides the 64-bit data into four 16-bit data according to the channel order. Then, the acquisition signal processing module 1124 combines the data from ADC0 and ADC1 on the I channel into one data and the data from ADC0 and ADC1 on the Q channel into one data. The two data from the I channel are directly added together, and the two data from the Q channel are directly added together. At this time, the synchronous acquisition control of the I and Q channels is completed.

[0068] In this module, after receiving the trigger signal TRIG sent by the first service decoding module 150, the synchronous receiving control module 1122 determines whether the working mode sent by the first service decoding module 150 is IQ mode. If it is IQ mode, as long as the trigger signal TRIG of either IQ channel goes high, the synchronous receiving control module 1122 will simultaneously control the data acquisition of both IQ channels to begin, and transmit the integrated I and Q channel data to the subsequent waveform data processing module 114 for processing. At this time, the I and Q channels can be output synchronously until the acquisition length is reached and then acquisition stops. At this time, the synchronous receiving control module 1122 will not send the I and Q channel data to the waveform data processing module 114. If no trigger signal TRIG is received, the synchronous receiving control module 1122 will not send the I and Q channel data to the waveform data processing module 114. When the working mode is not IQ, the synchronous receiving control module 1122 controls the data acquired by the I and Q channels to be output to the subsequent waveform data processing module 114 according to the respective trigger signals TRIG of the I and Q channels.

[0069] It is understood that the specific structure of the waveform data processing module 114 is not unique. The waveform data processing module 114 may include a calibration module and a digital resampling module. The calibration module is connected to the synchronization control module 112 and is used to calibrate the received raw waveform and output the calibrated waveform data. The digital resampling module is connected to the calibration module and the first communication module 120 and is used to resample the calibrated waveform data, generate the reconstructed waveform of the required arbitrary frequency, and send it to the first communication module 120.

[0070] As shown in Figure 3, the calibration module may specifically include at least one of a DC calibration module 40, an AC amplitude calibration module 41, and a low-pass filter module 42. Taking a calibration module that simultaneously includes a DC calibration module 40, an AC amplitude calibration module 41, and a low-pass filter module 42 as an example, all three modules are connected to the first service decoding module 150. The DC calibration module 40 is connected to the acquisition signal processing module 1124 in the synchronization control module 112. The AC amplitude calibration module 41 is connected to both the DC calibration module 40 and the low-pass filter module 42. The low-pass filter module 42 is connected to the digital resampling module. The DC calibration module 40 performs DC calibration on the received raw waveform according to the DC calibration coefficients issued by the first service decoding module 150 and then sends it to the AC amplitude calibration module 41, ensuring that the amplitude accuracy of the channel data meets the required specifications. Because the IQ channel has high requirements for AC flatness, the AC amplitude calibration module 41 also uses the AC calibration coefficients issued by the first service decoding module 150 to perform AC amplitude calibration on the waveform after DC calibration, ensuring that the amplitude accuracy of the channel data meets the requirements. The AC amplitude calibration module 42 then sends the AC amplitude calibrated waveform to the low-pass filter module 42. The low-pass filter module 42 generates filter coefficients based on the low-pass filter parameters issued by the first service decoding module 150 and performs low-pass filtering on the waveform, which can reduce the influence of high-frequency noise and improve performance. The waveform processed by the low-pass filter module 42 is then sent to the digital resampling module.

[0071] The external clock chip 130 is set to a fixed maximum sampling clock frequency, and the analog-to-digital converter 140 samples the analog waveform based on this maximum sampling clock frequency. The function of the digital resampling module is to resample the original waveform at the maximum sampling clock frequency into a reconstructed waveform at the desired frequency. The resampling principle uses the SINC function to recover the waveform of a continuous signal. Since the digital waveform acquisition unit 110 resamples the original waveform at a fixed maximum sampling frequency into a reconstructed waveform at an arbitrary frequency (less than the fixed maximum sampling frequency), and since the resampled frequency is less than or equal to the fixed maximum sampling rate, its function can be summarized as a decimal multiple sampling function. For a known continuous waveform x(n), to recover x(t) at any time, the Sinc function is used for data resampling recovery. The actual value of the recovered point is obtained by convolving the first 8 points and the last 8 points of the position of the valid point to be recovered with 16 Sinc continuous coefficients.

[0072] To recover the ideal SINC function, theoretically, an infinite number of coefficients need to be calculated, which is obviously impossible. Therefore, the SINC function model is divided into 1024 groups of coefficients, with 16 coefficients in each group, and stored in ROM. Then, the effective coefficients are read from ROM based on the effective position information. Since an infinite number of groups of coefficients cannot be stored, in order to achieve higher accuracy, the stored coefficients are not used directly when calculating the effective coefficients. Instead, each segment of coefficients is considered to be continuous, and the effective coefficients at any point can be obtained by using a linear weighting algorithm.

[0073] Based on this, referring to Figure 3, the digital resampling module may include an input waveform data buffer module 43, an effective position calculation module 44, an effective coefficient generation module 45, an effective data buffer module 46, and a data calculation module 47. The input waveform data buffer module 43 is connected to the calibration module, the effective position calculation module 44, and the effective data buffer module 46. The effective position calculation module 44 is connected to the effective coefficient generation module 45. The effective coefficient generation module 45 is connected to the data calculation module 47 and the effective data buffer module 46. The effective data buffer module 46 is connected to the data calculation module 47.

[0074] The input waveform data caching module 43 is specifically connected to the low-pass filter module 42 in the calibration module. It caches the calibrated waveform data and sends a start signal SINC_START to the valid position calculation module 44 when the number of cached data exceeds a set threshold. It also reads the valid data corresponding to the valid position from the cached data based on the received read enable signal and sends the read valid data to the valid data caching module 46 for caching. The valid position calculation module 44 calculates the valid position information based on the set step size and initial phase after receiving the start signal SINC_START. The data is sent to the effective coefficient generation module 45 and a read enable signal is sent to the input waveform data buffer module 43. The effective coefficient generation module 45 reads coefficients from multiple pre-stored coefficients based on the effective position information, obtains effective coefficients, sends them to the data calculation module 47, and sends a data read enable signal to the effective data buffer module 46. The effective data buffer module 46 reads the buffered effective data based on the received data read enable signal and sends it to the data calculation module 47. The data calculation module 47 performs convolution calculation based on the received effective coefficients and effective data to obtain the reconstructed waveform and sends it to the first communication module 120. The convolution formula is as follows:

[0075] Wherein, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the effective coefficients corresponding to the effective positions of the reconstruction points (a total of 16 effective coefficients), and DATA_IN represents the effective data corresponding to this effective position (also 16 points, the first 8 points and the last 8 points of this effective position). After multiplying and accumulating the effective coefficients and the original waveform 16 times, the reconstruction point of the corresponding reconstructed waveform is calculated.

[0076] The value of the threshold number is not unique and can be set according to actual needs. The first service decoding module 150 is connected to the effective position calculation module 44 to configure the step and initial phase. By controlling the step and initial phase, the digital resampling module can resample the initial waveform with a variable sampling frequency into a reconstructed waveform with a fixed maximum sampling frequency. At the same time, because the digital resampling module performs digital resampling, it can also achieve phase adjustment of the output waveform with an accuracy of up to 1ps.

[0077] Specifically, after receiving the waveform data output by the low-pass filter module 42, the input waveform data buffer module 43 can buffer it in an internal buffer unit (such as a FIFO). When the number of buffered data exceeds a set threshold (such as 16), the input waveform data buffer module 43 sends a start signal SINC_START to the valid position calculation module 44. Upon receiving the start signal SINC_START, the valid position calculation module 44 begins operation, calculating the valid position based on the STEP and initial phase PHASE information sent by the first service decoding module 150. The valid position can be understood as the position of the reconstructed waveform points. The calculated valid position information consists of a 16-bit integer and a 48-bit decimal. The initial position of the reconstructed waveform is determined by the initial phase PHASE, which refers to the valid position of the first point of the reconstructed waveform. The relationship between the reconstructed waveform point position and the original waveform point position is: Reconstructed waveform point position = (Original waveform point position - 1) * STEP + 1 + PHASE. The position of the original waveform points is also the position of the points in the calibrated waveform data. DC calibration, AC amplitude calibration, and filtering will not change the position of the points in the original waveform.

[0078] The step STEP is calculated as: Fixed maximum sampling rate (sampling clock frequency) / User-set sampling rate (reconstructed waveform frequency). Since the user-set sampling rate is less than or equal to the fixed maximum sampling rate, the value of STEP is greater than or equal to 1, which can be understood as a decimation operation at any multiple. The step STEP consists of a 16-bit integer and a 48-bit decimal. Because the fixed maximum sampling rate is set to 400MHz, the 48-bit decimal supports up to μHz, enabling resampling at sampling rates with μHz precision. To achieve a sampling rate resolution that allows for μHz adjustment, assuming A = 400MHz = 400 * 2^10 * 2^10 Hz and B = 1 μHz = (1 / 2^10 * 2^10) Hz, then A / B = 400 * 2^10 * 2^10 Hz / (1 / 2^10 * 2^10) Hz = 400 * 2^40 = 49 bits. Since the SINC algorithm divides the coefficients into 1024 parts, the minimum position information requires 400 * 2^40 / 1024 bits = 39 bits. This scheme uses 48 bits. The initial phase PHASE = number of points in one waveform cycle / (360° / phase of the reconstructed waveform). The output result is composed of a 16-bit integer and a 48-bit decimal, allowing for ps-level phase adjustment.

[0079] After obtaining the valid position information based on the set step and initial phase, the valid position calculation module 44 outputs the valid position information to the valid coefficient generation module 45. Simultaneously, it sends a read enable signal to the input waveform data buffer module 43 based on the determined valid position. The input waveform data buffer module 43 reads a data value based on the read enable signal sent by the valid position calculation module 44 and sends it to the valid data buffer module 46. At this time, the data stored in the valid data buffer module 46 is the valid data for that valid position. After the valid coefficient generation module 45 calculates the valid coefficient for that valid position, the valid data buffer module 46 reads the valid data and sends it to the data calculation module 47 for calculation.

[0080] The effective coefficient generation module 45 can store multiple sets (e.g., 1024 sets) of coefficients (16 coefficients per set) in the internal ROM (read-only memory) unit in advance. After receiving the effective position information, the effective coefficient generation module 45 can read out two adjacent sets of coefficients according to the integer position information of the effective position information, and calculate the effective coefficients by using a linear interpolation algorithm on the two sets of coefficients read according to the decimal position information of the effective position information.

[0081] Specifically, the effective coefficient generation module 45 reads the pre-stored coefficients from the ROM unit based on the effective position information. Since there are only 1024 pre-stored coefficients, which cannot meet the precision of 48-bit decimals, it reads two adjacent sets of coefficients (16 coefficients per set) based on the integer position information of the effective position information. Then, it calculates the two sets of coefficients based on the decimal position information of the effective position information using a linear interpolation algorithm: y_coe[n] = COE1[n] * tim_valid + COE2[n] * (1 - tim_valid), where n is between 0 and 15, to obtain the most accurate effective coefficients (16 coefficients). Here, COE1 represents the first set of coefficients in the two adjacent sets of coefficients read, COE2 represents the second set of coefficients in the two adjacent sets of coefficients read (both the first and second sets of coefficients have 16 coefficients), tim_valid represents the decimal position information in the effective position information, and y_coe represents the effective coefficients (16 coefficients) in the decimal position of the actual effective position information obtained by linear interpolation.

[0082] The valid data caching module 46 can store valid data in parallel into consecutive internal cache units (such as FIFOs) using a shifting method. Specifically, the valid data caching module 46 stores valid data in parallel into 16 FIFOs using a shifting method. The parallel storage is manifested in that the latest input data is stored in FIFO1, while the data in the original FIFO1 is stored in FIFO2, the data in the original FIFO2 is stored in FIFO3, and so on, that is, the 16 FIFOs store 16 consecutive data.

[0083] After the effective coefficient generation module 45 generates an effective coefficient, it outputs the effective coefficient to the data calculation module 47 and simultaneously sends a data read enable signal to the effective data buffer module 46. Based on the data read enable signal, the effective data buffer module 46 reads 16 effective data points from the 16 FIFOs and outputs them to the data calculation module 47. The data calculation module 47 performs a 16th-order convolution calculation based on the effective coefficient output by the effective coefficient generation module 45 and the effective data output by the effective data buffer module 46, calculating the resampled reconstructed waveform and outputting it to the subsequent first communication module 120.

[0084] The following example illustrates this. Assumption 1: The user sets the sampling rate (frequency of the reconstructed waveform) to 200MHz. Assumption 2: The phase of the reconstructed waveform is set to 3.6°. Assumption 3: The original waveform is an analog waveform with a signal frequency of 8MHz. In this case, the ADC collects data at 50 points per waveform cycle (number of sampling points per waveform cycle = fixed maximum sampling rate / signal frequency = 400MHz / 8MHz = 50). Therefore: Step = fixed maximum sampling rate / user-set sampling rate = 400MHz / 200MHz = 2; Initial phase PHASE = number of points per waveform cycle / (360° / phase of the reconstructed waveform) = 50 / (360° / 3.6) = 0.5. As shown in Figure 4, the effective position of the first point in the reconstructed waveform is determined by the initial phase PHASE, and the number of points in the reconstructed waveform corresponds to the effective position in the original waveform. The relationship between the reconstructed waveform point position and the original waveform point position is as follows: Reconstructed waveform point position = (Original waveform point position - 1) * STEP + 1 + PHASE = (Original waveform point position - 1) * 2 + 1 + 0.5, such as: 1----1.500, 2----3.500, 3----5.500, 4----7.500. Figure 4 illustrates the effect of user-set frequency, waveform point number, and initial phase on resampling, and their relationship with the effective position.

[0085] In one embodiment, as shown in Figure 2, the main test unit 200 further includes a second service decoding module 240. The second service decoding module 240 is connected to a host computer and a waveform receiving module 220. It configures parameters for the waveform receiving module 220 according to instructions from the host computer and performs waveform reading operations on the storage module 230 through the waveform receiving module 220. The second communication module 210, the waveform receiving module 220, and the second service decoding module 240 can be housed within the FPGA, while the storage module 230 is located outside the FPGA. Both the first service decoding module 150 and the second service decoding module 240 are directly controlled by the host computer, which independently sends parameter configurations; they are two independent modules and do not affect each other. The waveform receiving module 220 may specifically include a receiving control module 222 and a receiving control module 224. The receiving control module 222 is connected to the second communication module 210 and the read / write control module 224, and is used to receive the reconstructed waveform through the second communication module 210 and send a write request instruction to the read / write control module 224. The read / write control module 224 is connected to the storage module 230 and is used to store the reconstructed waveform into the storage module 230 according to the write request instruction.

[0086] Specifically, the DTG_CTRL port of the second service decoding module 240 is connected to the receiving control module 222 for parameter configuration, and the DDR_RQE port of the second service decoding module 240 is connected to the read / write control module 224 for waveform reading operations on the storage module 230. Specifically, after receiving the reconstructed waveform, the receiving control module 222, based on the sampling length, storage address, and other information issued by the second service decoding module 240, initiates a write request command for the I channel and / or Q channel to the read / write control module 224. The read / write control module 224 then writes the reconstructed waveform of the I channel and / or Q channel into the storage module 230 according to the write request command.

[0087] Referring to Figures 2 and 3, the complete processing procedure of the original waveform is described below: After the signal receiving device is powered on, the host computer communicates with the first service decoding module 150 and the second service decoding module 240 respectively and issues instructions. The first service decoding module 150 configures the parameters of the waveform data processing module 114 and the external clock chip 130 so that the external clock chip 130 outputs a sampling clock of a fixed frequency to the analog-to-digital converter 140. The second service decoding module 240 configures the parameters of the receiving control module 222.

[0088] The synchronous receiving control module 1122 receives and buffers the raw waveform output by the ADC chip. After receiving the trigger signal TRIG sent by the first service decoding module 150, it outputs the raw waveform to the acquisition signal processing module 1124 for waveform synthesis. The synthesized raw waveform is then input to the waveform data processing module 114 for resampling. In the waveform data processing module 114, the DC calibration module 40 and the AC amplitude calibration module 41 perform DC calibration and AC amplitude calibration on the raw waveform sequentially according to the configured DC calibration coefficients and AC calibration coefficients. The low-pass filtering module 42 performs low-pass filtering on the calibrated waveform according to the configured low-pass filter parameters and then sends it to the input waveform data buffer module 43 for buffering. When the number of buffered data exceeds a set threshold, the input waveform data buffer module 43 sends a start signal SINC_START to the effective position calculation module 44. After receiving the start signal SINC_START, the effective position calculation module 44 calculates the effective position information according to the configured step and initial phase and sends it to the effective coefficient generation module 45, and also sends a read enable signal to the input waveform data buffer module 43. The input waveform data buffer module 43 reads the valid data corresponding to the valid position from the buffered data according to the received read enable signal, and sends the read valid data to the valid data buffer module 46 for buffering. The valid coefficient generation module 45 reads coefficients from multiple pre-stored coefficients according to the valid position information, obtains the valid coefficients, sends them to the data calculation module 47, and sends a data read enable signal to the valid data buffer module 46. The valid data buffer module 46 reads the buffered valid data according to the received data read enable signal and sends it to the data calculation module 47. The data calculation module 47 performs convolution calculation based on the received valid coefficients and valid data to obtain the reconstructed waveform and sends it to the first communication module 120.

[0089] After receiving the reconstructed waveform through the second communication module 210, the receiving control module 222 sends a write request command to the read / write control module 224 according to the parameters configured in the second service decoding module 240. The read / write control module 224 then stores the reconstructed waveform into the storage module 230 according to the write request command. The host computer can also send commands to the read / write control module 224 to read the reconstructed waveform from the storage module 230.

[0090] In one embodiment, as shown in FIG5, a signal receiving method is also provided, including:

[0091] Step S110: The external clock chip in the sub-test unit outputs a fixed-frequency sampling clock to the analog-to-digital converter.

[0092] Step S120: The digital waveform acquisition unit in the sub-test unit receives the original waveform of the fixed frequency output by the analog-to-digital converter according to the sampling clock, performs resampling processing on the original waveform, generates the reconstructed waveform of the required arbitrary frequency, and sends it to the first communication module in the sub-test unit.

[0093] Step S130: The second communication module in the main test unit receives the reconstructed waveform sent by the first communication module and sends it to the waveform receiving module in the main test unit.

[0094] Step S140: The waveform receiving module stores the received reconstructed waveform into the storage module in the main test unit.

[0095] It is understood that the specific implementation of the above signal receiving method has been explained in detail in the above signal receiving device, and will not be repeated here.

[0096] In one embodiment, a mixed-signal test board is also provided, including the signal receiving device described above.

[0097] In one embodiment, a test machine is also provided, including a communication board, a backplane, and the aforementioned mixed-signal test board. The communication board is connected to the mixed-signal test board via the backplane. Furthermore, the test machine also includes a host computer that communicates with the communication board. The host computer can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc.

[0098] The above-mentioned signal receiving device, method, analog-to-digital hybrid test board, and test machine have the following advantages:

[0099] 1. This application uses an ADC chip to fix the sampling clock frequency. After power-on initialization, there is no need to repeatedly configure the external clock chip, which reduces the clock chip lock-up time caused by changing the sampling clock and improves test efficiency.

[0100] 2. This application uses an ADC chip with a fixed sampling clock frequency and performs resampling operations through a digital domain algorithm to achieve arbitrary frequency design. It can achieve resolution adjustment in μHz, which is a requirement that is difficult to achieve by adjusting the sampling rate through a clock chip.

[0101] 3. This application can implement both IQ and non-IQ functions, making it more flexible and convenient to use and improving the efficiency of equipment use.

[0102] 4. The control method of this application facilitates the expansion, reuse, and portability of program channels. It can be directly used in other projects. For program updates, it is only necessary to add or remove channels, which facilitates program code maintenance.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A signal receiving apparatus characterized by comprising: It includes a main test unit and sub-test units, wherein: The sub-test unit includes a digital waveform acquisition unit, a first communication module, and an external clock chip; The external clock chip outputs a sampling clock at a fixed frequency to the analog-to-digital converter; the digital waveform acquisition device connects the analog-to-digital converter and the first communication module; the digital waveform acquisition device receives the original waveform at a fixed frequency output by the analog-to-digital converter according to the sampling clock, performs resampling processing on the original waveform, generates a reconstructed waveform of any desired frequency, and sends it to the first communication module. The main test unit includes a second communication module, a waveform receiving module, and a storage module; The second communication module connects the first communication module and the waveform receiving module, and receives the reconstructed waveform through the second communication module and sends it to the waveform receiving module; the waveform receiving module is connected to the storage module and stores the received reconstructed waveform in the storage module.

2. The signal receiving apparatus according to claim 1, wherein The digital waveform acquisition device includes: The synchronization control module is connected to the waveform data processing module and the analog-to-digital converter. It is used to receive the original waveform of a fixed frequency output by the analog-to-digital converter and send the original waveform to the waveform data processing module after receiving a trigger signal. The waveform data processing module is connected to the first communication module, performs resampling processing on the original waveform, generates a reconstructed waveform of any required frequency, and sends it to the first communication module.

3. The signal receiving apparatus according to claim 2, wherein The synchronization control module includes: The synchronous receiving control module is connected to the acquisition signal processing module and two or more analog-to-digital converters. It receives the original waveforms output by each of the analog-to-digital converters and synchronously sends multiple original waveforms to the acquisition signal processing module after receiving a trigger signal. The acquisition signal processing module is connected to the waveform data processing module and is used to synthesize the received multiple raw waveforms and output one raw waveform to the waveform data processing module.

4. The signal receiving apparatus according to claim 2, wherein The waveform data processing module includes: The calibration module, connected to the synchronization control module, is used to calibrate the received raw waveform and output the calibrated waveform data. The digital resampling module, connected to the calibration module and the first communication module, is used to resample the calibrated waveform data, generate a reconstructed waveform of any desired frequency, and send it to the first communication module.

5. The signal receiving apparatus according to claim 4, wherein The calibration module includes at least one of a DC calibration module, an AC amplitude calibration module, and a low-pass filter module.

6. The signal receiving apparatus according to claim 4, wherein The digital resampling module includes: An input waveform data caching module is connected to the calibration module, the effective position calculation module, and the effective data caching module. It is used to cache the calibrated waveform data and send a start signal to the effective position calculation module when the number of cached data exceeds a set threshold. It also reads the effective data corresponding to the effective position from the cached data according to the received read enable signal and sends the read effective data to the effective data caching module for caching. The effective position calculation module is connected to the effective coefficient generation module. After receiving the start signal, it calculates the effective position information according to the set step and initial phase, sends it to the effective coefficient generation module, and sends a read enable signal to the input waveform data buffer module. The effective coefficient generation module is connected to the data calculation module and the effective data cache module. It is used to read coefficients from multiple pre-stored coefficients according to the effective position information, obtain effective coefficients and send them to the data calculation module, and send a data read enable signal to the effective data cache module. The effective data caching module is connected to the data calculation module and is used to read the cached effective data and send it to the data calculation module according to the received data read enable signal. The data calculation module is connected to the first communication module and is used to perform convolution calculation based on the received effective coefficients and effective data to obtain the reconstructed waveform and send it to the first communication module.

7. The signal receiving apparatus according to claim 6, wherein The effective data caching module stores the effective data in parallel into consecutive internal cache units using a shifting method; And / or the effective coefficient generation module reads two adjacent sets of coefficients based on the integer position information of the effective position information, and calculates the effective coefficients by using a linear interpolation algorithm on the two sets of coefficients read based on the decimal position information of the effective position information.

8. The signal receiving apparatus according to claim 6, wherein The data calculation module performs convolution calculation according to the received effective coefficient and effective data, including: Wherein, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point, and DATA_IN represents the valid data corresponding to the valid position.

9. The signal receiving apparatus according to claim 2, wherein The waveform receiving module includes: A receiving control module, connected to the second communication module and the read / write control module, is used to receive the reconstructed waveform through the second communication module and send a write request instruction to the read / write control module; The read / write control module is connected to the storage module and is used to store the reconstructed waveform into the storage module according to the write request instruction.

10. The signal receiving device according to claim 2, wherein, The sub-test unit further includes a first service decoding module, which is connected to the host computer, the digital waveform acquisition device, and the external clock chip. The first service decoding module configures the parameters of the digital waveform acquisition device and the external clock chip according to instructions issued by the host computer; and / or The main test unit also includes a second service decoding module, which is connected to the host computer and the waveform receiving module. The second service decoding module configures the parameters of the waveform receiving module according to the instructions issued by the host computer, and performs waveform reading operations on the storage module through the waveform receiving module.

11. A signal receiving method characterized by comprising: include: The external clock chip in the sub-test unit outputs a fixed-frequency sampling clock to the analog-to-digital converter. The digital waveform acquisition unit in the sub-test unit receives the original waveform at a fixed frequency output by the analog-to-digital converter according to the sampling clock, performs resampling processing on the original waveform, generates a reconstructed waveform at any required frequency, and sends it to the first communication module in the sub-test unit. The second communication module in the main test unit receives the reconstructed waveform sent by the first communication module and sends it to the waveform receiving module in the main test unit; The waveform receiving module stores the received reconstructed waveform into the storage module in the main test unit.

12. An analog-digital hybrid test board card, characterized by Includes the signal receiving device according to any one of claims 1-10.

13. A testing machine characterized by, It includes a communication board, a backplane, and the mixed analog-to-digital test board as described in claim 12.

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