Memory, storage device, and operation method for memory

Abstract

A memory (100), a storage device (300), and an operation method for the memory (100). The memory (100) comprises: a plurality of data storage blocks (11) and a check code storage block (12); and a data check circuit (20), configured to separately acquire stored data (DATA) and a corresponding first check code (ECC1) from the plurality of data storage blocks (11) and the check code storage block (12), and in response to a received mode selection signal, determine whether to execute a data check operation. The data check circuit (20) is further configured to, when the mode selection signal indicates that the memory (100) is in on-chip check mode, perform data check on the stored data (DATA) on the basis of the first check code (ECC1) and output the stored data (DATA) having undergone data check as first read-out data (R_Data1), and when the mode selection signal indicates that the memory (100) is in an off-chip check mode, directly output the stored data (DATA) and the first check code (ECC1) as second read-out data (R_Data2).

Description

A memory, a storage device, and a method of operating the memory.

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411455538.1, filed on October 18, 2024, entitled “A memory, a storage device and a method of operating a memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a memory, a storage device, and a method of operating the memory. Background Technology

[0004] With the rapid development of computer technology, the requirements for memory capacity and speed are constantly increasing. However, while memory capacity is increasing, the possibility of data errors is also increasing. To improve the reliability of data processing, ECC (Error Detection and Correction) technology is widely used in Dynamic Random Access Memory (DRAM). ECC checks reduce the failure rate of storage systems by encoding data, detecting and correcting a certain number of errors.

[0005] However, the implementation of the mainstream ECC verification scheme in the current market requires additional hardware circuits and algorithm support, which increases the production cost of DRAM storage devices. Summary of the Invention

[0006] This disclosure provides a memory, a storage device, and a method for operating the memory. In a first aspect, this disclosure provides a memory, including: a plurality of data storage blocks and a checksum storage block; a data verification circuit configured to obtain stored data and a corresponding first checksum from the plurality of data storage blocks and the checksum storage block respectively, and to determine whether to perform a data verification operation in response to a received mode selection signal; the data verification circuit is further configured to, when the mode selection signal indicates that the memory is in on-chip verification mode, perform data verification on the stored data according to the first checksum, and output the verified stored data as first read data; and when the mode selection signal indicates that the memory is in off-chip verification mode, directly output the stored data and the first checksum as second read data; wherein the first checksum in the second read data is used by an external memory controller to perform a data verification operation on the stored data.

[0007] In some embodiments, the memory further includes: an input / output circuit configured to receive the mode selection signal, and when the mode selection signal indicates that the memory is in on-chip verification mode, to serialize the received first read data according to a first burst length and generate a plurality of first output data strings to be output to a plurality of data ports; and when the mode selection signal indicates that the memory is in off-chip verification mode, to serialize the received second read data according to a second burst length and generate a plurality of second output data strings to be output to a plurality of data ports; wherein the first burst length is less than the second burst length.

[0008] In some embodiments, the first output data string includes a portion of the stored data that is serially output, and the second output data string includes a portion of the stored data that is serially output and a portion of the first checksum.

[0009] In some embodiments, the input / output circuit is further configured to receive an extended function indication signal, and when the mode selection signal indicates that the memory is in off-chip verification mode and the extended function indication signal indicates that the memory has extended function enabled, the received second read data and first extended data are serialized according to a third burst length to generate a plurality of third output data strings output to a plurality of the data ports; wherein, the third output data string includes a portion of the stored data, a portion of the first check code, and a portion of the first extended data serially output.

[0010] In some embodiments, the input / output circuit is further configured to, when the mode selection signal indicates that the memory is in the on-chip verification mode, parallelize a first input data string of a first burst length received from each of the data ports to generate first write data output to the data verification circuit; and when the mode selection signal indicates that the memory is in the off-chip verification mode, parallelize a second input data string of a second burst length received from each of the data ports to generate second write data output to the data verification circuit; wherein the first write data includes data to be stored, the second write data includes the data to be stored and a corresponding second checksum, the first input data string includes a serially input portion of the data to be stored, and the second input data string includes a serially input portion of the data to be stored and a portion of the second checksum.

[0011] In some embodiments, the data verification circuit is further configured to, when the mode selection signal indicates that the memory is in the on-chip verification mode, encode the data to be stored in the received first write data to generate a corresponding third check code, and store the data to be stored and the third check code into the plurality of data storage blocks and the check code storage block respectively; and when the mode selection signal indicates that the memory is in the off-chip verification mode, store the data to be stored in the received second write data and the second check code into the plurality of data storage blocks and the check code storage block respectively.

[0012] In some embodiments, the input / output circuit is further configured to receive an extended function indication signal, and when the mode selection signal indicates that the memory is in off-chip verification mode and the extended function indication signal indicates that the memory has extended function enabled, to parallelize the third input data string of the third burst length received from each of the data ports and generate third write data output to the data verification circuit; wherein the third write data includes the data to be stored, the corresponding second check code and the second extended data, and the third input data string includes a portion of the data to be stored, a portion of the second check code and a portion of the second extended data that were serially input.

[0013] In some embodiments, the memory further includes: a data transmission circuit connected between the data verification circuit and the input / output circuit, the data transmission circuit being configured to transmit the first read data or the second read data from the data verification circuit to the input / output circuit, and to transmit the first write data or the second write data from the input / output circuit to the data verification circuit.

[0014] In some embodiments, the input / output circuit includes a data conversion circuit, which includes multiple data conversion sub-circuits corresponding one-to-one with the multiple data ports; each data conversion sub-circuit includes a serializer and a parallelizer; the serializer is coupled to the data transmission circuit and the corresponding data port, respectively, and is configured to, when the mode selection signal indicates that the memory is in on-chip verification mode, serialize a portion of the stored data received from the data transmission circuit according to a first burst length, and generate a first output data string output to the corresponding data port; and when the mode selection signal indicates that the memory is in off-chip verification mode, serialize a portion of the stored data received from the data transmission circuit... The first input data string, after being serialized according to the second burst length, is used to generate a second output data string to be output to the corresponding data port. The parallelizer, coupled to the data transmission circuit and the corresponding data port, is configured to, when the mode selection signal indicates that the memory is in on-chip verification mode, parallelize the first input data string received from the corresponding data port to generate a portion of the first write data to be output to the data transmission circuit, and when the mode selection signal indicates that the memory is in off-chip verification mode, parallelize the second input data string received from the corresponding data port to generate a portion of the second write data to be output to the data transmission circuit.

[0015] In some embodiments, the input / output circuit further includes: a first-in-first-out (FIFO) register and a data driver; the FIFO register is coupled between the data transmission circuit and the data conversion circuit, and is configured to receive and buffer the first read data or the second read data from the data transmission circuit during a read operation of the memory, and to receive and buffer the first write data or the second write data after parallel processing from the data conversion circuit during a write operation of the memory; the data driver is coupled between the data conversion circuit and the plurality of data ports, and is configured to receive a plurality of serialized first output data strings or a plurality of second output data strings from the data conversion circuit during a read operation of the memory, and drive the output to the plurality of data ports, and to receive a corresponding plurality of first input data strings or a plurality of second input data strings through the plurality of data ports during a write operation of the memory, and drive the output to the data conversion circuit.

[0016] In some embodiments, the data transmission circuit includes: a storage data transmission bus and a checksum transmission bus; the storage data transmission bus is configured to transmit the stored data or the data to be stored; the checksum transmission bus is configured to receive the mode selection signal, and transmit the first checksum or the second checksum when the mode selection signal indicates that the memory is in off-chip checksum mode, and be disabled when the mode selection signal indicates that the memory is in on-chip checksum mode.

[0017] In some embodiments, the data transmission circuit further includes: an extended data bus; the extended data bus is configured to receive the mode selection signal and the extended function indication signal, and to transmit first extended data or second extended data when the mode selection signal indicates that the memory is in off-chip verification mode and the extended function indication signal indicates that the memory is in an extended function enabled state; otherwise, the extended data bus is disabled.

[0018] In a second aspect, embodiments of this disclosure provide a storage device including at least one storage channel, each of the storage channels including a plurality of memories as described in the first aspect.

[0019] Thirdly, embodiments of this disclosure provide an operation method for a memory, the memory including a plurality of data storage blocks and a check code storage block, the operation method including: obtaining stored data and a corresponding first check code from the plurality of data storage blocks and the check code storage block respectively; determining a check mode of the memory in response to a mode selection signal; when the mode selection signal indicates that the memory is in an on-chip check mode, performing data check on the stored data according to the first check code, and outputting the data-checked stored data as first read data; or when the mode selection signal indicates that the memory is in an off-chip check mode, directly outputting the stored data and the first check code as second read data; wherein, the first check code in the second read data is used by an external memory controller to perform a data check operation on the stored data.

[0020] In some embodiments, the operation method further includes: serializing the first read data or the second read data and then outputting it from the memory through multiple data ports; wherein, when the memory is in the on-chip verification mode, the first read data is serialized according to a first burst length to generate multiple first output data strings output through the multiple data ports; when the memory is in the off-chip verification mode, the second read data is serialized according to a second burst length to generate multiple second output data strings output through the multiple data ports; the first burst length is less than the second burst length.

[0021] In some embodiments, after directly outputting the stored data and the first checksum as the second read data, the operation method further includes: determining whether the expansion function of the memory is enabled; if the memory is in the off-chip verification mode and the expansion function is enabled, serializing the second read data and the first extended data according to a third burst length to generate a plurality of third output data strings output through a plurality of data ports; wherein, the third output data strings include a portion of the stored data, a portion of the first checksum, and a portion of the first extended data that are serially output.

[0022] Fourthly, embodiments of this disclosure provide a method for operating a memory, the method comprising: determining a verification mode of the memory in response to a mode selection signal; when the mode selection signal indicates that the memory is in an on-chip verification mode, parallelizing a first input data string of a first burst length received from each data port to generate first write data; when the mode selection signal indicates that the memory is in an off-chip verification mode, parallelizing a second input data string of a second burst length received from each data port to generate second write data; wherein the second burst length is greater than the first burst length, the first write data includes data to be stored, the second write data includes the data to be stored and a corresponding second checksum, the first input data string includes a serially input portion of the data to be stored, and the second input data string includes a serially input portion of the data to be stored and a portion of the second checksum.

[0023] In some embodiments, the memory includes a plurality of data storage blocks and a check code storage block, and the operation method further includes: when the memory is in the on-chip verification mode, encoding the data to be stored in the received first write data to generate a corresponding third check code, and storing the data to be stored and the third check code into the plurality of data storage blocks and the check code storage block respectively; when the memory is in the off-chip verification mode, storing the data to be stored in the received second write data and the second check code into the plurality of data storage blocks and the check code storage block respectively.

[0024] In some embodiments, when the mode selection signal indicates that the memory is in the off-chip verification mode, the operation method further includes: determining whether the memory's expansion function is enabled; if the memory is in the off-chip verification mode and the expansion function is enabled, parallelizing the third input data string of the third burst length received from each of the data ports to generate third write data; wherein, the third write data includes the data to be stored, the corresponding second check code, and the second extended data, and the third input data string includes a portion of the data to be stored, a portion of the second check code, and a portion of the second extended data that were serially input.

[0025] This disclosure embodiment, by incorporating a data verification circuit in the memory that allows for selection of on-chip and off-chip verification modes, enables flexible configuration of verification modes to improve the utilization of on-chip storage resources and increase the diversity of data protection schemes. Specifically, when the error risk of the memory cell array of the memory chip is higher, the on-chip verification mode can be selected to use on-chip stored checksums to detect and correct data errors occurring during data storage on the memory chip. When the error risk of the data transmission link in the storage system is higher, the off-chip verification mode can be selected to directly send the on-chip stored checksums and stored data to an external memory controller. This allows the memory controller to use the checksums to detect and correct data errors occurring in the complete data transmission link of the storage system. Thus, the memory provided in this disclosure embodiment, using the same checksum storage block, can compatiblely implement data verification functions performed on the memory chip and off-chip data verification functions performed by the controller, improving the utilization of on-chip checksum storage block resources and saving the additional storage resource consumption associated with other ECC schemes that perform error detection and correction across the entire data transmission link. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figures 1A and 1B are schematic diagrams of the structure of a memory provided in an embodiment of this disclosure;

[0028] Figures 2A-2H are schematic diagrams of another memory structure provided in the embodiments of this disclosure;

[0029] Figures 3A-3D are schematic diagrams illustrating the configuration of the input data string / output data string used in the embodiments of this disclosure;

[0030] Figures 4A and 4B are schematic diagrams of the structure of another memory provided in the embodiments of this disclosure;

[0031] Figure 5 is a schematic diagram of an input / output circuit provided in an embodiment of this disclosure;

[0032] Figure 6 is a schematic diagram of a data conversion circuit provided in an embodiment of this disclosure;

[0033] Figures 7A-7D are schematic diagrams of the data conversion sub-circuit and data transmission circuit provided in the embodiments of this disclosure;

[0034] Figures 8A and 8B are signal timing diagrams corresponding to the data conversion sub-circuit provided in the embodiments of this disclosure;

[0035] Figure 9 is a schematic diagram of the structure of a storage device provided in an embodiment of this disclosure;

[0036] Figure 10 is a flowchart illustrating a method for operating a memory according to an embodiment of this disclosure;

[0037] Figure 11 is another schematic flowchart of a memory operation method provided in an embodiment of this disclosure;

[0038] Figure 12 is a flowchart illustrating another method for operating a memory provided in an embodiment of this disclosure;

[0039] Figure 13 is another schematic flowchart of a memory operation method provided in an embodiment of this disclosure; Detailed Implementation

[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0041] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.

[0042] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0043] It should be noted that the brief descriptions of terms in this disclosure are only for the purpose of facilitating understanding of the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to be omnipresent but not exclusive. For example, a product or device that comprises a series of components is not necessarily limited to those components that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0044] In related technologies, to improve data integrity and system reliability, Error Checking and Correction (ECC) functionality has been added to memory. Current memory products employ various ECC implementation methods, such as On-Die ECC, Link ECC, and Side Band ECC. While all these methods provide data protection in memory systems, each has potential disadvantages: On-Die ECC requires integrating ECC logic circuitry within the memory chip and configuring a storage array for verification data, increasing the memory chip area and cost. Furthermore, On-Die ECC cannot provide any protection against data errors occurring on the data transmission link (the transmission link between memory and control, and the data transmission path within the memory itself), requiring combination with other ECC methods (such as Link ECC and Side Band ECC) to achieve data protection for the entire data transmission link; Link ECC requires additional ECC processing on the data transmission link, which may increase data transmission latency and affect overall system performance, and Link ECC does not provide any protection against data errors occurring on the storage array; Side Band ECC... ECC implementations require additional memory chips to store ECC data, which significantly increases the cost of storage system products.

[0045] To address the aforementioned problems of existing ECC schemes in memory, this disclosure provides a memory comprising: multiple data storage blocks and a checksum storage block; a data verification circuit configured to acquire stored data and a corresponding first checksum from the multiple data storage blocks and the checksum storage block respectively, and to determine whether to perform a data verification operation in response to a received mode selection signal; the data verification circuit is further configured to, when the mode selection signal indicates that the memory is in on-chip verification mode, perform data verification on the stored data according to the first checksum and output the verified stored data as first read data, and when the mode selection signal indicates that the memory is in off-chip verification mode, directly output the stored data and the first checksum as second read data; wherein, the first checksum in the second read data is used by an external memory controller to perform a data verification operation on the stored data. In this way, by setting a data verification circuit in the memory that can select between on-chip and off-chip verification modes, the verification mode can be flexibly configured to improve the utilization of on-chip storage resources and increase the diversity of data protection schemes. Specifically, when the error risk of the memory cell array of the memory chip is higher, the on-chip verification mode can be configured to use the on-chip stored checksum to detect and correct data errors occurring during data storage on the memory chip. When the error risk of the data transmission link in the storage system is higher, the off-chip verification mode can be configured to send the on-chip stored checksum and stored data directly to the external memory controller, so that the memory controller can use the checksum to detect and correct data errors occurring in the complete data transmission link of the storage system. Thus, the memory provided in this embodiment of the present disclosure, using the same checksum storage block, can compatiblely implement data verification functions performed on the memory chip and off-chip data verification functions performed by the controller. This allows for more efficient use of on-chip checksum storage block resources and saves the additional storage resource consumption incurred when using other ECC schemes (e.g., side-band ECC) that perform error detection and correction on the entire data transmission link.

[0046] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0047] In one embodiment of this disclosure, referring to Figures 1A-1B, a schematic diagram of the structure of a memory 100 provided in this embodiment is shown. As shown in Figures 1A-1B, the memory 100 includes: a plurality of data storage blocks 11 and a check code storage block 12; a data verification circuit 20, configured to obtain stored data DATA and a corresponding first check code ECC1 from the plurality of data storage blocks 11 and the check code storage block 12 respectively, and determine whether to perform a data verification operation in response to a received mode selection signal; the data verification circuit 20 is further configured to, when the mode selection signal indicates that the memory 100 is in on-chip verification mode, perform data verification on the stored data DATA according to the first check code ECC1, and output the verified stored data DATA as first read data R_Data1; and when the mode selection signal indicates that the memory 100 is in off-chip verification mode, directly output the stored data DATA and the first check code ECC1 as second read data R_Data2; wherein, the first check code ECC1 in the second read data R_Data2 is used by an external memory controller to perform a data verification operation on the stored data DATA (as shown in Figure 1B).

[0048] Specifically, when the mode selection signal is at the first level, it indicates that the memory 100 is in on-chip verification mode, and when it is at the second level, it indicates that the memory 100 is in off-chip verification mode. Here, the first level can be a high level (logic "1"), and the corresponding second level is a low level (logic "0"), or the first level can be a low level (logic "0"), and the corresponding second level is a high level (logic "1"). No specific limitation is made here.

[0049] As shown in Figures 1A and 1B, the memory 100 includes a storage region 10 and a peripheral circuit region. Functional circuits such as the data verification circuit 20 are located in the peripheral circuit region. The storage region 10 is used to store data and may include multiple memory banks (not shown in the figures). Each memory bank may include multiple storage sections (not shown in the figures) obtained by dividing the storage blocks in the bit line direction. Each storage section includes multiple data storage blocks 11 and checksum storage blocks 12. Each storage section also includes multiple sense amplifier arrays (not shown in the figures), which are disposed between the storage blocks. Each storage block may include multiple memory cells.

[0050] Referring again to Figures 1A-1B, the memory 100 provided in this embodiment of the present disclosure is provided with a data verification circuit 20 that can select on-chip verification mode and off-chip verification mode. By configuring the data verification mode, the data verification circuit 20 can flexibly choose how to use and transmit the first check code ECC1 and the stored data DATA. Specifically, as shown in Figure 1A, when the mode selection signal indicates that the memory 100 is configured in on-chip verification mode, the first verification code ECC1 is used to provide data protection for the internal data storage process of the memory. That is, the data verification circuit 20 will directly perform error detection and correction on the stored data DATA according to the first verification code ECC1. At this time, the first verification code ECC1 has been used by the data verification circuit 20 to complete the data verification function, and there is no need to output it. The data verification module 20 only outputs the stored data DATA after data verification as the first read data R_Data1. As shown in Figure 1B, when the mode selection signal indicates that the memory 100 is in off-chip verification mode, the first verification code ECC1 is used to provide data protection for the complete data transmission link of the storage system. That is, the data verification circuit 20 will no longer perform on-chip data verification operation, but will directly output the stored data DATA and the first verification code ECC1 as the second read data R_Data2. At this time, the output first verification code ECC1 will be received by the external memory controller to perform data verification operation on the stored data DATA. In this embodiment of the disclosure, the memory, through the flexible configuration of the data verification mode of the data verification circuit, realizes the compatibility of on-chip data verification function and off-chip data verification function using the same check code storage block resources. This can improve the utilization rate of on-chip check code storage resources, increase the diversity of data protection schemes, and save the additional storage resource consumption caused by adopting the off-chip data verification ECC scheme.

[0051] The number (bit width) of storage cells in checksum storage block 12 and data storage block 11 can be set to be the same or different. Specifically, the ratio of stored data DATA to the corresponding first checksum ECC1 is determined according to the data verification encoding method used in the storage system, and then the number of storage cells in checksum storage block 12 is selected accordingly. For example, if the DDR5 memory is configured with a data bus width of 8, a burst length (BL) of 16, 8 data storage blocks in each data segment, and Hamming code is used as the data verification method, the prefetched stored data DATA is 8(mat) * 16(BL) = 128 bits. The first checksum that needs to be prefetched for the 128 bits of stored data is 8 bits. In this case, the bit width of checksum storage block 12 can be set to half that of data storage block 1.

[0052] It should be noted that the memory 100 shown in Figures 1A and 1B has the same structure. This disclosure only shows the data interaction between the various circuit components when the memory 100 performs read access operations in different verification modes through Figures 1A and 1B.

[0053] In some embodiments of this disclosure, the value of the mode selection signal is determined by configuration parameters in the mode register of the memory, and the memory controller can modify the configuration parameters in the mode register of the memory through mode register read / write commands.

[0054] In some embodiments of this disclosure, multiple check code storage blocks 12 can be set in each storage segment of the memory to increase the number of first check codes ECC1 and improve the error correction capability of the memory.

[0055] In some embodiments of this disclosure, improvements are made to the original on-die ECC circuit of the memory by adding an on-chip verification mode selection function to obtain the data verification circuit in this disclosure. When the on-chip verification mode is selected, the data verification circuit enables the original on-die ECC circuit and performs data verification (i.e., error detection and / or error correction) on the stored data Data according to the first check code ECC1 obtained from the check code storage block. The verified Data is then output as the first read data R_Data1. When the off-chip verification mode is selected, the data verification circuit disables the data verification function of the original on-die ECC circuit, i.e., bypasses the original on-die ECC circuit. The data verification circuit outputs the obtained stored data DATA and the first check code ECC1 as the second read data R_Data2.

[0056] Referring to Figures 2A-2C, a schematic diagram of another memory structure provided in an embodiment of the present disclosure is shown. As shown in Figure 2A, the memory 100 further includes: an input / output circuit 40, configured to receive a mode selection signal, and when the mode selection signal indicates that the memory 100 is in on-chip verification mode, serialize the received first read data R_Data1 according to a first burst length BL1 (Burst Length 1) to generate a plurality of first output data strings Out_s1 (as shown in Figure 2A) output to a plurality of data ports (DQ) 50; and when the mode selection signal indicates that the memory is in off-chip verification mode, serialize the received second read data R_Data2 according to a second burst length BL2 (Burst Length 2) to generate a plurality of second output data strings Out_s2 (as shown in Figure 2B) output to a plurality of data ports 50; wherein, the first burst length BL1 is less than the second burst length BL2.

[0057] In this embodiment of the disclosure, when the memory 100 is in on-chip verification mode and off-chip verification mode, the amount of parallel data received by the input / output circuit 40 is different. The number of data ports 50 in the memory 100 is preset and fixed. Therefore, without adding extra data port resources, after the input / output circuit 40 serializes the received parallel data, the amount of serial data (burst length BL) that needs to be transmitted through each data port 50 is also different. Specifically, taking 128b of stored data, 8b of first checksum data, and 8 data ports (X8) as an example, in on-chip verification mode, as shown in Figure 2A, the first read data R_Data1 received by the input / output circuit 40 only includes the 128b stored data DATA after error detection and correction. The input / output circuit 40 only needs to serialize the 128b stored data DATA after error detection and correction to obtain 8 first output data strings Out_s1 corresponding to the 8 data ports 50. The serial data length of each first output data string Out_s1 is 128 / 8 = 16, that is, the corresponding first burst length BL1 is 16. In off-chip verification mode, as shown in Figure 2B, the second read data R_Data2 received by the input / output circuit 40 includes not only the 128b stored data DATA, but also the 8b first checksum ECC1 that needs to be transmitted externally. The input / output circuit 40 processes the second read data R_Data2 (128b Data + 8b...) into serial data. After ECC1 is serialized, eight second output data strings Out_s2 corresponding to the eight data ports 50 are obtained. The serial data length of each second output data string Out_s2 is (128+8) / 8=17, that is, the corresponding second burst length BL2 is 17. Therefore, when the memory 100 is in off-chip verification mode, it needs to transmit an additional 8b of the first check code ECC1 through the eight data ports 50. That is, each data port 50 needs to transmit an additional 1b of data. The second burst length BL2 of the second output data string Out_s2 transmitted by the data port 50 is greater than the first burst length BL1 corresponding to the first output data string Out_s1.

[0058] It should be noted that the input / output circuit 40 in this embodiment is configured with at least two data processing modes with different burst lengths to respectively match the processing requirements of different data received under the two data verification modes (the first readout data R_Data1 and the second readout data R_Data2 with different data outputs from the data verification circuit 20).

[0059] In one embodiment of this disclosure, referring to Figures 2A-2B and 3A, the first output data string Out_s1 includes a portion of the serially output stored data DATA, and the second output data string Out_s2 includes a portion of the serially output stored data DATA and a portion of the first check code ECC1.

[0060] It should be noted that the first burst length BL1 is related to the memory specifications and data bus bandwidth configuration, while the second burst length BL2 is set based on factors such as the first burst length BL1, the number of first checksums (ECC1) that need to be transmitted additionally, and the data bus width. The second burst length BL2 can be set to just meet the transmission requirements of the first checksums (ECC1) to save serial data transmission time, or it can be set slightly larger than the transmission requirements of the first checksums (ECC1) to reserve extra space in the second output data string Out_s2 to meet the data transmission requirements of other extended functions. Specifically, the memory's X4 / X8 / X16 / X32… configuration refers to the data bus width, which can also be understood as the number of parallel input / output data ports in the memory. The memory's burst length BL configuration refers to the number of data blocks continuously transmitted in a single memory access, which can also be understood as the number of data blocks continuously serially input / output at each data port in the memory. The memory's burst length and data bus bandwidth together affect the memory's data transmission efficiency and speed. Referring to Figures 2A-2C and 3A, the data transfer during a read operation of DDR5 is explained. As shown in Figure 3A, the memory 100 has an X8 data bus width configuration (i.e., the memory 100 has 8 parallel input / output data ports 50). A single read / write operation of the memory 100 requires the transfer of 128 bits of stored data. When the memory 100 is in on-chip parity mode, as shown in Figure 2A, the first burst length BL1 = 128 bits / 8 (X8) = 16, and all bits Out_s1<0:15> in the first output data string Out_s1 corresponding to each data port are used to transfer stored data. When the memory 100 is in off-chip parity mode... In check mode, as shown in Figure 2B, the first checksum ECC1, which requires additional transmission, is 8 bits. Each data port 50 only needs to transmit 1 bit of data. Theoretically, the burst length BL can be set to any value greater than or equal to 17. However, since DDR5 uses double-edge data sampling, odd burst lengths are not conducive to data transmission between the memory and the controller. Therefore, the burst length BL must be set to an even number. Thus, the second burst length BL2 is set to 18. At this time, the first 16 bits of the second output data string Out_s2 transmitted by each data port, Out_s2<0:15>, are used to transmit the stored data DATA, and the 17th bit BL2... <16> Used to transmit the first checksum ECC1, and the 18th bit BL2. <17> Used to transmit extended data RFU corresponding to other extended functions. It should be noted here that for other memory products, such as DDR4 chips, under the same conditions, the second burst length BL2 corresponding to the second output data string Out_s2 can be set to 17. In this case, the second output data string Out_s2<0:16> only includes: part of the stored data DATA and part of the first check code ECC1.

[0061] Referring again to Figures 3C-3D, which illustrate two input / output data configurations provided in embodiments of this disclosure. In the X4 data bus width configuration of the memory 100, a single read / write access requires the transmission of 64 bits of storage data, half the amount transmitted in the X8 configuration. When the memory 100 is in on-chip verification mode, the first burst length BL1 = 64 bits / 4(X4) = 16. Similar to the X8 configuration, all bits Out_s1<0:15> in the first output data string Out_s1 transmitted by each data port are used to transmit storage data. In off-chip data verification mode, the storage data (2*64 bits of storage data) for two read / write accesses corresponds to the same 8 bits of the first checksum ECC1 data. That is, the two read / write accesses require an additional 8 bits of the first checksum ECC1 data to be transmitted. The second burst length BL2 is set to 18. In this case, there are two specific data configuration methods: The first configuration method, as shown in Figure 3C, involves the 17th bit BL2 in the second output data string Out_s2 of the first read / write operation. <16> Used to transmit the 4-bit first checksum ECC1 (ECC<0:3>), the 18th bit BL2 <17> Used to transmit extended data (CRC<0:3>) corresponding to other extended functions of 4b, the 17th bit BL2 in the second output data string Out_s2 read for the second time. <16> Used to transmit the additional 4 bits of the first parity check M code ECC1 (ECC<4:7>), the 18th bit BL2 <17> The first configuration is used to transmit extended data (CRC<4:7>) corresponding to the other 4B extended functions. The second configuration, as shown in Figure 3D, uses bits 17-18 (BL2<16:17>) of the second output data string Out_s2 from the first read to transmit the 8b first checksum ECC1 (ECC<0:7>). Similarly, bits 17-18 (BL2<16:17>) of the second output data string Out_s2 from the second read are used to transmit extended data (CRC<0:7>) corresponding to the other 8b extended functions. The specific X4 data configuration can be determined based on the special bit (CA10) in the read command or the parameters in the mode register.

[0062] In one embodiment of this disclosure, continuing to refer to FIG2C and FIG3A, the input / output circuit 40 is further configured to receive an extended function indication signal. When the mode selection signal indicates that the memory 100 is in the off-chip verification mode and the extended function indication signal indicates that the memory 100 has the extended function enabled, the received second read data R_Data2 and the first extended data RFU1 are serialized according to the third burst length BL3 to generate a plurality of third output data strings Out_s3 output to a plurality of data ports 50. The third output data strings Out_s3 include a portion of the serially output stored data DATA, a portion of the first check code ECC1, and a portion of the first extended data RFU1.

[0063] Specifically, the extended function indication signal indicates that the extended function of memory 100 is enabled when it is at the third level, and indicates that the extended function of memory 100 is disabled when it is at the fourth level. Here, the third level can be a high level (logic "1"), and the corresponding fourth level is a low level (logic "0"), or the third level can be a low level (logic "0"), and the corresponding fourth level is a high level (logic "1"). No specific limitation is made here.

[0064] It should be noted that, as shown in Figures 2D and 3B-3D, the extended function can be a cyclic redundancy check (CRC) function, and the corresponding first extended data RFU1 can be cyclic redundancy check data CRC_code. At the same time, the extended function can also be other functions executed in the memory. This disclosure only uses the CRC function as an example of an extended function for illustration, and does not constitute a limitation on the embodiments of this disclosure.

[0065] As shown in Figures 2D and 3B, the input / output circuit 40 uses the second read data R_Data2 and the cyclic redundancy check data CRC_code (i.e., the first extended data), and the first 16 bits of the third output data string Out_s3 corresponding to each data port, Out_s2<0:15>, to transmit the stored data DATA, and the 17th bit BL2. <16> Used to transmit the first checksum ECC1, and the 18th bit BL2. <17> Used to transmit cyclic redundancy check (CRC) data CRC_code corresponding to the cyclic redundancy check (CRC) function.

[0066] Here, the third burst length BL3 and the second burst length BL2 can be set to be the same, as shown in Figures 3A-3D, where BL2 = BL3 = 18. In this case, the input / output circuit 40 only needs to implement two data conversion modes with two burst lengths, which can simplify the circuit structure of the input / output circuit 40 and help reduce power consumption and area. The third burst length BL3 and the second burst length BL2 can also be set to be different. For example, for DDR4 products, BL2 can be set to 17 and BL3 can be set to 18. Setting a smaller second burst length BL2 when there is no need to enable the extended function helps to shorten the data output time.

[0067] It should be noted that when the memory is in on-chip verification mode or the memory's expansion function is not enabled, there is no need to output extended data to the outside through data port 50, and the input / output circuit 40 does not need to process the extended data. For example, there is no need to receive and serialize the cyclic redundancy check data CRC_code. At this time, the circuit module in the input / output circuit 40 that processes extended data can be turned off or disabled, which can improve the data processing speed of the input / output circuit 40 and reduce its power consumption.

[0068] In one embodiment of this disclosure, continuing to refer to FIG2D, the memory 100 further includes a CRC check circuit 60, configured to obtain stored data DATA from a plurality of data storage blocks 11, and generate and output cyclic redundancy check data CRC_code corresponding to the stored data DATA when the mode selection signal indicates that the memory 100 is in off-chip check mode and the extension function indication signal indicates that the memory is enabled for extension function.

[0069] In one embodiment of this disclosure, when the memory 100 is in on-chip verification mode or the expansion function is not enabled, since the input / output circuit 40 does not receive and process other data (first check code ECC1 and cyclic redundancy check data CRC_code) other than the stored data DATA, the CRC verification circuit 60 can be disabled so that it does not receive and process the stored data DATA, thereby saving the internal power consumption of the memory.

[0070] The CRC check circuit 60 can be designed based on the available space for extended function data in the third output data string Out_s3. Taking Figure 3B as an example, there are 8 bits in the 8 third output data strings Out_s3 corresponding to the 8 data ports that can be configured as cyclic redundancy check data CRC_code, that is, 128b of stored data corresponds to 8b of cyclic redundancy check data, which can be encoded using ATM-4HEC encoding.

[0071] It should be noted that Figures 2A-2D respectively show the functions performed by each component circuit of the memory 100 when performing read access operations in different verification modes, as well as the data interaction between them.

[0072] Since the multiple data ports 50, input / output circuits 40, data transmission circuits 30, and data verification circuits 20 in the memory 100 provided in this embodiment can all perform bidirectional data processing and transmission functions, the aforementioned circuits in the memory 100 support not only read access operations but also write access operations. Next, referring to Figures 2E-2H and 3A-3D, the functions performed by each circuit and the data interaction between them when the memory 100 provided in this embodiment performs write access operations with different verification modes will be described.

[0073] In one embodiment of this disclosure, as shown in Figures 2E-2F, when the memory 100 performs a write operation, the input / output circuit 40 is further configured to, when the mode selection signal indicates that the memory 100 is in on-chip verification mode, as shown in Figure 2E, parallelize the first input data string In_s1 of the first burst length BL1 received from each data port 50 and generate the first write data W_Data1 output to the data verification circuit 20; and when the mode selection signal indicates that the memory 100 is in off-chip verification mode, as shown in Figure 2F, parallelize the second input data string In_s2 of the second burst length BL2 received from each data port 50 and generate the second write data W_Data2 output to the data verification circuit 20; wherein, the first write data W_Data1 includes the data to be stored data, the second write data W_Data2 includes the data to be stored data and the corresponding second check code ECC2, the first input data string In_s1 includes a serially input portion of the data to be stored data, and the second input data string In_s2 includes a serially input portion of the data to be stored data and a portion of the second check code ECC2.

[0074] In one embodiment of this disclosure, continuing to refer to Figures 2E-2F, the data verification circuit 20 is further configured to, when the mode selection signal indicates that the memory 100 is in on-chip verification mode, encode the data to be stored in the received first write data W_Data1 to generate a corresponding third check code ECC3, and store the data to be stored and the third check code ECC3 into multiple data storage blocks 11 and check code storage blocks 12 respectively; and when the mode selection signal indicates that the memory 100 is in off-chip verification mode, store the data to be stored and the second check code ECC2 in the received second write data W_Data2 into multiple data storage blocks 11 and check code storage blocks 12 respectively.

[0075] In one embodiment of this disclosure, continuing to refer to Figures 2G-2H, the input / output circuit 40 is further configured to receive an extended function indication signal, and when the mode selection signal indicates that the memory 100 is in off-chip verification mode and the extended function indication signal indicates that the memory 100 has the extended function enabled, the third input data string In_s3 of the third burst length BL3 received from each data port 50 is parallelized and processed to generate the third write data W_Data3 output to the data verification circuit 20;

[0076] The third data to be written, W_Data3, includes the data to be stored, the corresponding second check code ECC2, and the second extended data RFU2. The third input data string, In_s3, includes a portion of the data to be stored, a portion of the second check code ECC2, and a portion of the second extended data RFU2 that were serially input.

[0077] As mentioned earlier, the third burst length BL3 and the second burst length BL2 can be set to be the same or different.

[0078] It should be noted that when the memory is in on-chip verification mode or the memory's expansion function is not enabled, there is no need to receive external input extended data through data port 50, and the input / output circuit 40 does not need to process the extended data. For example, there is no need to receive and parallelize the cyclic redundancy check data CRC_code. At this time, the circuit module in the input / output circuit 40 that processes extended data can be turned off or disabled, which can improve the data processing speed of the input / output circuit 40 and reduce its power consumption.

[0079] In one embodiment of this disclosure, referring to FIG4A, the memory 100 further includes: a data transmission circuit 30 connected between the data verification circuit 20 and the input / output circuit 40. The data transmission circuit 30 is configured to transmit a first read data R_Data1 or a second read data R_Data2 from the data verification circuit 20 to the input / output circuit 40, and to transmit a first write data W_Data1 or a second write data W_Data2 from the input / output circuit 40 to the data verification circuit 20.

[0080] It should be noted that the data transmission circuit 30 in the memory 100 provided in this embodiment is only used for bidirectional transmission of internal data, such as drive enhancement, delay, synchronization, level conversion, etc., but does not perform any substantial data processing.

[0081] In one embodiment of this disclosure, referring to FIG4B, the data transmission circuit 30 can also receive an extended function indication signal. When the extended function indication signal indicates that the memory 100 enables the extended function, the data transmission circuit 30 is further configured to: during a read access operation, transmit the second read data R_Data2 and the cyclic redundancy check data CRC_code from the data verification circuit 20 and the CRC verification circuit 60 to the input / output circuit 40, respectively; during a write access operation, transmit the data to be stored data and the second check code ECC2 in the third write data W_Data3 from the input / output circuit 40 to the data verification circuit 20, and transmit the cyclic redundancy check data CRC_code in the third write data W_Data3 from the input / output circuit 40 to the CRC verification circuit 60.

[0082] It should be noted that the Cyclic Redundancy Check (CRC) function is used as an example of an extended function in Figure 4B. Extended functions can also be other functions executed in memory, and no specific limitation is made here.

[0083] In one embodiment of this disclosure, referring to Figures 7A-7B, the data transmission circuit 30 includes: a storage data transmission bus 31 and a check code transmission bus 32; the storage data transmission bus 31 is configured to transmit stored data DATA or data to be stored data; the check code transmission bus 32 is configured to receive a mode selection signal, and transmit a first check code ECC1 or a second check code ECC2 when the mode selection signal indicates that the memory 100 is in off-chip check mode, and be disabled when the mode selection signal indicates that the memory 100 is in on-chip check mode. Specifically, the storage data transmission bus 31 is used to transmit the stored data DATA in the first read data R_Data1 or the second read data R_Data2 from the data verification circuit 20 to the input / output circuit 40, and to transmit the data to be stored data in the first write data W_Data1 or the second write data W_Data2 from the input / output circuit 40 to the data verification circuit 20; the verification code transmission bus 32 is used to transmit the first verification code ECC1 in the second read data R_Data2 from the data verification circuit 20 to the input / output circuit 40, and to transmit the second verification code ECC2 in the second write data W_Data2 from the input / output circuit 40 to the data verification circuit 20.

[0084] Here, when the memory 100 is in on-chip verification mode, as shown in Figure 7B, the memory 100 does not need to receive external verification codes or output verification codes to the outside through the data port 50. The verification code transmission bus 32 in the memory 100 also does not need to transmit verification data such as the first verification code ECC1 or the second verification code ECC2. At this time, the verification code transmission bus 32 can be turned off or disabled to reduce the power consumption of data transmission in the memory.

[0085] It should be noted that when the memory 100 supports the extended function (the cyclic redundancy check function is used as an example of the extended function here), that is, when the extended function indication signal received by the data transmission circuit 30 indicates that the memory 100 enables the extended function, as shown in Figure 7C, the storage data transmission bus 31 and the check code transmission bus 32 are also used to transmit the data to be stored in the third write data W_Data3 and the second check code ECC2, respectively.

[0086] In one embodiment of this disclosure, referring to Figures 7C-7D, the data transmission circuit 30 further includes: an extended data bus 33; the extended data bus 33 is configured to receive a mode selection signal and an extended function indication signal, and to transmit first extended data or second extended data when the mode selection signal indicates that the memory is in off-chip verification mode and the extended function indication signal indicates that the memory is in extended function enabled state; otherwise, the extended data bus is disabled.

[0087] For the memory 100 that supports expansion functions, when the memory 100 is in on-chip verification mode or the expansion function of the memory is not enabled, as shown in Figure 7D, there is no need to receive external expansion data through the data port 50 or output expansion data to the outside through the data port 50. The expansion data bus 33 also does not need to transmit expansion data, and the input / output circuit 40 does not need to process the expansion data, such as cyclic redundancy check data CRC_code. At this time, the expansion data bus 33 can be turned off or disabled to reduce the power consumption of data transmission in the memory 100.

[0088] In one embodiment of this disclosure, referring to Figures 5, 6, 7A-7D, and 8A-8B, the input / output circuit 40 includes a data conversion circuit 42, which includes a plurality of data conversion sub-circuits 421 corresponding one-to-one with a plurality of data ports 50; each data conversion sub-circuit 421 includes a serializer 422 and a parallelizer 423.

[0089] The serializer 422 is coupled to the data transmission circuit 30 and the corresponding data port 50, respectively. It is configured to, as shown in Figures 7A and 8A, serialize a portion of the stored data DATA received from the data transmission circuit 30 according to the first burst length BL1 and generate a first output data string Out_s1 output to the corresponding data port 50 when the mode selection signal indicates that the memory 100 is in on-chip verification mode, and as shown in Figures 7B and 8B, serialize a portion of the stored data DATA and a portion of the first check code ECC1 received from the data transmission circuit 30 according to the second burst length BL2 and generate a second output data string Out_s2 output to the corresponding data port 50.

[0090] Parallelizer 423, coupled to data transmission circuit 30 and corresponding data port 50 respectively, is configured to, as shown in Figures 7A and 8A, parallelize the first input data string In_s1 received from the corresponding data port 50 and generate a portion of the first write data W_Data1 output to data transmission circuit 30 after parallel processing; and to, as shown in Figures 7B and 8B, parallelize the second input data string In_s2 received from the corresponding data port 50 and generate a portion of the second write data W_Data2 output to data transmission circuit 30 after parallel processing when the mode selection signal indicates that memory 100 is in off-chip verification mode, as shown in Figures 7B and 8B.

[0091] As shown in Figures 7B and 8B, the first write data W_Data1 output by each data port 50 includes part (16b) of the data to be stored, and the second write data W_Data2 includes part (16b) of the data to be stored and the corresponding part (1b) of the second check code ECC2.

[0092] In some embodiments, when the memory 100 supports the extended function, the serializer 422 can also be used to receive the extended function indication signal. When the mode selection signal indicates that the memory 100 is in the off-chip verification mode and the extended function indication signal indicates that the memory 100 has the extended function enabled, as shown in FIG7C and 8B, the serialization of a portion of the stored data DATA, a portion of the first check code ECC1, and a portion of the first extended data RFU1 received from the data transmission circuit 30 according to the third burst length BL3 generates a third output data string Out_s3 output to the corresponding data port 50. The parallelizer 423 can also be used to receive the extended function indication signal. When the mode selection signal indicates that the memory 100 is in the off-chip verification mode and the extended function indication signal indicates that the memory 100 has the extended function enabled, as shown in FIG7C and 8B, the parallelization of the third input data string In_s3 received from the corresponding data port 50 generates a portion of the data to be stored data, a portion of the second check code ECC2, and a portion of the second extended data RFU2 output to the data transmission circuit 30.

[0093] Here, we take the example of setting the third burst length BL3 and the second burst length BL2 to be the same, as shown in Figure 8B, where BL2 = BL3 = 18; in some other embodiments, the third burst length BL3 and the second burst length BL2 can also be set to different values. For example, for DDR4 products, BL2 can be set to 17 and BL3 can be set to 18. This disclosure does not make any specific limitations.

[0094] It should be noted that for the memory 100 that supports expansion function, if the memory 100 is in on-chip verification mode or the expansion function of the memory is not enabled, as shown in Figure 7D, the serializer 422 does not need to receive and process the first extended data RFU1, and the parallelizer 423 does not need to process and output the second extended data RFU2. The extended data is received from the outside through the data port 50 or output to the outside through the data port 50. At this time, the extended data bus 33 can be turned off or disabled, and the serializer 422 and the parallelizer 423 can be adjusted to not process the extended data to reduce the data processing time of the serializer 422 and the parallelizer 423, and save the internal power consumption of the memory.

[0095] In some embodiments, continuing to refer to FIG5, the input / output circuit 40 further includes: a first-in-first-out (FIFO) register 41 and a data driver 43; the FIFO register 41 is coupled between the data transmission circuit 30 and the data conversion circuit 42, and is configured to receive and buffer first read data R_Data1 or second read data R_Data2 from the data transmission circuit 30 during a read operation of the memory 100, and to receive and buffer first write data W_Data1 or second write data W_Data2 after parallel processing from the data conversion circuit 42 during a write operation of the memory 100. Data2; Data driver 43, coupled between data conversion circuit 42 and multiple data ports 50, is configured to receive multiple serialized first output data strings Out_s1 or multiple second output data strings Out_s2 from data conversion circuit 42 during read operation of memory 100 and drive them to the multiple data ports 50, and to receive corresponding multiple first input data strings In_s1 or multiple second input data strings In_s2 through multiple data ports 50 during write operation of memory 100 and drive them to the data conversion circuit 42.

[0096] It should be noted that when the memory 100 enables the extension function (the cyclic redundancy check function is used as an example of the extension function here), the first-in-first-out register 41 is also used to receive and buffer the first extension data or the second extension data (not shown in the figure), such as the cyclic redundancy check data CRC_code. The data driver 43 is also used to receive multiple serialized third output data strings Out_s3 and drive them to multiple data ports 50, and to receive the corresponding multiple third input data strings In_s3 through multiple data ports 50 and drive them to the data conversion circuit 42.

[0097] It should be noted that the memory provided in the above embodiments can be implemented in combination with each other. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment, and will not be repeated here to avoid repetition.

[0098] This disclosure also provides a storage device. Referring to FIG9, the storage device 300 includes at least one storage channel 400, and each storage channel 400 includes a plurality of memories 100 as provided in the above embodiments.

[0099] As shown in Figure 9, the storage device 300 can be a dual inline memory module (DIMM). Generally, for a DIMM with two storage channels, each side includes eight memory chips 100 and two ECC chips 200. Here, the ECC chips are side-band ECC chips. Although the side-band ECC chips can be used by the memory controller to detect and correct data errors that occur in the complete data transmission link of the storage system, they bring additional hardware costs and system complexity to the storage device 300. However, based on the memory 100 provided in this disclosure, the verification mode can be flexibly configured through the data verification circuit. When the error risk in the data transmission link of the storage system is higher, an off-chip verification mode can be selected to directly send the on-chip stored checksum and stored data to the external memory controller. This allows the memory controller to use the on-chip stored checksum to detect and correct data errors occurring in the complete data transmission link of the storage system. In this case, the checksum storage block inside the memory 100 can replace the function of the sideband ECC chip. That is, the memory 100 provided in this disclosure can use the same checksum storage block to compatiblely implement the data verification function executed on the memory chip and the off-chip data verification function executed by the memory controller, improving the utilization rate of the on-chip checksum storage block resources and saving the additional storage resource consumption caused by the storage device 300 using other ECC schemes such as sideband ECC. As shown in Figure 9, based on the memory 100 provided in this disclosure, the four ECC chips 200 in the storage device 300 can be eliminated, significantly reducing the hardware cost and system complexity of the storage device 300.

[0100] This disclosure also provides a method for operating a memory, wherein the memory includes multiple data storage blocks and a checksum storage block. Referring to FIG10, the method includes the following steps:

[0101] Step S11: During the read operation in the memory, the stored data and the corresponding first check code are obtained from multiple data storage blocks and check code storage blocks respectively;

[0102] Step S12: Determine the memory's verification mode in response to the mode selection signal;

[0103] Specifically, when the mode selection signal indicates that the memory is in on-chip verification mode, step S121 is executed: the stored data is verified according to the first verification code, and the verified stored data is output as the first read data; or,

[0104] When the mode selection signal indicates that the memory is in off-chip verification mode, step S122 is executed: the stored data and the first verification code are directly output as the second read data; wherein, the first verification code in the second read data is used by the external memory controller to perform data verification operation on the stored data.

[0105] In some embodiments, referring to Figures 1A-1B and 10, step S11 specifically includes: during a read operation performed by the memory 100, the data verification circuit 20 obtains stored data DATA and the corresponding first verification code ECC1 from multiple data storage blocks 11 and verification code storage blocks 12, respectively; step S12 specifically includes: the data verification circuit 20 determines the verification mode of the memory in response to a received mode selection signal; when the mode selection signal indicates that the memory 100 is in on-chip verification mode, the data verification circuit 20 performs data verification on the stored data DATA according to the first verification code ECC1, and outputs the verified stored data DATA as first read data R_Data1; when the mode selection signal indicates that the memory 100 is in off-chip verification mode, the data verification circuit 20 directly outputs the stored data DATA and the first verification code ECC1 as second read data R_Data2, and the first verification code ECC1 in the second read data R_Data2 is used to output to an external memory controller, and the memory controller performs an off-chip data verification operation on the stored data DATA.

[0106] Based on this operation method, the memory can flexibly choose how to use and transmit the first check code ECC1 and the stored data DATA during the read operation according to the verification mode. When the mode selection signal indicates that the memory is configured in on-chip verification mode, the first check code ECC1 is used to provide data protection for the internal data storage process of the memory. The memory will directly perform error detection and correction on the stored data DATA according to the first check code ECC1. At this time, the first check code ECC1 has been used in the memory and completed the data verification function. There is no need to output it. Only the stored data DATA after data verification needs to be output as the first read data R_Data1. When the mode selection signal indicates that the memory 100 is configured in off-chip verification mode, the first check code ECC1 is used to provide data protection for the complete data transmission link of the storage system. The memory will no longer perform on-chip data verification operation. Instead, the stored data DATA and the first check code ECC1 are directly output as the second read data R_Data2. At this time, the output first check code ECC1 will be received by the external memory controller to perform data verification operation on the completed stored data DATA. Therefore, the memory operation method provided in this disclosure, during the read operation, enables the use of the same check code data to achieve on-chip data verification and off-chip data verification functions, which can improve the utilization rate of on-chip check code storage resources, increase the diversity of data protection schemes, and save the additional storage resource consumption caused by using off-chip data verification ECC scheme.

[0107] In one embodiment of this disclosure, referring again to FIG10, after completing step S121 or step S122, the operation method further includes: step S13 (not shown in the figure): serializing the first read data or the second read data and outputting it from the memory through multiple data ports; specifically, when the memory is in on-chip verification mode, after completing step S121, step S131 is executed: serializing the first read data according to the first burst length and generating multiple first output data strings output through multiple data ports; when the memory is in off-chip verification mode, after completing step S122, step S132 is executed: serializing the second read data according to the second burst length and generating multiple second output data strings output through multiple data ports; wherein, the first burst length is less than the second burst length.

[0108] In some embodiments, referring to Figures 2A-2B and Figure 10, the specific process of step S13 includes: the input / output circuit 40 disposed in the memory 100 receives the first read data R_Data1 or the second read data R_Data2 from the data verification circuit 20, and after serializing the first read data R_Data1 or the second read data R_Data2, outputs it from the memory 100 through multiple data ports 50; specifically, the input / output circuit 40 receives a mode selection signal, and when the mode selection signal indicates that the memory 100 is in on-chip verification mode... The input / output circuit 40 serializes the received first read data R_Data1 according to the first burst length BL1, and generates multiple first output data strings Out_s1 to be output to multiple data ports 50. When the mode selection signal indicates that the memory 100 is in the off-chip verification mode, the input / output circuit 40 serializes the received second read data R_Data2 according to the second burst length BL2, and generates multiple second output data strings Out_s2 to be output to multiple data ports 50. The first burst length BL1 is less than the second burst length BL2.

[0109] In one embodiment of this disclosure, referring to FIG3A, the first output data string Out_s1 includes a portion of the serially output stored data DATA, and the second output data string Out_s2 includes a portion of the serially output stored data DATA and a portion of the first check code ECC1.

[0110] In one embodiment of this disclosure, as shown in FIG11, when the memory is in off-chip verification mode, after completing step S122, step S14 is executed: determining whether the memory's expansion function is enabled; if the memory is in off-chip verification mode and the expansion function is not enabled, after completing step S122, step S132 is executed: the second read data is serialized according to the second burst length to generate multiple second output data strings output through multiple data ports; if the memory is in off-chip verification mode and the expansion function is enabled, after completing step S122, step S133 is executed: the second read data and the first extended data are serialized according to the third burst length to generate multiple third output data strings output through multiple data ports; wherein, the third output data string includes a serially output portion of the stored data, a portion of the first check code, and a portion of the first extended data; while when the memory is in on-chip verification mode, after completing step S121, step S131 is executed directly: the first read data is serialized according to the first burst length to generate multiple first output data strings output through multiple data ports.

[0111] In some embodiments, referring to Figures 2A-2D, 3A, and 11, step S14, executed after step S122, specifically includes: the input / output circuit 40 further receives an extended function indication signal and determines whether the memory's extended function is enabled based on the extended function indication signal. When the mode selection signal indicates that the memory 100 is in off-chip verification mode and the extended function indication signal indicates that the memory's extended function is enabled, the input / output circuit 40 serializes the received second read data R_Data2 and first extended data RFU1 according to the third burst length BL3, and generates multiple third output data strings Out_s3 output to multiple data ports 50; wherein, as shown in Figure 3A, the third output data string Out_s3 includes a portion of the serially output stored data DATA, a portion of the first check code ECC1, and a portion of the first extended data RFU1. At this time, if the memory is in off-chip verification mode and the extended function is not enabled, the input / output circuit 40 serializes the received second read data R_Data2 according to the second burst length BL2, and generates multiple second output data strings Out_s2 output to multiple data ports 50.

[0112] Here, the third burst length BL3 and the second burst length BL2 can be set to be the same, as shown in Figures 3A-3D, where BL2 = BL3 = 18. The third burst length BL3 and the second burst length BL2 can also be set to be different. For example, for DDR4 products, BL2 can be set to 17 and BL3 can be set to 18.

[0113] It should be noted that the extended function can be a cyclic redundancy check function, and the corresponding first extended data RFU1 can be the cyclic redundancy check data CRC_code. At the same time, the extended function can also be other functions executed in memory.

[0114] It should also be noted that the memory operation methods provided in the above embodiments are all completed during the read access operation that begins after the memory receives a read command; and the above memory operation methods can all be applied to the memory 100 in the foregoing embodiments. For details not disclosed in the embodiments of the operation methods, please refer to the description of the embodiments of the foregoing memory 100 for understanding, and will not be repeated here.

[0115] This disclosure also provides another method for operating a memory, wherein the memory includes multiple data storage blocks and a checksum storage block. Referring to FIG12, the method includes the following steps:

[0116] Step S21: During a write operation in the memory, the parity mode of the memory is determined in response to a mode selection signal;

[0117] When the mode selection signal indicates that the memory is in on-chip verification mode, step S221 is executed: after parallelizing the first input data string of the first burst length received from each data port, the first write data is generated.

[0118] When the mode selection signal indicates that the memory is in off-chip verification mode, step S222 is executed: after parallelizing the second input data string of the second burst length received from each data port, the second write data is generated;

[0119] The second burst length is greater than the first burst length. The first written data includes the data to be stored. The second written data includes the data to be stored and the corresponding second check code. The first input data string includes a portion of the data to be stored that was serially input. The second input data string includes a portion of the data to be stored that was serially input and a portion of the second check code.

[0120] In some embodiments, referring to Figures 2E-2F and Figure 12, the specific process of step S21 includes: during a write operation of the memory 100, the input / output circuit 40 determines the memory's verification mode according to the received mode selection signal; when the mode selection signal indicates that the memory 100 is in on-chip verification mode, as shown in Figure 2E, the input / output circuit 40 parallelizes the first input data string In_s1 of the first burst length BL1 received from each data port 50 and generates the first write data W_Data1 output to the data verification circuit 20; when the mode selection signal indicates that the memory 100 is in off-chip verification mode, as shown in Figure 2... As shown in Figure F, the input / output circuit 40 parallelizes the second input data string In_s2 of the second burst length BL2 received from each data port 50, and generates the second write data W_Data2 output to the data verification circuit 20. The first write data W_Data1 includes the data to be stored, and the second write data W_Data2 includes the data to be stored and the corresponding second check code ECC2. The first input data string In_s1 includes the serially input part of the data to be stored, and the second input data string In_s2 includes the serially input part of the data to be stored and part of the second check code ECC2.

[0121] Based on the above operation method, the memory can flexibly select which type of write data to receive and process during the read operation according to the verification mode. When the mode selection signal indicates that the memory is configured in on-chip verification mode, the memory receives a first input data string containing only the data to be stored and processes it to generate the first write data. At this time, the memory needs to generate an internal third check code ECC3 based on the data to be stored, thereby realizing on-chip verification of the data. The memory can store the data to be stored and the internally generated third check code ECC3 into the data storage block and the check code storage block. When the mode selection signal indicates that the memory 100 is configured in off-chip verification mode, the memory receives a second input data string containing the data to be stored and a second check code and processes it to generate the second write data. The second check code ECC2 corresponding to the data to be stored is directly generated and sent by the external memory controller. At this time, the memory does not need to generate an internal third check code based on the data to be stored. The memory can directly store the data to be stored in the second write data W_Data2 and the externally received second check code ECC2 into the data storage block and the check code storage block. Therefore, the memory operation method provided in this embodiment of the present disclosure implements on-chip data verification and off-chip data verification functions based on mode selection signal compatibility during write operations. This can improve the utilization rate of on-chip check code storage resources, increase the diversity of data protection schemes, and save the additional storage resource consumption caused by adopting the off-chip data verification ECC scheme.

[0122] In one embodiment of this disclosure, referring again to FIG12, the operation method further includes: when the memory is in on-chip verification mode, step S221 is completed and steps S231 and S241 are executed: the data to be stored in the received first write data is encoded to generate a corresponding third check code; the data to be stored and the third check code are stored into multiple data storage blocks and a check code storage block, respectively; when the memory is in off-chip verification mode, step S222 is completed and step S232 is executed: the data to be stored in the received second write data and the second check code are stored into multiple data storage blocks and a check code storage block, respectively.

[0123] In some embodiments, referring to Figures 2E-2F and Figure 12, when the memory 100 is in on-chip verification mode, the data verification circuit 20 encodes the data to be stored in the received first write data W_Data1 to generate a corresponding third check code ECC3, and stores the data to be stored and the third check code ECC3 into multiple data storage blocks 11 and check code storage blocks 12, respectively. When the memory 100 is in off-chip verification mode, the data verification circuit 20 stores the data to be stored and the second check code ECC2 in the received second write data W_Data2 into multiple data storage blocks 11 and check code storage blocks 12, respectively.

[0124] In one embodiment of this disclosure, referring to FIG13, when the mode selection signal indicates that the memory is in off-chip verification mode, the operation method further includes: step S31: determining whether the memory's expansion function is enabled; if the memory is in off-chip verification mode and the expansion function is not enabled, steps S222 and S232 are executed sequentially: the second input data string received from each data port is parallelized and processed to generate second write data; the second read data is serialized according to the second burst length and processed to generate multiple second output data strings output through multiple data ports; if the memory is in off-chip verification mode and the expansion function is enabled, steps S223 and S233 are executed: the third input data string of the third burst length received from each data port is parallelized and processed to generate third write data; the data to be stored and the second check code in the received third write data are respectively stored into multiple data storage blocks and check code storage blocks; wherein, the third write data includes the data to be stored, the corresponding second check code and the second extended data, and the third input data string includes a serially input part of the data to be stored, a part of the second check code and a part of the second extended data.

[0125] In some embodiments, referring to Figures 2E-2H, 3A, and 13, when it is determined that the memory is in off-chip verification mode after executing step S21, step S31 specifically includes: the input / output circuit 40 also receives an extended function indication signal, and determines whether the extended function of the memory is enabled based on the extended function indication signal. When the mode selection signal indicates that the memory 100 is in off-chip verification mode and the extended function indication signal indicates that the memory has the extended function enabled, the third input data string In_s3 of the third burst length BL3 received from each data port 50 is parallelized and processed to generate the third write data W_Data3 output to the data verification circuit 20; wherein, the third write data W_Data3 includes the data to be stored data, the corresponding second check code ECC2, and the second extended data RFU2, and the third input data string In_s3 includes a portion of the serially input data to be stored data, a portion of the second check code ECC2, and a portion of the second extended data RFU2. Conversely, if the memory is in off-chip verification mode and the expansion function is not enabled, step S222 is executed, that is, the input / output circuit 40 parallelizes the second input data string In_s2 of the second burst length BL2 received from each data port 50 and generates the second write data W_Data2 output to the data verification circuit 20.

[0126] Here, the third burst length BL3 and the second burst length BL2 can be set to be the same, as shown in Figures 3A-3D, where BL2 = BL3 = 18. The third burst length BL3 and the second burst length BL2 can also be set to be different. For example, for DDR4 products, BL2 can be set to 17 and BL3 can be set to 18.

[0127] It should be noted that the extended function can be a cyclic redundancy check function, and the corresponding first extended data RFU1 can be the cyclic redundancy check data CRC_code. At the same time, the extended function can also be other functions executed in memory.

[0128] It should also be noted that the memory operation methods provided in the above embodiments are all completed during the write access operation that begins after the memory receives the write command; and the above memory operation methods can all be applied to the memory 100 in the foregoing embodiments. For details not disclosed in the embodiments of the operation methods, please refer to the description of the embodiments of the foregoing memory 100 for understanding, and will not be repeated here.

[0129] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0130] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0131] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory (100), comprising: Multiple data storage blocks (11) and check code storage blocks (12); The data verification circuit (20) is configured to obtain stored data (DATA) and the corresponding first check code (ECC1) from the plurality of data storage blocks (11) and the check code storage block (12) respectively, and determine whether to perform data verification operation in response to the received mode selection signal; The data verification circuit (20) is further configured to, when the mode selection signal indicates that the memory (100) is in on-chip verification mode, perform data verification on the stored data (DATA) according to the first verification code (ECC1) and output the verified stored data (DATA) as first read data (R_Data1); and when the mode selection signal indicates that the memory (100) is in off-chip verification mode, directly output the stored data (DATA) and the first verification code (ECC1) as second read data (R_Data2); wherein the first verification code (ECC1) in the second read data (R_Data2) is used by the external memory (100) controller to perform data verification operation on the stored data (DATA).

2. The memory (100) according to claim 1, characterized in that The memory (100) also includes: The input / output circuit (40) is configured to receive the mode selection signal, and when the mode selection signal indicates that the memory (100) is in on-chip verification mode, to serialize the received first read data (R_Data1) according to a first burst length and generate a plurality of first output data strings (Out_s1) to be output to a plurality of data ports (50); and when the mode selection signal indicates that the memory (100) is in off-chip verification mode, to serialize the received second read data (R_Data2) according to a second burst length and generate a plurality of second output data strings (Out_s2) to be output to a plurality of data ports (50); wherein the first burst length is less than the second burst length.

3. The memory (100) according to claim 2, characterized in that, The first output data string (Out_s1) includes a portion of the stored data (DATA) that is serially output, and the second output data string (Out_s2) includes a portion of the stored data (DATA) that is serially output and a portion of the first checksum (ECC1).

4. The memory (100) according to claim 2 or 3, characterized in that, The input / output circuit (40) is further configured to receive an extended function indication signal. When the mode selection signal indicates that the memory (100) is in off-chip verification mode and the extended function indication signal indicates that the memory (100) has the extended function enabled, the received second read data (R_Data2) and first extended data (RFU1) are serialized according to the third burst length to generate a plurality of third output data strings output to a plurality of data ports (50). The third output data string includes a portion of the serially output stored data (DATA), a portion of the first checksum (ECC1), and a portion of the first extended data (RFU1).

5. The memory (100) according to any one of claims 2-4, characterized in that, The input / output circuit (40) is further configured to, when the mode selection signal indicates that the memory (100) is in the on-chip verification mode, parallelize the first input data string (In_s1) of the first burst length received from each of the data ports (50) and generate the first write data (W_Data1) output to the data verification circuit (20); and when the mode selection signal indicates that the memory (100) is in the off-chip verification mode, parallelize the second input data string (In_s2) of the second burst length received from each of the data ports (50). The second write data (W_Data2) is generated and output to the data verification circuit (20); wherein, the first write data (W_Data1) includes the data to be stored (data), the second write data (W_Data2) includes the data to be stored (data) and the corresponding second check code (ECC2), the first input data string (In_s1) includes a portion of the data to be stored (data) input serially, and the second input data string (In_s2) includes a portion of the data to be stored (data) input serially and a portion of the second check code (ECC2).

6. The memory (100) according to claim 5, characterized in that, The data verification circuit (20) is further configured to, when the mode selection signal indicates that the memory (100) is in the on-chip verification mode, encode the data to be stored in the received first write data (W_Data1) to generate a corresponding third check code, and store the data to be stored and the third check code into the plurality of data storage blocks (11) and the check code storage block (12) respectively; and when the mode selection signal indicates that the memory (100) is in the off-chip verification mode, store the data to be stored and the second check code (ECC2) in the received second write data (W_Data2) into the plurality of data storage blocks (11) and the check code storage block (12) respectively.

7. The memory (100) according to claim 4 or 5, characterized in that, The input / output circuit (40) is further configured to receive an extended function indication signal, and when the mode selection signal indicates that the memory (100) is in off-chip verification mode and the extended function indication signal indicates that the memory (100) has enabled extended function, it will parallelize the third input data string (In_s3) of the third burst length received from each of the data ports (50) and generate a third write data (W_Data3) output to the data verification circuit (20); wherein the third write data (W_Data3) includes the data to be stored (data), the corresponding second check code (ECC2) and the second extended data (RFU2), and the third input data string (In_s3) includes a portion of the data to be stored (data), a portion of the second check code (ECC2) and a portion of the second extended data (RFU2) that were serially input.

8. The memory (100) according to any one of claims 2 to 7, characterized in that The memory (100) further includes a data transmission circuit (30) connected between the data verification circuit (20) and the input / output circuit (40). The data transmission circuit (30) is configured to transmit the first read data (R_Data1) or the second read data (R_Data2) from the data verification circuit (20) to the input / output circuit (40), and to transmit the first write data (W_Data1) or the second write data (W_Data2) from the input / output circuit (40) to the data verification circuit (20).

9. The memory (100) according to claim 8, characterized by The input / output circuit (40) includes a data conversion circuit (42), which includes a plurality of data conversion sub-circuits (421) corresponding one-to-one with the plurality of data ports (50); each of the data conversion sub-circuits (421) includes a serializer (422) and a parallelizer (423); The serializer (422), coupled to the data transmission circuit (30) and the corresponding data port (50), is configured to, when the mode selection signal indicates that the memory (100) is in on-chip verification mode, serialize a portion of the stored data (DATA) received from the data transmission circuit (30) according to a first burst length and generate a first output data string (Out_s1) output to the corresponding data port (50), and when the mode selection signal indicates that the memory (100) is in off-chip verification mode, serialize a portion of the stored data (DATA) and a portion of the first checksum (ECC1) received from the data transmission circuit (30) according to a second burst length and generate a second output data string (Out_s1) output to the corresponding data port (50). The parallelizer (423), coupled to the data transmission circuit (30) and the corresponding data port (50), is configured to, when the mode selection signal indicates that the memory (100) is in on-chip verification mode, process the first input data string (In_s1) received from the corresponding data port (50) in parallel and generate a portion of the first write data (W_Data1) output to the data transmission circuit (30). When the mode selection signal indicates that the memory (100) is in off-chip verification mode, process the second input data string (In_s2) received from the corresponding data port (50) in parallel and generate a portion of the second write data (W_Data2) output to the data transmission circuit (30).

10. The memory (100) according to claim 9, characterized by The input / output circuit (40) further includes: a first-in-first-out register (41) and a data driver (43); The first-in-first-out register (41) is coupled between the data transmission circuit (30) and the data conversion circuit (42) and is configured to receive and cache the first read data (R_Data1) or the second read data (R_Data2) from the data transmission circuit (30) during a read operation of the memory (100), and to receive and cache the first write data (W_Data1) or the second write data (W_Data2) after parallel processing from the data conversion circuit (42) during a write operation of the memory (100). The data driver (43), coupled between the data conversion circuit (42) and the plurality of data ports (50), is configured to receive, during a read operation of the memory (100), a plurality of serialized first output data strings (Out_s1) or a plurality of second output data strings (Out_s2) from the data conversion circuit (42) and drive them to the plurality of data ports (50), and during a write operation of the memory (100), receive, through the plurality of data ports (50), a corresponding plurality of first input data strings (In_s1) or a plurality of second input data strings (In_s2) and drive them to the data conversion circuit (42).

11. The memory (100) according to any one of claims 8-10, characterized by The data transmission circuit (30) includes: a storage data transmission bus (31) and a check code transmission bus (32); The storage data transmission bus (31) is configured to transmit the stored data (DATA) or the data to be stored (data); the check code transmission bus (32) is configured to receive the mode selection signal, and transmit the first check code (ECC1) or the second check code (ECC2) when the mode selection signal indicates that the memory (100) is in off-chip check mode, and be disabled when the mode selection signal indicates that the memory (100) is in on-chip check mode.

12. The memory (100) according to any one of claims 8 to 11, characterized in that The data transmission circuit (30) further includes: an extended data bus (33); The extended data bus (33) is configured to receive the mode selection signal and the extended function indication signal, and to transmit the first extended data (RFU1) or the second extended data (RFU2) when the mode selection signal indicates that the memory (100) is in the off-chip verification mode and the extended function indication signal indicates that the memory (100) is in the extended function enabled state; otherwise, the extended data bus (33) is disabled.

13. A storage device (300) comprising at least one storage channel, each of the storage channels comprising a plurality of memories (100) as claimed in any one of claims 1 to 12.

14. A method of operating a memory (100), characterized by, The memory (100) includes multiple data storage blocks (11) and a checksum storage block (12), and the operation method includes: The stored data (DATA) and the corresponding first check code (ECC1) are obtained from the plurality of data storage blocks (11) and the check code storage block (12), respectively; The verification mode of the memory (100) is determined in response to the mode selection signal; When the mode selection signal indicates that the memory (100) is in on-chip verification mode, the stored data (DATA) is verified according to the first check code (ECC1), and the verified stored data (DATA) is output as the first read data (R_Data1); or When the mode selection signal indicates that the memory (100) is in off-chip verification mode, the stored data (DATA) and the first check code (ECC1) are directly output as the second read data (R_Data2); The first check code (ECC1) in the second read data (R_Data2) is used by the external memory (100) controller to perform a data verification operation on the stored data (DATA).

15. The method of operation of claim 14, wherein, The operation method further includes: After serializing the first read data (R_Data1) or the second read data (R_Data2), it is output from the memory (100) through multiple data ports (50); When the memory (100) is in the on-chip verification mode, the first read data (R_Data1) is serialized according to the first burst length to generate multiple first output data strings (Out_s1) output through multiple data ports (50); when the memory (100) is in the off-chip verification mode, the second read data (R_Data2) is serialized according to the second burst length to generate multiple second output data strings (Out_s2) output through multiple data ports (50); the first burst length is less than the second burst length.

16. The method of claim 14, wherein, After directly outputting the stored data (DATA) and the first check code (ECC1) as the second read data (R_Data2), the operation method further includes: determining whether the expansion function of the memory (100) is enabled; If the memory (100) is in the off-chip verification mode and the expansion function is enabled, the second read data (R_Data2) and the first extended data (RFU1) are serialized according to the third burst length to generate multiple third output data strings output through multiple data ports (50); The third output data string includes a portion of the serially output stored data (DATA), a portion of the first checksum (ECC1), and a portion of the first extended data (RFU1).

17. A method of operating a memory (100), characterized by, The operation method includes: The verification mode of the memory (100) is determined in response to the mode selection signal; When the mode selection signal indicates that the memory (100) is in on-chip verification mode, the first input data string (In_s1) of the first burst length received from each data port (50) is parallelized and then the first write data (W_Data1) is generated. When the mode selection signal indicates that the memory (100) is in off-chip verification mode, the second input data string (In_s2) of the second burst length received from each of the data ports (50) is parallelized and then the second write data (W_Data2) is generated. Wherein, the second burst length is greater than the first burst length, the first write data (W_Data1) includes the data to be stored (data), the second write data (W_Data2) includes the data to be stored (data) and the corresponding second check code (ECC2), the first input data string (In_s1) includes a portion of the data to be stored (data) that was serially input, and the second input data string (In_s2) includes a portion of the data to be stored (data) that was serially input and a portion of the second check code (ECC2).

18. The method of operation of claim 17, wherein, The memory (100) includes multiple data storage blocks (11) and a checksum storage block (12), and the operation method further includes: When the memory (100) is in the on-chip verification mode, the data to be stored in the first written data (W_Data1) is encoded to generate a corresponding third verification code, and the data to be stored and the third verification code are stored in the plurality of data storage blocks (11) and the verification code storage block (12) respectively. When the memory (100) is in the off-chip verification mode, the data to be stored (data) and the second verification code (ECC2) in the received second write data (W_Data2) are respectively stored in the plurality of data storage blocks (11) and the verification code storage block (12).

19. The method of claim 17, wherein, When the mode selection signal indicates that the memory (100) is in the off-chip verification mode, the operation method further includes: Determine whether the expansion function of the memory (100) is enabled; If the memory (100) is in the off-chip verification mode and the expansion function is enabled, the third input data string (In_s3) of the third burst length received from each of the data ports (50) will be parallelized and then the third write data (W_Data3) will be generated. The third write data (W_Data3) includes the data to be stored (data), the corresponding second check code (ECC2), and the second extended data (RFU2), and the third input data string (In_s3) includes a portion of the data to be stored (data), a portion of the second check code (ECC2), and a portion of the second extended data (RFU2) that were serially input.

Images