System and method for controlling bus port of server, and non-volatile computer-readable storage medium and electronic device

Abstract

Provided in the embodiments of the present application are a system and method for controlling a bus port of a server, and a storage medium and an electronic device. The system for controlling a bus port of a server comprises: a processor, which is configured to receive a first instruction in a POST stage of a BIOS of a server, so as to control the on and off of a bus port of the server; a baseboard management controller, which is configured to receive a second instruction in a startup stage and an operation stage of the server, so as to control the on and off of the bus port; and a controller, which is respectively connected to the processor and the baseboard management controller, wherein the controller is configured to control the on and off of the bus port in the POST stage on the basis of a first control signal generated by means of the first instruction, or control the on and off of the bus port in the startup stage and the operation stage on the basis of a second control signal generated by means of the second instruction.

Description

Control systems and methods for server bus ports, non-volatile computer-readable storage media and electronic devices

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411440093.X, filed on October 15, 2024, entitled "Control System and Method for Server Bus Port, Storage Medium and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computers, and in particular to a control system and method for a server bus port, a non-volatile computer-readable storage medium, and an electronic device. Background Technology

[0004] Servers are equipped with bus ports, such as USB ports. USB ports are widely used for connecting mice, keyboards, storage devices, and various peripherals due to their plug-and-play nature, high transmission speed, and compatibility with multiple devices. However, despite the widespread popularity of USB ports' convenience, they also bring a series of security and management issues.

[0005] In existing server systems, users can flexibly control the opening and closing of USB ports (Universal Serial Bus ports) through relevant commands of the xHCI (eXtensible Host Controller Interface) driver under the server's OS. However, this method has poor security. For example, in server architectures where USB ports are expanded through PCIe to USB (PCIe to USB, PCIe (Peripheral Component Interconnect Express)) conversion chips, the opening and closing of USB ports is controlled by the BIOS (Basic Input / Output System) during the server's operating system startup phase. After entering the OS (Operating System), the USB ports can still be opened and closed via commands. Summary of the Invention

[0006] This application provides a control system and method for a server bus port, a non-volatile computer-readable storage medium, and an electronic device to at least solve the problem of low security in the control of server bus ports in related technologies.

[0007] According to one embodiment of this application, a control system for a server bus port is provided, comprising: a processor configured to receive a first instruction during the POST (Power-On Self-Test) phase of the server's BIOS to control the opening and closing of the server's bus port; a baseboard management controller configured to receive a second instruction during the server's startup and operation phases to control the opening and closing of the bus port; and a controller connected to both the processor and the baseboard management controller, configured to control the opening and closing of the bus port by generating a first control signal based on the first instruction during the POST phase, or by generating a second control signal based on the second instruction during the startup and operation phases.

[0008] In one exemplary embodiment, the system includes: an expansion device connected to both a processor and a controller, configured to receive a third instruction initiated by the processor in response to a first instruction during a POST phase and generate a third control signal from the first control signal; or, to receive a fourth instruction initiated by the processor during a startup phase and a runtime phase and generate a third control signal. The controller is configured to extract the third control signal generated by the expansion device, wherein a high-level third control signal is generated when the control bus port is open, and a low-level third control signal is generated when the control bus port is closed.

[0009] In one exemplary embodiment, the controller is configured to perform an AND operation on the first control signal during the POST phase to obtain a first target control signal, thereby controlling the opening and closing of the bus port. Specifically, when the first target control signal is high, the bus port is controlled to open, and when the first target control signal is low, the bus port is controlled to close.

[0010] In one exemplary embodiment, the system includes a conversion chip connected to both the processor and the controller. The conversion chip is configured to receive a first target control signal initiated by the controller in response to a first control signal during the POST phase, thereby controlling the opening and closing of the bus port.

[0011] In one exemplary embodiment, the conversion chip has a second pin and a bus pin. The second pin is connected to the controller, and the bus pin is connected to the bus port. The conversion chip is configured to receive a first target control signal through the second pin and control the opening and closing of the bus port through the bus port.

[0012] In one exemplary embodiment, the controller is configured to perform an AND operation on the second control signal during the startup and operation phases to obtain a second target control signal, thereby controlling the opening and closing of the bus port. Specifically, when the second target control signal is high, the bus port is controlled to open, and when the second target control signal is low, the bus port is controlled to close.

[0013] In one exemplary embodiment, the system includes a load switch connected to both the processor and a bus port. The load switch is configured to receive a second target control signal initiated by the controller in response to a second control signal during startup and operation phases. The system controls the opening and closing of the bus port by controlling the load switch to open and close. Specifically, when the second target control signal is low, the load switch is closed to close the bus port, and when the second target control signal is high, the load switch is opened to open the bus port.

[0014] In one exemplary embodiment, the system includes: a load switch connected to a controller, the controller being configured to, during the POST phase, extract a fourth control signal generated by the load switch and, in response to a fifth instruction initiated by a received baseboard management controller, generate a high-level fifth control signal, wherein the first control signal includes the fourth control signal and the fifth control signal, the fourth control signal being high-level when the control bus port is open and low-level when the control bus port is closed; or, the controller is configured to, during the startup and operation phases, extract the high-level fourth control signal generated by the load switch and, in response to a fifth instruction initiated by a received baseboard management controller, generate a fifth control signal, wherein the fifth control signal being high-level when the control bus port is open and low-level when the control bus port is closed.

[0015] In one exemplary embodiment, the system includes a conversion chip and an expansion device. The conversion chip is connected to a processor and a controller, respectively. The expansion device is connected to the processor and the controller, respectively. The controller is configured to, during the POST phase, extract a sixth control signal from the second control signals generated by the expansion device in response to a received sixth instruction initiated by the processor; and generate a high-level seventh control signal from the second control signals in response to a received seventh instruction initiated by the baseboard management controller, wherein the sixth control signal is high when the control bus port is open and low when the control bus port is closed; or, the controller is configured to, during the startup and operation phases, extract a high-level sixth control signal from the second control signals generated by the expansion device in response to a received sixth instruction initiated by the processor; and generate a seventh control signal from the second control signals in response to a received seventh instruction initiated by the baseboard management controller, wherein the seventh control signal is high when the control bus port is open and low when the control bus port is closed.

[0016] In one exemplary embodiment, a first pin is deployed on the conversion chip and connected to the controller. The conversion chip is configured to receive an eighth instruction initiated by the processor in response to a first instruction during the startup and operation phases of the server, and to generate an eighth control signal in the second control signal. The controller is configured to extract the eighth control signal through the first pin during the startup and operation phases of the server.

[0017] According to another embodiment of this application, a method for controlling a server bus port is provided. A processor, a controller, and a bus port are deployed sequentially on the server. The server is configured to allow control of the bus port's operating state via the operating system during the processor's operating system runtime. The method is applied to a first controller, which is connected to both the processor and the controller. The method includes: during the operating system startup process, detecting the startup running state of the bus port within the operating system, wherein the startup running state indicates the bus port's operating state at operating system startup; generating a target control signal matching the startup running state based on the startup running state, wherein the target control signal adjusts the connection state of the bus port's power supply line on the controller to match the startup running state; and sending the target control signal to the controller, wherein the controller is configured to control the bus port's power supply line according to the target control signal.

[0018] In one exemplary embodiment, generating a target control signal that matches the startup running state based on the startup running state includes: detecting an initial control signal set that matches the startup running state based on the startup running state; and generating the target control signal based on the initial control signal set.

[0019] In one exemplary embodiment, the control device includes a load switch and a conversion chip. A first controller is connected to both the load switch and the conversion chip. An expansion device is also deployed in the server. The first controller is connected to the expansion device. Based on the startup running state, the controller detects an initial control signal set matching the startup running state, including: extracting a first initial control signal corresponding to the startup running state output by the expansion device, detecting a second initial control signal corresponding to the startup running state, and extracting a third initial control signal corresponding to the startup running state output by the conversion chip. The initial control signal set includes a first control signal set, which includes a first initial control signal, a second initial control signal, and a third initial control signal. Alternatively, the controller extracts a fourth initial control signal corresponding to the startup running state output by the expansion device, detects a fifth initial control signal corresponding to the startup running state, and extracts a sixth initial control signal corresponding to the startup running state output by the load switch. The initial control signal set includes a second control signal set, which includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal.

[0020] In one exemplary embodiment, the server further deploys a second controller, which is connected to the first controller. The first controller detects a second initial control signal corresponding to a startup running state, including: when the startup running state includes the detected running state set by the second controller, receiving a first signal generation instruction initiated by the second controller, wherein the first signal generation instruction instructs the first controller to generate a second initial control signal corresponding to a second signal parameter, the second signal parameter being a signal parameter corresponding to the startup running state set by the second controller, the second signal parameter indicating that the second initial control signal is high when the startup running state indicates that the bus port is open, and low when the startup running state indicates that the bus port is closed; and responding to the first signal generation instruction, generating the second initial control signal corresponding to the second signal parameter.

[0021] In an exemplary embodiment, the expansion device is connected to the processor. Before extracting the fourth initial control signal corresponding to the startup running state output by the expansion device, the method further includes: if the startup running state is extracted from a startup item, extracting a third signal parameter corresponding to the startup running state by the processor, wherein the third signal parameter is used to indicate that the fourth initial control signal is high when the startup running state indicates that the bus port is open, and to indicate that the fourth initial control signal is low when the startup running state indicates that the bus port is closed; and controlling the expansion device to generate and output the fourth initial control signal corresponding to the third signal parameter by the processor through a first bus between the processor and the expansion device.

[0022] In one exemplary embodiment, the server further deploys a second controller, which is connected to the first controller. The first controller detects a fifth initial control signal corresponding to the startup running state, including: when the startup running state includes the detected running state set by the second controller, receiving a second signal generation instruction initiated by the second controller, wherein the second signal generation instruction instructs the first controller to generate a fifth initial control signal corresponding to a fourth signal parameter. The fourth signal parameter is a signal parameter corresponding to the startup running state set by the second controller, which indicates that the fifth initial control signal is high when the startup running state indicates that the bus port is open, and low when the startup running state indicates that the bus port is closed; and responding to the second signal generation instruction, generating the fifth initial control signal corresponding to the fourth signal parameter.

[0023] In one exemplary embodiment, generating a target control signal based on an initial set of control signals includes: performing a bitwise AND operation on a first set of control signals to obtain a first reference control signal when the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup and operation state, wherein the initial set of control signals includes the first set of control signals and the target control signal includes the first reference control signal; and performing a bitwise AND operation on a second set of control signals to obtain a second reference control signal when the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup and operation state, wherein the initial set of control signals includes the second set of control signals and the target control signal includes the second reference control signal.

[0024] In one exemplary embodiment, performing a bitwise AND operation on a first set of control signals to obtain a first reference control signal includes: When the startup state is when the first set of control signals, extracted from a startup item, includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup state is enabled, performing a bitwise AND operation on the first initial control signal, the second initial control signal, and the third initial control signal to obtain a first reference control signal, wherein when the startup state is enabled, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is high; when the startup state is when the first set of control signals, extracted from a startup item, includes a first initial control signal, the second initial control signal, and the third initial control signal, and the startup state is disabled, performing a bitwise AND operation on the first initial control signal, the second initial control signal, and the third initial control signal to obtain a first reference control signal, wherein when the startup state is disabled, the first initial control signal is set to a low level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is high. When the first initial control signal is low, and the second initial control signal is low, the first control signal set includes the first initial control signal, the second initial control signal, and the third initial control signal, and the bus port is open, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. When the bus port is open, the first initial control signal is set to high, the second initial control signal is set to high, the third initial control signal is set to high, and the first reference control signal is high. When the second initial control signal is low, and the first control signal set includes the first initial control signal, the second initial control signal, and the third initial control signal, and the bus port is closed, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. When the bus port is closed, the first initial control signal is set to high, the second initial control signal is set to low, the third initial control signal is set to high, and the first reference control signal is low.

[0025] In one exemplary embodiment, performing a bitwise AND operation on the second set of control signals to obtain a second reference control signal includes: when the startup running state is extracted from the startup item, and the second set of control signals includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup running state is that the bus port is open, performing a bitwise AND operation on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup running state is that the bus port is open, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, and the sixth initial control signal is set to a high level. The sixth initial control signal is set to high level, and the second reference control signal is also set to high level. During startup, when the second control signal set includes the fourth, fifth, and sixth initial control signals (extracted from the startup item) and the bus port is closed, a bitwise AND operation is performed on the fourth, fifth, and sixth initial control signals to obtain the second reference control signal. Specifically, when the bus port is closed during startup, the fourth initial control signal is set to low level, the fifth initial control signal is set to high level, and the sixth initial control signal is set to high level. The second reference control signal is low. In the startup running state, where the second controller's operating state is detected, the second control signal set includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal, and the bus port is open, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the bus port is open during startup, the fourth initial control signal is set to high, the fifth initial control signal is set to high, the sixth initial control signal is set to high, and the second reference control signal is high. In the startup running state, where the second controller's operating state is detected, the second control signal set includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal, and the bus port is closed, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the bus port is closed during startup, the fourth initial control signal is set to high, the fifth initial control signal is set to low, the sixth initial control signal is set to high, and the second reference control signal is high.

[0026] In one exemplary embodiment, the controller includes a conversion chip and a bus connector. The conversion chip has a second pin and a bus pin, and the bus connector has a bus port. The bus pin is connected to the bus connector. A first controller is connected to the second pin and sends a target control signal to the controller, including: initiating the target control signal to the second pin. The conversion chip is configured to connect and maintain the power supply line between the bus pin and the bus port when the target control signal is high, and to disconnect the power supply line between the bus pin and the bus port when the target control signal is low. Alternatively, the controller includes a load switch. The first controller is connected to the load switch and sends a target control signal to the controller, including: initiating the target control signal to the load switch. The load switch is configured to connect and maintain the power supply line between the load switch and the bus port when the target control signal is high, and to disconnect the power supply line between the load switch and the bus port when the target control signal is low.

[0027] According to another embodiment of this application, a control device for a server bus port is also provided. A processor, a controller, and a bus port are deployed sequentially on the server. The server is configured to allow control of the bus port's operating state via the operating system during the processor's operating system runtime. The device is configured as a first controller, connected to both the processor and the controller. The device includes: a first detection module, configured to detect the bus port's startup running state in the operating system during the operating system startup process, wherein the startup running state indicates the bus port's running state at operating system startup; a generation module, configured to generate a target control signal matching the startup running state, wherein the target control signal adjusts the connection state of the bus port's power supply line on the controller to match the startup running state; and a sending module, configured to send the target control signal to the controller, wherein the controller is configured to control the bus port's power supply line according to the target control signal.

[0028] According to yet another embodiment of this application, a non-volatile computer-readable storage medium is also provided, wherein a computer program is stored in the non-volatile computer-readable storage medium, and the computer program is configured to execute the steps in any of the above method embodiments when it is run.

[0029] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein a computer program is stored in the memory and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0030] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0031] Through this application, the server's processor can control the opening and closing of the server's bus port during the POST phase, and the server's baseboard management controller can control the opening and closing of the bus port during the server's startup and operation phases. In this way, the controller can control the power supply line of the bus port according to the corresponding control signal, thereby realizing the control of the opening and closing of the bus port. For example, when the power supply circuit of the bus port is disconnected, the bus port can no longer be opened by software-level commands. Therefore, the problem of low security in the control of the server bus port can be solved, thereby improving the security of the control of the server bus port. Attached Figure Description

[0032] Figure 1 is a schematic diagram of an optional server bus port control system according to an embodiment of this application;

[0033] Figure 2 is a schematic diagram of an optional server bus port control system according to an embodiment of this application;

[0034] Figure 3 is a hardware structure block diagram of a server device according to an embodiment of the present application of a server bus port control method;

[0035] Figure 4 is a flowchart of a server bus port control method according to an embodiment of this application;

[0036] Figure 5 is a schematic diagram of an optional target control signal generation according to an embodiment of this application;

[0037] Figure 6 is a structural block diagram of a control device for a server bus port according to an embodiment of this application. Detailed Implementation

[0038] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0039] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0040] The terms used in the embodiments of this application are explained as follows:

[0041] USB: Universal Serial Bus;

[0042] OC: Over Current;

[0043] BIOS: Basic Input Output System.

[0044] This embodiment provides a server bus port control system. Figure 1 is a schematic diagram of an optional server bus port control system according to an embodiment of this application. As shown in Figure 1, the server bus port control system includes: a processor configured to receive a first instruction during the POST phase of the server's BIOS to control the opening and closing of the server's bus port; a baseboard management controller configured to receive a second instruction during the server's startup and operation phases to control the opening and closing of the bus port; and a controller connected to the processor and the baseboard management controller, respectively. The controller is configured to control the opening and closing of the bus port by generating a first control signal according to the first instruction during the POST phase, or to control the opening and closing of the bus port by generating a second control signal according to the second instruction during the startup and operation phases.

[0045] Optionally, in this embodiment, the server may, but is not limited to, have a bus port deployed. The bus port may, but is not limited to, be configured to connect to a bus device. When the bus port is open, the bus device connected to the bus port may, but is not limited to, be allowed to interact with the server. For example, the bus device connected to the bus port may be configured to allow read or write operations on the data stored on the server. When the bus port is closed, the bus device connected to the bus port may be configured not to interact with the server.

[0046] As an alternative example, the bus port may include, but is not limited to, ports that conform to the target bus protocol. For example, the target bus protocol may include, but is not limited to, the USB (Universal Serial Bus) protocol or the PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) protocol, etc., and the bus port may include, but is not limited to, USB ports or PCIe interfaces, etc.

[0047] Optionally, in this embodiment, the processor may include, but is not limited to, a CPU (Central Processing Unit) or GPU (Graphics Processing Unit) deployed on the server. Taking the processor as an example, the processor may receive the first instruction during the POST (Power-On Self Test) phase of the server's BIOS (Basic Input Output System) to control the opening and closing of the bus port.

[0048] Optionally, in this embodiment, the controller may include, but is not limited to, a CPLD (Complex Programmable Logic Device) or FPGA (Field Programmable Gate Array) deployed in the server, and the controller and the baseboard management controller may be connected via, but are not limited to, a bus.

[0049] In one exemplary embodiment, the system further includes: an expansion device connected to both the processor and the controller, configured to receive a third instruction initiated by the processor in response to a first instruction during the POST phase and generate a third control signal from the first control signal; or, to receive a fourth instruction initiated by the processor during the startup and operation phases and generate a third control signal. The controller is configured to extract the third control signal generated by the expansion device, wherein a high-level third control signal is generated when the control bus port is open, and a low-level third control signal is generated when the control bus port is closed.

[0050] Optionally, in this embodiment, the expansion device may include, but is not limited to, devices configured to expand the input and output interfaces of the server. For example, the expansion device may include, but is not limited to, IO (Input / Output) Expanders.

[0051] In one exemplary embodiment, the system further includes: a controller configured to perform an AND operation on a first control signal during the POST phase to obtain a first target control signal, thereby controlling the opening and closing of a bus port, wherein the bus port is opened when the first target control signal is high, and the bus port is closed when the first target control signal is low.

[0052] Optionally, in this embodiment, when all control signals in the first control signal are at a high level, an AND operation is performed on the first control signal to obtain a first target control signal at a high level; when at least one control signal in the first control signal is at a low level, an AND operation is performed on the first control signal to obtain a first target control signal at a low level.

[0053] It should be noted that the high and low levels involved in the embodiments of this application are logic levels. For example, the level state when the voltage is higher than the voltage threshold may be, but is not limited to, a high level, and the level state when the voltage is lower than the voltage threshold may be, but is not limited to, a low level.

[0054] In one exemplary embodiment, the system further includes a conversion chip connected to both the processor and the controller. The conversion chip is configured to receive a first target control signal initiated by the controller in response to a first control signal during the POST phase, thereby controlling the opening and closing of the bus port.

[0055] Optionally, in this embodiment, the conversion chip may, but is not limited to, be configured to convert the server's first bus port to a second bus port, wherein the first bus port supports a first bus protocol, the second bus port supports a second bus protocol, and the first bus protocol and the second bus protocol are different. For example, the conversion chip includes a PCIe to USB chip, the first bus protocol may, but is not limited to, include the PCIE protocol, and the second bus protocol may, but is not limited to, include the USB port.

[0056] In one exemplary embodiment, the conversion chip has a second pin and a bus pin. The second pin is connected to the controller, and the bus pin is connected to the bus port. The conversion chip is configured to receive a first target control signal through the second pin and control the opening and closing of the bus port through the bus port.

[0057] Optionally, in this embodiment, the second pin may include, but is not limited to, an OC pin, and the bus pin may include, but is not limited to, a USB pin (or a pin that supports other bus protocols; this application does not impose any restrictions on this). The conversion chip may receive a first target control signal through the second pin. When the first target control signal is high, the chip connects and maintains the connection between the corresponding bus port and the conversion chip. For example, the conversion chip turns on and maintains the signal and power of the bus port, and the bus port is turned on. When the first target control signal is low, the chip disconnects the connection between the bus port and the conversion chip. For example, the conversion chip disconnects the signal and power of the bus port, and the bus port is turned off.

[0058] In one exemplary embodiment, the controller is configured to perform an AND operation on the second control signal during the startup and operation phases to obtain a second target control signal, thereby controlling the opening and closing of the bus port. Specifically, when the second target control signal is high, the bus port is controlled to open, and when the second target control signal is low, the bus port is controlled to close.

[0059] Optionally, in this embodiment, when all control signals in the second control signal are at a high level, an AND operation is performed on the second control signal to obtain a high-level second target control signal; when at least one control signal in the second control signal is at a low level, an AND operation is performed on the second control signal to obtain a low-level second target control signal.

[0060] In one exemplary embodiment, the system includes a load switch connected to both the processor and a bus port. The load switch is configured to receive a second target control signal initiated by the controller in response to a second control signal during startup and operation phases. The system controls the opening and closing of the bus port by controlling the load switch to open and close. Specifically, when the second target control signal is low, the load switch is closed to close the bus port, and when the second target control signal is high, the load switch is opened to open the bus port.

[0061] Optionally, in this embodiment, the server may, but is not limited to, be equipped with a load switch and a power supply. The power supply may, but is not limited to, be connected to the bus port through the load switch. When the second target control signal is low, the load switch may, but is not limited to, be turned off, disconnecting the connection between the power supply and the bus port, and the bus port will appear to be off. When the second target control signal is high, the load switch may, but is not limited to, be turned on, connecting and maintaining the connection between the power supply and the bus port, and the bus port will appear to be on.

[0062] In one exemplary embodiment, the system includes: a load switch connected to a controller, the controller being configured to, during the POST phase, extract a fourth control signal generated by the load switch and, in response to a fifth instruction initiated by a received baseboard management controller, generate a high-level fifth control signal, wherein the first control signal includes the fourth control signal and the fifth control signal, the fourth control signal being high-level when the control bus port is open and low-level when the control bus port is closed; or, the controller is configured to, during the startup and operation phases, extract the high-level fourth control signal generated by the load switch and, in response to a fifth instruction initiated by a received baseboard management controller, generate a fifth control signal, wherein the fifth control signal being high-level when the control bus port is open and low-level when the control bus port is closed.

[0063] Optionally, in this embodiment, when it is desired to control the bus port to be turned on, the controller generates a high-level fifth control signal; when it is desired to control the bus port to be turned off, the controller generates a low-level fifth control signal. The high and low levels can be represented by corresponding identifiers, for example, 1 represents a high level and 0 represents a low level.

[0064] In one exemplary embodiment, the system includes a conversion chip and an expansion device. The conversion chip is connected to a processor and a controller, respectively. The expansion device is connected to the processor and the controller, respectively. The controller is configured to, during the POST phase, extract a sixth control signal from the second control signals generated by the expansion device in response to a received sixth instruction initiated by the processor; and generate a high-level seventh control signal from the second control signals in response to a received seventh instruction initiated by the baseboard management controller, wherein the sixth control signal is high when the control bus port is open and low when the control bus port is closed; or, the controller is configured to, during the startup and operation phases, extract a high-level sixth control signal from the second control signals generated by the expansion device in response to a received sixth instruction initiated by the processor; and generate a seventh control signal from the second control signals in response to a received seventh instruction initiated by the baseboard management controller, wherein the seventh control signal is high when the control bus port is open and low when the control bus port is closed.

[0065] Optionally, in this embodiment, the expansion device and the processor may be connected via a bus, but are not limited to this connection. It is understood that the processor sends a sixth instruction to the expansion device via the bus, and the expansion device responds to the received sixth instruction by generating a high-level sixth control signal. As an optional example, the sixth instruction carries the signal parameters of the sixth control signal, such as a high level or a low level.

[0066] In one exemplary embodiment, the following is included: a first pin is deployed on a conversion chip, the first pin is connected to a controller, the conversion chip is configured to receive an eighth instruction initiated by a processor in response to a first instruction during the startup phase and the running phase of the server, generate an eighth control signal in a second control signal, and the controller is configured to extract the eighth control signal through the first pin during the startup phase and the running phase of the server.

[0067] Optionally, in this embodiment, the conversion chip may, but is not limited to, have a first pin deployed on it. For example, the first pin may, but is not limited to, include a PPON pin. In such a case, the controller can extract the eighth control signal generated by the conversion chip through the PPON pin. As an optional example, the eighth control signal may, but is not limited to, be a high level.

[0068] To better understand the control system for the server bus port in the embodiments of this application, the control system for the server bus port in the embodiments of this application will be explained and described below with reference to optional embodiments, which may be applied to, but are not limited to, the embodiments of this application.

[0069] Figure 2 is a schematic diagram of an optional server bus port control system according to an embodiment of this application. As shown in Figure 2, the explanation and description can be based on, but is not limited to, a server architecture with a USB port extended through a PCIe to USB conversion chip, a bus port including a USB port, a first controller including a CPLD, a second controller including a BMC (Baseboard Management Controller), a processor including a CPU, a conversion chip including a PCIe to USB chip, an expansion device including an IO Expander, and a load switch including a Load Switch. The BMC and BIOS can respectively control the USB port power supply and OC pin to turn the USB port on and off.

[0070] The server has CPU0 and CPU1 deployed, connected to each other. CPU0 acts as the main processor. The processor may include, but is not limited to, CPU0. CPU0 is connected to both the IO Expander and the PCIe to USB chip. The PCIe to USB chip has OC pins (equivalent to the second pin), PPON pins (equivalent to PPON pins), and USB pins (equivalent to bus pins). The USB pins connect to a USB Connector, which has a bus port. The USB Connector may, but is not limited to, connect to a power supply (e.g., P5V_STBY) via a load switch. The CPLD is connected to the IO Expander, BMC, and the PCIe to USB chip. Users can, but are not limited to, configure the USB port to be enabled or disabled via the network on the BMC.

[0071] Figure 2 illustrates only one USB port design. The CPU expands the USB ports via a PCIe to USB converter chip. The converter chip connects to the CPU upstream via PCIe and outputs USB 2.0 and USB 3.0 signals downstream to the USB connector, thus expanding the USB interface. Through this USB connector, the CPU system can communicate with USB devices such as USB flash drives, mice, and keyboards. The PCIe to USB converter chip has two pins, PPON and OC, for functional control of this USB port. The PPON pin is configured to control the power supply to the USB port. After the converter chip powers on and loads its code, it pulls this pin high to control the power supply to the USB port. In this embodiment, the PPON pin is connected to the CPLD via the FM_CTL_PPON signal. The OC pin is configured to monitor the overcurrent status of the USB port. When an overcurrent occurs at the USB port, the PCIe to... The USB conversion chip will shut down the corresponding USB port and report an exception to the CPU system. In this embodiment, the CPLD is connected to the OC pin via the FM_OC_N signal; the BMC is connected to the CPLD via the BMC_PLD_SMBUS bus signal, and transmits relevant information about controlling the USB port to the CPLD via the bus; the CPU is connected to the IO Expander via the HOST_SMBUS bus signal, and uses the IO Expander to expand IO. The expanded FM_BIOS_PPON signal is connected to the CPLD to control the power supply of the USB port, and the expanded FM_BIOS_OC_N signal is used to actively trigger the overcurrent state of the USB port; the system-side P5V_STBY is connected to the USB connector via a load switch to power the USB device. The CPLD is connected to the load switch via the FM_LS_EN signal and is set to control the opening and closing of the load switch, i.e., the USB power supply. At the same time, the CPLD monitors whether the load switch is in an overcurrent state via the FM_LS_OC_N signal.

[0072] Internally, the CPLD identifies the PPON_EN and OC_N signals issued by the BMC by parsing the I2C signals. The PPON signal is ANDed with the FM_BIOS_PPON and FM_CTL_PPON signals and output to the FM_LS_EN signal; that is, if any one of these signals is low, FM_LS_EN is low, and the load switch is off. The OC_N signal is ANDed with the FM_LS_OC_N and FM_BIOS_OC_N signals and output to the FM_OC_N signal; that is, if any one of these signals is low, FM_OC_N is low, triggering an overcurrent state on this port, shutting down the USB port signal, and reporting an overcurrent exception to the CPU system. Through this embodiment, the BMC and BIOS can control the USB port power control port to turn on and off, or they can force the corresponding port to detect an overcurrent exception state through the OC pin of the PCIe to USB converter chip to control the USB port's on / off state.

[0073] The methods and embodiments provided in this application can be executed in a server device or a similar computing device. Taking a server device as an example, FIG3 is a hardware structure block diagram of a server device for a server bus port control method according to an embodiment of this application. As shown in FIG3, the server device may include one or more (only one is shown in FIG3) processors 302 (processors 302 may include, but are not limited to, microprocessors MCUs or programmable logic devices FPGAs, etc.) and a memory 304 configured to store data. The server device may also include a transmission device 306 configured for communication and an input / output device 308. Those skilled in the art will understand that the structure shown in FIG3 is only illustrative and does not limit the structure of the server device. For example, the server device may also include more or fewer components than shown in FIG3, or have a different configuration than shown in FIG3.

[0074] The memory 304 may be configured to store computer programs, such as application software programs and modules, like the computer program corresponding to the server bus port control method in this embodiment. The processor 302 executes various functional applications and data processing by running the computer program stored in the memory 304, thereby implementing the aforementioned method. The memory 304 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 304 may further include memory remotely located relative to the processor 302, and these remote memories can be connected to the server device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0075] The transmission device 306 is configured to receive or transmit data via a network. Optional examples of the network may include a wireless network provided by the communication provider of the server device. In one example, the transmission device 306 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 306 may be a Radio Frequency (RF) module, configured to communicate wirelessly with the Internet.

[0076] This embodiment provides a method for controlling a server bus port. A processor, a controller, and a bus port are deployed on the server in sequence. The server is configured to allow control of the bus port's operating state via the operating system while the processor's operating system is running. The method is applied to a first controller, which is connected to both the processor and the controller. Figure 4 is a flowchart of the server bus port control method according to an embodiment of this application. As shown in Figure 4, the process includes the following steps:

[0077] Step S402: During the operating system startup process, the startup running status of the bus port in the operating system is detected, wherein the startup running status is used to indicate the running status of the bus port when the operating system starts.

[0078] Step S404: Based on the startup and operation status, generate a target control signal that matches the startup and operation status. The target control signal is used to adjust the connection status of the power supply line of the bus port on the controller to match the startup and operation status.

[0079] Step S406: Send a target control signal to the controller, wherein the controller is configured to control the power supply line of the bus port according to the target control signal.

[0080] Through the above steps, the server's processor can control the opening and closing of the server's bus port during the POST phase, and the server's baseboard management controller can control the opening and closing of the bus port during the server's startup and operation phases. In this way, the controller can control the power supply line of the bus port according to the corresponding control signal, thereby controlling the opening and closing of the bus port. For example, when the power supply circuit of the bus port is disconnected, the bus port cannot be opened by software commands. Therefore, the problem of low security in the control of the server bus port can be solved, thereby improving the security of the control of the server bus port.

[0081] In the technical solution provided in step S202 above, the startup running state can be, but is not limited to, used to indicate the running state of the bus port during the startup of the server's operating system. For example, the bus port is set to open or closed during the startup of the operating system.

[0082] Optionally, in this embodiment, the startup and running status of the bus port in the operating system can be detected in the following way, but is not limited to: detecting the startup and running status of the bus port from the BIOS options of the server, wherein the startup and running status of the bus port is recorded in the BIOS options and the startup and running status of the bus port recorded in the BIOS options is set to allow adjustment.

[0083] Optionally, in this embodiment, the startup and running status of the bus port in the operating system can be detected in the following ways, but not limited to: detecting the startup and running status of the bus port set by the second controller in the server. It should be noted that the second controller can also adjust the startup and running status of the bus port at any time during the server's operation.

[0084] In the technical solution provided in step S204 above, the connection state of the power supply line may include, but is not limited to, disconnecting the power supply line between the bus port and the controller, or connecting the power supply line between the bus port and the controller. It can be understood that the power supply line may include, but is not limited to, the power supply line that is physically connected between the bus port and the controller.

[0085] In one exemplary embodiment, a target control signal matching the startup running state can be generated based on the startup running state in the following manner, but not limited to: detecting an initial control signal set matching the startup running state based on the startup running state; and generating the target control signal based on the initial control signal set.

[0086] As an optional example, the controller includes a load switch and a conversion chip. Based on the startup operating state, it detects an initial set of control signals matching the startup operating state, including: when a target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup operating state, detecting a first set of control signals from the load switch matching the startup operating state, wherein the initial set of control signals includes the first set of control signals; and when a target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup operating state, detecting a second set of control signals from the conversion chip matching the startup operating state, wherein the initial set of control signals includes the second set of control signals.

[0087] Optionally, in this embodiment, the first set of control signals may include, but is not limited to, control signals for controlling the connection status of the power supply lines of the bus port on the load switch, and the second set of control signals may include, but is not limited to, control signals for controlling the connection status of the power supply lines of the bus port on the conversion chip.

[0088] Figure 5 is a schematic diagram of an optional target control signal generation according to an embodiment of the present application. As shown in Figure 5, the start-up running states allowed by the bus port may include, but are not limited to, start-up running states 1 to 3. In this case, if the user desires start-up running state 2, the initial control signal set matching start-up running state 2 may be detected, and the target control signal may be generated based on the initial control signal set.

[0089] In one exemplary embodiment, the control device includes a load switch and a conversion chip. A first controller is connected to both the load switch and the conversion chip. An expansion device is also deployed in the server. The first controller is connected to the expansion device. Based on the startup and operation state, the controller detects an initial control signal set that matches the startup and operation state: extracts a first initial control signal corresponding to the startup and operation state output by the expansion device, detects a second initial control signal corresponding to the startup and operation state, and extracts a third initial control signal corresponding to the startup and operation state output by the conversion chip. The initial control signal set includes a first control signal set, which includes a first initial control signal, a second initial control signal, and a third initial control signal. Alternatively, the controller extracts a fourth initial control signal corresponding to the startup and operation state output by the expansion device, detects a fifth initial control signal corresponding to the startup and operation state, and extracts a sixth initial control signal corresponding to the startup and operation state output by the load switch. The initial control signal set includes a second control signal set, which includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal.

[0090] As an optional example, the expansion device is connected to the processor. Before extracting the first initial control signal corresponding to the startup running state output by the expansion device, the method further includes: if the startup running state is extracted from the startup item, extracting the first signal parameter corresponding to the startup running state by the processor; controlling the expansion device to generate and output the first control signal corresponding to the first signal parameter by the processor through the first bus between the processor and the expansion device, wherein the first signal parameter is used to indicate that the first control signal is high level when the startup running state is used to indicate that the bus port is open, and to indicate that the first control signal is low level when the startup running state is used to indicate that the bus port is closed.

[0091] As an optional example, a target pin is deployed on the conversion chip, and a first controller is connected to the first pin to extract the third initial control signal corresponding to the start-up running state output by the conversion chip, including: extracting the third initial control signal through the target pin.

[0092] In an exemplary embodiment, the server further deploys a second controller, which is connected to the first controller. The first controller detects a second initial control signal corresponding to a startup running state. When the startup running state includes the detected running state set by the second controller, the server receives a first signal generation instruction initiated by the second controller. This first signal generation instruction instructs the first controller to generate a second initial control signal corresponding to a second signal parameter. The second signal parameter is a signal parameter corresponding to the startup running state set by the second controller. This second signal parameter indicates that the second initial control signal is high when the startup running state indicates that the bus port is open, and low when the startup running state indicates that the bus port is closed. The server then generates the second initial control signal corresponding to the second signal parameter in response to the first signal generation instruction.

[0093] Optionally, in this embodiment, the first controller and the second controller may be connected via a bus, but not limited to. For example, the second controller may include, but is not limited to, a baseboard management controller (BMC), and the first controller may include, but is not limited to, a CPLD or FPGA deployed in the server. Taking the second controller including a BMC and the first controller including a CPLD as an example, the CPLD may, but is not limited to, generate a second initial control signal in response to the received first signal generation command.

[0094] In one exemplary embodiment, the expansion device is connected to the processor. Before extracting the fourth initial control signal corresponding to the startup running state output by the expansion device: if the startup running state is extracted from the startup item, the processor extracts the third signal parameter corresponding to the startup running state. The third signal parameter is used to indicate that the fourth initial control signal is high when the startup running state indicates that the bus port is open, and to indicate that the fourth initial control signal is low when the startup running state indicates that the bus port is closed. The processor controls the expansion device to generate and output the fourth initial control signal corresponding to the third signal parameter through the first bus between the expansion device and the processor.

[0095] Optionally, in this embodiment, the expansion device may include, but is not limited to, devices configured to expand the input and output interfaces of the server. For example, the expansion device may include, but is not limited to, IO (Input / Output) Expanders.

[0096] Optionally, in this embodiment, the startup and running status of the bus port recorded in the startup item is set to be adjustable. It is understood that the startup and running status of the bus port recorded in the startup item may change dynamically. For example, the startup and running status of the bus port recorded in the startup item may be changed from on to off. After the startup and running status of the bus port recorded in the startup item is adjusted, it may take effect after restarting the server, thereby resetting the startup and running status of the bus port.

[0097] Optionally, in this embodiment, the processor can control the expansion device to generate and output the fourth initial control signal corresponding to the third signal parameter via a first bus between the processor and the expansion device in the following manner: the processor sends a target instruction to the expansion device via the first bus, wherein the target instruction is used to instruct the expansion device to generate the fourth control signal corresponding to the third signal parameter, and the expansion device is configured to generate the fourth control signal corresponding to the third signal parameter in response to the received target instruction.

[0098] In one exemplary embodiment, the server further deploys a second controller, which is connected to the first controller. The first controller detects a fifth initial control signal corresponding to the startup running state. When the startup running state includes the detected running state set by the second controller, the server receives a second signal generation instruction initiated by the second controller. This second signal generation instruction instructs the first controller to generate a fifth initial control signal corresponding to a fourth signal parameter. The fourth signal parameter is a signal parameter corresponding to the startup running state set by the second controller. This fourth signal parameter indicates that the fifth initial control signal is high when the startup running state indicates that the bus port is open, and low when the startup running state indicates that the bus port is closed. The server then generates the fifth initial control signal corresponding to the fourth signal parameter in response to the second signal generation instruction.

[0099] Optionally, in this embodiment, the second signal generation instruction may, but is not limited to, carry a fourth signal generation parameter, or the fourth signal generation parameter may be obtained from a control method and a signal generation parameter that have a corresponding relationship. The control method includes a method of controlling the startup and running state. For example, the control method may, but is not limited to, controlling the startup and running state of the bus port through the second controller, or controlling the startup and running state of the bus port by adjusting the startup item, etc.

[0100] In one exemplary embodiment, a target control signal may be generated based on an initial set of control signals in the following manner, but not limited to: when the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup and operation state, an AND operation is performed on the first set of control signals to obtain a first reference control signal, wherein the initial set of control signals includes the first set of control signals and the target control signal includes the first reference control signal; when the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup and operation state, an AND operation is performed on the second set of control signals to obtain a second reference control signal, wherein the initial set of control signals includes the second set of control signals and the target control signal includes the second reference control signal.

[0101] Optionally, in this embodiment, the first reference control signal can be obtained by performing a bitwise AND operation on the first control signal set in the following manner, but not limited to: performing a bitwise AND operation on each control signal in the first control signal set to obtain the first reference control signal, wherein the first reference control signal obtained by performing a bitwise AND operation on the first control signal set is high when all control signals in the first control signal set are high; and the first reference control signal obtained by performing a bitwise AND operation on the first control signal set is low when at least one control signal in the first control signal set is low.

[0102] Optionally, in this embodiment, the second reference control signal can be obtained by performing a bitwise AND operation on the second control signal set in the following manner, but not limited to: performing a bitwise AND operation on each control signal in the second control signal set to obtain the second reference control signal, wherein the second reference control signal obtained by performing a bitwise AND operation on the second control signal set is high when all control signals in the second control signal set are high; and the second reference control signal obtained by performing a bitwise AND operation on the second control signal set is low when at least one control signal in the second control signal set is low.

[0103] In one exemplary embodiment, a first reference control signal can be obtained by performing a bitwise AND operation on the first set of control signals, but not limited to the following: When the startup state is when the first set of control signals, extracted from the startup item, includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup state is enabled, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. In the enabled startup state, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is high. Alternatively, when the startup state is when the first set of control signals, extracted from the startup item, includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup state is disabled, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. In the disabled startup state, the first initial control signal is set to a low level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is high. When the first initial control signal is low, and the first control signal set includes the first initial control signal, the second initial control signal, and the third initial control signal, and the bus port is open, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. Specifically, when the bus port is open, the first initial control signal is set to high, the second initial control signal is set to high, the third initial control signal is set to high, and the first reference control signal is high. When the first initial control signal is low, and the bus port is closed, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. Specifically, when the bus port is closed, the first initial control signal is set to high, the second initial control signal is set to low, the third initial control signal is set to high, and the first reference control signal is low.

[0104] Optionally, in this embodiment, the control method includes controlling the startup and operation state. For example, the control method may include, but is not limited to, controlling the startup and operation state of the bus port through a second controller, or controlling the startup and operation state of the bus port by adjusting the startup item. Under different control methods, the control signals included in the first control signal set on which the first reference control signal is based may include, but are not limited to, the same control signals. However, the signal parameters (e.g., high level or low level, etc.) of the control signals included in the first control signal set may be different. It is understood that for different control methods, the same control signals in the first control signal set may have different signal parameters. For example, signal A may be high level or low level under different control methods.

[0105] To better understand the server bus port control method in the embodiments of this application, the server bus port control method in the embodiments of this application will be explained and described below with reference to optional embodiments, which may be applicable to, but are not limited to, the embodiments of this application.

[0106] As an optional implementation, the enabling and disabling of bus ports can be controlled via the BMC or by modifying BIOS options. For example, by modifying BIOS options, the enabling and disabling of USB ports can be controlled by controlling the power on and off of the bus ports. It should be noted that after modifying the BIOS options, the settings must be saved and the system restarted for the USB ports to be enabled and disabled.

[0107] After the server system powers on, the PCIe to USB converter chip powers on and loads its code, which then pulls the FM_CTL_PPON signal (equivalent to the third initial control signal, or the eighth control signal) high and enables USB 2.0 and USB 3.0 signals. At this time, if the user does not perform any operation on the USB port through the BMC, the PPON_EN signal (equivalent to the second initial control signal, or the seventh control signal) and the OC_N signal (equivalent to the fifth initial control signal, or the fifth control signal) in the CPLD's internal logic are high by default and do not affect the opening and closing of the USB port.

[0108] If the USB port is enabled by default in the BIOS options (equivalent to boot options), during this POST loading process, the FM_BIOS_PPON signal (equivalent to the sixth control signal, or the first initial control signal) of the IO Expander is controlled high via the HOST_SMBUS bus of CPU0. The CPLD logic ANDs the PPON signal with the FM_BIOS_PPON signal and the FM_CTL_PPON signal (equivalent to the third initial control signal, or the eighth control signal). If the result is high, the output FM_LS_EN signal (equivalent to the first reference control signal, or the second target control signal) is high, the load switch is in the on state, and P5V_STBY (equivalent to power supply) outputs P5V_USB0 normally through the load switch. If devices such as mice, keyboards, and USB flash drives are plugged in, the device power supply is normal, and the USB signal can communicate normally, so the USB connector port appears to be on. After entering the OS, the FM_BIOS_PPON signal remains high, and the bus port of the USB connector remains on.

[0109] If you change the BIOS options to disable the USB port, save the options, and restart the system, during this POST loading process, the BIOS will control the FM_BIOS_PPON signal of the IO Expander to be low via the HOST_SMBUS bus on CPU0. The CPLD logic will AND the PPON signal with the FM_BIOS_PPON signal and the FM_CTL_PPON signal. If the result is low, the output FM_LS_EN signal will be low, the load switch will be in the off state, and P5V_STBY will not be able to output P5V_USB0 normally through the load switch. If devices such as mice, keyboards, and USB flash drives are plugged in, the USB signal can communicate normally, but there is no power to the devices, so the USB connector port appears to be closed. After entering the OS, the FM_BIOS_PPON signal will still remain low, and the bus port of the USB connector will remain in the closed state.

[0110] As an alternative implementation, for example, users can directly control the USB port's on and off status by controlling the power supply of the bus port through the BMC. Once the port status modification operation is issued under the control of the BMC, the USB port can be turned on and off immediately.

[0111] After the server system powers on, the PCIe to USB conversion chip powers on and loads its code, which then pulls the FM_CTL_PPON signal high and enables USB 2.0 and USB 3.0 signals. At this time, the BIOS is set to enable the USB port by default, so the FM_BIOS_PPON signal and the FM_BIOS_OC_N signal (equivalent to the third control signal, or the fourth initial control signal) are high and do not affect the opening or closing of the USB port.

[0112] If the user defaults to enabling the USB port under the BMC, the BMC communicates with the CPLD via BMC_PLM_SMBUS to control the PPON_EN signal to be high. The CPLD logic ANDs the PPON_EN signal with the FM_BIOS_PPON signal and the FM_CTL_PPON signal, outputting the FM_LS_EN signal high. The load switch is in the ON state, and P5V_STBY outputs P5V_USB0 normally through the load switch. If devices such as mice, keyboards, and USB flash drives are plugged in, the devices are powered normally, and the USB signal can communicate normally, so the USB connector port appears to be ON. If the user modifies the BMC to disable the USB port, the BMC immediately controls the PPON_EN signal to be low through BMC_PLM_SMBUS communication with the CPLD. The CPLD logic ANDs the PPON_EN signal with the FM_BIOS_PPON signal and the FM_CTL_PPON signal, outputting the FM_LS_EN signal low. The load switch changes to the OFF state, and P5V_STBY cannot output P5V_USB0 through the load switch. The USB device power is off, so the USB connector port appears to be OFF.

[0113] In this way, the power status of the USB port can be controlled through BIOS options and BMC to enable and disable the USB port. The control logic of the USB port by BMC and BIOS is integrated into the CPLD, and the two different control logics of BIOS options and BMC are implemented at the same time.

[0114] In one exemplary embodiment, a second reference control signal can be obtained by performing a bitwise AND operation on the second set of control signals, but not limited to, in the following manner: When the startup running state is such that the second set of control signals is extracted from the startup item, includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the bus port is enabled, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the bus port is enabled during startup, the fourth initial control signal is set to a high level, and the fifth initial control signal is set to a low level. When the second initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is set to a high level. During startup, when the second control signal set includes the fourth, fifth, and sixth initial control signals (extracted from the startup item) and the bus port is closed, a bitwise AND operation is performed on the fourth, fifth, and sixth initial control signals to obtain the second reference control signal. Specifically, when the bus port is closed during startup, the fourth initial control signal is set to a low level, the fifth initial control signal is set to a high level, and the sixth initial control signal is set to a high level. When the second reference control signal is high and the second initial control signal is low, and the second initial control signal is low, the startup operation state is the operating state set by the detected second controller, and the second control signal set includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal, and the startup operation state is when the bus port is open, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the startup operation state is when the bus port is open, the fourth initial control signal is set to high, the fifth initial control signal is set to high, and the sixth initial control signal is set to high. The control signal is high level; in the startup running state, the second controller's set running state is detected, and the second control signal set includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal, and the bus port is closed in the startup running state, an AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. In the startup running state, when the bus port is closed, the fourth initial control signal is set to high level, the fifth initial control signal is set to low level, the sixth initial control signal is set to high level, and the second reference control signal is high level.

[0115] Optionally, in this embodiment, the control method includes controlling the startup and operation state. For example, the control method may include, but is not limited to, controlling the startup and operation state of the bus port through a second controller, or controlling the startup and operation state of the bus port by adjusting the startup item. Under different control methods, the control signals included in the second control signal set on which the second reference control signal is based may include, but are not limited to, the same control signals. However, the signal parameters (e.g., high level or low level, etc.) of the control signals included in the second control signal set may be different. It is understood that for different control methods, the same control signals in the second control signal set may have different signal parameters. For example, signal A may be high level or low level under different control methods.

[0116] To better understand the server bus port control method in the embodiments of this application, the server bus port control method in the embodiments of this application will be explained and described below with reference to optional embodiments, which may be applicable to, but are not limited to, the embodiments of this application.

[0117] The enabling and disabling of bus ports can be controlled, but is not limited to, through the BMC or by modifying BIOS options. As an optional implementation, users can enable and disable USB ports via an OC overcurrent signal by modifying BIOS options; however, after modifying the BIOS options, the settings must be saved and the system restarted for the USB ports to be enabled and disabled.

[0118] After the server system powers on, the PCIe to USB converter chip powers on and loads its code, which then pulls the FM_CTL_PPON signal high and enables USB 2.0 and USB 3.0 signals. At this time, if the user does not perform any operation on the USB port through the BMC, the PPON_EN and OC_N signals in the CPLD's internal logic are high by default and do not affect the opening and closing of the USB port. The BIOS does not perform any additional control on the FM_BIOS_PPON signal and sets it to high by default (e.g., high level). Therefore, the CPLD outputs the FM_LS_EN signal high, the load switch is on, and P5V_STBY outputs P5V_USB0 normally through the load switch.

[0119] If the USB port is enabled by default, during this POST loading process, the FM_BIOS_OC_N signal of the IO Expander is controlled high via the HOST_SMBUS bus of CPU0, and the load switch outputs power normally. In the absence of OC, the output FM_LS_OC_N signal is high. The CPLD logic ANDs the OC_N signal with the FM_BIOS_OC_N signal and the FM_LS_OC_N signal (equivalent to the sixth initial control signal or the fourth control signal). If the result is high, the output FM_OC_N signal (equivalent to the first target control signal or the second reference control signal) is high, and the conversion chip is in normal working condition. The USB 2.0 signal and USB 3.0 signal output from the corresponding port are normal. If devices such as mice, keyboards, and USB flash drives are plugged in, the device power is normal, and the USB signal can communicate normally, so the USB connector port appears to be enabled. After entering the OS, the FM_BIOS_OC_N signal remains high, and the USB connector port remains enabled.

[0120] If the BIOS option is changed to disable the USB port, and the option is saved and the system is restarted, during this POST loading process, the FM_BIOS_OC_N signal of the IO Expander is controlled low via the HOST_SMBUS bus on CPU0. The load switch outputs power normally. When the load switch does not experience overcurrent OC, the output FM_LS_OC_N signal is high. The CPLD logic ANDs the OC_N signal with the FM_BIOS_OC_N signal and the FM_LS_OC_N signal. If the result is low, the output FM_OC_N signal is low, and the conversion chip enters the overcurrent abnormal working state, shutting down the relevant signals and power of the corresponding port. Thus, the USB connector port appears to be closed. After entering the OS, the FM_BIOS_OC_N signal remains low, and the USB connector port remains closed.

[0121] In the technical solution provided in step S206 above, the controller can, but is not limited to, control the power supply line of the bus port according to the target control signal in the following ways: when the target control signal is low, the power supply line of the control bus port is disconnected; when the target control signal is low, the power supply line of the control bus port is connected and maintained.

[0122] As an alternative implementation, users can directly enable and disable the USB port via the OC overcurrent signal through the BMC. Once the port status modification operation is issued under the BMC, the USB port can be enabled and disabled immediately.

[0123] After the server system powers on, the PCIe to USB conversion chip powers on and loads its code, which then controls the FM_CTL_PPON signal to go high and enables the USB 2.0 and USB 3.0 signals. At this time, the BIOS is set to enable the USB port by default, so the FM_BIOS_PPON and FM_BIOS_OC_N signals are high and do not affect the opening or closing of the USB port.

[0124] If the user defaults to enabling the USB port under the BMC, the BMC communicates with the CPLD via BMC_PLM_SMBUS to control OC_N to be high. The CPLD logic ANDs OC_N with the FM_BIOS_OC_N and FM_LS_OC_N signals, outputting the FM_OC_N signal high. The conversion chip is in normal working condition, and the USB 2.0 and USB 3.0 signals output from the corresponding port are normal. If devices such as mice, keyboards, and USB flash drives are plugged in, and the device power is normal, the USB signal can communicate normally, so the USB connector port appears to be enabled. If the user modifies the BMC to disable the USB port, the BMC communicates with the CPLD via BMC_PLM_SMBUS to immediately pull the OC_N signal low (e.g., low level). The CPLD logic ANDs the OC_N signal with the FM_BIOS_OC_N and FM_LS_OC_N signals, outputting the FM_OC_N signal low. The conversion chip then enters an overcurrent abnormal working state, shutting down the relevant signals and power of the corresponding port, so the USB connector port appears to be disabled.

[0125] In this way, it is possible to enable and disable the USB port by controlling the overcurrent signal status of the USB port through BIOS options and BMC, and to consolidate the control logic of the USB port by BMC and BIOS into CPLD, while implementing two different control logics of BIOS options and BMC.

[0126] In one exemplary embodiment, the controller includes a conversion chip and a bus connector. The conversion chip has a second pin and a bus pin, and the bus connector has a bus port. The bus pin is connected to the bus connector. A first controller is connected to the second pin and sends a target control signal to the controller. The target control signal is initiated to the second pin, wherein the conversion chip is configured to connect and maintain the power supply line between the bus pin and the bus port when the target control signal is high, and to disconnect the power supply line between the bus pin and the bus port when the target control signal is low. Alternatively, the controller includes a load switch, and the first controller is connected to the load switch. Sending a target control signal to the controller includes initiating a target control signal to the load switch, wherein the load switch is configured to connect and maintain the power supply line between the load switch and the bus port when the target control signal is high, and to disconnect the power supply line between the load switch and the bus port when the target control signal is low.

[0127] Optionally, in this embodiment, when the target control signal is low, the power supply lines between the bus pin and the bus port can be disconnected, for example, the conversion chip can turn off the signal and power supply of the bus port, and the bus port will appear to be off. When the target control signal is high, the power supply lines between the bus pin and the bus port can be connected and maintained, for example, the conversion chip can turn on and maintain the signal and power supply of the bus port, and the bus port will appear to be on.

[0128] Optionally, in this embodiment, the server is also equipped with a power supply. The power supply is connected to the bus port via a load switch. The power supply can be disconnected from the bus port by controlling the load switch to turn off when the target control signal is low, thereby turning off the bus port. Alternatively, the power supply can be connected and maintained between the power supply and the bus port by controlling the load switch to turn on when the target control signal is low, thereby turning on the bus port.

[0129] It is understood that, through the embodiments of this application, users can enable and disable the USB port by modifying BIOS options (equivalent to boot options) and controlling the power supply and OC overcurrent signal separately under the BMC. To ensure USB safety, the USB port will be in a closed state after being disabled by any method. In addition, for the two control methods of power supply and OC overcurrent signal, users can choose to use a single method to enable and disable the USB port, or they can disable the power supply and OC overcurrent signal together to completely disable the power supply and signal, thus ensuring that the USB port is completely disabled. The open and closed states of the USB port are shown in Table 1.

[0130] Table 1

[0131] In Table 1, “x” represents any state.

[0132] Through the embodiments of this application, for the USB port extended through the PCIe to USB conversion chip, the USB port can be turned on and off by setting BIOS options. Moreover, the state set in the BIOS cannot be modified by software under the OS, which improves system security. The USB port can be turned on and off through the BMC, and the change of USB port state takes effect immediately without the need for additional restart operations.

[0133] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0134] This embodiment also provides a server bus port control device, which is configured to implement the above embodiments and optional implementations; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0135] Figure 6 is a structural block diagram of a server bus port control device according to an embodiment of this application. As shown in Figure 6, the device includes a processor, a controller, and a bus port deployed sequentially on a server. The server is configured to allow control of the bus port's operating state via the operating system during processor operation. The device is applied to a first controller, which is connected to both the processor and the controller. The device includes:

[0136] The first detection module 602 is configured to detect the startup and running status of the bus port in the operating system during the operating system startup process, wherein the startup and running status is used to indicate the running status of the bus port when the operating system starts.

[0137] The generation module 604 is configured to generate a target control signal that matches the startup and operation state based on the startup and operation state. The target control signal is used to adjust the connection state of the power supply line of the bus port on the controller to match the startup and operation state.

[0138] The transmitting module 606 is configured to send a target control signal to the controller, wherein the controller is configured to control the power supply line of the bus port according to the target control signal.

[0139] With the above-described device, the server's processor can control the opening and closing of the server's bus port during the POST phase, and the server's baseboard management controller can control the opening and closing of the bus port during the server's startup and operation phases. In this way, the controller can control the power supply line of the bus port according to the corresponding control signal, thereby controlling the opening and closing of the bus port. For example, when the power supply circuit of the bus port is disconnected, the bus port cannot be opened by software commands. Therefore, the problem of low security in the control of the server bus port can be solved, thereby improving the security of the control of the server bus port.

[0140] In one exemplary embodiment, the generation module includes:

[0141] The detection unit is configured to detect a set of initial control signals that match the startup and operation state.

[0142] The generation unit is configured to generate the target control signal based on the initial set of control signals.

[0143] In one exemplary embodiment, the detection unit is configured as follows:

[0144] Extract the first initial control signal corresponding to the startup and operation state output by the expansion device, detect the second initial control signal corresponding to the startup and operation state, and extract the third initial control signal corresponding to the startup and operation state output by the conversion chip. The initial control signal set includes the first control signal set, which in turn includes the first initial control signal, the second initial control signal, and the third initial control signal; or,

[0145] Extract the fourth initial control signal corresponding to the start-up state output by the extended device, detect the fifth initial control signal corresponding to the start-up state, and extract the sixth initial control signal corresponding to the start-up state output by the load switch. The initial control signal set includes the second control signal set, which includes the fourth, fifth, and sixth initial control signals.

[0146] In one exemplary embodiment, the server is further deployed with a second controller, the first controller being connected to the second controller, and the detection unit is configured as follows:

[0147] When the startup running state includes the running state set by the detected second controller, a first signal generation instruction initiated by the second controller is received. The first signal generation instruction is used to instruct the first controller to generate a second initial control signal corresponding to the second signal parameter. The second signal parameter is the signal parameter corresponding to the startup running state set by the second controller. The second signal parameter is used to indicate that the second initial control signal is high level when the startup running state is used to indicate that the bus port is open, and to indicate that the second initial control signal is low level when the startup running state is used to indicate that the bus port is closed.

[0148] In response to the first signal generation command, a second initial control signal corresponding to the second signal parameters is generated.

[0149] In one exemplary embodiment, the apparatus further includes:

[0150] The extraction module is configured to connect the expansion device to the processor. Before extracting the fourth initial control signal corresponding to the startup running state output by the expansion device, when the startup running state is extracted from the startup item, the processor extracts the third signal parameter corresponding to the startup running state. The third signal parameter is used to indicate that the fourth initial control signal is high when the startup running state is used to indicate that the bus port is open, and to indicate that the fourth initial control signal is low when the startup running state is used to indicate that the bus port is closed.

[0151] The output module is configured to control the expansion device via a first bus between the processor and the expansion device to generate and output a fourth initial control signal corresponding to the third signal parameter.

[0152] In one exemplary embodiment, the server is further deployed with a second controller, the first controller being connected to the second controller, and the detection unit is configured as follows:

[0153] In the startup and operation state, including the detected operation state set by the second controller, a second signal generation instruction initiated by the second controller is received. The second signal generation instruction is used to instruct the first controller to generate a fifth initial control signal corresponding to a fourth signal parameter. The fourth signal parameter is a signal parameter corresponding to the startup and operation state set by the second controller. The fourth signal parameter is used to indicate that the fifth initial control signal is high level when the startup and operation state indicates that the bus port is open, and to indicate that the fifth initial control signal is low level when the startup and operation state indicates that the bus port is closed.

[0154] In response to the second signal generation command, a fifth initial control signal corresponding to the fourth signal parameter is generated.

[0155] In one exemplary embodiment, the generation unit is configured as follows:

[0156] When the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the start-up operation state, an AND operation is performed on the first control signal set to obtain the first reference control signal, wherein the initial control signal set includes the first control signal set and the target control signal includes the first reference control signal;

[0157] When the target control signal is used to adjust the connection state of the power supply line on the bus port on the conversion chip to match the startup and operation state, a bitwise AND operation is performed on the second control signal set to obtain the second reference control signal. The initial control signal set includes the second control signal set, and the target control signal includes the second reference control signal.

[0158] In one exemplary embodiment, the generation unit is configured as follows:

[0159] When the startup running state is in the case that the first control signal set is extracted from the startup item, includes the first initial control signal, the second initial control signal, and the third initial control signal, and the startup running state is enabled, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. In the case that the startup running state is enabled, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is set to a high level.

[0160] When the startup running state is when the first control signal set includes the first initial control signal, the second initial control signal, and the third initial control signal extracted from the startup item, and the startup running state is closed, an AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. In the case where the startup running state is closed, the first initial control signal is set to low level, the second initial control signal is set to high level, the third initial control signal is set to high level, and the first reference control signal is low level.

[0161] When the startup running state is the running state set by the detected second controller, and the first control signal set includes the first initial control signal, the second initial control signal, and the third initial control signal, and the startup running state is that the bus port is open, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. When the startup running state is that the bus port is open, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a high level.

[0162] When the startup running state is the running state set by the detected second controller, and the first control signal set includes the first initial control signal, the second initial control signal, and the third initial control signal, and the startup running state is that the bus port is closed, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. In the case that the startup running state is that the bus port is closed, the first initial control signal is set to a high level, the second initial control signal is set to a low level, the third initial control signal is set to a high level, and the first reference control signal is a low level.

[0163] In one exemplary embodiment, the generation unit is further configured as follows:

[0164] In the startup running state, where the second control signal set includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal, and the bus port is open, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. In the startup running state where the bus port is open, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is set to a high level.

[0165] In the startup running state, where the second control signal set includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal, and the bus port is closed, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. In the startup running state where the bus port is closed, the fourth initial control signal is set to low level, the fifth initial control signal is set to high level, the sixth initial control signal is set to high level, and the second reference control signal is low level.

[0166] When the startup running state is the running state set by the detected second controller, and the second control signal set includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal, and the startup running state is that the bus port is open, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. When the startup running state is that the bus port is open, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level.

[0167] When the startup running state is the running state set by the detected second controller, and the second control signal set includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal, and the startup running state is that the bus port is closed, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the startup running state is that the bus port is closed, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a low level, the sixth initial control signal is set to a high level, and the second reference control signal is set to a high level.

[0168] In one exemplary embodiment, the controller includes a conversion chip and a bus connector. The conversion chip has a second pin and a bus pin, the bus connector has a bus port, the bus pin is connected to the bus connector, a first controller is connected to the second pin, and the transmitting module includes:

[0169] The first initiating unit is configured to send a target control signal to the second pin. The conversion chip is configured to connect and maintain the power supply line between the bus pin and the bus port when the target control signal is high, and to disconnect the power supply line between the bus pin and the bus port when the target control signal is low; or...

[0170] The control device includes a load switch, a first controller connected to the load switch, and a transmitting module including a second initiating unit configured to initiate a target control signal to the load switch, wherein the load switch is configured to connect the power supply line between the load switch and the bus port and maintain the power supply line of the bus port when the target control signal is high, and the load switch is configured to disconnect the power supply line between the load switch and the bus port when the target control signal is low.

[0171] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0172] Embodiments of this application also provide a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0173] In one exemplary embodiment, the aforementioned non-volatile computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0174] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0175] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0176] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0177] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0178] Embodiments of this application also provide a computer program that includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps in any of the above method embodiments.

[0179] The optional examples in this embodiment can refer to the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0180] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0181] The above are merely optional embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A control system for a server bus port, Its features are, include: The processor is configured to receive a first instruction during the Power-On Self-Test (POST) phase of the server's Basic Input / Output System (BIOS) to control the opening and closing of the server's bus ports; The baseboard management controller is configured to receive a second instruction during the server's startup and operation phases to control the opening and closing of the bus port. The controller is connected to both the processor and the baseboard management controller. The controller is configured to control the opening and closing of the bus port by generating a first control signal according to the first instruction during the POST phase, or to control the opening and closing of the bus port by generating a second control signal according to the second instruction during the startup phase and the running phase.

2. The system according to claim 1, characterized in that, includes: An expansion device is connected to both the processor and the controller. The expansion device is configured to receive a third instruction initiated by the processor in response to the first instruction during the POST phase and generate a third control signal from the first control signal; or, during the startup phase and the running phase, receive a fourth instruction initiated by the processor and generate the third control signal. The controller is configured to extract the third control signal generated by the expansion device, wherein a high-level third control signal is generated when the bus port is controlled to be open, and a low-level third control signal is generated when the bus port is controlled to be closed.

3. The system according to claim 1, characterized in that, includes: The controller is configured to perform an AND operation on the first control signal during the POST phase to obtain a first target control signal, thereby controlling the opening and closing of the bus port. Specifically, when the first target control signal is high, the bus port is controlled to open; when the first target control signal is low, the bus port is controlled to close.

4. The system according to claim 1, characterized in that, comprising: A conversion chip is connected to both the processor and the controller. The conversion chip is configured to receive a first target control signal initiated by the controller in response to the first control signal during the POST phase, thereby controlling the opening and closing of the bus port.

5. The system according to claim 4, characterized in that, comprising: The conversion chip has a second pin and a bus pin. The second pin is connected to the controller, and the bus pin is connected to the bus port. The conversion chip is configured to receive the first target control signal through the second pin and to control the opening and closing of the bus port through the bus port.

6. The system according to claim 1, characterized in that, comprising: The controller is configured to perform an AND operation on the second control signal during the startup phase and the operation phase to obtain a second target control signal, thereby controlling the opening and closing of the bus port. Specifically, when the second target control signal is high, the bus port is controlled to open; when the second target control signal is low, the bus port is controlled to close.

7. The system according to claim 1, characterized in that, includes: A load switch is connected to both the processor and the bus port. The load switch is configured to receive a second target control signal initiated by the controller in response to the second control signal during the startup phase and the operation phase. By controlling the opening and closing of the load switch, the opening and closing of the bus port can be achieved. Specifically, when the second target control signal is low, the load switch is controlled to close, thereby closing the bus port; when the second target control signal is high, the load switch is controlled to open, thereby opening the bus port.

8. The system according to claim 1, characterized in that, comprising: A load switch, connected to the controller, is configured to, during the POST phase, extract a fourth control signal generated by the load switch and, in response to a received fifth instruction initiated by the baseboard management controller, generate a high-level fifth control signal. The first control signal includes the fourth and fifth control signals. When the bus port is controlled to be open, the fourth control signal is high; when the bus port is controlled to be closed, the fourth control signal is low, or... The controller is configured to extract the high-level fourth control signal generated by the load switch during the startup phase and the operation phase, and to generate the fifth control signal in response to a fifth instruction initiated by the received baseboard management controller, wherein the fifth control signal is high-level when the bus port is controlled to be turned on, and low-level when the bus port is controlled to be turned off.

9. The system of claim 1, Its features are, The system includes a conversion chip and an expansion device. The conversion chip is connected to both the processor and the controller. The expansion device is also connected to both the processor and the controller. The controller is configured to, during the POST phase, extract a sixth control signal from the second control signal generated by the expansion device in response to a received sixth instruction initiated by the processor; and generate a high-level seventh control signal from the second control signal in response to a received seventh instruction initiated by the baseboard management controller. The sixth control signal is high when the bus port is controlled to be open, and low when the bus port is controlled to be closed. Alternatively... The controller is configured to, during the startup and operation phases, extract a high-level sixth control signal from the second control signal generated by the extended device in response to a received sixth instruction initiated by the processor; and generate a seventh control signal from the second control signal in response to a received seventh instruction initiated by the baseboard management controller, wherein the seventh control signal is high-level when the bus port is controlled to be turned on, and low-level when the bus port is controlled to be turned off.

10. The system according to claim 1, characterized in that, comprising: The conversion chip has a first pin, which is connected to the controller. The conversion chip is configured to receive an eighth instruction initiated by the processor in response to the first instruction during the startup and operation phases of the server, and generate an eighth control signal in the second control signal. The controller is configured to extract the eighth control signal through the first pin during the startup and operation phases of the server.

11. A method for controlling a server bus port, characterized in that, A server is configured to deploy a processor, a controller, and a bus port connected in sequence. The server is configured to allow control of the bus port's operating state via the operating system of the processor during runtime. The method is applied to a first controller, which is connected to both the processor and the controller. The method includes: During the startup process of the operating system, the startup running status of the bus port in the operating system is detected, wherein the startup running status is used to indicate the running status of the bus port when the operating system starts. Based on the startup and operation state, a target control signal matching the startup and operation state is generated, wherein the target control signal is used to adjust the connection state of the power supply line of the bus port on the controller to match the startup and operation state; The target control signal is sent to the controller, wherein the controller is configured to control the power supply line of the bus port according to the target control signal.

12. The method according to claim 11, characterized in that, The step of generating a target control signal matching the startup and operation state includes: Based on the startup and operation status, detect the set of initial control signals that match the startup and operation status; The target control signal is generated based on the initial set of control signals.

13. The method according to claim 12, characterized in that, The control device includes a load switch and a conversion chip. The first controller is connected to both the load switch and the conversion chip. The server also has an expansion device, and the first controller is connected to the expansion device. The step of detecting an initial control signal set matching the startup running state includes: extracting a first initial control signal corresponding to the startup running state output by the extended device, detecting a second initial control signal corresponding to the startup running state, and extracting a third initial control signal corresponding to the startup running state output by the conversion chip, wherein the initial control signal set includes a first control signal set, which includes the first initial control signal, the second initial control signal, and the third initial control signal; or, The fourth initial control signal corresponding to the startup and operation state output by the extended device is extracted, and the fifth initial control signal corresponding to the startup and operation state is detected. The sixth initial control signal corresponding to the startup and operation state output by the load switch is extracted. The initial control signal set includes a second control signal set, which includes the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal.

14. The method according to claim 13, characterized in that, The server is also equipped with a second controller, and the first controller is connected to the second controller. The detection of the second initial control signal corresponding to the startup and running state includes: When the startup running state includes the detected running state set by the second controller, a first signal generation instruction initiated by the second controller is received. The first signal generation instruction is used to instruct the first controller to generate a second initial control signal corresponding to a second signal parameter. The second signal parameter is a signal parameter corresponding to the startup running state set by the second controller. The second signal parameter is used to indicate that the second initial control signal is at a high level when the startup running state indicates that the bus port is open, and to indicate that the second initial control signal is at a low level when the startup running state indicates that the bus port is closed. In response to the first signal generation instruction, a second initial control signal corresponding to the second signal parameter is generated.

15. The method according to claim 13, characterized in that, The expansion device is connected to the processor. Before extracting the fourth initial control signal corresponding to the startup running state output by the expansion device, the method further includes: When the startup running state is extracted from the startup item, the processor extracts the third signal parameter corresponding to the startup running state. The third signal parameter is used to indicate that the fourth initial control signal is high when the startup running state indicates that the bus port is open, and to indicate that the fourth initial control signal is low when the startup running state indicates that the bus port is closed. The processor controls the expansion device to generate and output the fourth initial control signal corresponding to the third signal parameter via a first bus between the processor and the expansion device.

16. The method according to claim 13, characterized in that, The server is also equipped with a second controller, and the first controller is connected to the second controller. The detection of the fifth initial control signal corresponding to the startup and running state includes: When the startup running state includes the detected running state set by the second controller, a second signal generation instruction initiated by the second controller is received. The second signal generation instruction is used to instruct the first controller to generate a fifth initial control signal corresponding to a fourth signal parameter. The fourth signal parameter is a signal parameter corresponding to the startup running state set by the second controller. The fourth signal parameter is used to indicate that the fifth initial control signal is high when the startup running state indicates that the bus port is open, and to indicate that the fifth initial control signal is low when the startup running state indicates that the bus port is closed. In response to the second signal generation instruction, the fifth initial control signal corresponding to the fourth signal parameter is generated.

17. The method according to claim 12, characterized in that, The step of generating the target control signal based on the initial control signal set includes: When the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the start-up state, an AND operation is performed on the first control signal set to obtain a first reference control signal, wherein the initial control signal set includes the first control signal set, and the target control signal includes the first reference control signal; When the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup and operation state, an AND operation is performed on the second control signal set to obtain a second reference control signal, wherein the initial control signal set includes the second control signal set, and the target control signal includes the second reference control signal.

18. The method according to claim 17, characterized in that, The step of performing a bitwise AND operation on the first set of control signals to obtain a first reference control signal includes: In the startup running state, where the first control signal set extracted from the startup item includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup running state is enabled, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. Specifically, when the startup running state is enabled, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a high level. In the startup running state, where the first control signal set extracted from the startup item includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup running state is off, an AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. Specifically, when the startup running state is off, the first initial control signal is set to a low level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is set to a low level. When the startup running state is the running state set by the detected second controller, and the first control signal set includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup running state is when the bus port is open, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. Specifically, when the startup running state is when the bus port is open, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a high level. When the startup running state is the running state set by the detected second controller, and the first control signal set includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup running state is when the bus port is closed, a bitwise AND operation is performed on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal. Specifically, when the startup running state is when the bus port is closed, the first initial control signal is set to a high level, the second initial control signal is set to a low level, the third initial control signal is set to a high level, and the first reference control signal is set to a low level.

19. The method according to claim 17, characterized in that, The step of performing a bitwise AND operation on the second set of control signals to obtain a second reference control signal includes: In the startup running state, where the second control signal set extracted from the startup item includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup running state is characterized by the bus port being open, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the startup running state is characterized by the bus port being open, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is set to a high level. In the startup running state, where the second control signal set extracted from the startup item includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup running state is characterized by a bus port being closed, an AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the startup running state is characterized by a bus port being closed, the fourth initial control signal is set to a low level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is set to a low level. When the startup running state is the running state set by the detected second controller, and the second control signal set includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup running state is when the bus port is open, an AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the startup running state is when the bus port is open, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is set to a high level. When the startup running state is the detected running state set by the second controller, and the second control signal set includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup running state is when the bus port is closed, a bitwise AND operation is performed on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal. Specifically, when the startup running state is when the bus port is closed, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a low level, the sixth initial control signal is set to a high level, and the second reference control signal is also set to a high level.

20. The method according to claim 11, characterized in that, The controller includes a conversion chip and a bus connector. The conversion chip has a second pin and a bus pin. The bus connector has a bus port. The bus pin is connected to the bus connector. The first controller is connected to the second pin. Sending the target control signal to the controller includes: The target control signal is sent to the second pin, wherein the conversion chip is configured to connect and maintain the power supply line between the bus pin and the bus port when the target control signal is high, and to disconnect the power supply line between the bus pin and the bus port when the target control signal is low; or, The control device includes a load switch, and the first controller is connected to the load switch. Sending the target control signal to the control device includes: initiating the target control signal to the load switch, wherein the load switch is configured to connect the power supply line between the load switch and the bus port and maintain the power supply line of the bus port when the target control signal is high, and the load switch is configured to disconnect the power supply line between the load switch and the bus port when the target control signal is low.

21. A control device for a server bus port, characterized in that, A server is configured to deploy a processor, a controller, and a bus port connected in sequence. The server is configured to allow control of the bus port's operating status via the operating system of the processor during operation. The device is applied to a first controller, which is connected to both the processor and the controller. The device includes: The first detection module is configured to detect the startup and running status of the bus port in the operating system during the startup process of the operating system, wherein the startup and running status is used to indicate the running status of the bus port when the operating system starts. The generation module is configured to generate a target control signal that matches the startup running state based on the startup running state, wherein the target control signal is used to adjust the connection state of the power supply line of the bus port on the controller to match the startup running state; The transmitting module is configured to send the target control signal to the controller, wherein the controller is configured to control the power supply line of the bus port according to the target control signal.

22. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 11 to 20.

23. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 11 to 20.

24. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method described in any one of claims 11 to 20.

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