Successive approximation engine, frequency adjustment circuit and method for adjusting an output frequency

Abstract

The invention relates to a successive approximation (SA) engine (54) comprising: A first signal input (2); a second signal input (4); A reset signal output (6) as well as an second output (10); A bit counter (16); a register (14); the bit counter (16) and the register (14) being connected to the first signal input (2) and successive approximation (SA) comparator (12); wherein the SA comparator is connected with the second input (4) in order to count the edges of the second input signal within a predetermined period. The invention further relates to a circuit for adjusting an output frequency independence of an input frequency and a method for such an adjustment.

Description

[0001] 2024PF00610 1

[0002] SUCCESSIVE APPROXIMATION ENGINE , FREQUENCY ADJUSTMENT CIRCUIT AND METHOD FOR ADJUSTING AN OUTPUT FREQUENCY

[0003] DESCRIPTION

[0004] TECHNICAL FIELD

[0005] The invention relates to a successive approximation engine , a frequency adj ustment circuit and a method for adj usting an output frequency .

[0006] BACKGROUND

[0007] It is commonly known that it is necessary for some applications to adapt an output frequency to an input frequency . One of the commonly known systems is so called phase locked loop or phase lock loop ( PLL ) . Such PLL generates an output signal whose phase is fixed relative to the phase of an input signal . However, it is rather time consuming to adj ust the frequency with a PLL, i f the starting phase and frequency are rather di f ferent from each other . In systems , in particular with a limited power supply, it is desirable to speed up the adj ustment procedure .

[0008] SUMMARY

[0009] In accordance with an aspect of the invention a successive approximation ( SA) engine , is provided, the SA engine comprising : a first signal input ; a second signal input ; a reset signal output as well as an second output ; a bit counter ; a register ; the bit counter and the register being connected to the first signal input and successive approximation ( SA) comparator ; wherein the SA comparator is connected with the second input in order to count the edges of the second input signal within a predetermined period . 2024PF00610 2

[0010] The first signal input is in particular connected to a reference clock . The second signal input is in particular connected to a frequency divider .

[0011] The engine does in particular comprise reset circuit comprising a delay gate and an "and" gate . The reset circuit generates a reset signal when the reference signal fed into the first signal input changes signal level form low to high .

[0012] The counter might be for example a three-bit counter and the register might be for example a five-bit register however it is possible to vary the number of bits for the counter and the register .

[0013] The SA comparator is in particular configured to output an edge count signal command which might be a low signal for edge counts of zero and one and a high signal for edge counts above one . The edge count signal is fed into as the bit register for computing a second output of the SA engine . Such an SA comparator might be provided with a number of flip flop elements , which can be in particular reset at an end of a measuring period or a beginning of a measuring period, respectively .

[0014] The bit counter might be connected to a first output of the SA engine which might be in particular an output for an enable / disable signal .

[0015] In accordance with another aspect of the invention a circuit for adj usting an output frequency in dependence of an input frequency is provided, the circuit comprising : a phase lock-loop ( PLL ) circuit and a successive approximation ( SA) engine , wherein the SA engine is configured to coarse tune the output frequency of the circuit and the PLL circuit is configured to fine tune the output frequency . 2024PF00610 3

[0016] Tuning a frequency of the circuit with an SA engine has the advantage to reduce the number of cycles necessary by a considerable amount , saving time and energy during start-up .

[0017] According to one embodiment , the PLL circuit comprises a phase frequency detector, a filter and a voltage controlled oscillator, wherein the phase frequency detector compares the output signal of the voltage controlled oscillator with the input signal . In particular the phase frequency detector might be enabled or disabled depending on whether the circuit is in a coarse tuning mode or a fine tuning mode .

[0018] According to one embodiment , the SA engine is an SA engine as described above .

[0019] According to one embodiment , the SA engine is configured to control the numbers of a current sources for the voltage controlled oscillator . In particular, the SA engine is provided with a current source circuit which comprises a number of individual current sources having a di f ferent current strength . In particular, the current source circuit might have a number of current sources wherein neighboring current sources are doubling in strengths . Thus , for example source 1 has a first strength and source 2 has twice the first strength and so on .

[0020] According to one embodiment , in the control voltage of the PLL circuit is hal f of the supply voltage .

[0021] According to one embodiment , the PLL circuit further comprises a frequency divider, for dividing the signal of the voltage controlled oscillator and for feeding this signal to the successive approximation ( SA) engine .

[0022] According to one embodiment , the circuit is provided with a current source circuit for providing the voltage controlled oscillator with an input current , the current source circuit might be connected to the control voltage Vctri . The advantage 2024PF00610 4 of a current source circuit connected to the control voltage is that a circuit can be more easily adapted to a chance of outer conditions like temperature changes . In particular, in an embodiment , in which the current source circuit is connected to the control voltage by being connected to a compensator circuit part or loop filter, the current source circuit might be configured as low gain current source circuit . Furthermore , the loop filter, which is configured with a capacitor it might be provided with a small capacitor . I f the current source circuit is not provided as a low gain circuit it is typically necessary to provide a VCO with a higher gain which makes it necessary to provide a capacitor with a higher capacitance in the loop filter, which needs a bigger area in the circuit . The si ze of such a capacitor is critical for the si ze of the complete circuit .

[0023] In accordance with an another aspect of the invention a method for adj usting an output frequency in dependence of an input frequency using a circuit as described above is provided, the method comprising :

[0024] Step 1 Resetting a feedback divider and the successive approximation ( SA) comparator ;

[0025] Step 2 Setting an oscillator frequency to a first frequency by choosing a first number of current sources ; Step 3 counting the rising edges of frequency divider clock signal

[0026] Step 4 i f the number of rising edges is above 1 , reducing the input current for the oscillator ; resetting the feedback divider, increasing the bit counter by 1 and repeating step 3 ; i f the number of rising edges is 1 or 0 , increasing the input current for the oscillator ; resetting the feedback divider, increasing the bit counter by 1 and repeating step 3 ; i f the bit counter is set to its maximum counts , continue with Step 5 ; 2024PF00610 5

[0027] Step 5 enable frequency adj ustment by a phase locking loop, in particular by enabling phase lock-loop ( PLL ) circuit .

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Exemplary embodiments of the invention are discussed below with reference to the accompanying drawings

[0030] FIG . 1 shows a circuit for adj usting a frequency;

[0031] FIG . 2 shows a diagram of the di f ferent signals ;

[0032] FIG . 3 shows a SA engine ;

[0033] FIG . 4 shows an alternative embodiment of the circuit for adj usting a frequency and

[0034] FIG . 5 shows a time diagram comparing phase locking time between a classical PLL circuit and the proposed circuit .

[0035] DETAILED DESCRIPTION

[0036] FIG . 1 shows a circuit 50 for adj usting as a frequency . The circuit comprises two subcircuits , a PLL circuit 52 and an SA engine 54 . The circuits are interconnected in such a way that the frequency can be coarse tuned via the SA engine 54 , before fine tuning via the PLL circuit 52 . The circuit is further provided with an input 80 for the input of the reference clock signal ( ref_clk) and an output 82 for the output of an output signal . The PLL circuit 52 might be provided with a phase frequency detector ( PFD) 60 , a charge pump, a current source circuit 66 , a voltage controlled oscillator 64 as well as a feedback divider 68 .

[0037] The coarse tuning via the SA engine 54 is performed with a predetermined number of clock cycles . In the current example , 2024PF00610 6 six clock cycles from the reference clock are used for the frequency coarse tuning .

[0038] The principle for the SA engine will now be described with reference to FIG . 1 to 3 , wherein FIG . 2 depicts the di f ferent signals through six clock cycles and FIG . 3 depicts the SA engine .

[0039] The control voltage Vctri of the PLL circuit is set to hal f of the supply voltage , in particular by choosing the resistances R3 and R4 having the same resistance value .

[0040] On the first rising ref_clk edge the D<4> signal from the SA engine 54 to a current source circuit 66 is set to high, a short reset signal is generated by the SA-engine 54 in order to reset the feedback divider or frequency divider ( : N) 68 . This reset signal is shown in FIG . 2 at BIT<4> in the second line RST . A high current is generated by the current source circuit 66 to generate a high frequency by a voltage controlled oscillator (VCO) 64 of the PLL circuit 52 . Thus , the PLL circuit 52 is set to a high frequency, which is divided by the frequency divider 68 . The output of the frequency divider is a clock signal , the fdiv_clk signal which is fed into the SA engine as second input signal into the second input 4 of the SA engine . Beside the fdiv_clk signal , the ref_clk signal is fed into the first input 2 of the SA engine . The SA engine is configured to count the number of rising edges of the fdiv_clk signal within one period of the ref_clk signal . In particular, the SA engine 54 comprises an SA comparator 12 comprising the second input 4 of the SA engine , a counter 16 and a bit register 14 , as well as a reset circuit . The SA comparator 12 is configured with a series of flip flop elements . Thus , i f the number of rising edges of the fdiv_clk signal is two or more , the signal edge count , depicted in the fourth line of FIG . 2 is set to high . I f the number of rising edges of the fdiv_clk signal is one , the signal edge count remains at low . This signal is fed into the register 14 of the SA engine 54 . Thus , the D<4> output signal of the SA engine is set to low, which reduces the 2024PF00610 7 current of the current source circuit 66 and thus the VCO frequency drops .

[0041] The procedure is repeated for the BIT<3> and for determining whether the D<3> output signal has to be set to high or low . In the situation shown in FIG . 2 , the fdiv_clk signal has two rising edges , which means that the edge count is set to high and D<3> output signal is set to low .

[0042] The procedure is repeated for the BIT<2> and for determining whether the D<2> output signal has to be set to high or low . In the situation shown in FIG . 2 , the fdiv_clk signal has only one rising edge , which means that the edge count remains low and D<2> output signal is set to high, in order to increase the current of the current source circuit 66 and thus the frequency of the VCO 64 .

[0043] The procedure is repeated for the BIT<1> and for determining whether the D<1> output signal has to be set to high or low . The frequency is determined to be still to low . Thus , D<1> is set to high .

[0044] The procedure is repeated for the BIT<0> and for determining whether the D<0> output signal has to be set to high or low . As depicted in FIG . 2 , there is a second rising edge at the and of the fdiv_clk signal , thus edge count is set to high . Thus , the frequency is determined to be a little bit to high . Thus , D<0> is set to low .

[0045] At the end of the tuning phase the signal EN is set to high, PED is enabled and PLL continues to operate as a classical analog PLL but with the frequency which is close to the target frequency and with the very small phase error ref_clk vs . fdiv_clk . The phase error is equal to duration of the reset pulse signal , compare FIG . 2 . Since the frequency is close to target frequency and the phase error is very small , the PLL will need only few clock cycles to lock i . e . to start . The startup time is measured as a di f ference between 2024PF00610 8 the time when the PLL is locked and the time when PLL is enabled .

[0046] On every ref_clk rising edge in tuning phase the SA comparator is reset to 0 including the flip flops of the SA comparator, i.e. the comparator is ready for edge detection in the next cycle.

[0047] The proposed design of the circuit allows attaining the target frequency considerably faster.

[0048] FIG. 5 shows a comparison of a simulation of an implementation of the above circuit into a 180 nm CMOS technology. The PLL input frequency is 32 kHz (ref_clk frequency) and the output frequency is 20 MHz. The SA register is implemented as a 5-bit register. The same PLL is simulated in two cases, with and without the current invention. The startup time is measured as a difference between when the lock signal is set to high and a time when the PLL is enabled (pll_en set to high) . The proposed solution improves startup time more than 7 times, as shown in FIG. 5.

[0049] FIG. 4 shows an alternative circuit for adjusting a frequency. The design of the circuit in FIG. 1 and FIG. 4 differ in the layout of the current source circuit and the loop filter 72.

[0050] In FIG. 4 the current source circuit 66 is separated from the loop filter 72. However, this design is less flexible for example considering temperature variations. The current source circuit 66 of FIG. 4 is configured with a Digital to analog converter. This implementation is suitable in cases where PLL operating conditions (temperature, supply voltage) do not change too much from the conditions at which PLL frequency tuning (the VCO target frequency adjustment) was done (e.g. T=20C and VDD=1.8V) . However, if conditions change above a predetermined, the input current for the VCO circuit 2024PF00610 9 has to be readj usted, which means to restart the tuning of the circuit .

[0051] In comparison, the implementation of FIG . 1 comprises a low gain current source circuit 66 which is connected to the loop filter 72 . In this implementation, the current source circuit output depends on the control voltage Vctri , thus there is a higher flexibility on operating conditions , e . g . temperature variations , which can be compensated without rerunning the tuning of the circuit . This implementation has the further advantage , that the capacitor Cl can be chosen to be smaller . As this capacitor is critical to the area necessary for the circuit , a smaller capacitor Cl reduces the necessary area . In particular, the area might be 30% smaller compared to a classical PLL circuit .

[0052] 2024PF00610 10

[0053] LIST OF REFERENCE SIGNS

[0054] First input of SA engine 2 Second input of SA engine 4 Reset output of SA engine 6 First output of SA engine 8 Second output of SA engine 10 SA comparator of SA engine 12 Register of SA engine 14 Counter of SA engine 16 circuit 50

[0055] PLL circuit 52 SA Engine 54 Phase frequency detector 60 Filter 62 Voltage controlled oscillator 64 Current source circuit 66

[0056] Feedback divider 68 loop filter 72 input of circuit 80 output of circuit 82

Claims

2024PF00610 11CLAIMS1. Successive approximation (SA) engine (54) , comprising: A first signal input (2) ; a second signal input (4) ; a reset signal output (6) as well as an second output (10) ; a bit counter (16) ; a register ( 14 ) ; the bit counter (16) and the register (14) being connected to the first signal input (2) and a successive approximation (SA) comparator (12) ; wherein the SA comparator (12) is connected with the second input (4) in order to count the edges of the second input signal within a predetermined period.

2. Circuit (50) for adjusting an output frequency in dependence of an input frequency, comprising: a phase lock-loop (PLL) circuit (52) and a successive approximation (SA) engine (54) , wherein the SA engine (54) is configured to coarse tune the output frequency of the circuit (50) and the PLL circuit (52) is configured to fine tune the output frequency.

3. Circuit (50) according to claim 2, wherein the PLL circuit (52) comprises a phase frequency detector (60) , a filter (62) and a voltage controlled oscillator (64) , wherein the phase frequency detector (60) compares the output signal of the voltage controlled oscillator (64) with the input signal .

4. Circuit (50) according to claim 2 or 3, wherein the SA engine (54) is an SA engine (54) according to claim 1.

5. Circuit (50) according to one of the claims 2-4, wherein the SA engine (54) is configured to control the numbers of a current sources for the voltage controlled oscillator (64) .2024PF00610 126. Circuit (50) according to one of claims 2 to 5 , wherein the control voltage Vctri of the PLL circuit (52) is half of the supply voltage.

7. Circuit (50) according to one of claims 3 to 6, wherein the PLL circuit (52) further comprises a frequency divider (68) , for dividing the signal of the voltage controlled oscillator (64) and for feeding this signal to the successive approximation (SA) engine (54) .

8. Circuit (50) according to one of claims 3 to 6, wherein the circuit (50) is provided with a current source circuit (66) for providing the voltage controlled oscillator (64) with an input current, the current source circuit (66) might be connected to the control voltage Vctri .

9. Method for adjusting an output frequency in dependence of an input frequency using a circuit according to one of claims 2 to 7, comprising:Step 1 Resetting a feedback divider (68) and the successive approximation (SA) comparator (12) ;Step 2 Setting an oscillator frequency to a first frequency by choosing a first number of current sources; Step 3 counting the rising edges of frequency divider clock signalStep 4 if the number of rising edges is above 1, reducing the input current for the oscillator; resetting the feedback divider, increasing the bit counter by 1 and repeating step 3; if the number of rising edges is 1 or 0, increasing the input current for the oscillator; resetting the feedback divider (68) , increasing the bit counter by 1 and repeating step 3; if the bit counter is set to its maximum counts, continue with Step 5; Step 5 enable frequency adjustment by a phase locking loop, in particular by enabling phase lock-loop (PLL) circuit

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