Substrate having sige layer on silicon substrate and method for producing same

Abstract

The present invention is a method for producing a substrate that has a SiGe layer on a silicon substrate, said method comprising: a step for, with respect to a silicon substrate having a main front surface, a main back surface, and an edge part, vapor-depositing an SiGe layer on the main front surface, on the edge part, and on a region of the main back surface adjacent to the edge part; and a step for removing, via polishing, the SiGe layer vapor-deposited on the edge part and on the region of the main back surface adjacent to the edge part, and leaving the SiGe layer vapor-deposited on the main front surface. Thus, provided is a method which is for producing a substrate that has a SiGe layer on a silicon substrate and which significantly improves bowing of the substrate.

Description

A substrate having a SiGe layer on a silicon substrate and a method for manufacturing the same.

[0001] The present invention relates to a substrate having a SiGe layer on a silicon substrate and a method for manufacturing the same.

[0002] SiGe and Ge are materials widely used in various devices such as electronic, optical, and RF devices. In particular, SiGe has recently been proposed as a replacement for the Fin structure currently used in logic ICs, and GAA and even CFETs (which stack NMOS and CMOS) have been proposed for next-generation semiconductors. SiGe plays an important role in the manufacturing process of these materials (Non-Patent Document 1).

[0003] However, SiGe is known to be a material that, in its equilibrium phase diagram, has a large separation between its liquidus and solidus lines, resulting in a large partition coefficient of 2 to 5, making it prone to polycrystallization. Even if single crystals can be grown, the growth rate is slow, making it difficult to maintain on a permanent basis (Non-Patent Literature 2).

[0004] Therefore, for semiconductor devices, SiGe is grown on Si substrates, and such substrates are sometimes called virtual SiGe substrates. In this SiGe growth (heteroepitaxial growth), it is important to consider how to mitigate the difference in lattice constants between Si and Ge. The lattice constant of Si crystals is 0.5431 nm, and the lattice constant of Ge crystals is 0.56754 nm, resulting in a difference of approximately 4.5% between the two. To mitigate this difference in lattice constants, SiGe uses a SiGe mixed crystal. If the composition ratio of Ge is x, the lattice constant of the SiGe mixed crystal is "0.5431 nm + x × 0.02 nm + x squared × 0.0027 nm". For example, if we assume x is 0.3, the lattice constant becomes 0.5493 ​​nm, and the lattice mismatch is only 0.14%. This lattice mismatch can cause dislocations and defects to grow in the epitaxial layer that grows afterward, leading to a deterioration in quality. However, it is believed that a critical film thickness exists, and even if there is a lattice mismatch, defects will not occur as long as this critical film thickness is not exceeded (Non-Patent Document 3).

[0005] Japanese Patent Publication No. 2010-267969 Japanese Patent Publication No. 2005-011848

[0006] Materials from the 1st Research Meeting of the Industry-Academia Collaboration Committee on Crystal Growth, Processing, and Evaluation of Semiconductors, Japan Society of Applied Physics, "Crystal Technology Supporting the Resurgence of Semiconductors," (June 21, 2023) Ichiro Yonenaga, "Growth of High-Quality SiGe Crystals and Elucidation of Basic Physical Properties," Materia, 47(1), 3 (2008) Katsuaki Sato, "Fundamentals and Challenges of Heteroepitaxy: 1st Research Meeting of the 3C-SiC Technology Research Group for IoT in Harsh Environments" (2019) Wong, Lydia Helena, "Strain relaxation in SiGe / Si heteroepitaxy," Nanyang Technological University, Singapore. D. Rouchon et al. , “Germanium content and strain in Si1-xGex alloys characterized by Raman spectroscopy”, J. Crystal Growth, 392, 66 (2014).

[0007] In reality, SiGe substrates are required that have SiGe epitaxial films of 1 μm or even thicker, rather than the thin SiGe epitaxial films of the critical thickness mentioned above. Therefore, due to the difference in lattice constants, lattice-like irregularities occur on the surface, known as cross-hatching, and dislocations from the interface between the Si substrate and the SiGe epitaxial layer can reach the surface, generating defects. In addition to these, there is also the problem of wafer warping caused by this difference in lattice constants (this warping is not limited to SiGe substrates but is common to heteroepitaxial growth substrates).

[0008] As mentioned above, this warping problem is caused by lattice mismatch, and has traditionally been avoided by optimizing epitaxial growth conditions (e.g., buffer structure) along with defect reduction.

[0009] For example, Patent Document 2 discloses an improved method for manufacturing a semiconductor substrate, comprising: a first step of forming a SiGe concentration gradient layer on a Si single crystal substrate in which the Ge concentration increases with thickness; a second step of forming a SiGe concentration constant layer on the SiGe concentration gradient layer in which the Ge concentration is constant; and a third step of forming a strained Si layer on the SiGe concentration constant layer, wherein at least one of the layers in the first, second, and third steps is formed by epitaxial growth. The method further includes a step of removing the epitaxial layers formed on the back surface and chamfered surface of the substrate during epitaxial growth, following the third step. In this method, the production of a so-called buffer layer is limited to a forward-graded buffer layer (in which the Ge concentration increases with thickness), but in reality, a reverse-graded buffer layer in which a layer with a high concentration is formed and then the concentration is temporarily reduced has also been proposed (for example, Non-Patent Document 4), so a good SiGe substrate is not necessarily provided. In other words, it is clear that the method is limited as described above because it cannot solve the problem of warping (BOW) in addition to defects.

[0010] The present invention was made to solve the above problems and aims to provide a method for manufacturing a substrate having a SiGe layer on a silicon substrate that significantly improves substrate warping, i.e., BOW.

[0011] The present invention has been made to achieve the above objective and provides a method for manufacturing a substrate having a SiGe layer on a silicon substrate, comprising the steps of vapor-depositing a SiGe layer on the main surface, on the edge portion, and on a region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion, and removing the SiGe layer vapor-deposited on the edge portion and on the region adjacent to the edge portion on the main back surface by polishing, leaving the SiGe layer vapor-deposited on the main surface.

[0012] According to this method for fabricating a substrate having a SiGe layer on a silicon substrate, even when forming a thick SiGe epitaxial layer, the warping (BOW) of the substrate is reduced, and a virtual SiGe substrate can be fabricated in which cross-hatching caused by lattice mismatch between silicon and SiGe on the surface is suppressed.

[0013] In this case, the area adjacent to the edge portion on the main back surface can be set to 1 μm to 5 μm from the boundary between the main back surface and the edge portion toward the center of the silicon substrate.

[0014] This makes it possible to further reduce the warping (BOW) of the circuit board.

[0015] In this case, the SiGe layer on the surface of the silicon substrate may be lattice-relaxed, and the SiGe layer on the surface side of the silicon substrate at the edge portion may contain SiGe having tensile stress.

[0016] This further reduces the board warp (BOW).

[0017] In this case, the SiGe layer on the back side of the silicon substrate at the edge portion and in the region adjacent to the edge portion on the main back surface may be made non-lattice relaxed, and the SiGe layer on the back side of the silicon substrate at the edge portion and in the region adjacent to the edge portion on the main back surface may be made to contain SiGe having compressive stress.

[0018] This further reduces the board warp (BOW).

[0019] In this case, the step of leaving the SiGe layer in place may include, in this order, the step of removing the SiGe layer at the edge portion, the step of removing the SiGe layer in the region adjacent to the edge portion on the main back surface, and the step of polishing the surface of the SiGe layer on the main surface.

[0020] This allows for a further reduction in substrate warping (BOW) and a reduction in defects on the SiGe layer surface.

[0021] In this case, during the step of polishing the surface of the SiGe layer on the main surface, the surface of the SiGe layer on the main surface can be polished so that the surface roughness Sa measured by AFM in a 30 μm square area is 0.2 nm or less.

[0022] By polishing the surface so that the surface roughness Sa measured in a 30 μm square area using AFM is 0.2 nm or less, the effects of cross-hatching can be more effectively mitigated.

[0023] The present invention has also been made to achieve the above objective, and provides a substrate having a SiGe layer on a silicon substrate having a diameter of 300 mm having a main surface, a main back surface and an edge portion, wherein the main back surface and the edge portion are not provided with a SiGe layer, and the main surface is provided with a lattice-relaxed SiGe layer, the Bow of the substrate is 5 μm or less, and the surface roughness Sa of the SiGe layer, measured by AFM in a 30 μm square area, is 0.2 nm or less.

[0024] With a substrate having a SiGe layer on a silicon substrate, even with a thick SiGe epitaxial layer, the substrate warpage (BOW) is reduced, and the cross-hatching that occurs on the surface due to lattice mismatch between silicon and SiGe is suppressed, resulting in a virtual SiGe substrate.

[0025] As described above, according to the method for manufacturing a substrate having a SiGe layer on a silicon substrate of the present invention, even when forming a thick SiGe epitaxial layer, it is possible to manufacture a virtual SiGe substrate in which substrate warping (BOW) is reduced and cross-hatching caused on the surface due to lattice mismatch between silicon and SiGe is suppressed. Furthermore, according to the substrate having a SiGe layer on a silicon substrate of the present invention, even with a thick SiGe epitaxial layer, substrate warping (BOW) is reduced and cross-hatching caused on the surface due to lattice mismatch between silicon and SiGe is suppressed, resulting in a virtual SiGe substrate.

[0026] In particular, the small BOW (Body Edge) makes it less likely for defocusing to occur in processes such as photolithography, and also helps to suppress transport errors caused by substrate warping in various device manufacturing processes.

[0027] This is a schematic cross-sectional view of a substrate having a SiGe layer on a silicon substrate according to an embodiment of the present invention. This is a schematic cross-sectional view of the edge portion of a silicon substrate in the step of providing a SiGe epitaxial layer particularly on the edge portion of the silicon substrate according to an embodiment of the present invention. This shows the results of Raman spectroscopy measurements performed at various positions on the edge of the SiGe substrate of the present invention in which the SiGe layer has been formed ((a) edge surface, (b) edge back surface). This shows the change in BOW at each stage in the example: silicon substrate, after epitaxial growth, after edge polishing, after back surface polishing (removal of SiG from the outer periphery of the back surface), and after surface polishing.

[0028] The present invention will be described in detail below with reference to the drawings, but the present invention is not limited to these descriptions.

[0029] As described above, there was a need for a method to manufacture a substrate having a SiGe layer on a silicon substrate (hereinafter also referred to as a "virtual SiGe substrate," "SiGe substrate," or "SiGe epitaxial substrate") that would significantly improve substrate warping (BOW).

[0030] The inventors of this invention have diligently studied the above-mentioned problems and, as a result, have focused not only on the growth conditions for SiGe epitaxial growth, but also on the stress applied to the entire substrate, and in particular on the stress of the SiGe film that wraps around the edges of the substrate and the back surface of the substrate during epitaxial growth. They have found that it is possible to control this stress, that is, to control the warp (BOW) of the substrate by focusing not only on the epitaxial growth conditions but also on the effects of processing. In other words, by combining the adjustment of processing conditions after epitaxial growth in addition to the epitaxial growth conditions, the warp (BOW) of the substrate can be significantly improved. Based on these findings, the inventors of this invention have completed the present invention.

[0031] In other words, as a result of diligent study on the above problems, the present inventors have found that by a method for manufacturing a substrate having a SiGe layer on a silicon substrate, which includes the steps of vapor-depositing a SiGe layer on the main surface, on the edge portion, and on the region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion, and removing the SiGe layer vapor-deposited on the edge portion and the region adjacent to the edge portion on the main back surface by polishing, leaving the SiGe layer vapor-deposited on the main surface, even with a thick SiGe epitaxial layer, it is possible to manufacture a virtual SiGe substrate in which the warping (BOW) of the substrate is reduced and cross-hatching that occurs on the surface due to lattice mismatch between silicon and SiGe is suppressed, even with a thick SiGe epitaxial layer, and thus the present invention has been completed.

[0032] The inventors have also conducted extensive research on the above-mentioned problems and have found that a silicon substrate with a diameter of 300 mm having a main surface, a main back surface, and an edge portion, and a SiGe layer formed on the silicon substrate, wherein the main back surface and the edge portion are not provided with a SiGe layer, and the main surface is provided with a lattice-relaxed SiGe layer, the Bow of the substrate is 5 μm or less, and the surface roughness Sa of the SiGe layer, measured by AFM in a 30 μm square area, is 0.2 nm or less, can reduce the warping (BOW) of the substrate even with a thick SiGe epitaxial layer, and can also suppress cross-hatching on the surface caused by lattice mismatch between silicon and SiGe, thus completing the present invention.

[0033] Furthermore, Patent Document 1 discloses a method for simultaneously polishing both sides of a silicon substrate in which SiGe is laminated on one side, and depositing a stress compensation layer on the side opposite to the side on which SiGe is laminated. However, in this method, SiGe remains on at least the back surface, and there is no mention of SiGe at the edges. As a result, SiGe remains, and there are concerns about the use of this substrate, such as the possibility of contamination of process equipment by SiGe, diffusion of Ge due to heat treatment in the device process, and disruption of the stress balance between the front and back surfaces for stress compensation when the SiGe composition profile changes as the process such as etching progresses.

[0034] [Substrate having a SiGe layer on a silicon substrate] Figure 1 shows a schematic cross-sectional view of a SiGe substrate in an embodiment of the present invention. As shown in Figure 1, the SiGe substrate in an embodiment of the present invention is a SiGe substrate (SiGe epitaxial substrate) 1 in which a SiGe layer 3 is grown on a silicon substrate (silicon single crystal substrate) 2.

[0035] The silicon substrate 2 is a silicon substrate with a diameter of 300 mm having a main surface, a main back surface, and an edge portion 4. Other conditions are not particularly limited; it may be doped, the conductivity type may be p-type or n-type, the resistivity may be low or high, and it can be a silicon single crystal substrate manufactured using the same single crystal manufacturing equipment and procedures as conventional methods.

[0036] The SiGe layer 3 is not present on the main back surface or edge portion 4 of the silicon substrate 2, but a lattice-relaxed SiGe layer 3 is present on the main surface. The Bow of the SiGe substrate 1 is 5 μm or less, and the surface roughness Sa of the SiGe layer 3, measured by AFM in a 30 μm square area, is 0.2 nm or less. Since both Bow and surface roughness Sa are better when they are small, the lower limit for both is 0 nm.

[0037] The SiGe layer 3 grown on the silicon substrate 2 generates defects due to the lattice constant difference. However, for the SiGe substrate according to the present invention as described above, even if it is a thick SiGe epitaxial layer, the warp (BOW) of the substrate is reduced, and moreover, it becomes a virtual SiGe substrate in which the crosshatch generated on the surface due to the lattice mismatch between silicon and SiGe is suppressed.

[0038] Particularly, since the BOW is small, for example, it is difficult to cause defocus in the photolithography process, and it is possible to suppress the occurrence of transfer errors caused by the warp of the substrate in various device processes.

[0039] [Method for manufacturing a substrate having a SiGe layer on a silicon substrate] Next, a general manufacturing method of the SiGe substrate will be described. As shown in FIG. 1, a SiGe layer 3 is grown on the silicon substrate 2. There are no particular restrictions on the growth conditions of SiGe, but generally, under reduced pressure conditions, monogerman (GeH ４ ), and monosilane (SiH ４ ) or dichlorosilane (H ２ SiCl ２ ) gas is used as a raw material, and it is grown at a temperature of 600 to 800°C.

[0040] In addition, in order to relax the introduction of dislocations due to the lattice constant difference of the SiGe layer 3 grown on the silicon substrate 2, a forward tilt buffer layer in which the Ge concentration in SiGe is gradually increased as disclosed in Patent Document 2, or conversely, a SiGe layer having a high Ge concentration as disclosed in Non-Patent Document 4 is grown, and an inverse tilt buffer layer in which the Ge concentration is decreased may be devised.

[0041] Next, the manufacturing method of the SiGe substrate according to the present invention will be described below by explaining each step in order. The manufacturing method of the SiGe substrate according to the present invention is a method for growing a SiGe layer 3 by vapor phase on the main surface, the main back surface, and the edge vicinity region 7 (hereinafter also referred to as the "edge vicinity part") adjacent to the edge part on the main surface, on the edge part 4, and on the main back surface of the silicon substrate 2 having a main surface, a main back surface, and an edge part 4, and a method for manufacturing a SiGe substrate 1 including a step of removing the SiGe layer 3 grown by vapor phase on the edge part 4 and on the region 7 adjacent to the edge part on the main back surface by polishing and leaving the SiGe layer 3 grown by vapor phase on the main surface.

[0042] (Step of growing SiGe layer by vapor phase) First, the epitaxial growth of the SiGe layer 3 on the silicon substrate 2 will be described by focusing on the edge part 4 of the silicon substrate 2 shown in FIG. 2. In the manufacturing method of the SiGe substrate of the present invention, when the SiGe layer 3 is grown by vapor phase on the silicon substrate 2, the SiGe layer 3 is intentionally grown by vapor phase on the edge part 4 and the edge vicinity part 7 as well. In the edge part 4, there are R-shaped portions in the X1 part 5 on the front surface side and the X2 part 6 on the back surface side.

[0043] The range of the edge vicinity part 7 can be set to be 1 μm or more and 5 μm or less from the boundary between the main back surface and the edge part 4 toward the center of the silicon substrate 2. Thereby, the warp (BOW) of the substrate can be further reduced.

[0044] FIG. 3 shows the results ((a) edge part surface, (b) edge part back surface) of Raman spectroscopic measurement at each position of the end of the SiGe substrate 1 on which the SiGe layer 3 is formed. The SiGe layer 3 on the surface of the silicon substrate 2 can be considered to be lattice-relaxed. That is, the SiGe grown on the R-shaped portion of the edge part 4 can be lattice-relaxed SiGe on the surface in the X1 part 5 on the front surface side, and the film can be formed so that the layer contains SiGe having tensile stress in the X1 part 5. At this time, as disclosed in Non-Patent Document 5, the Si-Si Raman shift in relaxed SiGe is 500 to 502 cm －１ and as shown in FIG. 3(a), the surface of the silicon substrate 2 is relaxed SiGe, and although there are parts in the X1 part 5 that are below 500 cm －１ it is generally 500 to 502 cm－１ It can be seen that it is a tensile stress. As a result, the warp (BOW) of the substrate can be further reduced.

[0045] On the other hand, assuming that the SiGe layer 3 in the back surface side (X2 part 6) of the silicon substrate 2 in the edge part 4 and in the vicinity of the edge 7 is not lattice-relaxed, the SiGe layer 3 in the X2 part 6 and in the vicinity of the edge 7 can contain SiGe having compressive stress. Actually, as shown in FIG. 3(b), the Raman shift on the back surface is 504 to 504.5 cm near the edge of the back surface －１ and also 502 cm in the X2 part 6 －１ which is larger than. As seen from the Raman of Si—Si in relaxed SiGe as in Non-Patent Document 5 (500 to 502 cm －１ ), it can be seen that it has a large compressive stress. As a result, the warp (BOW) of the substrate can be further reduced.

[0046] Several methods for adjusting the way of applying stress are conceivable and are not particularly limited, but it can be carried out by the substrate and a susceptor that supports the substrate during epitaxial growth. For example, a susceptor with holes opened around it can be used, and growth can be carried out so that gas circulates into the periphery of the back surface. By doing so, the edge part on the surface side becomes relaxed SiGe except for the outermost periphery, the back surface has conditions optimized for the surface side, and for partial growth, it becomes SiGe having the above-mentioned compressive stress.

[0047] (Step of leaving the SiGe layer) Next, the SiGe layer 3 in the edge part 4 and on the back surface is removed by polishing, and the SiGe layer 3 on the main surface is left. The step of leaving the SiGe layer can include, in this order, a step of removing the SiGe layer 3 in the edge part 4, a step of removing the SiGe layer 3 in the vicinity of the edge 7, and a step of polishing the surface of the SiGe layer 3 on the main surface.

[0048] As a result, the warp (BOW) of the substrate can be further reduced, and the defects on the surface of the SiGe layer 3 can be further reduced.

[0049] Patent Document 2 states that the SiGe epitaxial layer can be removed by wet etching, but due to its composition, SiGe is easily etched unevenly, making uniform removal difficult. For this reason, polishing such as CMP is preferable. The amount of polishing performed on the edge portion 4 and the back surface of the SiGe should be set so that each SiGe is completely removed.

[0050] By performing CMP (Chemical Polishing) on ​​the outermost surface, surface cross-hatching can be further reduced, and by removing the stress remaining in the outermost layer, BOW (Block Edge) can be further relaxed. The amount of CMP used in this process can be adjusted so that the surface roughness Sa measured in a 30 μm square area by AFM (Aluminum Focusing Microscope) becomes 0.2 nm or less, thereby more effectively mitigating the effects of cross-hatching. Since a smaller surface roughness Sa is desirable, the lower limit can be set to 0 nm.

[0051] The present invention will be described in detail below with reference to examples, but this is not intended to limit the present invention.

[0052] SiGe epitaxial substrates were fabricated as follows: A single-crystal silicon substrate with a diameter of 300 mm, a crystal orientation (100), boron doping, and a resistivity of 10 Ω·cm was prepared, and its BOW was first measured using an LNSW manufactured by Kobelco Research Institute.

[0053] Next, in a reduced-pressure CVD apparatus, SiH ２ Cl ２ Gas and GeH ４ Using gas as a raw material, a 5 μm thick SiGe (Ge composition ratio = 30%) layer was grown on a single-crystal silicon substrate with a gas flow rate of 1000 sccm, a chamber pressure of 10 Torr (1333 Pa), a growth temperature of 610°C, and a growth time of 60 min.

[0054] For this process, a perforated susceptor was used to support the substrate, allowing SiGe to grow on the back surface as well. The BOW of the substrate after epitaxial growth was measured in the same way as the substrate before epitaxial growth.

[0055] Next, the edges were polished using a polishing method similar to that used for general silicon wafer edge polishing. However, it was found that the polishing speed of SiGe was about 1 / 5 that of Si, and the polishing time was five times longer than that required for removing 5 μm of silicon. In this state, the BOW of the substrate was measured in the same way as the substrate before epitaxial growth.

[0056] Next, the SiGe on the back surface was polished using the same polishing method as for general silicon wafer back surface polishing. However, since the polishing speed of SiGe is about 1 / 5 that of Si, the polishing time was five times longer than the time required to remove 5 μm of silicon. In this state, the BOW of the substrate was measured in the same way as the substrate before epitaxial growth.

[0057] Finally, the surface of the SiGe layer remaining on the main surface of the silicon single crystal substrate was polished, taking into account that the polishing speed of SiGe is about 1 / 5 that of silicon. In order to reduce the Sa to 0.2 nm or less using a 30 μm square AFM, it was necessary to polish the SiGe surface to 90 nm. In this state, the BOW of the substrate was measured in the same way as the substrate before epitaxial growth.

[0058] Figure 4 summarizes the changes in BOW at each stage. The BOW on the initial substrate is very small, but after SiGe epitaxial growth, the BOW becomes larger on the negative side (concave shape). After this, polishing the edges and removing the SiGe alleviates the concave shape, and removing the SiGe from the back surface significantly improves the BOW, resulting in a convex shape. Performing CMP on the surface further improves the BOW.

[0059] As described above, according to the embodiments of the present invention, a good virtual (relaxed) SiGe substrate with a small BOW and suppressed surface roughness Sa was obtained.

[0060] This specification includes the following embodiments: [1]: A method for manufacturing a substrate having a SiGe layer on a silicon substrate, comprising the steps of vapor-depositing a SiGe layer on the main surface, on the edge portion, and on a region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion, and removing the SiGe layer vapor-deposited on the edge portion and on a region adjacent to the edge portion on the main back surface by polishing, leaving the SiGe layer vapor-deposited on the main surface. [2]: A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to [1], further comprising setting the range of the region adjacent to the edge portion on the main back surface to be 1 μm or more and 5 μm from the boundary between the main back surface and the edge portion toward the center of the silicon substrate. [3]: A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to [1] or [2], further comprising setting the SiGe layer on the surface of the silicon substrate to be lattice-relaxed, and the SiGe layer on the surface side of the silicon substrate of the edge portion to contain SiGe having tensile stress. [4]: A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to [1], [2], or [3], wherein the SiGe layer on the back side of the silicon substrate at the edge portion and in the region adjacent to the edge portion on the main back surface is not lattice relaxed, and the SiGe layer on the back side of the silicon substrate at the edge portion and in the region adjacent to the edge portion on the main back surface contains SiGe having compressive stress. [5]: A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to [1], [2], [3], or [4], wherein the step of leaving the SiGe layer includes, in this order, the steps of removing the SiGe layer at the edge portion, removing the SiGe layer in the region adjacent to the edge portion on the main back surface, and polishing the surface of the SiGe layer on the main surface. [6] A method for producing a substrate having a SiGe layer on a silicon substrate according to [5], comprising the step of polishing the surface of the SiGe layer on the main surface, wherein the surface of the SiGe layer on the main surface is polished such that the surface roughness Sa measured by AFM in a 30 μm square area is 0.2 nm or less.[7] A substrate having a SiGe layer on a silicon substrate, comprising a silicon substrate with a diameter of 300 mm having a main surface, a main back surface and an edge portion, and a SiGe layer formed on the silicon substrate, wherein the main back surface and the edge portion are not provided with a SiGe layer, and the main surface is provided with a lattice-relaxed SiGe layer, the Bow of the substrate is 5 μm or less, and the surface roughness Sa of the SiGe layer, when measured in a 30 μm square area by AFM, is 0.2 nm or less.

[0061] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention.

Claims

1. A method for manufacturing a substrate having a SiGe layer on a silicon substrate, comprising the steps of: vapor-depositing a SiGe layer on the main surface, on the edge portion, and on a region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion; and removing the SiGe layer vapor-deposited on the edge portion and on a region adjacent to the edge portion on the main back surface by polishing, leaving the SiGe layer vapor-deposited on the main surface.

2. The method for manufacturing a substrate having a SiGe layer on a silicon substrate according to claim 1, characterized in that the range of the region adjacent to the edge portion on the main back surface is 1 μm or more and 5 μm or less from the boundary between the main back surface and the edge portion toward the center of the silicon substrate.

3. A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to claim 1, characterized in that the SiGe layer on the surface of the silicon substrate is lattice-relaxed, and the SiGe layer on the surface side of the silicon substrate at the edge portion contains SiGe having tensile stress.

4. A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to claim 1, characterized in that the SiGe layer in the region adjacent to the edge portion on the back side of the silicon substrate at the edge portion and on the main back side is not lattice relaxed, and the SiGe layer in the region adjacent to the edge portion on the back side of the silicon substrate at the edge portion and on the main back side contains SiGe having compressive stress.

5. The method for manufacturing a substrate having a SiGe layer on a silicon substrate according to any one of claims 1 to 4, characterized in that the step of leaving the SiGe layer includes, in this order: removing the SiGe layer at the edge portion; removing the SiGe layer in a region adjacent to the edge portion on the main back surface; and polishing the surface of the SiGe layer on the main surface.

6. The method for producing a substrate having a SiGe layer on a silicon substrate according to claim 5, characterized in that, in the step of polishing the surface of the SiGe layer on the main surface, the surface of the SiGe layer on the main surface is polished so that the surface roughness Sa measured by AFM in a 30 μm square area is 0.2 nm or less.

7. A silicon substrate having a SiGe layer, comprising a silicon substrate with a diameter of 300 mm having a main surface, a main back surface and an edge portion, and a SiGe layer formed on the silicon substrate, wherein the main back surface and the edge portion are not provided with a SiGe layer, and the main surface is provided with a lattice-relaxed SiGe layer, the Bow of the substrate is 5 μm or less, and the surface roughness Sa of the SiGe layer, when measured in a 30 μm square area by AFM, is 0.2 nm or less.

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