Field-effect transistor
The field-effect transistor design with independently connected gate electrodes and diamond layers with differing thermal properties addresses yield loss by preventing short circuits and leakage currents, ensuring reliable integration of multiple elements.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HONDA MOTOR CO LTD
- Filing Date
- 2025-10-15
- Publication Date
- 2026-04-23
AI Technical Summary
Conventional field-effect transistors with integrally connected gate electrodes experience yield loss due to leakage currents and characteristic degradation from defects or substrate distortions, particularly when multiple sets of elements are integrated.
The design includes a field-effect transistor with independently arranged gate electrodes connected via conductors, ensuring larger distances between dissimilar electrodes to mitigate thermal distortions, and using diamond layers with different thermal properties to prevent short circuits and leakage currents.
This design effectively suppresses short circuits and maintains electrode integrity, thereby preventing yield loss and characteristic degradation during integration of multiple sets of elements.
Smart Images
Figure JP2025036394_23042026_PF_FP_ABST
Abstract
Description
Field-effect transistor
[0001] The present invention relates to a field-effect transistor. This application claims priority based on Japanese Patent Application No. 2024-184251 filed on October 18, 2024, and incorporates its content herein by reference.
[0002] Conventionally, a field-effect transistor having an annular gate electrode surrounding a source electrode or a drain electrode is known (see, for example, Patent Document 1 and Patent Document 2).
[0003] Japanese Patent Application Laid-Open No. 2017-143122 International Publication No. 2023 / 243556
[0004] In the above-described conventional field-effect transistor, for example, even when a plurality of sets of elements are integrated with a combination of one gate electrode and one source electrode or drain electrode surrounded by one gate electrode as one set of elements, it is desired to suppress a decrease in yield. For example, in the above-described conventional technology, when the gate electrodes of a plurality of sets of elements have a shape that is integrally connected in advance, if a leakage current occurs between the source electrode or drain electrode and the gate electrode in some elements due to defects in the semiconductor material or distortion of the substrate, the characteristics may disappear in a plurality of adjacent sets of elements.
[0005] An aspect of the present invention aims to provide a field-effect transistor capable of suppressing a decrease in yield when a plurality of sets of elements are integrated.
[0006] A field-effect transistor according to a first aspect of the present invention comprises: a bulk layer; a conductive layer provided at the leading edge of the bulk layer in a predetermined direction and having different thermal characteristics from the bulk layer; a source region, a drain region, and a channel region provided at the leading edge of the conductive layer in the predetermined direction; a source electrode provided at the leading edge of the source region in the predetermined direction, a drain electrode provided at the leading edge of the drain region in the predetermined direction, and a gate electrode provided at the leading edge of the channel region in the predetermined direction via an insulating layer; wherein the outer shape of the gate electrode in a plan view from the predetermined direction surrounds the outer periphery of a first region among the source region and the drain region, and the second region among the source region and the drain region is arranged around the outer periphery of the gate electrode, and the distance between the short side of the gate electrode and the source electrode or the drain electrode provided in the first region is relatively greater than the distance between the long side of the gate electrode and the source electrode or the drain electrode provided in the first region.
[0007] A second embodiment is a field-effect transistor as described in the first embodiment, wherein the conductive layer is a p-type diamond layer made of diamond doped with acceptor impurities, and the bulk layer is an i-type diamond layer made of intrinsic diamond semiconductor.
[0008] A third embodiment is a field-effect transistor according to the first or second embodiment, comprising: a first conductor extending in a direction parallel to the short side at a position facing the short side; and a second conductor connecting the short side and the first conductor.
[0009] A fourth embodiment is a field-effect transistor as described in the third embodiment, wherein the first gate electrode and the second gate electrode, which are provided on both sides of the first conductor sandwiched along the direction parallel to the long side, are positioned so as to be offset by a predetermined distance along the direction parallel to the short side.
[0010] According to the first embodiment described above, even if distortion and displacement due to thermal shrinkage occur due to differences in the thermal properties of the bulk layer and the conductive layer, the occurrence of short circuits can be suppressed by increasing the distance between dissimilar electrodes in the longitudinal direction, where deformation is relatively greater than in the short direction. By ensuring a desired margin in the distance between dissimilar electrodes, it is possible to suppress the occurrence of short circuits during electrode pattern formation, even in areas where distortion and displacement occur.
[0011] In the second embodiment described above, even if distortion occurs in the i-type diamond layer due to thermal shrinkage of the p-type diamond layer required for the arrangement of each electrode, short circuits between dissimilar electrodes can be suppressed.
[0012] In the third embodiment described above, each of the multiple gate electrodes is connected to the first conductor by a second conductor, allowing each gate electrode to be provided independently, compared to, for example, a configuration in which multiple gate electrodes are pre-connected integrally. For example, even if leakage current occurs between some gate electrodes and the source or drain electrode due to defects in the semiconductor material, selective connection with the second conductor can suppress the abnormality from affecting the entire system. By avoiding connection with the second conductor in the abnormal parts, the loss of overall characteristics can be suppressed, and a decrease in yield when multiple sets of elements are integrated can be suppressed.
[0013] In the fourth embodiment described above, the second conductor connected to the first gate electrode and the second conductor connected to the second gate electrode can be connected to different positions on the first conductor while suppressing an increase in the length of each other.
[0014] This is a schematic plan view showing the configuration of a field-effect transistor according to an embodiment of the present invention. This is a cross-sectional in a modified example of an embodiment of the present invention.
[0015] Hereinafter, a field-effect transistor according to an embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 is a schematic plan view showing the configuration of the field-effect transistor 10 of the embodiment. Figure 2 is a cross-sectional view showing the configuration of the field-effect transistor 10 of the embodiment. In the following, the axial directions of the X, Y, and Z axes, which are mutually orthogonal in three-dimensional space, are parallel to the respective axes of the field-effect transistor 10. For example, the Z-axis direction is parallel to the thickness direction of the field-effect transistor 10.
[0016] As shown in Figures 1 and 2, the field-effect transistor 10 of the embodiment comprises, for example, a bulk layer 11, a conductive layer 12, an insulating layer 13, a source electrode 14, a drain electrode 15, and a gate electrode 16. For example, at least one combination of source electrode 14 and gate electrode 16 constitutes one element 17. The bulk layer 11 is, for example, an i-type diamond layer made of intrinsic diamond semiconductor. The i-type diamond layer is a pure diamond active layer formed by diamond in a nearly undoped state (so-called intrinsic semiconductor) that contains, for example, almost no n-type or p-type dopants (impurities).
[0017] The conductive layer 12 is a p-type diamond layer made of diamond doped with acceptor impurities such as boron atoms. The conductive layer 12 is formed by a p-type semiconductor with a relatively high carrier concentration. ＋ This is a diamond layer. The conductive layer 12 is provided at the leading edge in the Z-axis direction of the bulk layer 11, for example, by a homoepitaxial growth method. The conductive layer 12 has different thermal properties from the bulk layer 11. Thermal properties include, for example, the coefficient of thermal expansion. For example, the coefficient of thermal expansion of the conductive layer 12 is greater than that of the bulk layer 11. The conductive layer 12 comprises, for example, a source region 21 (first region) and a drain region 22 (second region), and a channel region 23 provided between the source region 21 and the drain region 22.
[0018] The source electrode 14 is provided, for example, at the tip of the source region 21 in the Z-axis direction. For example, the external shape of the source electrode 14 in a plan view from the Z-axis direction is rectangular, having a short side along the X-axis direction and a long side along the Y-axis direction. The drain electrode 15 is provided, for example, at the tip of the drain region 22 in the Z-axis direction. For example, the external shape of the drain electrode 15 in a plan view from the Z-axis direction is comb-like, having a plurality of protrusions 15b extending along the Y-axis direction from an integral base end 15a. The plurality of protrusions 15b are arranged, for example, at appropriate intervals along the X-axis direction.
[0019] The gate electrode 16 is provided at the tip in the Z-axis direction of the channel region 23 via an insulating layer 13. The gate electrode 16 is electrically insulated from each of the source electrode 14 and drain electrode 15 by the insulating layer 13. For example, the outer shape of the gate electrode 16 in a plan view from the Z-axis direction is a rectangular ring surrounding the outer circumference of the source region 21 and source electrode 14. The gate electrode 16 is positioned, for example, between adjacent protrusions 15b along the X-axis direction of the drain electrode 15. Of the outer circumference of the gate electrode 16, the outer circumference other than the short side portion 16a connected to the first conductor 31 by the second conductor 32 (described later) is surrounded by the drain region 22 and the base end portion 15a and adjacent protrusions 15b of the drain electrode 15. Multiple gate electrode 16s constituting multiple sets of elements 17 are, for example, arranged independently without being connected to each other and lined up at appropriate intervals along a direction parallel to each short side portion 16a (i.e., the X-axis direction).
[0020] The field-effect transistor 10 of this embodiment includes, for example, a first conductor 31 and a plurality of second conductors 32 connected to each gate electrode 16. For example, the shape of the first conductor 31 in a plan view from the Z-axis direction is such that it extends along the X-axis direction parallel to each short side portion 16a of each gate electrode 16, at a position in the Y-axis direction opposite to the short side portion 16a of each gate electrode 16 that is not surrounded by the drain electrode 15. For example, the shape of each of the plurality of second conductors 32 in a plan view from the Z-axis direction extends along the Y-axis direction and connects the first conductor 31 to each short side portion 16a of each gate electrode 16 that is not surrounded by the drain electrode 15.
[0021] In the field-effect transistor 10 of this embodiment, in a plan view of the conductive layer 12 from the Z-axis direction, the distance between adjacent dissimilar electrodes is set to be relatively larger in the longitudinal direction compared to the transverse direction. For example, of the two short sides 16a of the gate electrode 16, the distance LS1 in the Y-axis direction between the short side 16a surrounded by the drain electrode 15 and the source electrode 14 is relatively larger than the distance LS2 in the X-axis direction between the long side 16b of the gate electrode 16 and the source electrode 14. For example, of the two short sides 16a of the gate electrode 16, the distance LD1 in the Y-axis direction between the short side 16a surrounded by the drain electrode 15 and the drain electrode 15 (base end 15a) is relatively larger than the distance LD2 in the X-axis direction between the long side 16b of the gate electrode 16 and the drain electrode 15 (protruding portion 15b).
[0022] As described above, according to the field-effect transistor 10 of the embodiment, even if distortion and misalignment occur due to differences in the thermal characteristics of the bulk layer 11 and the conductive layer 12, for example, due to thermal shrinkage, the occurrence of short circuits between dissimilar electrodes can be suppressed. By increasing the distance between dissimilar electrodes in the longitudinal direction, where deformation is relatively greater than in the short direction, a desired margin can be secured for the distance between dissimilar electrodes, and even in areas where distortion and misalignment occur, for example, short circuits can be suppressed during the formation of the electrode pattern.
[0023] For example, the thermal expansion coefficient of the p-type diamond layer, which is the conductive layer 12 required for the arrangement of each electrode 14, 15, and 16, is greater than that of the i-type diamond layer, which is the bulk layer 11. Therefore, the thermal contraction of the p-type diamond layer may cause distortion in the i-type diamond layer. In directions where the deformation is relatively large, a larger margin is set for the distance between dissimilar electrodes, thereby suppressing short circuits between dissimilar electrodes during the formation of the electrode pattern.
[0024] Each of the multiple gate electrodes 16 is connected to the first conductor 31 by a second conductor 32. This allows each gate electrode 16 to be electrically independent, compared to, for example, a configuration in which the multiple gate electrodes 16 are pre-connected integrally. For example, even if leakage current occurs between some gate electrodes 16 and the source electrode 14 or drain electrode 15 due to defects or distortion in the semiconductor material, selective connection by the second conductor 32 can suppress the occurrence of abnormalities in the surrounding area or the entire system. By avoiding connection by the second conductor 32 in abnormal areas, the loss of characteristics in the surrounding area or the entire system can be suppressed, thereby suppressing a decrease in yield when multiple sets of elements 17 are integrated.
[0025] (Modifications) Modifications of the embodiment will be described below. Note that parts identical to those in the above-described embodiment will be denoted by the same reference numerals and their descriptions will be omitted or simplified. In the above-described embodiment, the plurality of gate electrodes 16 constituting the plurality of sets of elements 17 are arranged along a direction parallel to each short side portion 16a (i.e., the X-axis direction), but this is not limited to this. For example, a plurality of gate electrodes 16 may be provided on both sides that sandwich the first conductor 31 along a direction parallel to each long side portion 16b (i.e., the Y-axis direction). Figure 3 is a cross-sectional view showing the configuration of a modified field-effect transistor 10A of the embodiment. As shown in Figure 3, the modified field-effect transistor 10A includes, for example, a plurality of sets of elements 17, which consist of a plurality of first elements 17a arranged on the first side and a plurality of second elements 17b arranged on the second side of the two sides that sandwich the first conductor 31 along the Y-axis direction.
[0026] The modified field-effect transistor 10A includes, for example, a drain electrode 15 having a plurality of comb-shaped protrusions 15b extending toward the first conductor 31 along the Y-axis on both the first and second sides. Each gate electrode 16 in each of the plurality of first elements 17a and plurality of second elements 17b is arranged between adjacent protrusions 15b along the X-axis of the drain electrode 15. The plurality of gate electrodes 16 constituting the plurality of first elements 17a and the plurality of gate electrodes 16 constituting the plurality of second elements 17b are arranged, for example, at positions offset by a predetermined distance Lx along the direction parallel to each short side portion 16a (i.e., the X-axis direction). The predetermined distance Lx is, for example, half the distance between the centers of adjacent gate electrodes 16 along the X-axis direction.
[0027] According to a modified embodiment, the second conductor 32 connected to the gate electrode 16 of the first element 17a and the second conductor 32 connected to the gate electrode 16 of the second element 17b can be connected to different positions on the first conductor 31 while suppressing an increase in their respective lengths.
[0028] In the embodiment described above, the outer shape of the gate electrode 16 is a rectangular annular shape surrounding the outer periphery of the source region 21 and the source electrode 14, but it is not limited to this. For example, the outer shapes of the source region 21 and the source electrode 14 and the outer shapes of the drain region 22 and the drain electrode 15 may be interchanged. For example, the outer shape of the source electrode 14 may be comb-shaped, the outer shape of the drain electrode 15 may be rectangular, and the outer shape of the gate electrode 16 may be a rectangular annular shape surrounding the outer periphery of the drain region 22 and the drain electrode 15.
[0029] In the embodiments described above, the conductive layer 12 is a p-type diamond layer, but it is not limited to this, and may be an n-type diamond layer made of diamond to which donor impurities such as phosphorus atoms have been added.
[0030] The embodiments of the present invention are presented as examples and are not intended to limit the scope of the invention. These embodiments can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.
[0031] 10, 10A... Field-effect transistor, 11... Bulk layer, 12... Conductive layer, 13... Insulating layer, 14... Source electrode, 15... Drain electrode, 15a... Base end, 15b... Protruding part, 16... Gate electrode, 16a... Short side, 16b... Long side, 17... Element, 17a... First element, 17b... Second element, 21... Source region (First region), 22... Drain region (Second region), 23... Channel region, 31... First conductor, 32... Second conductor.
Claims
1. A field-effect transistor comprising: a bulk layer; a conductive layer provided at the leading edge of the bulk layer in a predetermined direction and having different thermal properties from the bulk layer; a source region, a drain region, and a channel region provided at the leading edge of the conductive layer in the predetermined direction; a source electrode provided at the leading edge of the source region in the predetermined direction, a drain electrode provided at the leading edge of the drain region in the predetermined direction, and a gate electrode provided at the leading edge of the channel region in the predetermined direction via an insulating layer; wherein the outer shape of the gate electrode in a plan view from the predetermined direction surrounds the outer periphery of a first region among the source region and the drain region, and a second region among the source region and the drain region is arranged around the outer periphery of the gate electrode, and the distance between the short side of the gate electrode and the source electrode or the drain electrode provided in the first region is relatively greater than the distance between the long side of the gate electrode and the source electrode or the drain electrode provided in the first region.
2. The field-effect transistor according to claim 1, wherein the conductive layer is a p-type diamond layer made of diamond doped with acceptor impurities, and the bulk layer is an i-type diamond layer made of intrinsic diamond semiconductor.
3. A field-effect transistor according to claim 1 or claim 2, comprising: a first conductor extending in a direction parallel to the short side at a position opposite to the short side; and a second conductor connecting the short side and the first conductor.
4. The field-effect transistor according to claim 3, wherein the first gate electrode and the second gate electrode, which are provided on both sides of the first conductor sandwiched along a direction parallel to the long side, are positioned so as to be offset by a predetermined distance along a direction parallel to the short side.