Electronic device and method for performing branch prediction

Abstract

The present disclosure provides an electronic device for performing branch prediction. A method for the electronic device may comprise the operations of: identifying an input branch instruction; and, on the basis of at least one of a plurality of BTB sets in a branch target buffer, performing prediction for acquiring a predicted target address for the input branch instruction. The plurality of BTB sets can include a first BTB set having first ways for random branch types including a return branch type, and a second BTB set having one or more second ways that are only for the return branch type, and the number of first ways of the first BTB set can be set to a value that is equal to the value of way set associativity of the BTB.

Description

Electronic device and method for performing branch prediction

[0001] The present disclosure relates to an electronic device and method for performing branch prediction.

[0002] Recent processors (e.g., CPUs) adopt a pipeline architecture to maximize performance, enabling the parallel processing of multiple instructions. However, for the efficient operation of the pipeline, branch prediction technology—which anticipates the results of branch instructions and executes them in advance—is crucial. This is because inaccurate branch prediction can lead to frequent pipeline flushing, resulting in performance degradation.

[0003] The branch target buffer (BTB) is a critical component of branch prediction. The BTB stores information regarding the address of a branch instruction and the target address to which it will jump, helping the processor predict the target address of the corresponding branch before executing the instruction. This reduces latency during the execution of branch instructions. Therefore, there is a growing need for technologies to improve the structure of the BTB in order to increase the accuracy of branch prediction and enhance pipeline performance.

[0004] The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure.

[0005] According to one embodiment, an electronic device may be provided. The electronic device may include at least one processor comprising a processing circuit and a memory comprising at least one storage medium for storing instructions. When the instructions are executed by the processor, the electronic device may cause at least one operation to be performed. The at least one operation may include an operation of identifying an input branch instruction. The at least one operation may include an operation of performing a prediction to obtain a predicted target address for the input branch instruction based on at least one of a plurality of BTB sets within a branch target buffer (BTB). The plurality of BTB sets may include a first BTB set comprising first ways for any branch types including a return branch type, and a second BTB set comprising one or more second ways used for the return branch type. Based on the fact that a branch instruction having the above return branch type is included in the first way of the first BTB set, the type of the branch instruction having the above return branch type can be identified through the type field included in the first way. Based on the fact that a branch instruction having the above return branch type is included in the second way of the second BTB set, the type of the branch instruction having the above return branch type can be identified without the type field.

[0006] According to one embodiment, a method of operation of an electronic device may be provided. The method of operation of the electronic device may include at least one operation. The at least one operation may include an operation of identifying an input branch instruction. The at least one operation may include an operation of performing a prediction to obtain a predicted target address for the input branch instruction based on at least one of a plurality of BTB sets within a branch target buffer (BTB). The plurality of BTB sets may include a first BTB set including first ways for any branch types including a return branch type, and a second BTB set including one or more second ways used for the return branch type. Based on the fact that a branch instruction having the return branch type is included in the first way of the first BTB set, the type of the branch instruction having the return branch type may be identified through a type field included in the first way. Based on the fact that a branch instruction having the above return branch type is included in the second way of the above second BTB set, the branch instruction having the above return branch type can be identified as a type without the type field.

[0007] According to one embodiment, a storage medium may be provided for storing at least one instruction readable by a computer. The at least one instruction may cause the electronic device to perform at least one operation when executed by at least a part of at least one processor of the electronic device. The at least one operation may include an operation of identifying an input branch instruction. The at least one operation may include an operation of performing a prediction to obtain a predicted target address for the input branch instruction based on at least one of a plurality of BTB sets within a branch target buffer (BTB). The plurality of BTB sets may include a first BTB set containing first ways for any branch types including a return branch type, and a second BTB set containing second ways used for the return branch type. Based on the branch instruction having the return branch type being included in the first way of the first BTB set, the branch instruction having the return branch type may be identified as a branch instruction type through a type field included in the first way. Based on the fact that a branch instruction having the above return branch type is included in the second way of the above second BTB set, the branch instruction having the above return branch type can be identified as a type without the type field.

[0008] In relation to the description of the drawings, the same or similar reference numerals may be used for identical or similar components.

[0009] FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments of the present disclosure.

[0010] FIG. 2a is a drawing illustrating the architecture of a processor according to one embodiment of the present disclosure.

[0011] FIG. 2b is a diagram illustrating the frontend configuration of the processor of FIG. 2a.

[0012] FIG. 2c is a diagram illustrating the configuration of a branch predictor included in the front-end configuration of the processor of FIG. 2b.

[0013] FIG. 2d is a drawing illustrating the configuration of a fetch block according to one embodiment of the present disclosure.

[0014] FIG. 3a is a flowchart illustrating an operation for performing branch prediction according to one embodiment of the present disclosure.

[0015] FIG. 3b is a drawing illustrating a baseline BTB structure according to one embodiment of the present disclosure.

[0016] FIG. 4a is a flowchart illustrating an operation to perform a BTB update according to one embodiment of the present disclosure.

[0017] FIG. 4b is a drawing illustrating information used for selecting a victim way according to one embodiment of the present disclosure.

[0018] FIG. 5 is a flowchart illustrating the branch prediction operation of an electronic device according to one embodiment of the present disclosure.

[0019] FIG. 6 is a drawing illustrating the configuration of a first BTB structure according to one embodiment of the present disclosure.

[0020] FIG. 7 is a drawing illustrating the configuration of a second BTB structure according to one embodiment of the present disclosure.

[0021] FIG. 8 is a flowchart illustrating a BTB update operation according to one embodiment of the present disclosure.

[0022] FIG. 9 is a flowchart illustrating an invalid entry search operation according to one embodiment of the present disclosure.

[0023] FIG. 10 is a flowchart illustrating a damage entry selection operation according to one embodiment of the present disclosure.

[0024] FIG. 11a is a drawing comparing the increase in BTB size of a first BTB structure and a second BTB structure according to an embodiment of the present disclosure as the number of return ways increases.

[0025] FIG. 11b is a diagram comparing the increase in BTB size of a baseline BTB structure with an increase in the value of the correlation according to one embodiment of the present disclosure.

[0026] FIG. 12 is a diagram comparing the performance of a second BTB structure according to an increase in the number of return ways, according to one embodiment of the present disclosure.

[0027] FIG. 13 is a drawing comparing the performance of a first BTB structure and a second BTB structure according to one embodiment of the present disclosure.

[0028] FIG. 14 is a drawing comparing the performance of a first BTB structure and a baseline BTB structure according to one embodiment of the present disclosure.

[0029] Hereinafter, embodiments of the present disclosure are described in detail with reference to the drawings so that those skilled in the art can easily practice them. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein. In relation to the description of the drawings, the same or similar reference numerals may be used for identical or similar components. Furthermore, in the drawings and related descriptions, descriptions of well-known functions and configurations may be omitted for clarity and brevity.

[0030] FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments of the present disclosure.

[0031] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) through a first network (198) (e.g., a short-range wireless communication network) or with an electronic device (104) or a server (108) through a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) through a server (108). According to one embodiment, the electronic device (101) may include a processor (120), memory (130), input module (150), sound output module (155), display module (160), audio module (170), sensor module (176), interface (177), connection terminal (178), haptic module (179), camera module (180), power management module (188), battery (189), communication module (190), subscriber identification module (196), or antenna module (197). In some embodiments, at least one of these components (e.g., connection terminal (178)) may be omitted from the electronic device (101), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (176), camera module (180), or antenna module (197)) may be integrated into a single component (e.g., display module (160)).

[0032] The processor (120) can control at least one other component (e.g., hardware or software component) of the electronic device (101) connected to the processor (120) by executing software (e.g., program (140)), and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (120) can store commands or data received from other components (e.g., sensor module (176) or communication module (190)) in volatile memory (132), process the commands or data stored in volatile memory (132), and store the resulting data in non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., central processing unit or application processor) or an auxiliary processor (123) that can operate independently or together with it (e.g., graphics processing unit, neural processing unit (NPU), image signal processor, sensor hub processor, or communication processor). For example, if the electronic device (101) includes a main processor (121) and an auxiliary processor (123), the auxiliary processor (123) may be configured to use lower power than the main processor (121) or to be specialized for a designated function. The auxiliary processor (123) may be implemented separately from the main processor (121) or as part thereof.

[0033] The auxiliary processor (123) may control at least some of the functions or states associated with at least one component of the electronic device (101) (e.g., display module (160), sensor module (176), or communication module (190)) on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (123) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (180) or communication module (190)). According to one embodiment, the auxiliary processor (123) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (101) itself where the artificial intelligence is performed, or through a separate server (e.g., server (108)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0034] The memory (130) can store various data used by at least one component of the electronic device (101) (e.g., processor (120) or sensor module (176)). The data may include, for example, input data or output data for software (e.g., program (140)) and related commands. The memory (130) may include volatile memory (132) or non-volatile memory (134).

[0035] The program (140) may be stored as software in memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0036] The input module (150) can receive commands or data to be used for a component of the electronic device (101) (e.g., processor (120)) from outside the electronic device (101) (e.g., user). The input module (150) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0037] The sound output module (155) can output a sound signal to the outside of the electronic device (101). The sound output module (155) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0038] The display module (160) can visually provide information to an external (e.g., user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0039] The audio module (170) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150) or output sound through the sound output module (155) or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (101).

[0040] The sensor module (176) can detect the operating state of the electronic device (101) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (176) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0041] The interface (177) may support one or more specified protocols that can be used for the electronic device (101) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (102)). According to one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0042] The connection terminal (178) may include a connector through which the electronic device (101) can be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0043] The haptic module (179) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module (179) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0044] The camera module (180) can capture still images and video. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0045] The power management module (188) can manage the power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0046] The battery (189) can supply power to at least one component of the electronic device (101). According to one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0047] The communication module (190) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may include one or more communication processors that operate independently of the processor (120) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a communication module (192) (e.g., cellular communication module, short-range communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (194) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (104) through a first network (198) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (199) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The communication module (192) can identify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (196).

[0048] The communication module (192) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The communication module (192) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The communication module (192) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The communication module (192) can support various requirements specified in the electronic device (101), external electronic device (e.g., electronic device (104)), or network system (e.g., second network (199)). According to one embodiment, the communication module (192) can support a Peak data rate (e.g., 20 Gbps or more) for eMBB realization, loss coverage (e.g., 164 dB or less) for mMTC realization, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for URLLC realization.

[0049] An antenna module (197) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (198) or a second network (199), may be selected from the plurality of antennas, for example, by a communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (197).

[0050] According to various embodiments, the antenna module (197) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0051] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface) and exchange signals (e.g., commands or data) with each other.

[0052] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) through a server (108) connected to a second network (199). Each of the external electronic devices (102, or 104) may be the same or different type of device as the electronic device (101). According to one embodiment, all or part of the operations performed on the electronic device (101) may be performed on one or more of the external electronic devices (102, 104, or 108). For example, if the electronic device (101) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (101) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (101) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In one embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server using machine learning and / or neural networks. According to one embodiment, the external electronic device (104) or the server (108) may be included within a second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0053] FIG. 2a is a drawing illustrating the architecture of a processor according to one embodiment of the present disclosure.

[0054] FIG. 2b is a diagram illustrating the frontend configuration of the processor of FIG. 2a.

[0055] FIG. 2c is a diagram illustrating the configuration of a branch predictor included in the front-end configuration of the processor of FIG. 2b.

[0056] FIG. 2d is a drawing illustrating the configuration of a fetch block according to one embodiment of the present disclosure.

[0057] Referring to FIGS. 2a and 2b, the processor (200) (e.g., the processor (120) of FIG. 1) may include a front end (201) and a back end (202).

[0058] According to one embodiment, the frontend (201) may be responsible for an initial stage of fetching and processing program instructions. The frontend (201) may perform the role of appropriately preparing instructions in the initial stage and transmitting them to the backend (202).

[0059] According to one embodiment, the frontend (201) may include an instruction fetch unit (220), a branch predictor (BP) (210), a branch prediction corrector (230), an instruction decoder (240), and / or an issue queue (250).

[0060] According to one embodiment, the instruction fetch unit (220) can perform the role of fetching instructions from memory or a cache (e.g., instruction (I)-cache) based on a program counter (PC).

[0061] According to one embodiment, the branch predictor (210) can perform a prediction for a branch instruction. If a prediction failure (miss prediction) occurs by the branch predictor, a pipeline flush occurs and performance may be degraded. Here, a pipeline flush may be, for example, an operation to clear all instructions in the pipeline to remove incorrect instructions (e.g., instructions executed due to a branch prediction failure) during the processor's instruction processing and replace them with correct instructions.

[0062] According to one embodiment, the instruction decoder (240) can interpret the instruction and convert it into a control signal that the processor (200) can understand. For example, the instruction decoder can analyze the code and operands of the instruction to determine what operation to perform.

[0063] According to one embodiment, the issue queue (250) may sequentially wait for commands interpreted by the command decoder and prepare them for delivery to the backend (202). The commands may be stored in the issue queue before being delivered to the appropriate execution unit later.

[0064] According to one embodiment, the backend (202) may perform the role of actually executing instructions retrieved from the frontend (201). For example, the backend (202) may handle instruction execution and the storage of operation results. The backend (202) may include an instruction scheduler, execution units, a register file, a reorder buffer (ROB), and / or a commit stage.

[0065] According to one embodiment, the instruction scheduler receives instructions from the issue queue, transmits them to an execution unit, and schedules and executes them.

[0066] According to one embodiment, the execution unit can actually perform the operation directed by the instruction. Each execution unit can process a specific type of operation.

[0067] According to one embodiment, a register file may be a high-speed memory that stores data used by an execution unit. The register file may store operands or operation results when the execution unit performs an operation.

[0068] According to one embodiment, the reorder buffer can perform the role of recording the results after executing instructions in an out-of-order execution processor by rearranging them in the order of the program.

[0069] According to one embodiment, the commit step may be a step of writing the result to a register file or memory after an instruction has been successfully executed. For example, the commit step may change the state by committing instructions in the order of the program.

[0070] Referring to FIGS. 2b and 2c, the front end (201) of the processor (200) may include a plurality of pipelines. For example, the front end (200) may include a branch predictor pipeline and an instruction fetch pipeline. The branch predictor pipeline may include a branch predictor (210), and the instruction fetch pipeline may include an instruction fetch unit (220). The branch predictor (210) and the instruction fetch unit (220) may be connected to a fetch target queue (FTQ) (230).

[0071] According to one embodiment, the FTQ (230) may perform the role of managing target addresses to fetch instructions. For example, the FTQ (230) may perform the role of a queue capable of storing target addresses of multiple instructions generated by the branch predictor (210). According to one embodiment, the FTQ (230) may include a queue used to sort blocks fetched from the instruction cache. According to one embodiment, the FTQ (230) may have a variable size that changes dynamically depending on the situation.

[0072] According to one embodiment, the FTQ (230) may process multiple branch prediction results of the branch predictor (210) in sequence and pass the target address to the instruction fetch unit (220). Through this FTQ (230), instructions can be fetched continuously without interrupting the pipeline. The FTQ (230) may include multiple FTQ entries. Each FTQ entry may correspond to an instruction block (fetch block) aligned to a specified size (e.g., 64 bytes) and may be fitted within a single instruction (I)-cache line (e.g., 64 bytes). In this disclosure, the FTQ (230) may also be referred to as a fetch queue (FT). According to one embodiment, the FTQ entries may span multiple cache lines or adapt to different cache line sizes.

[0073] According to one embodiment, the instruction fetch unit (220) may fetch one or more FTQ entries per cycle depending on the bandwidth of the I-cache. According to one embodiment, the i-cache is a cache that stores instructions, and the bandwidth may refer to the amount of data that the cache can process.

[0074] According to one embodiment, if a branch is resolved to be miss predicted, the FTQ (230) may be flushed. For example, if the expected path differs from the actual path where the program is executed, the processor (200) may determine that the branch is incorrectly predicted (predicted to be miss predicted), and in this case, the FTQ (230) may be flushed. Here, the branch may refer to, for example, a path that requires selection during program execution. The branch may be resolved, for example, at the decode stage or after execution. When the branch is resolved, the branch predictor (210)(s) may be updated. Here, resolving the branch may include checking the execution result of the branch instruction and / or performing a correction (or correction) after it is determined that the prediction was incorrect (predicted to be miss predicted). Here, modification (or correction) may include modifying (or correcting) the correct command flow. In this disclosure, the resolve of a branch may be expressed by various expressions having equivalent meanings, such as confirmation, confirmation, determination, judgment, correction, modification, and cleanup of a branch. For example, if a branch is resolved in the decoding phase, the branch predictor (210)(s) may be updated by a corrected branch target (e.g., post-fetch corrected target). That a branch is resolved in the decoding phase may mean, for example, that the branch is determined to be a prediction failure in the decoding phase, or that the branch is modified after being determined to be a prediction failure in the decoding phase. For example, if a branch is resolved after execution, the branch predictor (210)(s) may be updated by a resolved branch target.The fact that a branch is resolved after execution may include determining an error (branch error) after the branch is executed, for example, determining the branch error after the branch is executed and correcting the error, or verifying and cleaning up the branch result after the branch is executed. Through the update operation of this branch predictor (210), branch prediction can be performed more accurately when a similar situation occurs later.

[0075] According to one embodiment, the branch target buffer (BTB) (213) may be updated only when a branch is taken. According to one embodiment, the BTB (213) may be updated only when a branch is selected and taken (a taken branch). For example, since the BTB (213) is a buffer used to remember the target (e.g., target address) of a previously visited branch, when the same branch is reached again, it can be processed to move quickly using the information stored in the buffer.

[0076] According to one embodiment, the branch predictor (210) may operate ahead of the instruction fetch unit (e.g., instruction fetch pipeline) (220) and may store entries within the FTQ (230). The branch predictor (210) may include a return address stack (RAS) (211), an indirect predictor (212), a BTB (e.g., branch target buffer) (213), and / or a branch direction predictor (214) (e.g., TAGE). The branch predictor (210) may evaluate whether there is a branch instruction in a cache line and predict whether the branch will be fulfilled to provide the next target address for the subsequent cycle. The branch predictor(s) may provide the prediction result (whether it will be fulfilled) and may provide target addresses for the indirect type branch and the return type branch. A return type branch can be, for example, a branch instruction (e.g., the RET instruction) used to terminate a specific function or subroutine and return to the location where it was called. Return type branches can be used, for instance, to revert the program flow immediately after a function call or to return to the location where a subroutine was called when it finished. For instance, the return address is stored on the stack upon a function call, and the program can return to that return address when the RET instruction is executed.

[0077] According to one embodiment, RAS (211) can be used to store a return address when a subroutine is called and to return to that return address when the subroutine is completed.

[0078] According to one embodiment, the indirect predictor (212) can perform the role of predicting an indirect branch command.

[0079] According to one embodiment, the BTB (213) may store the target address of a previously executed branch instruction. Through the BTB (213), the target address of the branch instruction can be predicted, and the performance of the processor can be optimized. In the present disclosure, the BTB (213) may be referred to as the main BTB.

[0080] According to one embodiment, the branch direction predictor (214) can perform the role of predicting whether a branch instruction will be executed or not taken. Through the branch direction predictor (214), the direction of the branch can be predicted so that the flow of instructions can be optimized.

[0081] Referring to FIG. 2d, the fetch block (250) (or the address field of the fetch block (250)) may include tag information / field (251), offset information / field (252) and / or index information / field (253).

[0082] According to one embodiment, the tag field (251) is composed of the upper bits of a cache or memory address and can be used to determine which memory address the data stored in the cache actually corresponds to. For example, the tag field (251) can be used to find an entry containing a matching tag among several entries included in the BTB (213).

[0083] According to one embodiment, the offset field (252) may indicate the location (or offset) where a specific instruction (e.g., a branch instruction) is located within a fetch block. Since multiple instructions may be included within a fetch block, the offset may be used to identify where a specific instruction is located within the fetch block. For example, assuming the fetch block is 64 bytes in size, the offset may indicate the location where a specific instruction starts within the fetch block (e.g., bytes 0, 4, 8, 16).

[0084] According to one embodiment, the index field (253) may be used to locate a specific set within the BTB (213). For example, if the BTB (213) is configured in a set-associative manner, the index field (253) may be used to identify which set the corresponding fetch block is stored in. According to one embodiment, multiple branches may be detected and hit in the BTB (213) for a single index. For example, the maximum number of branch hits may be limited by the associativity of the BTB (213) (e.g., two BTB way0, BTB way1 associations).

[0085] FIG. 3a is a flowchart illustrating an operation for performing branch prediction according to one embodiment of the present disclosure.

[0086] FIG. 3b is a drawing illustrating a baseline BTB structure according to one embodiment of the present disclosure.

[0087] According to one embodiment, branch prediction may rely on a BTB hit through a BTB (e.g., BTB (213) in FIG. 2c). When a BTB hit occurs, other predictors (e.g., RAS (211), indirect predictor (212), branch direction predictor (214) in FIG. 2c) may perform predictions based on the branch type.

[0088] According to one embodiment, for a branch having a return branch type (return type branch), a RAS (e.g., RAS (211) of FIG. 2c) may provide a target address (branch target address). Thus, the target address of the BTB may not be used for the return type branch. The return type branch may be, for example, a branch instruction (e.g., a RET instruction) used to terminate a specific function or subroutine and return to the location where it was called. The return type branch may be used, for example, to return the program flow to immediately after a function call and to return to the location where it was called when a subroutine ends. For example, the return address is stored on the stack when the function is called, and when the RET instruction is executed, it can return to that return address.

[0089] According to one embodiment, for a branch having an indirect branch type (indirect type branch), if the prediction (indirect prediction) by an indirect predictor (e.g., the indirect predictor (212) of FIG. 2c) is successful, the indirect predictor may provide a branch target address, and if the indirect prediction fails, the BTB may provide a target address. For all other types of branches that are not return type branches or indirect type branches (e.g., conditional branches), the BTB may provide a target address. In this disclosure, the terms branch and branch instruction may be used interchangeably. For example, a branch being detected may be understood as a branch instruction being detected. An indirect branch may be an instruction that branches the flow of a program by referencing an address stored in a register or memory, for example, without using a direct address value. Indirect branches can be used, for example, when the address to branch to is dynamically determined during program execution. Conditional branches can be, for example, instructions that branch to a specified address only when a specific condition is true. For example, conditional branches may include instructions such as BEQ (branch if equal) and BNE (branch if Not Equal) that move only when a condition is true, but are not limited thereto.

[0090] According to one embodiment, a plurality of branches may be discovered (or detected) through a single BTB lookup. In the present disclosure, the number of branches (or branch instructions) detected through a single BTB lookup may be designated as "number_of_branches_detected". All branches detected by the BTB may be predicted by a branch predictor (e.g., branch predictor (210) of FIGS. 2b and 2c) until it is predicted that the branch will be executed. If no branch is predicted to be executed by the branch predictor(s), the target address may be the next instruction address used for the BTB lookup in the next cycle.

[0091] According to one embodiment, an FTQ entry may be generated in each cycle. The FTQ entry may include, for example, a virtual instruction start address, a terminating instruction offset, an instruction type (branch type) of each branch instruction, and / or a terminating instruction prediction in the case of a branch instruction.

[0092] Hereinafter, with reference to FIG. 3a, an example of a branch prediction operation of an electronic device (e.g., the electronic device (101) of FIG. 1) is described. To perform a branch prediction operation, the electronic device may first perform a BTB lookup on an input fetch block (e.g., the fetch block (250) of FIG. 2d). If the corresponding branch instruction is stored in the BTB, a BTB hit occurs and the corresponding branch instruction can be detected. Based on the number of branch instructions detected through the BTB lookup, the electronic device may run a loop such as the one exemplified in FIG. 3a to perform a prediction for each of the multiple branch instructions.

[0093] In operation 301, the electronic device may identify the first branch instruction among the branch instructions detected through a BTB lookup and set the counter of the branch instruction to 0. In the present disclosure, the counter of the branch instruction may be referred to as the branch counter.

[0094] In operation 303, the electronic device may determine whether the branch counter is less than number_of_branches_detected. If the branch counter is greater than or equal to number_of_branches_detected, the electronic device may terminate the branch prediction operation. If the branch counter is less than number_of_branches_detected, the electronic device may perform operation 305.

[0095] In operation 305, the electronic device may obtain branch-related information (e.g., branch instruction offset, branch target address, and / or information about the branch type) for the corresponding branch instruction from the BTB. The BTB may have at least one BTB table having a specified BTB structure, and each entry of the BTB table may include a BTB entry field. The specified BTB structure may include, for example, the baseline BTB structure of FIG. 3b, the first BTB structure of FIG. 6, and / or the second BTB structure of FIG. 7. An embodiment in which the electronic device obtains branch-related information from the BTB of the baseline BTB structure of FIG. 3b using information related to the fetch block (e.g., fields (251, 252, 253) of FIG. 2d) is described below with reference to FIG. 3b.

[0096] In operation 307, the electronic device can determine whether the branch type is a return branch type based on information about the branch type. If the branch type is a return branch type, the electronic device can perform operation 309. If the branch type is not a return branch type, the electronic device can perform operation 313.

[0097] In operation 309, the electronic device can use RAS to perform a prediction for the corresponding branch instruction (return type branch instruction). Through the prediction using RAS, the electronic device can obtain a target address for the corresponding branch instruction (branch target address). In operation 311, the electronic device can output the branch target address obtained (or predicted) from RAS.

[0098] In operation 313, the electronic device can determine whether the branch type is an indirect branch type. If the branch type is an indirect branch type, the electronic device can perform operation 315. If the branch type is not an indirect branch type, the electronic device can perform operation 319.

[0099] In operation 315, the electronic device may use an indirect predictor to perform a prediction for the corresponding branch instruction (indirect type branch instruction). If the prediction using the indirect predictor is successful, the electronic device may obtain the target address (branch target address) for the corresponding branch instruction from the indirect predictor. If the prediction using the indirect predictor fails, the electronic device may obtain the target address (branch target address) for the corresponding branch instruction from the BTB. In operation 317, the electronic device may output the branch target address obtained (or predicted) from the indirect predictor or the BTB.

[0100] In operation 319, the electronic device may use a branch direction predictor (e.g., the branch direction predictor (214) of FIG. 2c) to make a prediction for the corresponding branch instruction (e.g., other branch instructions that are not of return type and indirect type). The electronic device may use the branch direction predictor to predict whether the branch instruction is taken or not taken. In operation 321, the electronic device may identify whether it is predicted to be taken or not taken based on the prediction result of operation 319. In operation 323, based on the prediction that the branch instruction is taken, the electronic device may output a target address (branch target address) obtained from the BTB. In operation 325, if the prediction that the branch instruction is not taken, the address and instruction size of the current branch instruction may be output. Subsequently, in operation 327, the electronic device can increment the branch counter (e.g., increment by 1) and perform a prediction for the next branch instruction. By running a loop in this manner, a prediction can be performed for each of the multiple branch instructions included in the input fetch block. Meanwhile, as described above, the branch prediction operation of FIG. 3a can perform branch prediction using different predictors for each branch type based on information about the branch type obtained from the BTB.

[0101] Hereinafter, with reference to FIG. 3b, an example of a BTB structure used for branch prediction and a BTB lookup operation using said BTB structure will be described. In the present disclosure, the BTB structure of FIG. 3b may be referred to as a baseline BTB structure.

[0102] Referring to FIG. 3b, according to one embodiment, the baseline BTB structure may be set as a set-associative structure. For example, as illustrated in FIG. 3b, the baseline BTB structure may have an N-way set-associative structure. Here, the set may be a set of entries (or ways) that can be indexed by a single index value (301). In the present disclosure, ways and entries may be used interchangeably.

[0103] According to one embodiment, a BTB can be indexed in various ways. For example, a BTB can be indexed using a hash function based on the cache line start address of a fetch block (e.g., fetch block (250) of FIG. 2d). In this set-associative structure, the number of ways per set may be equal to the value of associativity (=N). For example, if the associativity is 8, the number of ways per set within the corresponding BTB (or BTB table) may be 8. Through a baseline BTB structure configured with this set-associative structure, multiple branch instructions can be processed simultaneously in parallel. In this disclosure, associativity may be referred to as way set associativity or set associativity.

[0104] According to one embodiment, the baseline BTB structure may include M sets. Here, M (>=1) may be the same as or different from N (>=1). A BTB table composed of such N ways and M sets may include N*M entries.

[0105] According to one embodiment, each entry of a BTB table may include a BTB entry field (320). The BTB entry field (320) may include, for example, a valid field, a tag field, a type field, an offset field, and / or a target address field.

[0106] According to one embodiment, the valid field may be a field of a specified size (e.g., 1 bit) indicating whether the entry is valid. For example, if set to a first value (e.g., 1 or true), the valid field may indicate that the entry is valid, and if set to a second value (e.g., 0 or false), the valid field may indicate that the entry is invalid. In the present disclosure, the valid field may be referred to as a "valid flag".

[0107] According to one embodiment, the tag field may include a tag value used to identify the address of the corresponding branch instruction within the fetch block. The tag field may be a field of a specified size (e.g., 8 bits) having a separate table for additional n-bit MSB (most significant bit) tag matching.

[0108] According to one embodiment, the type field may be a field of a specified size (e.g., 2 bits) representing the branch type of the branch instruction. The branch type may include, for example, a return branch type, an indirect branch type and / or other branch types (e.g., a conditional branch).

[0109] According to one embodiment, the offset field may indicate the location of a branch instruction. For example, the offset field may indicate the relative location of the branch instruction within a fetch block. The offset value of the offset field may be set to a value indicating, for example, how many bytes away the branch instruction is from the start address of the fetch block (e.g., the start address of the cache line). The offset field may, for example, be a 4-bit field for a 64-byte cache line. If the BTB index covers one or more cache lines, the offset value of the offset field may increase accordingly.

[0110] According to one embodiment, the target address field may be a field of a specified size (e.g., 64 bits) representing a target address. The target address may correspond to, for example, an address to jump to when it is predicted that the corresponding branch instruction will be executed. The target address field may occupy the largest area within the BTB entry.

[0111] According to one embodiment, the size of a BTB entry named "btb_entry_size" may be the sum of all bits of all fields within the entry. According to one embodiment, the total number of BTB entries named "number_of_btb_entries" and the size of the BTB named "btb_size" may be equal to the following Equation 1:

[0112] [Mathematical Formula 1]

[0113] number_of_btb_entries = sets * associativity

[0114] btb_size = number_of_btb_entries * btb_entry_size

[0115] Here, as described above, "sets" is the number of sets in the set-association structure, and "associativity" may be the degree of association in the set-association structure.

[0116] According to one embodiment, an electronic device may perform a BTB lookup using the patch block address field of a patch block. For example, when a new fetch block is requested by a processor (e.g., processor (200) of FIG. 2), the electronic device may perform a BTB lookup using the patch block address field of the corresponding patch block. According to one embodiment, the input for the BTB lookup may be fields of the fetch block (e.g., fields (251, 252, 253) of FIG. 2d) and / or a cache line start address.

[0117] According to one embodiment, the electronic device may determine whether to search for a set within the BTB by using the value of an index field (e.g., index field (253) in FIG. 2d) within the patch block address field. After discovering a specific set (e.g., set 1 in FIG. 3b) using an index (301) obtained based on the value of the index field, the electronic device may perform tag and offset comparisons for each entry within the set. Tag comparison may include, for example, comparing the value of a tag field in the BTB entry field (320) with the value of a tag field in the fetch block address field (e.g., tag field (251) in FIG. 2d). Offset comparison may include, for example, comparing the value of an offset field in the BTB entry field (320) with the value of an offset field in the fetch block address field (e.g., offset field (252) in FIG. 2d).

[0118] According to one embodiment, a branch hit condition through a BTB lookup may include the following two conditions:

[0119] - Condition 1: The value of the tag field of the BTB entry field (320) matches the value of the tag field of the fetch block address field.

[0120] - Condition 2: The value of the offset field of the fetch block address field is greater than or equal to the value of the offset field of the BTB entry field (320).

[0121] If both of these conditions are satisfied, it can be determined that a BTB has been hit. As BTB accuracy increases, the probability of failure in branch prediction may decrease.

[0122] According to one embodiment, multiple branches can be detected and hit within a BTB for a single index. The maximum number of branch hits, referred to as the "maximum number of branch hits," may be limited by the value of the associativity of the BTB.

[0123] FIG. 4a is a flowchart illustrating an operation to perform a BTB update according to one embodiment of the present disclosure.

[0124] FIG. 4b is a diagram illustrating information used for selecting a victim way according to one embodiment of the present disclosure.

[0125] According to one embodiment, the BTB update operation of FIG. 4a can be performed, for example, using the baseline BTB structure of FIG. 3b.

[0126] According to one embodiment, the BTB can be updated only for the taken branch.

[0127] According to one embodiment, an electronic device (e.g., the electronic device (101) of FIG. 1) can calculate a tag and / or index for an input branch instruction based on the start address (e.g., cache line start address) of a fetch block containing the branch instruction to be updated (input branch instruction). For example, the electronic device can calculate a tag and index for an input branch instruction based on the cache line start address of the corresponding fetch block and the address of the corresponding branch instruction. Depending on the BTB implementation method, different hash functions may be used for calculating the index and tag.

[0128] According to one embodiment, the electronic device can check for a matching entry through a BTB lookup. For example, the electronic device can check whether there is an entry (matching entry) in BTB[index] that has the same offset and tag as the input branch instruction. All ways in BTB (or BTB[index]) (e.g., way 0, ..., way N-1, where N is equal to associativity) can be checked for matching. If a matching entry is found, the electronic device can update this entry. If no matching entry is found, the electronic device can check for an invalid entry. An entry in way may be invalid if the value of the valid field of that entry is set to false (e.g., valid flag = false). This usually occurs at the start of the program or during the initial training of BTB[index]. If the valid field of an entry is set to true (e.g., valid flag = true), it may not be reset back to false. If an entry with a valid field value set to false (an invalid entry) is found, the electronic device may update this entry.

[0129] According to one embodiment, the electronic device may replace the least important entry. If no matching entry or invalid entry is found, the electronic device may replace the least important entry (e.g., victim entry) if all entries in BTB[index] are valid (e.g., learned at least once). The least important entry is, for example, the least important entry and may be an entry targeted for replacement for the accuracy of branch prediction. Ideally, the least recently used (LRU) algorithm should be used to determine the victim entry, but a pseudo-LRU (PLRU) algorithm may be used to improve hardware performance.

[0130] Hereinafter, with reference to FIGS. 4a and 4b, an example of information used to select a damaged entry during a BTB update operation and a BTB update operation is described. In the present disclosure, the information used to select a damaged entry may be referred to as PLRUm (PLRU based on MRU (most recently used)) information, PLRUm bit.

[0131] Referring to FIG. 4a, in operation 401, the electronic device can obtain a tag and / or index for a branch instruction to be updated (an input branch instruction). For example, the electronic device can calculate a tag and / or index for an input branch instruction based on the start address of a fetch block containing the input branch instruction (e.g., a cache line start address). For example, the electronic device can calculate a tag and index for a branch instruction based on the cache line start address of the corresponding fetch block and the address of the input branch instruction.

[0132] In operation 403, the electronic device may perform a BTB lookup. For example, the electronic device may perform a lookup on the entries of ways within the set(s) corresponding to BTB[index] based on the acquired tag and index. For example, when performing the BTB lookup, the electronic device may check all ways of BTB (or BTB[index]) (e.g., way 0, ..., way N-1, where N is equal to associativity) for matching.

[0133] In operation 405, the electronic device may determine whether an entry of any way (or all ways) within the set(s) corresponding to BTB[index] (e.g., a way entry within BTB[index]) has the same offset (branch instruction offset) and tag as an input branch instruction. If they have the same offset and tag, operation 407 may be performed. If they do not have the same offset and tag, operation 409 may be performed.

[0134] In operation 407, the electronic device can update an entry (matching entry) corresponding to a matched way within BTB[index] having the same offset and tag as the input branch command. The update of the matching entry may include, for example, updating the value of each field within the entry field of the matching entry (e.g., field (320) in FIG. 3b, field (751, 752) in FIG. 7) to a value corresponding to the input branch command.

[0135] In operation 409, the electronic device can determine whether any way entry (a way entry within BTB[index]) in the set corresponding to BTB[index] has a valid field / flag (valid flag = false). In other words, the electronic device can determine whether any BTB way entry having a valid flag of false exists in the set corresponding to BTB[index]. If the valid flag has a false value (valid flag = false), operation 411 may be performed. According to one embodiment, if the valid flag has a false value, the electronic device may determine that the entry is invalid. As described above, the valid flag becoming false may occur during training of the initial value, and once set to true, it may not be reset to false again. If the valid field / flag has a true value (valid flag = true), operation 413 may be performed.

[0136] In operation 411, the electronic device can update an entry in BTB[index] (an invalid entry in BTB[index]) corresponding to a way in which the valid field / flag has a false value (valid flag = false). The update of the invalid entry may include, for example, updating the value of each field in the entry field of the invalid entry (e.g., field (320) in FIG. 3b, field (751, 752) in FIG. 7) to a value corresponding to the input branch command.

[0137] In operation 413, the electronic device can acquire (or select) a damage way based on PLRUm information. The operation of selecting a damage way is described below with reference to FIG. 4b. In operation 415, the electronic device can update an entry (a damage way entry in BTB[index]) corresponding to the damage way in BTB[index]. The update of the damage way entry may include, for example, an operation of updating the value of each field within the entry field of the damage way entry (e.g., field (320) in FIG. 3b, field (751, 752) in FIG. 7) to a value corresponding to an input branch command.

[0138] Hereinafter, with reference to FIG. 4b, an example of a BTB replacement algorithm based on PLRU is described. The BTB replacement algorithm may be an example of a BTB replacement algorithm that utilizes PLRUm information based on the MRU (most recently used) characteristic. This algorithm uses PLRUm information containing a set of PLRUm bits, and each PLRUm bit may correspond to a way of the BTB. According to one embodiment, the PLRUm information may be included in the corresponding BTB table.

[0139] According to one embodiment, each way may have a PLRUm bit (1 bit per way).

[0140] According to one embodiment, when a way is accessed, the PLRUm bit corresponding to that way may be set to a first value (e.g., 1 or true). For example, the PLRUm bit state of cycle 8 in FIG. 4b shows that way 0 and way 3 were accessed between cycles 2 and 8. Whenever a way entry in BTB[index] is accessed during prediction and a transition is predicted by BP(s), or whenever a way entry in BTB[index] is updated, the corresponding PLRUm bit may be set to 1.

[0141] According to one embodiment, at least one PLRUm bit in the PLRUm information must always be 0. For example, as exemplified in the PLRUm bit state of cycle 9 of FIG. 4b, if all other PLRUm bits are 1 while way 2 is accessed, all PLRUm bits can be reset to 0 and the PLRUm bit of the accessed way can be set to 1. This prevents a deadlock situation in the PLRUm information.

[0142] According to one embodiment, the damage way may be selected based on the first entry where the PLRUm bit is 0. This method guarantees a good approximation of LRU and often outperforms tree-PLRU and other PLRU heuristics in cache replacement algorithms.

[0143] According to one embodiment, the number of PLRUm bits named "number of PLRUm bits" may be equal to the number of ways (or associativity) per set.

[0144] According to one embodiment, when selecting a damage way in any given cycle, the electronic device may select the first way having the first 0 value among the PLRUm bits as the damage way based on the left-to-right direction. For example, in cycle 2, the damage way may be way 0 (the way having the first 0 value among the PLRUm bits), in cycle 8, the damage way may be way 2 (the way having the first 0 value among the PLRUm bits), and in cycle 9, the damage way may be way 0 (the way having the first 0 value among the PLRUm bits).

[0145] Meanwhile, increasing the accuracy of branch predictions to reduce branch miss prediction rates has been the focus of research for decades. These efforts have primarily concentrated on the following two approaches:

[0146] a) First Approach: An approach that improves the branch direction predictor and increases the size of the BTB.

[0147] Conditional branches are the most common branches in workloads and generally have the highest miss prediction rates; therefore, much research has been conducted in the past to improve branch direction predictors. For example, various techniques have been developed focusing on increasing the prediction accuracy of branch direction predictors for CPUs, but there has been no significant innovation recently. Compared to TAGE (TAgged GEometric) predictors and their variants, the improvement of branch direction predictor accuracy appears to have reached a saturation point.

[0148] Additionally, while the size of the BTB can be increased simply by increasing the number of BTB entries (number_of_btb_entries), number_of_btb_entries is a design constraint and is difficult to set too high due to overall CPU silicon size constraints.

[0149] b) Second Approach: An approach that improves the accuracy and efficiency of BTB by optimizing the BTB structure and size

[0150] Through this second approach, the overall branch prediction ratio can be increased compared to the default BTB structure (e.g., the baseline BTB structure in Fig. 3b). For example, the first BTB structure and the second BTB structure in Figs. 6 and 7 may be BTB structures that follow this approach. Most research on the second approach focuses on maintaining the overall branch prediction accuracy while reducing the BTB size, or further improving accuracy by slightly increasing the BTB size.

[0151] The key idea of ​​the second approach is to detect as many implemented branches as possible (mostly conditional branches), thereby ensuring that most branches hit by the BTB are accurately predicted by the branch predictor.

[0152] However, storing all implemented branches in the BTB is impractical because it significantly increases the BTB size, and there are design constraints, particularly since a branch that has been implemented once is not always implemented. Therefore, the second approach aims to modify the BTB structure to reduce the size while maintaining accuracy, or to slightly increase the size to improve accuracy, rather than simply increasing the BTB size. Below, with reference to the respective figures, the first BTB structure and the second BTB structure modified in contrast to the baseline BTB structure of FIG. 3a according to the second approach are described, and an operation for performing branch prediction using at least one BTB table having the first BTB structure and the second BTB structure is described.

[0153] FIG. 5 is a flowchart illustrating the branch prediction operation of an electronic device according to one embodiment of the present disclosure.

[0154] FIG. 6 is a drawing illustrating the configuration of a first BTB structure according to one embodiment of the present disclosure.

[0155] FIG. 7 is a drawing illustrating the configuration of a second BTB structure according to one embodiment of the present disclosure.

[0156] Referring to FIG. 5, in operation 510, an electronic device (e.g., electronic device (101) of FIG. 1) can identify an input branch instruction (or a fetch block containing an input branch instruction). For example, the electronic device can identify an input branch instruction within a fetch block based on the fact that a fetch block (e.g., fetch block (250) of FIG. 2d) is requested by a processor (e.g., processor (200) of FIG. 2a).

[0157] In operation 520, the electronic device may perform a prediction to obtain a predicted target address for an input branch instruction based on at least one of a plurality of BTB sets within the BTB, using at least one branch predictor (e.g., the branch predictor (210) of FIG. 2b and 2c). According to one embodiment, the electronic device may perform operation 520 using at least one BTB table having a specified BTB structure. The specified BTB structure may include, for example, the baseline BTB structure (300) of FIG. 3a, the first BTB structure (600) of FIG. 6, and / or the second BTB structure (700) of FIG. 7. Operation 520 may include, for example, at least one of the branch prediction operations of FIG. 3a.

[0158] According to one embodiment, the first BTB structure (600) and the second BTB structure (700) may be BTB structures modified from the baseline BTB structure (300) of FIG. 3b. The first BTB structure (600) and the second BTB structure (700) may be structures that omit the target address field for at least one return type branch instruction from the BTB. As described above, since the return type branch instruction obtains the target address from the RAS (e.g., the RAS (211) of FIG. 2c), the target address is not required in the BTB. Therefore, the target address field, which occupies the most space (e.g., 64 bits) in the BTB, may be unnecessary. According to one embodiment, the number of ways included in each set of the first BTB structure and the second BTB structure may be set to a value equal to the value of the way set associativity of the BTB.

[0159] Hereinafter, with reference to FIG. 6, the first BTB structure (600) will be described exemplarily.

[0160] Referring to FIG. 6, the first BTB structure (600) may include a first BTB table (BTB table 1) dedicated to non-return type branch instructions and a second BTB table (BTB table 2) dedicated to return type branch instructions. The first BTB table includes N ways (way 0 to N-1), each way may include an entry that cannot predict a return type branch (return type branch instruction). The second BTB table includes K ways named "return way" (return way 0 to K-1), each return way may be reserved for a fetch block containing a return type branch (return type branch instruction). An entry of each way includes a target address field. For example, an entry of each way may include an entry field (310) that is included in an entry of the baseline BTB (300) of FIG. 3a. In contrast, each return way entry does not include a target address field. For example, each return way entry may include at least one of the fields from which the target address field is excluded from the entry field (310) included in the entry of the baseline BTB (300) of FIG. 3A.

[0161] According to one embodiment, the electronic device may obtain an index value (601) corresponding to an input branch command and determine whether to search for a set within the BTB using the index value (601). The index value (601) may be obtained, for example, based on an index field of a fetch block address field (e.g., index field (253) in FIG. 2d). For example, as illustrated in FIG. 6, the electronic device may identify that a second set (Set 1) is set to the same index value as the index value (601) and perform tag and offset comparisons for each entry in the second set (610) of the first BTB table and each entry in the second set (620) of the second BTB table. The tag comparison may include, for example, comparing the value of the tag field of the BTB entry field with the value of the tag field of the fetch block address field (e.g., tag field (251) in FIG. 2d). Offset comparison may include, for example, comparing the value of the offset field of the BTB entry field with the value of the offset field of the fetch block address field (e.g., the offset field (252) of FIG. 2d). The electronic device can identify whether a branch hit condition is satisfied by using the results of tag comparison and offset comparison.

[0162] The first BTB structure (600) of FIG. 6 described above has a technical challenge of determining how many ways to set to be dedicated to return type instructions. This depends heavily on the workload. For example, if only one way is set to be dedicated to the return type branch, performance may be significantly degraded in certain workloads that may require multiple return branch instructions per BTB set (index). Conversely, increasing the number of ways dedicated to the return branch type does not always improve performance in all workloads. Therefore, the first BTB structure (600) has limitations that need to be carefully managed on a workload-by-workload basis to balance performance across various workloads.

[0163] Below, with reference to FIG. 7, the second BTB structure (700) will be described exemplarily.

[0164] According to one embodiment, the second BTB structure (700) (or the first BTB table within the second BTB structure (700)) may have an N-way set-association structure.

[0165] Referring to FIG. 7, the second BTB structure (700) may include a first BTB table (BTB table 1) that handles all types of branch instructions (or multiple types of branch instructions including return type branch instructions) and a second BTB table (BTB table 2) used for return type branch instructions. The second BTB table (BTB table 2) may, for example, be dedicated to return type branch instructions or be used exclusively to return type branch instructions. For example, the second BTB table (BTB table 2) may include a second BTB set(s) that include one or more ways dedicated to return type branch instructions, or a second BTB set(s) that include one or more ways used exclusively to return type branch instructions.

[0166] According to one embodiment, a first BTB table includes N ways (way 0 to N-1, where N is equal to associativity), and each way may include an entry capable of predicting any type of branch (any type of branch instruction). In the present disclosure, a way of the first BTB table may be referred to as a first way, a basic way.

[0167] According to one embodiment, the second BTB table includes ways named K “return ways” (return way 0 to K-1, where K is the same as or different from N), and each return way may be reserved for a fetch block containing a return type branch (return type branch instruction). In other words, each return way may be used to predict only return type branches (return type branch instructions). In the present disclosure, the ways of the second BTB table may be referred to as the second way, the return way, or the dedicated return way. Thus, unlike the first BTB structure (600), the ways of the first BTB table in the second BTB structure (700) are not dedicated only to non-return branches. The second BTB structure (700) is configured so that each way of the first BTB table is used to predict all types of branch instructions, thereby allowing the ways to be utilized flexibly and efficiently.

[0168] According to one embodiment, each way entry of the first BTB table may include a first entry field (741). In the present disclosure, the way entry of the first BTB table may be referred to as the first entry and the first type entry. The first entry field (741) may include, for example, a valid field, a tag field, a type field, an offset field, and / or a target address field. The definition of each field included in the first entry field (741) may follow the definition of each corresponding field included in the entry field (320) of FIG. 3B. Thus, since the first entry field (741) is used to predict all types of return branch instructions including the return branch type, it must include a type field and a target address field.

[0169] According to one embodiment, each way entry of the second BTB table may include a second entry field (742). In the present disclosure, the return way entry of the second BTB table may be referred to as a second entry or a second type entry. The second entry field (742) may include, for example, a valid field, a tag field, and / or an offset field. The definition of each field included in the second entry field (742) may follow the definition of each corresponding field included in the entry field (320) of FIG. 3B. Thus, since the second entry field (742) is used to predict only the branch instruction of the return branch type, it is not necessary to include a target address field. Additionally, since the second entry field (742) is dedicated to the return branch type, there is no need to distinguish between types, so a type field may not be included.

[0170] According to one embodiment, the second BTB structure (700) may allow more return type branch instructions than the number of dedicated return ways (return_ways) for BTB[index](set) when necessary. For example, in the second BTB structure (700), the first BTB table may include at least one way for at least one return type branch instruction. In the present disclosure, the way for the return type branch instruction included in the first BTB table may be referred to as an extended return way.

[0171] According to one embodiment, the number of extended return instructions named "extended_return_insts" represents the maximum number of return type branch instructions (return instructions) that may exist among the ways (way 0 to way N-1) in BTB[index] (set). The total number of return instructions for both way (N) and return_way (X) is equal to the associativity.

[0172] extended_return_insts = associativity - X

[0173] Through this, the maximum number of return commands allowed in the second BTB structure (700) can be maintained as the same as the baseline BTB structure (e.g., the baseline BTB structure (300) of FIG. 3b).

[0174] According to one embodiment, the maximum number of return type branch instructions can maintain a maximum number of return instructions similar to the baseline BTB structure (e.g., the baseline BTB structure (300) of FIG. 3b).

[0175] According to one embodiment, the second BTB structure (700) can limit the maximum number of return type branch instructions in any given cycle to a value equal to the number of ways (i.e., associativity) per BTB index (set), just like the baseline BTB structure (e.g., baseline BTB structure (300) of FIG. 3b). By doing so, the second BTB structure (700) can ensure the same or improved workload performance without degrading performance, unlike the first BTB structure (600), which degrades performance compared to the baseline BTB structure as the number of return type branches increases.

[0176] According to one embodiment, an update of at least one BTB can be performed using a branch instruction offset, a branch type, and / or a cache line start address.

[0177] According to one embodiment, the second BTB structure (700) may complement and extend any other BTB structure that accesses the branch predictor (e.g., the baseline BTB structure (300) of FIG. 3b or the first BTB structure (600) of FIG. 6).

[0178] According to one embodiment, the second BTB structure (700) may further include a third BTB table (BTB table 3) that provides information about the type of way that the return type branch command was last accessed. For example, the second BTB structure (700) may include the third BTB table together with the first BTB table and the second BTB table. Unlike the first BTB structure (600) of FIG. 6, in the case of the second BTB structure (700), in addition to the return way (dedicated return way) in the second BTB table dedicated to the return type branch, a way (extended return way) for the return type branch may also be set in the first BTB table, so it is necessary to provide information to determine whether the return type branch command was last accessed from the return way or from the way. According to one embodiment, the third BTB table may include a single way named "last_access_return_way". Each entry of last_access_return_way may include last_access_return_way field / information. last_access_return_way information may be referred to as last_access_return_way bits. last_access_return_way information may be used to select a return way for BTB updates. According to one embodiment, the electronic device may use a third table to efficiently map return type branches by branching them into a return way method (e.g., a method dedicated to a specific command branch) and a way method (e.g., a method that handles all types of branch commands). For example, a true value stored in the last_access_return_way field (730) of the third table may be branched as the last accessed branch being a return way method, and a false value as a way.

[0179] According to one embodiment, the electronic device obtains an index value (701) corresponding to an input branch command and can determine whether to search for a set within the third BTB table using the index value (701). For example, if the index value (701) is a value corresponding to the second set (Set 1), the electronic device can obtain the last_access_return_way field / information included in the second set within the third BTB table.

[0180] Below, details of the second BTB structure (700) are exemplified.

[0181] (1) For way(s) (way 0 to way N-1) of the first BTB table,

[0182] Here, N is equal to the associativity of BTB (number of ways per set).

[0183] Ways can store predictions (e.g., predicted target addresses) for any type of branch.

[0184] Each entry (first type entry) may include a first entry field (741) including, for example, valid, tag, type, offset, and target address fields. In the present disclosure, the first entry field (741) may be referred to as the first type entry field.

[0185] (2) For the return way(s) (return_way 0 to return_way X-1) of the second BTB table,

[0186] Here, X is the number of return ways, which is a design choice, and X (1>=) may be the same as or different from N (1>=).

[0187] Return ways can be dedicated only to return type branch instructions.

[0188] Since the return type instruction fetches the target address in the RAS, each entry does not require a type and / or target address field. Each entry (second type entry) may include a second entry field (742) including, for example, Valid, Tag, and / or Offset fields. In this disclosure, the second entry field (742) may be referred to as the second type entry field.

[0189] (3) Regarding the calculation of index (701),

[0190] The index can be calculated from the cache line start address for the input fetch block.

[0191] Compatible with other BTB structures using different index calculation hash functions.

[0192] (4) Regarding PLRUm information,

[0193] PLRUm information can indicate whether the corresponding way has been accessed. For example, if the corresponding way has been accessed, the corresponding bit of PLRUm information is set to a first value (e.g., 1 or true), and if the corresponding way has not been accessed, the corresponding bit of PLRUm information can be set to a second value (e.g., 0 or false). The structure of PLRUm information used in the second BTB structure and the algorithm for setting the value of said information may follow, for example, the algorithm of FIG. 4b.

[0194] PLRUm information can be divided into the following two categories:

[0195] - Category 1: A PLRUm bit (PLRUm way bit) corresponding to a way can be allocated 1 bit for each way from way 0 to way N-1. PLRUm way information (751) containing PLRUm way bits can be included in a first BTB table. In the present disclosure, the PLRUm way information / table (751) may be referred to as a first MRU (most recently used) PLRU information / table.

[0196] - Category 2: PLRUm bits (PLRUm return_way bits) corresponding to the return way may be allocated 1 bit for each return_way from return_way 0 to return_way X-1. PLRUm return_way information (752) containing PLRUm return_way bits may be included in a second BTB table. In this disclosure, PLRUm return_way information / table (752) may be referred to as a second MRU PLRU information / table.

[0197] The total number of ways named "total_ways" is as follows:

[0198] total_ways = N + X

[0199] Here, N is the total number of ways, and X is the total number of return_ways.

[0200] (5) For the last_access_return_way (e.g., 1 bit) of the third BTB table,

[0201] The last_access_return_way information included in the entry of the last_access_return_way indicates which way entry was last accessed among ways (way 0 to way N-1) or return ways (return_way 0 to return_way X-1) during a prediction or update, while accessing a return type branch instruction from BTB[index]. If true (e.g., 1), the last_access_return_way information indicates that the entry from return ways (return entry) was last accessed. If false (e.g., 0), the last_access_return_way information indicates that the entry from ways (return entry) was last accessed.

[0202] According to one embodiment, the number of sets per table of each BTB table included in the second BTB structure (700) may be the same (e.g., each BTB table may include M sets) or different (e.g., the first BTB table may include M sets, and the second BTB table may include L sets different from M).

[0203] FIG. 8 is a flowchart illustrating a BTB update operation according to one embodiment of the present disclosure.

[0204] FIG. 9 is a flowchart illustrating an invalid entry search operation according to one embodiment of the present disclosure.

[0205] FIG. 10 is a flowchart illustrating a damage entry selection operation according to one embodiment of the present disclosure.

[0206] According to one embodiment, the BTB update operation of FIG. 8, the invalid entry search operation of FIG. 9, and the damaged entry selection operation of FIG. 10 may be operations that utilize, for example, the second BTB structure (700) of FIG. 7. The invalid entry search operation of FIG. 9 and the damaged entry selection operation of FIG. 10 may be operations included in the BTB update operation of FIG. 8.

[0207] Below, an example of a BTB update operation is described with reference to FIG. 8.

[0208] In operation 801, an electronic device (e.g., electronic device (101) of FIG. 1) can obtain information regarding the offset (branch instruction offset), type (branch type), and / or cache line start address for the branch instruction (input branch instruction) to be updated. According to one embodiment, the branch instruction offset, branch type, and / or cache line start address are required for the BTB update. Unlike the BTB update operation of FIG. 4a, the BTB update operation of FIG. 8, which uses the second BTB structure (700), requires information regarding the branch type for the BTB update. For example, the BTB update operation of FIG. 8 can efficiently perform the update operation for the branch type instruction in a different way based on the information regarding the branch type.

[0209] In operation 803, the electronic device can determine whether the branch type is a return branch type based on information about the branch type. If the branch to be updated in BTB[index] is a return type branch, operation 805 may be performed. If the branch to be updated in BTB[index] is not a return type branch (i.e., a non-return type branch), operation 807 may be performed. Operation 807 may proceed in the same manner as the BTB update operation following the update algorithm of FIG. 4a. Operation 807 may include, for example, at least one of operations 401 to 415 of FIG. 4a.

[0210] In operation 805, the electronic device may obtain a tag and / or index for a branch instruction to be updated (an input branch instruction). For example, the electronic device may calculate a tag and / or index for an input branch instruction based on the start address of a fetch block containing the input branch instruction (e.g., a cache line start address). For example, the electronic device may calculate a tag and index for a branch instruction based on the cache line start address of the corresponding fetch block and the address of the input branch instruction.

[0211] In operation 809, the electronic device may perform a BTB lookup (e.g., a BTB[index] lookup). For example, the electronic device may perform a lookup (query) on the entries of ways within the set(s) corresponding to BTB[index] (e.g., the first set (710) of the first BTB table in FIG. 7, the second set (720) of the second BTB table, and / or the third set (730) of the third BTB table) based on the acquired tags and index.

[0212] In operation 811, to check for a matching entry for a return type branch, the electronic device may calculate the number of return instructions currently existing within the ways (e.g., from way 0 to way N-1) (num_return_insts). This number cannot exceed extended_return_insts. According to one embodiment, extended_return_insts may include the maximum number of return type branch instructions that may exist at btb[index] among the ways (from way 0 to way N-1).

[0213] In operation 813, the electronic device can find an entry (matching entry) that has the same offset and tag as the input branch instruction in the ways (extended return ways) (0 to N-1) or return_ways (dedicated return ways) (0 to X-1) of BTB[index]. If a matching entry is found through operation 813, the electronic device can update the entry. Through this, the update of BTB is completed.

[0214] In operation 815, based on the discovery of a matching entry, the electronic device may update the entry (matching entry) corresponding to the matched way or return way within BTB[index]. The update of the matching entry may include, for example, updating the value of each field within the entry field of the matching entry (e.g., fields (751, 752) of FIG. 7) to a value corresponding to the input branch command.

[0215] In operation 817, based on the fact that no matching entry is found, the electronic device may find an invalid entry in BTB[index] through a specified invalid entry finding algorithm. In this disclosure, the invalid entry finding algorithm may be referred to as an invalid entry checking algorithm.

[0216] According to one embodiment, the electronic device may find a suitable invalid entry and perform an update on the return type branch. For example, if no matching entry is found, the electronic device may perform the invalid entry discovery operation of FIG. 9. The invalid entry discovery operation of FIG. 9 may be performed, for example, by using a specified invalid entry verification algorithm.

[0217] According to one embodiment, for a return type branch instruction, finding an invalid entry in the return ways (from return_way 0 to return_way X-1) is prioritized. For example, operation 901 of FIG. 9 may be performed prior to operation 905. According to one embodiment, if an invalid entry is found within the return ways, the electronic device updates the entry. If no invalid entry is found within the return ways, the electronic device searches for an invalid entry within the ways (from way 0 to way N-1). If an invalid entry is found within the ways and num_return_insts is less than extended_return_insts, the electronic device may update the invalid entry. This completes the BTB update. Otherwise, a replacement damaged way entry is found through the damaged way selection operation of FIG. 10. The damaged way selection operation may be performed using, for example, a specified PLRUm algorithm (e.g., MPLRUm algorithm).

[0218] Below, with reference to FIG. 9, an example of an invalid entry detection operation will be described.

[0219] In operation 901, the electronic device can determine whether an entry (any BTB return_way entry) of any return way (return_way 0 to return_way X-1) in the set corresponding to BTB[index] has its valid flag set to false (valid flag = false). In other words, the electronic device can determine whether any BTB return_way entry with a valid flag value of false exists in the set corresponding to BTB[index]. If the valid flag of an entry is set to false, the electronic device can identify the entry as invalid. The valid flag being set to false may occur primarily during the initial learning of BTB[index] at the start of the program. Once the valid flag is set to true, it is not changed back to false. If valid flag is set to false, operation 903 may be performed. If valid flag is set to true, operation 905 may be performed.

[0220] In operation 903, the electronic device can update an entry in BTB[index] (an invalid entry in BTB[index]) corresponding to a return way set to valid flag = false. The update of the invalid entry may include, for example, updating the value of each field in the entry field of the invalid entry (e.g., the second entry field (752) of FIG. 7) to a value corresponding to an input branch command.

[0221] In operation 905, the electronic device can determine whether an entry (any BTB way entry) of any way (way 0 to way N-1) in the set corresponding to BTB[index] has its valid flag set to false (valid flag = false). In other words, the electronic device can determine whether any BTB way entry with a valid flag value of false exists in the set corresponding to BTB[index]. If the valid flag of an entry is set to false, the electronic device can identify the entry as invalid. The valid flag being set to false may occur primarily during the initial learning of BTB[index] at the start of the program. Once the valid flag is set to true, it is not changed back to false. If valid flag is set to false, operation 907 may be performed. If valid flag is set to true, operation 909 may be performed.

[0222] In operation 907, the electronic device can determine whether the number of return instructions (number_return_insts) is less than the number of extended return instructions (extended_return_insts). If number_return_insts is less than extended_return_insts, operation 913 may be performed. In operation 913, the electronic device may update the entry in BTB[index] (invalid entry in BTB[index]) corresponding to the way having valid flag = false. The update of the invalid entry may include, for example, updating the value of each field within the entry field of the invalid entry (e.g., the first entry field (751) in FIG. 7) to a value corresponding to the input branch instruction. If number_return_insts is not less than extended_return_insts, operation 909 may be performed. In this case, because no more ways for return type instructions can be added due to the limit on the number of extended return instructions, the selection of a victim way is required.

[0223] In operation 909, the electronic device may select a victim way (victim_way) through a specified PLRUm algorithm (MPLRUm algorithm). In operation 911, the electronic device may replace an entry in BTB[index] corresponding to the victim way. The update of the victim way entry may include, for example, an operation to update the value of each field within the entry field of the victim way entry (e.g., fields (751, 752) of FIG. 7) to a value corresponding to the input branch command.

[0224] According to one embodiment, the victim way selection operation of operation 909 may include, for example, the victim way selection operation of FIG. 10. The PLRUm algorithm (MPLRUm algorithm) used for the victim way selection operation of FIG. 10 is different from the basic PLRUMs algorithm used for the victim way selection operation of FIG. 4a (e.g., operation 413), but the PLRUm bit assignment algorithm for generating PLRUm information of FIG. 4b and the structure of the generated PLRUm information are maintained identically. The proposed MPLRUm algorithm is required to select the victim way when updating BTB[index] with a return type branch instruction.

[0225] According to one embodiment, an electronic device may select a victim way from return ways or ways based on last_access_return_way information. As described above, last_access_return_way information indicates whether a return type branch command was last accessed in return ways (from return_way 0 to return_way X-1) or in ways (from way 0 to way N-1). If the return type branch command was last accessed in ways (from way 0 to way N-1), the last_access_return_way information may be set to a first value (e.g., 0). If the return type branch command was last accessed in return ways (from return_way 0 to return_way X-1), the last_access_return_way information may be set to a second value (e.g., 1). Based on the last_access_return_way information, the electronic device may preferentially select a victim way from a way other than the last accessed way. This is because a way other than the last accessed way corresponds to a way that is used less frequently.

[0226] According to one embodiment, the electronic device may select a victim way from the return ways. For example, the electronic device may select the first victim_way from the return ways (return_way 0 to return_way X-1) where the PLRUm return_way bit is 0, based on the PLRUm return_way information (e.g., PLRUm return_way bits (751) of FIG. 7) being set to a first value indicating that the return type branch last accessed the way. (Always, at least one bit is set to 0).

[0227] According to one embodiment, the electronic device may select a victim way from the ways. For example, the electronic device may select the first victim_way in ways (way 0 through way N-1) where the corresponding PLRUm return_way bit is 0, based on PLRUm way information (e.g., PLRUm way bits (752) of FIG. 7) being set to a second value indicating that the return type branch last accessed the return way. (Always, at least one bit is set to 0).

[0228] Below, with reference to FIG. 10, an example of a damage way selection operation will be described.

[0229] In operation 1001, the electronic device can determine whether the last_access_return_way information is set to 0. If the last_access_return_way information is set to 0 (e.g., the return type branch was last accessed on a way), the electronic device can select a victim way from the return ways (from return_way 0 to return_way X-1). In this case, since the return type branch was last accessed on a way, the victim way may be set on a relatively less used return way. If the last_access_return_way information is set to 1 (e.g., the return type branch was last accessed on a return way), the electronic device can preferentially select a victim way from the ways (from way 0 to way N-1). In this case, since the return type branch was last accessed on a return way, the victim way may be set on a relatively less used way.

[0230] In operation 1003, based on the last_access_return_way information being set to 0, the electronic device checks the corresponding PLUMs return way bit (the first PLUMs return way bit) that has a value of 0 in the return ways (return_way 0 to return_way X-1) and can select the corresponding return way as the victim way. For an explanation of the selection of the victim way based on the PLUMs return way information, refer to the explanation in FIG. 4b.

[0231] In operation 1005, based on the last_access_return_way information being set to 1, the electronic device can determine whether the number of return instructions (number_return_insts) in the ways (way 0 to way N-1) is equal to the number of extended return instructions (extended_return_insts). If number_return_insts and extended_return_insts are equal, operation 1007 may be performed. Through this, the first entry satisfying the condition with a return type branch instruction where the PLRUm bit is 0 is selected as the victim way. If there is no such entry, the victim way may be selected from the return ways. If number_return_insts and extended_return_insts are not equal, operation 1019 may be performed.

[0232] In operation 1007, the electronic device may identify the first way and set the way index of that way to 0. In operation 1009, the electronic device may determine whether the way index is less than N (= associativity). If the way index is less than N, operation 1011 may be performed. If the way index is not less than N, operation 1003 may be performed.

[0233] In operation 1011, the electronic device may determine whether an entry in the way is a return instruction and whether the PLUMs bit corresponding to that entry is 0. If an entry in the way is a return instruction and the PLUMs bit corresponding to that entry is 0, operation 1013 may be performed. Otherwise, operation 1017 may be performed. In operation 1013, the electronic device may select the way as a victim way. In operation 1017, the electronic device may increment the way index (e.g., by 1) and repeat operations 1009 through 1017 for the next way. These loop operations may be performed sequentially for ways until a victim way is selected.

[0234] In operation 1019, the electronic device checks the corresponding PLUMs way bits that have a value of 0 and can select the corresponding way as the victim way (the first PLUMs return way bit). For example, if num_return_insts is less than extended_return_insts, the electronic device can select the victim_way from the ways. For an explanation of the selection of the victim way based on PLUMs way information, refer to the description in FIG. 4b. This means that since the number of return instructions in the ways (way 0 to way N-1) is less than the number of extended return instructions, another entry can be selected as a substitute for the return type branch.

[0235] In operation 1021, the electronic device may replace the victim way entry with an input branch command to be updated. The update of the victim way entry may include, for example, an operation to update the value of each field within the entry field of the victim way entry (e.g., fields (751, 752) of FIG. 7) to a value corresponding to the input branch command.

[0236] The operation described in FIGS. 8 to 10 above allows return type branch instructions to be managed efficiently, minimizes the impact on performance, and prioritizes the optimal use of BTB storage space. The MPLRUm algorithm described above can resolve the limitations of the BTB structure by flexibly processing return type branches.

[0237] FIG. 11a is a drawing comparing the increase in BTB size of a first BTB structure and a second BTB structure according to an embodiment of the present disclosure as the number of return ways increases.

[0238] FIG. 11b is a diagram comparing the increase in BTB size of a baseline BTB structure with an increase in the value of the correlation according to one embodiment of the present disclosure.

[0239] The embodiments of FIGS. 11a and 11b follow the simulation settings of Table 1 below.

[0240]

[0241] Table 1 shows the settings for the size of the fields included in the BTB entry field, the size of the PLRUm bit, the number of BTB sets (=256), and the associativity (=8). The simulation is performed through a specified framework (e.g., the open-source gem5 framework). The number of sets is applied equally to the BTB table of the baseline BTB structure, each BTB table of the first BTB structure (e.g., the first BTB structure (600) of FIG. 6), and each BTB table of the second BTB structure (e.g., the second BTB structure (700) of FIG. 7), and the same index function is used to access the return way and the base way.

[0242] FIG. 11a compares the increase in BTB storage for the first BTB structure and the second BTB structure with respect to an increase in the number of return ways (X). This increase is relative to a baseline BTB structure with associativity=8 (e.g., the baseline BTB structure (300) of FIG. 3b). For example, when the number of return ways is 1, the storage space of the first BTB structure and the second BTB structure increases by approximately 3% compared to the storage space of the baseline BTB structure. As exemplified in FIG. 11a, the increase in BTB size between the first and second methods with respect to an increase in the number of return ways (X) is negligible. This is because the additional size required in the second BTB structure compared to the first BTB structure is only 1 bit of last_access_return_way information for each BTB[index].

[0243] Figure 11b compares the increase in BTB size of a baseline BTB structure with increasing associativity. For example, increasing the associativity in the baseline BTB structure by just 1 (e.g., from 8 to 9) increases the total BTB size by 13%. This increase is due to the fact that each BTB entry in the baseline BTB structure includes a target address field. Therefore, simply increasing associativity is not feasible within a limited hardware budget. In contrast, if a second BTB structure is used instead of the baseline BTB structure, return ways can be efficiently added while minimizing the impact on the total BTB storage size. This can be achieved without significantly increasing the BTB size and can provide a more practical solution than increasing associativity in the baseline BTB structure.

[0244] FIG. 12 is a diagram comparing the performance of a second BTB structure according to an increase in the number of return ways, according to one embodiment of the present disclosure.

[0245] FIG. 13 is a drawing comparing the performance of a first BTB structure and a second BTB structure according to one embodiment of the present disclosure.

[0246] FIG. 14 is a drawing comparing the performance of a first BTB structure and a baseline BTB structure according to one embodiment of the present disclosure.

[0247] In the simulation example of FIG. 12, the simulation settings follow the settings of Table 1, assuming that associativity is fixed at 8, and the performance values ​​correspond to relative performance based on the performance of a baseline BTB structure with associativity set to 8 (e.g., baseline BTB structure (300) of FIG. 3b). return_ways #1 shows the performance relative to the baseline BTB structure for each workload in the settings of return_ways = 1 and associativity = 8 (3% increase in BTB size), return_ways #2 shows the performance relative to the baseline BTB structure for each workload in the settings of return_ways = 2 and associativity = 8 (7% increase in BTB size), and return_ways #3 shows the performance relative to the baseline BTB structure for each workload in the settings of return_ways = 3 and associativity = 8 (10% increase in BTB size).

[0248] As illustrated in FIG. 12, in the second BTB structure (e.g., the second BTB structure (700) of FIG. 7), it can be seen that performance is improved or remains the same even if the number of return ways increases. For example, it can be seen that performance is significantly improved even when the number of return ways increases by 2 and the BTB size increases by about 7%. For example, in the "PDF rendering," "horizon detection," and "speech recognition" workloads, performance increases by 1% to 2%; in the "image compression," "N-Body physics," and "image restoration" workloads, performance increases by 2% to 3%; in the "HTML5" and "camera" workloads, performance increases by 4% to 5%; and in the "SQLite" and "face recognition" workloads, performance increases by more than 6%.

[0249] In the simulation example of Fig. 13, the simulation settings follow the settings of Table 1, and it is assumed that the number of return ways is fixed at 2 and the associativity is fixed at 8, and the performance value corresponds to the relative performance based on the performance of the baseline BTB structure with associativity = 8.

[0250] As illustrated in Fig. 13, the second BTB structure demonstrates relatively improved performance compared to the first BTB structure under the same conditions. For example, the method using the second BTB structure shows a performance improvement of more than 6% compared to the method using the first BTB structure for specific workloads (e.g., "HTML5," "face recognition"). Additionally, the second BTB structure maintains or improves overall performance, providing a more stable basis for determining design choices such as the number of return ways.

[0251] In the simulation example of Fig. 14, the simulation settings follow the settings of Table 1, and the number of return ways for the second BTB structure is set to 2 and the associativity is set to 8, and the associativity of the baseline BTB structure is set to 10, and a performance comparison is shown.

[0252] As exemplified in Figure 14, the baseline BTB structure increases the BTB size by 25% as associativity increases from 8 to 10, and while the performance improvement rate of the baseline BTB is similar to that of the second BTB structure for most workloads, performance drops significantly in the "Clang" workload.

[0253] With the second BTB structure, the BTB size increases by only 7% as the return way is set to 2, yet the performance improvement rate of the baseline BTB is similar to that of the second BTB structure for most workloads. As such, the second BTB structure can maintain the same or similar performance while requiring 18% less storage space to increase associativity. Thus, utilizing the second BTB structure can provide an efficient and space-saving solution for improving BTB performance. This can be an approach that yields significant benefits without drastically changing the microarchitecture parameters of the processor (e.g., CPU).

[0254] According to one embodiment of the present disclosure, an electronic device may include at least one processor comprising a processing circuit; and a memory comprising at least one storage medium for storing instructions. The electronic device may identify an input branch instruction and perform a prediction to obtain a predicted target address for said input branch instruction based on at least one of a plurality of BTB sets within a branch target buffer (BTB). The plurality of BTB sets may include: a first BTB set comprising first ways for any branch types including a return branch type, and a second BTB set comprising one or more second ways used for said return branch type. When a branch instruction having said return branch type is included in a first way of the first BTB set, the type of the branch instruction having said return branch type may be identified through a type field included in said first way. When a branch instruction having the above return branch type is included in the second way of the above second BTB set, the branch instruction having the above return branch type can be identified as a type without the above type field.

[0255] According to one embodiment, the second BTB set may include one or more second ways dedicated to the return branch type (return type branch instruction), or one or more second ways used exclusively to the return branch type (return type branch instruction).

[0256] According to one embodiment, the number of the first ways of the first BTB set is set to a value equal to the value of the way set associativity of the BTB, and the number of the second ways of the second BTB set is set to be less than or equal to the value of the way set associativity, and among the first ways of the first BTB set, the number of first ways including a branch command having the return branch type can be set up to a value obtained by subtracting the number of the second ways of the second BTB set from the value of the way set associativity.

[0257] According to one embodiment, the plurality of BTB sets further include a third BTB set including a third way, and the third way of the third BTB set may include last access return way information indicating whether a branch instruction having the return branch type was last accessed from the first way of the first BTB set or the second way of the second BTB set.

[0258] According to one embodiment, each first way of the first BTB set includes a first type entry for a branch instruction, and each second way of the second BTB set includes a second type entry for a branch instruction, wherein the first type entry includes a type field and a target address field indicating the target address of the corresponding branch instruction, and the type field and the target address field may not be included in the second type entry.

[0259] According to one embodiment, the first type entry and the second type entry may include at least one of: validity information indicating whether the entry associated with the corresponding branch instruction is valid, tag information including a tag for identifying the corresponding branch instruction, and offset information including an offset associated with the location of the corresponding branch instruction.

[0260] According to one embodiment, the first BTB set, the second BTB set, and the third BTB set have the same index, and the index is associated with address information of the input branch instruction, and the address information may include at least one of the cache line address or the instruction address of the input branch instruction.

[0261] According to one embodiment, the electronic device can update the BTB based on the branch type information of the input branch command.

[0262] According to one embodiment, the update operation of the BTB may include: an operation of identifying whether the branch type of the input branch instruction is a return branch type based on the branch type information of the input branch instruction; an operation of determining whether a matching entry for the input branch instruction exists within the first BTB set or the second BTB set based on offset information and tag information of the input branch instruction based on identifying that the branch type is a return branch type; and an operation of updating the matching entry if the matching entry exists.

[0263] According to one embodiment, the update operation of the BTB may include: an operation to determine whether the invalid entry exists in the second BTB set based on valid information of the ways of the second BTB set when the matching entry does not exist; and an operation to update the invalid entry when the invalid entry exists in the second BTB set.

[0264] According to one embodiment, the update operation of the BTB may include: an operation to determine whether the invalid entry exists in the first set based on valid information of the ways of the first BTB set when the invalid entry does not exist in the second BTB set; and an operation to determine whether to update the invalid entry based on the number of the first ways of the first BTB set including the branch instruction having the return branch type, based on whether the invalid entry exists in the first BTB set.

[0265] According to one embodiment, the operation of determining whether to update the invalid entry may include: an operation of updating the invalid entry when it is determined to update the invalid entry; and, when it is determined not to update the invalid entry, an operation of selecting a victim way for updating the input branch instruction from the first ways in the first BTB set or the second ways in the second BTB set based on the last access return way information in the third way of the third BTB set.

[0266] According to one embodiment, when the last access return way information is set to a first value indicating that a branch command having the return branch type is last accessed from a first way within the first BTB set, the method may include: an operation of selecting the damaged way from the second ways within the second BTB set based on second MRU (most recently used) PLRU (pseudo least recently used) information for the second ways; and when the last access return way information is set to a second value indicating that a branch command having the return branch type is last accessed from a second way within the second BTB set, the method may include an operation of selecting the damaged way from the first ways within the first BTB set based on first MRU PLRU information for the first ways.

[0267] According to one embodiment, the first MRU PLRU information includes a number of bits equal to the number of first ways of the first BTB set, and each bit of the first MRU PLRU information indicates whether the corresponding first way of the first BTB set has been accessed, and the second MRU PLRU information includes a number of bits equal to the number of second ways of the second BTB set, and each bit of the second MRU PLRU information indicates whether the corresponding second way of the second BTB set has been accessed.

[0268] The embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" each may include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish said components from other said components and do not limit said components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as “coupled” or “connected” to another (e.g., 2nd) component, with or without the terms “functionally” or “communicationly,” it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0269] The term “module” as used in the embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0270] One embodiment of the present document may be implemented as software (e.g., program (140) of FIG. 1) comprising one or more instructions stored in a storage medium (e.g., internal memory (136) of FIG. 1 or external memory (138) of FIG. 1) that is readable by a machine (e.g., electronic device (101) of FIG. 1). For example, a processor (e.g., processor (120) of FIG. 1) of the machine (e.g., electronic device (101) of FIG. 1) may call at least one of the one or more instructions stored from the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0271] According to one embodiment, the method according to the embodiments disclosed herein may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0272] According to one embodiment, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to one embodiment, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to one embodiment, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In an electronic device, At least one processor including a processing circuit; and It includes memory comprising at least one storage medium for storing instructions, and When the above instructions are executed individually or collectively by the at least one processor, the electronic device: Identify input branch commands, Causing to perform a prediction to obtain a predicted target address for the input branch instruction based on at least one of a plurality of sets of BTBs within a branch target buffer (BTB), and The above multiple BTB sets are: A first BTB set including first ways for any branch types including a return branch type, and It includes a second BTB set comprising one or more second ways used for the above return branch type, and Based on the fact that a branch instruction having the above return branch type is included in the first way of the above first BTB set, the type of the branch instruction having the above return branch type is identified through the type field included in the above first way, and An electronic device in which, based on the fact that a branch instruction having the above return branch type is included in the second way of the above second BTB set, the branch instruction having the above return branch type is identified as a type without the type field.

2. In Paragraph 1, The number of the first ways of the first BTB set is set to a value equal to the value of the way set associativity of the BTB, and The number of the second ways of the second BTB set is set to be less than or equal to the value of the way set association, and An electronic device, wherein among the first ways of the first BTB set, the number of first ways including a branch command having the return branch type can be set up to a value obtained by subtracting the number of second ways of the second BTB set from the value of the way set association.

3. In Paragraph 1, The above multiple BTB sets are: An electronic device further comprising a third BTB set including a third way, wherein the third way of the third BTB set includes last access return way information indicating whether a branch instruction having the return branch type was last accessed from the first way of the first BTB set or the second way of the second BTB set.

4. In Paragraph 1, Each first way of the above first BTB set includes a first type entry for a branch instruction, and Each second way of the above second BTB set includes a second type entry for a branch instruction, and An electronic device wherein the first type entry comprises the type field and a target address field indicating the target address of the corresponding branch instruction, and the type field and the target address field are not included in the second type entry.

5. In Paragraph 4, The above-mentioned first type entry and the above-mentioned second type entry are: Validity information indicating whether the entry associated with the branch command is valid, Tag information including a tag for identifying the corresponding branch command, and An electronic device comprising at least one of offset information including an offset associated with the location of the corresponding branch instruction.

6. In Paragraph 3, An electronic device wherein the first BTB set, the second BTB set, and the third BTB set have the same index, the index is associated with address information of the input branch instruction, and the address information includes at least one of the cache line address or the instruction address of the input branch instruction.

7. In Paragraph 3, When the above instructions are executed individually or collectively by the at least one processor, the electronic device: An electronic device that causes the BTB to be updated based on branch type information of the above input branch command.

8. In Paragraph 7, The update operation of the above BTB is: An operation to identify whether the branch type of the input branch command is a return branch type based on the branch type information of the input branch command; An operation to determine whether a matching entry for the input branch instruction exists within the first BTB set or the second BTB set, based on the offset information and tag information of the input branch instruction, based on identifying that the branch type is the return branch type; and An electronic device comprising an operation to update the matching entry when the matching entry exists.

9. In Paragraph 8, The update operation of the above BTB is: If the above matching entry does not exist, an operation to determine whether an invalid entry exists in the second BTB set based on the valid information of the ways of the second BTB set; and An electronic device comprising an operation to update the invalid entry when the invalid entry exists within the second BTB set.

10. In Paragraph 9, The update operation of the above BTB is: If the above invalid entry does not exist in the second BTB set, the operation of determining whether the above invalid entry exists in the first set based on the valid information of the ways of the first BTB set; and An electronic device comprising an operation to determine whether to update the invalid entry based on the number of the first way of the first BTB set including the branch instruction having the return branch type, based on the fact that the invalid entry exists within the first BTB set.

11. In Paragraph 9, The action determining whether to update the above invalid entry is: If it is decided to update the above invalid entry, the operation of updating the above invalid entry; and An electronic device comprising the operation of selecting a victim way to update the input branch command from the first ways in the first BTB set or the second ways in the second BTB set, based on the last access return way information within the third way of the third BTB set, when deciding not to update the above invalid entry.

12. In Paragraph 11, When the above last access return way information is set to a first value indicating that a branch command having the above return branch type is last accessed from a first way within the above first BTB set, the operation of selecting the damage way from the second ways within the above second BTB set based on second MRU (most recently used) PLRU (pseudo least recently used) information for the second ways; and An electronic device comprising an operation of selecting the damage way from the first ways in the first BTB set based on first MRU PLRU information for the first ways, when the last access return way information is set to a second value indicating that a branch command having the return branch type is last accessed from the second way in the second BTB set.

13. In Paragraph 12, The first MRU PLRU information includes a number of bits equal to the number of first ways of the first BTB set, and each bit of the first MRU PLRU information indicates whether the corresponding first way of the first BTB set has been accessed. An electronic device, wherein the second MRU PLRU information comprises a number of bits equal to the number of second ways of the second BTB set, and each bit of the second MRU PLRU information indicates whether the corresponding second way of the second BTB set has been accessed.

14. In a method of an electronic device, An action that identifies input branch commands; and The method includes an operation to perform a prediction for obtaining a predicted target address for the input branch instruction based on at least one of a plurality of sets of BTBs within a branch target buffer (BTB), and The above multiple BTB sets are: A first BTB set including first ways for any branch types including a return branch type, and It includes a second BTB set comprising one or more second ways used for the above return branch type, and Based on the fact that a branch instruction having the above return branch type is included in the first way of the above first BTB set, the type of the branch instruction having the above return branch type is identified through the type field included in the above first way, and A method in which a branch instruction having the above return branch type is included in the second way of the above second BTB set, wherein the branch instruction having the above return branch type is identified as a type without the type field.

15. In Paragraph 14, The number of the first ways of the first BTB set is set to a value equal to the value of the way set associativity of the BTB, and The number of the second ways of the second BTB set is set to be less than or equal to the value of the way set association, and A method in which, among the first ways of the first BTB set, the number of first ways including a branch command having the return branch type can be set up to a value obtained by subtracting the number of second ways of the second BTB set from the value of the way set association.

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