Gallium nitride device suppressing back gate effect and monolithic dual gallium nitride device

Abstract

One embodiment provides a gallium nitride device comprising: a silicon substrate; a channel forming layer disposed on the silicon substrate and formed as a gallium nitride (GaN)-based semiconductor layer to create a current path and induce an electron channel; a gate control layer disposed on the channel forming layer to control channel conductance by transferring a gate potential; and a gate electrode disposed on the gate control layer, wherein a bias voltage is directly applied to the silicon substrate through the channel forming layer.

Description

Gallium nitride device suppressing back-gate effect and monolithic dual gallium nitride device

[0001] The present embodiment relates to a GaN (gallium nitride)-based power semiconductor device.

[0002] From electric vehicles, renewable energy generation inverters, data center power supplies, 5G and next-generation communication base stations, to power conversion modules for home appliances, the need for semiconductor devices that simultaneously satisfy high-speed switching and high power density is expanding significantly.

[0003] For example, electric vehicle chargers and battery management systems require rapid switching of high voltage and high current, while maximizing energy efficiency by minimizing power loss is emerging as a critical challenge in data center power supplies. Furthermore, in renewable energy inverters and grid-connected systems, miniaturization and high efficiency of power converters through high-frequency driving are essential. In these applications, the performance limitations of conventional silicon power devices are clearly evident, leading to a significant increase in the need for wide bandgap semiconductor devices.

[0004] Against this backdrop, gallium nitride (GaN) power semiconductors are attracting attention as next-generation power conversion devices because they can realize high-speed switching operation and low conduction losses based on their high electron mobility and wide bandgap characteristics. In particular, GaN-on-Si technology, which involves forming GaN on a silicon substrate, is being actively researched in low-voltage and medium-voltage power applications due to its advantages in terms of wafer size expansion and manufacturing cost reduction.

[0005] However, in GaN-on-Si devices, the silicon substrate parasitically acts as a gate, resulting in a back-gate effect that affects the device's threshold voltage and conduction resistance (Rds_on). This effect hinders stable device operation and causes problems such as losses and characteristic degradation during switching.

[0006] To address this, a GaN-on-SOI (Silicon-On-Insulator) structure has been proposed in the past. The SOI substrate forms an insulating layer between the silicon substrate and the GaN layer, thereby fundamentally blocking the influence of the substrate potential on the device channel. Additionally, a method is used to eliminate the back-gate effect by suppressing parasitic current paths using a deep trench isolation process.

[0007] However, SOI-based approaches have drawbacks, such as complex manufacturing processes and significantly increased production costs for wafers and devices. Not only are GaN wafers themselves expensive, but the SOI structure also requires the formation of additional insulating layers and trench processes, which reduces the price competitiveness of the products.

[0008] Against this backdrop, the objective of the present embodiment is, in one aspect, to provide a gallium nitride device that can be manufactured with a simple process while suppressing the back gate effect occurring in a gallium nitride device formed on a silicon substrate. In another aspect, the objective of the present embodiment is to provide a gallium nitride device that can secure stable electrical characteristics without applying a separate insulating layer or SOI process by applying a bias voltage to a silicon substrate using TGV (Through-GaN-Via). In yet another aspect, the objective of the present embodiment is to provide a gallium nitride monolithic dual device that integrates a plurality of gallium nitride devices monolithically on a silicon substrate, while ensuring operational stability and reliability of each device even in a dual device structure.

[0009] To achieve the aforementioned objective, one embodiment provides a gallium nitride device comprising: a silicon substrate; a channel forming layer disposed on the silicon substrate and composed of a GaN (Gallium Nitride)-based semiconductor layer to form a current path and induce an electron channel; a gate control layer disposed on the channel forming layer to control the conduction of the channel by transmitting a gate potential; and a gate electrode disposed on the gate control layer, and a bias voltage directly applied to the silicon substrate by penetrating the channel forming layer.

[0010] The ground voltage can be supplied as the above bias voltage.

[0011] The channel forming layer may include a GaN channel layer disposed on the silicon substrate to form a current path and an AlGaN barrier layer disposed on the GaN channel layer to induce an electron channel through a polarization effect.

[0012] The above gate control layer may be composed of a P-type doped GaN layer (P-GaN layer).

[0013] A source electrode and a drain electrode are disposed on both sides with the gate control layer in between, and a passivation layer covering the source electrode and the drain electrode may be further disposed.

[0014] In the above channel forming layer, an insulating region may be formed in the periphery of the active channel region defined between the source electrode and the drain electrode.

[0015] Through-GaN-Via (TGV) can be formed to penetrate the passivation layer and the insulating region.

[0016] Another embodiment provides a monolithic dual gallium nitride device comprising: a silicon substrate; a channel forming layer disposed on the silicon substrate and composed of a GaN (Gallium Nitride)-based semiconductor layer to form a current path and induce an electron channel; a first gate control layer and a second gate control layer disposed on a first region and a second region of the channel forming layer, respectively, to control the conduction of the channel by transmitting a gate potential; a first gate electrode and a second gate electrode disposed on the first gate control layer and the second gate control layer, respectively; and a TGV (Through-GaN-Via) that penetrates the channel forming layer and applies a bias voltage to the silicon substrate.

[0017] A first GaN device including the first gate control layer and the first gate electrode and a second GaN device including the second gate control layer and the second gate electrode are formed, a ground voltage is supplied to the source electrode of the first GaN device and a power supply voltage is supplied to the drain electrode of the second GaN device, and a switching node may be formed at the portion where the drain electrode of the first GaN device and the source electrode of the second GaN device are connected.

[0018] A passivation layer covering the source electrode and drain electrode of the first GaN device and the source electrode and drain electrode of the second GaN device may be further disposed.

[0019] In the above channel forming layer, an insulating region may be formed in the periphery of the active channel region defined between the source electrode and the drain electrode in each GaN device.

[0020] The TGV can be formed to penetrate the passivation layer and the insulation region.

[0021] A first TGV may be formed to penetrate the passivation layer, the insulation region, and the channel forming layer in the first region, and a second TGV may be formed to penetrate the passivation layer, the insulation region, and the channel forming layer in the second region.

[0022] The above power supply voltage can be supplied as the above bias voltage.

[0023] Half the level of the above power supply voltage can be supplied as the above bias voltage.

[0024] The above ground voltage is supplied as the above bias voltage, and the channel width of the second GaN device may be wider than the channel width of the first GaN device, or the channel length of the second GaN device may be shorter than the channel length of the first GaN device.

[0025] The channel forming layer may include a GaN channel layer disposed on the silicon substrate to form a current path and an AlGaN barrier layer disposed on the GaN channel layer to induce an electron channel through a polarization effect.

[0026] The first gate control layer and the second gate control layer may be composed of a P-type doped GaN layer (P-GaN layer).

[0027] Another embodiment provides a monolithic dual gallium nitride device comprising: a silicon substrate; a channel forming layer disposed on the silicon substrate and composed of a GaN (Gallium Nitride)-based semiconductor layer to form a current path and induce an electron channel; a first gate control layer and a second gate control layer disposed on a first region and a second region of the channel forming layer, respectively, to control the conduction of the channel by transmitting a gate potential; and a first gate electrode and a second gate electrode disposed on the first gate control layer and the second gate control layer, respectively, and directly applying a bias voltage to the silicon substrate by penetrating the channel forming layer.

[0028] As described above, according to the present embodiment, the back gate effect occurring in a gallium nitride device formed on a silicon substrate can be effectively suppressed. Furthermore, according to the present embodiment, by applying a bias voltage directly to the silicon substrate through a TGV (Through-GaN-Via), additional insulating layers or complex isolation processes, as in conventional SOI structures, are unnecessary, thereby reducing manufacturing costs. Moreover, according to the present embodiment, even when multiple gallium nitride devices are monolithically integrated on a silicon substrate, stable operation of each device can be guaranteed, and accordingly, the implementation of integrated power conversion devices such as dual devices or half-bridge structures becomes easier.

[0029] FIG. 1 is a circuit diagram of a power converter to which a gallium nitride element according to one embodiment can be applied.

[0030] FIG. 2 is a cross-sectional view of a first gallium nitride element according to one embodiment.

[0031] FIG. 3 is a cross-sectional view of a monolithic dual gallium nitride device according to one embodiment.

[0032] Figure 4 is a first example diagram showing the conduction resistance according to voltage in a GaN device.

[0033] Figure 5 is a second example diagram showing the conduction resistance according to voltage in a GaN device.

[0034] Figure 6 is a cross-sectional view of a gallium nitride device having a GaN-on-SOI structure.

[0035] Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. It should be noted that in assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present invention, if it is determined that a detailed description of related known components or functions could obscure the essence of the invention, such detailed description is omitted.

[0036] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the present invention. These terms are intended only to distinguish the components from other components, and the essence, order, or sequence of the components is not limited by the terms. Where it is stated that a component is "connected," "combined," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but that another component may also be "connected," "combined," or "connected" between each component.

[0037] FIG. 1 is a circuit diagram of a power converter to which a gallium nitride element according to one embodiment can be applied.

[0038] Referring to FIG. 1, the power converter (100) may include a plurality of GaN elements (112a, 112b), a gate driver (120), an inductor (L), etc.

[0039] A plurality of GaN devices (112a, 112b) and a gate driver (120) may be embedded within a single semiconductor package, and an inductor (L) may be placed outside the semiconductor package and electrically connected to the plurality of GaN devices (112a, 112b) through the terminals of the semiconductor package. Alternatively, only the plurality of GaN devices (112a, 112b) may be embedded within the semiconductor package, and the gate driver (120) may be placed outside the semiconductor package and electrically connected to the plurality of GaN devices (112a, 112b) through the terminals of the semiconductor package.

[0040] Each GaN device (112a, 112b) can be individually packaged, and according to the embodiment, a plurality of GaN devices (112a, 112b) can be packaged together as a monolithic dual GaN device (110).

[0041] A plurality of GaN devices (112a, 112b) can form a half-bridge circuit. In the half-bridge circuit, the first GaN device (112a) may be placed on the low side and the second GaN device (112b) may be placed on the high side.

[0042] In a half-bridge circuit, a ground voltage (VG) is supplied to the source electrode (S1) of the first GaN device (112a), and a gate signal output from the gate driver (120) can be supplied to the gate electrode (G1) of the first GaN device (112a). A power supply voltage (VI) is supplied to the drain electrode (D2) of the second GaN device (112b), and a different gate signal output from the gate driver (120) can be supplied to the gate electrode (G2) of the second GaN device (112b). Additionally, the drain electrode (D1) of the first GaN device (112a) and the source electrode (S2) of the second GaN device (112b) are electrically connected, and a switching node (Nsw) can be formed at this connection point.

[0043] One side of the inductor (L) is connected to the switching node (Nsw), and an output voltage (VO) can be formed on the other side.

[0044] The turn-on intervals of each GaN device (112a, 112b) can be controlled so as not to overlap with each other. For example, the second GaN device (112b) may be turned off during the time interval when the first GaN device (112a) is turned on, and the first GaN device (112a) may be turned off during the time interval when the second GaN device (112b) is turned on.

[0045] When the first GaN device (112a) is turned on, a ground voltage (VG) may be formed at the switching node (Nsw). And when the second GaN device (112b) is turned on, a power supply voltage (VI) may be formed at the switching node (Nsw).

[0046] The magnitude of the power supply voltage (VI) may be a low level of 40V or less and a medium level of 100V or less. When the power supply voltage (VI) has such magnitude, a plurality of GaN devices (112a, 112b) can be packaged together as a monolithic dual GaN device (110).

[0047] FIG. 2 is a cross-sectional view of a first gallium nitride element according to one embodiment.

[0048] Referring to FIG. 2, the first GaN device (112a) may include a silicon substrate (210), a channel forming layer (220), a gate control layer (230a), a gate electrode (G1), a TGV (Through-GaN-Via), etc.

[0049] The silicon substrate (210) is formed of single-crystal silicon, and a wafer diameter of 150 mm or more may be used, and a wafer with a diameter of 200 mm or more may be used to improve productivity.

[0050] The resistivity of the silicon substrate (210) can be selected according to device operation and substrate bias stability. In one embodiment, a high-resistance substrate (e.g., several Ω·cm or more or several hundred Ω·cm or more) may be used to suppress parasitic current within the substrate, and in another embodiment, an intermediate resistivity range (e.g., several Ω·cm to several tens of Ω·cm) may be used to ensure uniformity of potential distribution when substrate bias is applied through TGV. The doping polarity may be selected from n-type or p-type and may be determined according to compatibility with substrate bias conditions (VG, VI, ½VI) and device isolation strategies.

[0051] The thickness of the silicon substrate (210) is several hundred μm (e.g., about 725 μm) in the initial state, and can be thinned by back grinding (e.g., in the range of 200 μm to 400 μm) in consideration of reducing thermal resistance and package stackability in subsequent processes.

[0052] The thermal conductivity characteristics of the silicon substrate (210) provide a path for discharging heat from the device toward the package, and if necessary, a back metal layer (e.g., Ti / Ni / Ag, etc.) may be formed on the back surface of the substrate to provide thermal diffusion and an electrical reference potential. However, in this embodiment, since the substrate bias is applied directly from the upper surface through the TGV described later, the formation of the back metal layer may be optional.

[0053] Meanwhile, in this embodiment, a method of using TGV by directly applying a bias voltage to a silicon substrate (210) is described, but this embodiment is not limited thereto. For convenience of explanation, a method of using TGV by directly applying a bias voltage to a silicon substrate (210) is described below.

[0054] A channel forming layer (220) may be disposed on a silicon substrate (210). The channel forming layer (220) may be composed of a GaN (Gallium Nitride)-based semiconductor layer to form a current path and induce an electron channel.

[0055] A channel forming layer (220) may be formed on a multilayer buffer structure to relieve stress that may arise from differences in lattice constants and thermal expansion coefficients with respect to a silicon substrate (210). For example, an aluminum nitride (AlN) nucleation layer, a carbon-doped GaN high-resistance layer, or an AlGaN / GaN superlattice layer may be introduced as a lower buffer layer to suppress the occurrence of defects due to lattice mismatch and minimize leakage current.

[0056] In one embodiment, the thickness of the channel forming layer (220) can be formed in the range of tens of nm to hundreds of nm, and this can be optimized according to current capacity and breakdown voltage requirements. Since the crystal quality of the channel forming layer is directly related to the performance of the device, high-quality growth techniques such as Metal-Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) can be used in the epitaxial growth process.

[0057] The channel forming layer may include a GaN channel layer disposed on a silicon substrate (210) to form a current path and an AlGaN barrier layer disposed on the GaN channel layer to induce an electron channel through a polarization effect.

[0058] The GaN channel layer is generally formed from undoped GaN (UID GaN) without impurities, providing high electron mobility and low scattering characteristics. The AlGaN barrier layer controls the strength of the polarization electric field according to the composition ratio of Al (e.g., 15% to 30%), thereby controlling the density and characteristics of the two-dimensional electron gas (2DEG) formed at the interface.

[0059] The thickness of the AlGaN barrier layer can be formed in the range of several nanometers to tens of nanometers; if it is excessively thick, cracking or stress problems may occur, and if it is excessively thin, it is difficult to secure a sufficient 2DEG density. Therefore, the optimal thickness can be set according to the target current capacity and breakdown voltage characteristics of the device.

[0060] Additionally, a surface treatment or a thin passivation insulating film may be further formed on the surface of the AlGaN barrier layer to improve the junction stability of the subsequent gate control layer (230a), which lowers the surface charge trap density and improves critical voltage stability.

[0061] In this way, the channel forming layer (220) provides a high-density 2DEG conduction path through a combination of a GaN channel layer and an AlGaN barrier layer, thereby playing a key role in realizing high-speed switching characteristics and low conduction loss of the gallium nitride device.

[0062] A gate control layer (230a) may be disposed on the channel forming layer (220). The gate control layer (230a) can control the conduction of the channel by transmitting a gate potential.

[0063] The gate control layer (230a) can be formed of P-type doped GaN (P-GaN). The P-GaN layer is placed on an AlGaN barrier layer to control the formation and blocking of a two-dimensional electron gas (2DEG) according to the potential applied from the gate electrode (G1). Through this, the device does not have a depletion-mode characteristic in which it is normally in a conductive state, and can implement an enhancement-mode operation in which the channel conducts only when a gate signal is applied.

[0064] The P-GaN layer can be doped with impurities such as magnesium (Mg) to secure a hole concentration, and the doping concentration and thickness are key factors determining the magnitude of the threshold voltage (Vth).

[0065] A gate insulator may be further disposed on top of the gate control layer (230a), and high-k insulating materials such as silicon nitride (SiN), aluminum oxide (Al₂O₃), and hafnium oxide (HfO₂) may be used. The gate insulator provides electrical insulation between the gate electrode and the P-GaN, reduces gate leakage current, and performs the function of ensuring long-term reliability.

[0066] A gate electrode (G1) may be disposed on the gate control layer (230a). Additionally, a source electrode (S1) and a drain electrode (D1) may be disposed on both sides with the gate control layer (230a) in between.

[0067] Additionally, a passivation layer (240) covering the source electrode (S1) and the drain electrode (D1) may be further disposed.

[0068] The gate electrode (G1) is formed as a metal layer and determines whether the channel conducts by transmitting a gate signal to the gate control layer (230a). The gate electrode may be formed from a metal or metal alloy such as nickel (Ni), gold (Au), titanium (Ti), aluminum (Al), molybdenum (Mo), or titanium nitride (TiN), and may be selected based on heat resistance, contact stability, and process compatibility.

[0069] The source electrode (S1) and the drain electrode (D1) can be formed to be electrically connected to the channel forming layer (220). To this end, the AlGaN barrier layer in the region where the source electrode and the drain electrode are formed is removed through an etching process, and the underlying GaN channel layer is exposed. Subsequently, an ohmic contact with low contact resistance can be realized by stacking metals such as titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au) and performing rapid thermal annealing.

[0070] The passivation layer (240) covers the source electrode (S1), the drain electrode (D1), and the adjacent semiconductor surface to protect the device and provide electrical stability. The passivation layer can be formed from insulating films such as silicon nitride (SiN), silicon oxide (SiO₂), and aluminum oxide (Al₂O₃). The passivation layer not only protects the device from the external environment but also has the effect of suppressing surface charge traps, thereby mitigating critical voltage fluctuations and current instability.

[0071] In the channel forming layer (220), an insulating region (260a, 260b) may be formed in the periphery of the active channel region defined between the source electrode (S1) and the drain electrode (D1).

[0072] The insulating region (260a, 260b) can be formed by nitrogen ion implantation. When nitrogen ions are injected into the channel-forming layer (220), defects are locally formed in the crystal lattice, significantly reducing electrical conductivity, thereby converting the region into an insulating region with high resistivity characteristics. This insulating region electrically defines the active channel region of the device and prevents the formation of leakage current or parasitic channels between devices.

[0073] The insulating region (260a, 260b) is positioned along the outer edge of the active channel region to induce current to flow only through the active channel region during device operation. This stabilizes the current path and improves the on and off state characteristics of the device. Additionally, it can contribute to reducing switching losses by suppressing parasitic capacitance and current dispersion phenomena that may occur during high-frequency driving.

[0074] In other embodiments, the insulating region may be formed by an oxidation process or an insulating film filling process instead of ion implantation. For example, the insulating region can be realized by forming a trench and then filling it with a silicon oxide film (SiO₂) or a silicon nitride film (SiN), which has the effect of further enhancing electrical isolation between devices.

[0075] Meanwhile, a TGV (250a) may be formed in the first GaN device (112a) to apply a bias voltage (Vbias) to a silicon substrate (210) by penetrating the channel forming layer (220). The TGV (250a) may be composed of a via hole (252) and a filling metal (254). In some cases, a structure in which a filling metal (254) is inserted into a via hole (252) is called a TGV plug, but for convenience of explanation, it will be referred to as a TGV below.

[0076] The via hole (252) of the TGV (250a) can be formed to penetrate the channel forming layer (220) using microfabrication techniques such as dry etching or laser drilling. The diameter of the via hole (252) can be formed in the range of hundreds of nanometers to tens of micrometers, which can be optimized according to the integration density and bias current capacity of the device.

[0077] An insulating liner may be additionally formed on the inner wall of the via hole (252). The insulating liner may be formed from an insulating material such as silicon oxide (SiO₂), silicon nitride (SiN), or aluminum oxide (Al₂O₃), and prevents electrical leakage between the filling metal (254) inside the via hole and the surrounding semiconductor region. A barrier layer and a seed layer may be further formed on the insulating liner, and these layers serve to prevent the diffusion of the filling metal (254) and ensure uniformity of the plating process.

[0078] The filling metal (254) can be formed from metals such as tungsten (W), copper (Cu), and aluminum (Al), and the via holes are filled using methods such as electroplating, chemical vapor deposition (CVD), and physical vapor deposition (PVD). The filling metal (254) is electrically connected to the silicon substrate (210) to enable substrate potential control, and as a result, can suppress the back gate effect occurring in the channel forming layer (220).

[0079] When a passivation layer (240) is formed on the first GaN device (112a), the TGV (250a) can be formed by penetrating the passivation layer (240). At this time, the passivation layer (240) may be selectively removed in the area where the via hole (252) is opened, or a penetration process may be performed through etching.

[0080] Additionally, when an insulating region (260a, 260b) is formed in the channel forming layer (220), the TGV (250a) may be formed to penetrate a part of the insulating region (260a, 260b). Since the insulating region is placed at the outer edge of the active channel region, if the position of the TGV (250a) is properly designed, electrical connection to the substrate can be secured without directly encroaching on the active channel region.

[0081] Accordingly, the TGV (250a) can penetrate the section overlapping with the passivation layer (240) and the insulating region (260a, 260b), and by optimizing the penetration location and path, the problem of damage to the active channel region can be prevented. Accordingly, the TGV (250a) can maintain the electrical characteristics and reliability of the device while providing a stable electrical path for applying substrate bias.

[0082] As the bias voltage (Vbias), ground voltage, power supply voltage, or 1 / 2 power supply voltage (VG, VI, ½VI) may be supplied.

[0083] FIG. 3 is a cross-sectional view of a monolithic dual gallium nitride device according to one embodiment.

[0084] Referring to FIG. 3, the dual GaN device (110) may include a silicon substrate (210), a channel forming layer (220), a first gate control layer (230a), a second gate control layer (230b), a first gate electrode (G1), a second gate electrode (G2), TGVs (250a, 250b), etc.

[0085] A channel forming layer (220) may be disposed on a silicon substrate (210). The channel forming layer (220) may be composed of a GaN (Gallium Nitride)-based semiconductor layer to form a current path and induce an electron channel.

[0086] A gate control layer (230a, 230b) may be disposed on the channel forming layer (220). The gate control layer (230a, 230b) can control the conduction of the channel by transmitting a gate potential.

[0087] The dual GaN device (110) can be divided into two regions (ARa, ARb). Additionally, a first gate control layer (230a) can be disposed on the first region (ARa) of the channel forming layer (220), and a second gate control layer (230b) can be disposed on the second region (ARb) of the channel forming layer (220).

[0088] And, a first gate electrode (G1) may be disposed on the first gate control layer (230a), and a second gate electrode (G2) may be disposed on the second gate control layer (230b).

[0089] A first GaN device (112a) including a first gate control layer (230a) and a first gate electrode (G1) may be formed in a first region (ARa) of a dual GaN device (110), and a second GaN device (112b) including a second gate control layer (230b) and a second gate electrode (G2) may be formed in a second region (ARb).

[0090] In the first GaN device (112a), a source electrode (S1) and a drain electrode (D1) may be disposed on both sides with the first gate control layer (230a) in between. In the second GaN device (112b), a source electrode (S2) and a drain electrode (D2) may be disposed on both sides with the second gate control layer (230b) in between.

[0091] A ground voltage (VG) can be supplied to the source electrode (S1) of the first GaN device (112a), and a power supply voltage (VI) can be supplied to the drain electrode (D2) of the second GaN device (112b). Additionally, a switching node (Nsw) can be formed at the portion where the drain electrode (D1) of the first GaN device (112a) and the source electrode (S2) of the second GaN device (112b) are connected.

[0092] A passivation layer (240) covering the source electrode (S1) and drain electrode (D1) of the first GaN device (112a) and the source electrode (S2) and drain electrode (D2) of the second GaN device (112b) may be further disposed in the dual GaN device (110).

[0093] In the channel forming layer (220), an insulating region (260a, 260b, 260c) may be formed in the periphery of an active channel region defined between the source electrode (S1, S2) and the drain electrode (D1, D2) in each GaN device (112a, 112b).

[0094] And, TGV (250a, 250b) is formed by penetrating the passivation layer (240), the insulating region (260a, 260b, 260c) and the channel forming layer (220), and such TGV (250a, 250b) can apply a bias voltage (Vbias) to the silicon substrate (210).

[0095] The dual GaN device (110) may include a first GaN device (112a) and a second GaN device (112b), and at least one TGV may be formed in each GaN device (112a, 112b). For example, a first TGV (250a) may be formed in the first GaN device (112a), and a second TGV (250b) may be formed in the second GaN device (112b).

[0096] The first TGV (250a) can be formed to penetrate the passivation layer (240), the insulation region (260a), and the channel forming layer (220) in the first region (ARa). And, the second TGV (250b) can be formed to penetrate the passivation layer (240), the insulation region (260b), and the channel forming layer (220) in the second region (ARb).

[0097] As the bias voltage (Vbias), the ground voltage (VG), the power supply voltage (VI), or the half power supply voltage (½VI) may be supplied. However, this embodiment is not limited to this, and a voltage having a different voltage level may be supplied as the bias voltage (Vbias). Below, the description will focus on examples in which the three types of voltages mentioned above are supplied as the bias voltage (Vbias).

[0098] Figure 4 is a first example diagram showing the conduction resistance according to voltage in a GaN device.

[0099] In FIG. 4, the conduction resistance (Rds_on) according to the voltage between the substrate (SUB) and the source electrode (S2) of the second GaN device placed on the high side in a half-bridge structure—voltage applied to the body—is exemplarily illustrated. In FIG. 4, the horizontal axis represents the voltage (V_SUB-S2) obtained by subtracting the voltage of the source electrode (S2) from the voltage of the silicon substrate (SUB), and the vertical axis represents the normalized conduction resistance (Rds_on).

[0100] When the second GaN device placed on the high side is turned on, a power supply voltage (VI) is formed at the source electrode (S2). At this time, when the voltage supplied to the silicon substrate through the TGV is a ground voltage of 0V, the V_SUB-S2 voltage becomes a -power supply voltage (-VI). When the power supply voltage is 20V, V_SUB-S2 becomes -20V when the second GaN device is turned on.

[0101] According to Fig. 4, since the conduction resistance (Rds_on) does not change until the voltage applied to the body becomes -20V, when the power supply voltage is at a low level of less than 20V, there is no problem in controlling the conduction resistance (Rds_on) of the second GaN device placed on the high side even if the ground voltage is supplied to the silicon substrate through the TGV.

[0102] However, if the power supply voltage increases slightly, the conduction resistance (Rds_on) may increase; in this case, if the conduction resistance (Rds_on) is reduced by adjusting the channel width (W) and / or channel length (L) of the second GaN device placed on the high side, it may not be a problem.

[0103] For example, when a ground voltage is supplied as a bias voltage and the power supply voltage is at a middle level of 40V, the channel width of the second GaN device can be designed to be wider than the channel width of the first GaN device or the channel length of the second GaN device can be designed to be shorter than the channel length of the first GaN device.

[0104] Figure 5 is a second example diagram showing the conduction resistance according to voltage in a GaN device.

[0105] The voltage (V_SUB-S1) between the substrate (SUB) and the source electrode (S1) of the first GaN device placed on the low side of the half-bridge structure is exemplarily illustrated in the lower graph of FIG. 5. Also, the conduction resistance (Rds_on) of the first GaN device placed on the low side of the half-bridge structure is exemplarily illustrated in the upper graph of FIG. 5. In the lower and upper graphs of FIG. 5, the horizontal axis is the time axis.

[0106] In the example of Fig. 5, a power supply voltage (VI) is supplied to the silicon substrate (SUB).

[0107] When 40V is supplied as the power supply voltage and 40V, which is the same as the power supply voltage, is supplied as the bias voltage of the silicon substrate, when the first GaN device placed on the low side is turned on, a positive voltage of power supply voltage minus ground voltage is applied to the body of the first GaN device. When a positive voltage is applied to the body of the first GaN device placed on the low side, the conduction resistance (Rds_on) does not change significantly, as shown in the upper graph of Fig. 5.

[0108] However, when the first GaN device is turned off, a voltage of 0V is applied to the body of the first GaN device. At this time, when the positive voltage of the power supply voltage and ground voltage is applied to the body and then removed, the conduction resistance of the first GaN device increases instantaneously, and a certain amount of time may be required for recovery. If the switching frequency is faster than the recovery time, the conduction resistance (Rds_on) of the low-side switch increases, and a phenomenon may occur where the conduction resistance (Rds_on) varies according to the PWM (Pulse Width Modulation) duty cycle.

[0109] Meanwhile, considering the above, a voltage having a voltage level between the ground voltage level and the power supply voltage level may be supplied as a bias voltage. For example, a voltage (½VI) corresponding to half the level of the power supply voltage may be supplied as a bias voltage.

[0110] In a half-bridge structure, when a bias voltage of ½VI is applied, -½VI may be applied to the body of the second GaN device when the second GaN device placed on the high side is turned on. Also, when the first GaN device placed on the low side is turned on, ½VI may be applied to the body of the first GaN device. In this way, by applying a voltage of the ½VI level as a bias voltage, the maximum absolute voltage applied to the body of both the first GaN device and the second GaN device can be limited to ½VI.

[0111] When the power supply voltage (VI) is 40V, the maximum voltage applied to the body of the second GaN device placed on the high side becomes -20V, and as shown in Fig. 4, the DC conduction resistance (Rds_on) hardly changes.

[0112] In addition, the voltage applied to the body of the first GaN device placed on the low side can be up to 20V, and the maximum value of the transient change of the conduction resistance (Rds_on) at the moment the body voltage is removed and the recovery time can also be effectively limited.

[0113] Figure 6 is a cross-sectional view of a gallium nitride device having a GaN-on-SOI structure.

[0114] Referring to FIG. 6, a gallium nitride device (10) with a GaN-on-SOI structure may include a silicon substrate (28), an insulating layer (27), a silicon layer (21), a GaN layer (22), a gate control layer (23), a passivation layer (24), a sub-contact (25), electrodes (S1, S2, D1, D2, G1, G2), etc.

[0115] In a GaN-on-SOI structure, an insulating layer (27) is interposed between the silicon substrate (28) and the GaN layer (22), so that the substrate potential is structurally blocked from directly affecting the channel. Additionally, the backgate effect is suppressed because the upper silicon layer (21) is fixed to a reference potential through the SUB contact (25). However, to manufacture such an SOI structure, an oxide film must first be formed between two silicon wafers and then bonded to produce an SOI wafer with a buried BOX, and in some cases, a process of thinning the upper silicon layer is also involved. Subsequently, a Deep Trench Isolation process is added to ensure insulation between devices, which involves a complex process of etching deep trenches with a high aspect ratio and filling them with insulating material. This series of processes significantly increases the wafer manufacturing cost and is a factor that increases the cost and time of the device post-processing.

[0116] On the other hand, the gallium nitride device of the present embodiment does not require an SOI wafer or a deep trench process. Instead, a channel forming layer and a gate structure are formed on a standard GaN-on-Si wafer, and then a TGV penetrating the channel forming layer is provided to apply a bias voltage to the silicon substrate. This method allows for the omission of high-cost processes such as BOX formation, wafer bonding, and deep trench insulation, thereby reducing manufacturing costs, while also suppressing the back-gate effect by directly controlling the potential of the silicon substrate.

[0117] As described above, according to the present embodiment, the back gate effect occurring in a gallium nitride device formed on a silicon substrate can be effectively suppressed. Furthermore, according to the present embodiment, by applying a bias voltage directly to the silicon substrate through a TGV (Through-GaN-Via), additional insulating layers or complex isolation processes, as in conventional SOI structures, are unnecessary, thereby reducing manufacturing costs. Moreover, according to the present embodiment, even when multiple gallium nitride devices are monolithically integrated on a silicon substrate, stable operation of each device can be guaranteed, and accordingly, the implementation of integrated power conversion devices such as dual devices or half-bridge structures becomes easier.

[0118] Terms such as "include," "compose," or "have" as described above, unless specifically stated otherwise, mean that the relevant component may be inherent; therefore, they should be interpreted as allowing for the inclusion of additional components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0119] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

Claims

1. Silicon substrate; A channel forming layer disposed on the above silicon substrate and composed of a GaN (Gallium Nitride)-based semiconductor layer that forms a current path and induces an electron channel; A gate control layer disposed on the above-mentioned channel forming layer and controlling the conduction of the channel by transmitting a gate potential; and It includes a gate electrode disposed on the gate control layer, and Directly applying a bias voltage to the silicon substrate by penetrating the channel forming layer, Gallium nitride element.

2. In Paragraph 1, A gallium nitride element in which the ground voltage is supplied as the above bias voltage.

3. In Paragraph 1, A gallium nitride device comprising a channel forming layer, wherein the channel forming layer comprises a GaN channel layer disposed on the silicon substrate to form a current path and an AlGaN barrier layer disposed on the GaN channel layer to induce an electron channel through a polarization effect.

4. In Paragraph 1, A gallium nitride device in which the gate control layer is composed of a P-type doped GaN layer (P-GaN layer).

5. In Paragraph 4, Source electrodes and drain electrodes are arranged on both sides with the above gate control layer in between, and A gallium nitride device having a passivation layer further disposed over the source electrode and the drain electrode.

6. In Paragraph 5, A gallium nitride device in which an insulating region is formed in the periphery of an active channel region defined between the source electrode and the drain electrode within the channel forming layer.

7. In Paragraph 6, A gallium nitride device in which a TGV (Through-GaN-Via) is formed to penetrate the passivation layer and the insulating region.

8. Silicon substrate; A channel forming layer disposed on the above silicon substrate and composed of a GaN (Gallium Nitride)-based semiconductor layer that forms a current path and induces an electron channel; A first gate control layer and a second gate control layer, each disposed on a first region and a second region of the channel forming layer and controlling the conduction of the channel by transmitting a gate potential; A first gate electrode and a second gate electrode respectively disposed on the first gate control layer and the second gate control layer; and A TGV (Through-GaN-Via) that penetrates the channel forming layer and applies a bias voltage to the silicon substrate, Monolithic dual gallium nitride device.

9. In Paragraph 8, A first GaN device including the first gate control layer and the first gate electrode and a second GaN device including the second gate control layer and the second gate electrode are formed, and A monolithic dual gallium nitride device in which a ground voltage is supplied to the source electrode of the first GaN device and a power supply voltage is supplied to the drain electrode of the second GaN device, and a switching node is formed at the portion where the drain electrode of the first GaN device and the source electrode of the second GaN device are connected.

10. In Paragraph 9, A monolithic dual gallium nitride device having a passivation layer further disposed over the source electrode and drain electrode of the first GaN device and the source electrode and drain electrode of the second GaN device.

11. In Paragraph 10, A monolithic dual gallium nitride device in which, within the channel forming layer, an insulating region is formed at the periphery of an active channel region defined between a source electrode and a drain electrode in each GaN device.

12. In Paragraph 11, A monolithic dual gallium nitride device in which the TGV is formed to penetrate the passivation layer and the insulating region.

13. In Paragraph 12, A monolithic dual gallium nitride device in which a first TGV is formed to penetrate the passivation layer, the insulation region, and the channel forming layer in the first region, and a second TGV is formed to penetrate the passivation layer, the insulation region, and the channel forming layer in the second region.

14. In Paragraph 9, A monolithic dual gallium nitride device in which the above power supply voltage is supplied as the above bias voltage.

15. In Paragraph 9, A monolithic dual gallium nitride device in which half the level of the above power supply voltage is supplied as the above bias voltage.

16. In Paragraph 9, A monolithic dual gallium nitride device in which the ground voltage is supplied as the bias voltage, and the channel width of the second GaN device is wider than the channel width of the first GaN device or the channel length of the second GaN device is shorter than the channel length of the first GaN device.

17. In Paragraph 8, A monolithic dual gallium nitride device comprising a channel forming layer disposed on a silicon substrate to form a current path, a GaN channel layer disposed on the GaN channel layer to induce an electron channel through a polarization effect.

18. In Paragraph 8, A monolithic dual gallium nitride device in which the first gate control layer and the second gate control layer are composed of a P-type doped GaN layer (P-GaN layer).

19. Silicon substrate; A channel forming layer disposed on the above silicon substrate and composed of a GaN (Gallium Nitride)-based semiconductor layer that forms a current path and induces an electron channel; A first gate control layer and a second gate control layer, each disposed on a first region and a second region of the channel forming layer and controlling the conduction of the channel by transmitting a gate potential; and It includes a first gate electrode and a second gate electrode respectively disposed on the first gate control layer and the second gate control layer, and A monolithic dual gallium nitride device that directly applies a bias voltage to the silicon substrate by penetrating the channel forming layer.

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