Pcie clock gating circuit and pcie clock control method

Abstract

Provided in the present application are a PCIe clock gating circuit and a PCIe clock control method. The circuit comprises: a link width control circuit, a link rate control circuit and a link state control circuit, wherein the link width control circuit is used for outputting, when a current link width is less than a maximum width, a control signal for turning off a clock of a module related to a non-current link width; the link rate control circuit is used for outputting a control signal for turning off a clock of a module related to a non-current rate; the link state control circuit is used for outputting, when a current link state is an abnormal operation state, a control signal for turning off a clock of a module related to the abnormal operation state, the module related to the abnormal operation state comprising related modules corresponding to link states other than the current link state; and the link state control circuit is also used for outputting, when being in a normal operation state, a control signal for turning off clocks of a training code streaming sending module, a training code stream receiving module and a module related to link training.

Description

A PCIe clock gating circuit and a PCIe clock control method

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411491674.6, filed on October 24, 2024, entitled "A PCIe Clock Gating Circuit and a PCIe Clock Control Method", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application belongs to the field of chip technology, and specifically relates to a PCIe clock gating circuit and a PCIe clock control method. Background Technology

[0004] With the iterative upgrades of the PCIe protocol, which has now been updated to version 6.0, the power consumption of PCIe systems has gradually increased along with the addition of functions and complexity. Although PCIe systems have built-in low-power management (L1 state), entering the low-power state requires negotiation between both ends, and data transmission stops when the entire system enters low-power mode. Therefore, PCIe's L1 low-power state can only solve the power consumption problem when the link is idle. Summary of the Invention

[0005] The purpose of this application is to provide a PCIe clock gating circuit and a PCIe clock control method, which aims to solve the power consumption problem when the PCIe system link is idle.

[0006] According to a first aspect of this application, a PCIe clock gating circuit is provided, comprising: a link width control circuit, a link rate control circuit, and a link state control circuit; wherein...

[0007] The link width control circuit is used to output a clock control signal to shut down non-current width related modules when the current link width is less than the maximum width; the non-current width related modules include related modules of other channels other than the channel corresponding to the current link width, and related modules corresponding to other link widths other than the current link width;

[0008] The link rate control circuit is used to output a control signal to shut down the clock of modules that are not related to the current rate. The modules that are not related to the current rate include modules related to other link rates besides the current link rate.

[0009] The link state control circuit is used to output a control signal to shut down the clock of the abnormal working state related modules when the current link state is an abnormal working state. The abnormal working state related modules include related modules corresponding to other link states other than the current link state.

[0010] The link state control circuit is also used to output a control signal to shut down the clock of the training stream sending module, the training stream receiving module, and the link training related modules during normal operation.

[0011] In an optional implementation, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of an offset removal module, a scrambling / descrambling module, and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module, and a message receiving module corresponding to the other link widths.

[0012] In an optional implementation, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of the following: a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5; and at least one of the following: a PAM4 encoding / decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6. When the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2. The non-current rate related modules include at least one of the following: a message receiving and processing module and a message sending and processing module; and at least one of the following: a PAM4 encoding / decoding module, a message receiving and processing module, and a message sending and processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of the following: an 8b / 10b conversion module, a message receiving and processing module, and a message sending and processing module corresponding to Gen1 or Gen2; and at least one of the following: a 128b / 130b conversion module, a message receiving and processing module, a message sending and processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5.

[0013] In an optional implementation, the abnormal operating states include: the link establishment phase state, the link recovery phase state, and the low-power state. The abnormal operating state-related modules corresponding to the link establishment phase state include modules other than the training stream sending module, the training stream receiving module, the link peer detection module, the link polling module, and the link equalization module. The abnormal operating state-related modules corresponding to the link recovery phase state include modules other than the training stream sending module, the training stream receiving module, the link rate switching module, and the link width switching module. The abnormal operating state-related modules corresponding to the low-power state include modules other than the management module corresponding to the current low-power sub-state.

[0014] In an optional implementation, the PCIe clock gating circuit further includes: a logic OR gate;

[0015] The OR gate is used to perform a logical OR operation on multiple control signals to be output to the same clock.

[0016] In an optional implementation, the PCIe clock gating circuit further includes: a register enable signal output circuit;

[0017] The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the set register, so as to enable the control signal output to the clock.

[0018] According to a second aspect of this application, a PCIe clock control method is provided, comprising:

[0019] When the current link width is less than the maximum width, the link width control circuit outputs a clock control signal to shut down modules that are not related to the current width; the modules that are not related to the current width include modules related to other channels other than the channel corresponding to the current link width, and modules related to other link widths other than the current link width.

[0020] The link rate control circuit outputs a clock control signal to shut down modules related to non-current rates. These non-current rate related modules include modules related to other link rates besides the current link rate.

[0021] When the current link state is in an abnormal working state, the link state control circuit outputs a clock control signal to shut down the modules related to the abnormal working state. The modules related to the abnormal working state include the modules corresponding to other link states other than the current link state.

[0022] When the current link state is in normal working state, the link state control circuit outputs a control signal to shut down the clock of the training stream sending module, the training stream receiving module, and the link training related modules.

[0023] In an optional implementation, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of an offset removal module, a scrambling / descrambling module, and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module, and a message receiving module corresponding to the other link widths.

[0024] In an optional implementation, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of the following: a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5; and at least one of the following: a PAM4 encoding / decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6. When the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2. The non-current rate related modules include at least one of the following: a message receiving and processing module and a message sending and processing module; and at least one of the following: a PAM4 encoding / decoding module, a message receiving and processing module, and a message sending and processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of the following: an 8b / 10b conversion module, a message receiving and processing module, and a message sending and processing module corresponding to Gen1 or Gen2; and at least one of the following: a 128b / 130b conversion module, a message receiving and processing module, a message sending and processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5.

[0025] In an optional implementation, the abnormal operating states include: the link establishment phase state, the link recovery phase state, and the low-power state. The abnormal operating state-related modules corresponding to the link establishment phase state include modules other than the training stream sending module, the training stream receiving module, the link peer detection module, the link polling module, and the link equalization module. The abnormal operating state-related modules corresponding to the link recovery phase state include modules other than the training stream sending module, the training stream receiving module, the link rate switching module, and the link width switching module. The abnormal operating state-related modules corresponding to the low-power state include modules other than the management module corresponding to the current low-power sub-state.

[0026] In an optional implementation, the method further includes:

[0027] Multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate.

[0028] In an optional implementation, the multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate, including:

[0029] The register enable signal output circuit outputs an enable signal to the logic OR gate;

[0030] The enable signal and multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate.

[0031] Compared with related technologies, the technical solution of this application has the following advantages:

[0032] The PCIe clock gating circuit proposed in this application can effectively reduce the dynamic power consumption of the entire PCIe system. By distinguishing the actual working modules through PCIe link width, link speed, and link operating scenario, the clock of inactive modules can be turned off, which can significantly reduce clock and logic flips. Compared with clock gating that inserts registers in related technologies, the module-level clock module requires fewer hardware resources and is simpler to design.

[0033] In addition, the module-level clock gating circuit controls the clock opening and closing without software intervention; all control is completed automatically by hardware. At the same time, software can control the opening and closing of the clock gating, increasing the flexibility of the entire solution.

[0034] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures and processes shown in the description and the accompanying drawings. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 is a structural block diagram of a PCIe clock gating circuit according to an exemplary embodiment of this application.

[0037] Figure 2 is a schematic diagram of the module clock controlled by the link width control circuit according to an exemplary embodiment of the present application.

[0038] Figure 3 is a schematic diagram of the module clock controlled by the link rate control circuit according to an exemplary embodiment of the present application.

[0039] Figure 4 is a schematic diagram of the clock of the module controlled by the link state control circuit according to an exemplary embodiment of the present application.

[0040] Figure 5 is a schematic diagram illustrating the working principle of the PCIe clock control circuit according to an exemplary embodiment of this application.

[0041] Figure 6 is a flowchart of a PCIe clock control method according to an exemplary embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] Because PCIe has many features and cannot enter a low-power state when the link is under load, dynamic power consumption accounts for a relatively high proportion of the total power consumption in PCIe systems, and clock-flip power consumption accounts for a very high proportion of dynamic power consumption. Generally, register gating is added during the design of PCIe systems to reduce the flipping of register D and clock flipping, thereby reducing dynamic power consumption.

[0044] PCIe link widths can support up to x16. When system traffic is low, such a large link width is unnecessary. PCIe systems allow both ends to negotiate and reduce the link width. When an unused link enters electrical idle, the clock of the corresponding link can be turned off, thereby reducing the dynamic power consumption of the PCIe system.

[0045] As the PCIe protocol iterates and its functionality increases, the scale of PCIe systems also grows. PCIe systems need to be backward compatible with previous versions, resulting in a greater number of features that the system must support. Even if older features are not used, their clock and logic flips still contribute to dynamic power consumption. However, in reality, PCIe typically operates stably in only one link configuration most of the time. This means that most modules responsible for different link widths and speeds are idle, thus avoiding the dynamic power consumption caused by clock flips in these modules. Furthermore, a significant portion of the logic modules in a PCIe system are used for link training, but these modules do not need to operate when the PCIe system is running (state machine in L0 state). The clock and logic flips of these modules contribute to dynamic power consumption.

[0046] Furthermore, related technologies for PCIe systems reduce dynamic power consumption by adding register gating. Register gating has several drawbacks: 1. It consumes significant control resources; 2. It negatively impacts timing; 3. It has limited impact on dynamic gating efficiency; 4. The register gating logic cannot be reused. Related technologies using module-level clock gating mostly employ customized logic, which cannot be reused when the PCIe system is upgraded or the application scenario changes.

[0047] Based on the above analysis, this application proposes a PCIe clock gating circuit, which has the following characteristics:

[0048] 1. Utilize the characteristics of PCIe systems operating at one link width (x1, x2, x4, x8, and x16) and one link rate (8b / 10b encoding for Gen1 or Gen2, 128b / 130b encoding for Gen3, Gen4, or Gen5, and PAM4 encoding for Gen6) to design clock gating. Use module-level clock gating to shut down the clocks of other inactive modules with the corresponding link width and link rate. This reduces clock and logic flips of related modules, thereby reducing dynamic power consumption.

[0049] 2. Utilize the characteristic that PCIe system link training-related modules do not work in the L0 state to design a clock gating system, and use module-level clock gating to turn off the clocks of all modules related to link training.

[0050] 3. Use dedicated clock gating circuits and package them into general-purpose clock gating component modules (CBBs). Using circuits specifically optimized for clock gating, which can provide better performance and lower leakage current, and instantiating them at the top level after packaging them into modules can increase the reusability of module-level clock gating.

[0051] 4. Add register enable for module-level clock gating. The host can control the clock gating switch by configuring registers. When the enable switch is on, the hardware controls whether the clock gating is turned off. When the enable switch is off, the clock gating is always on. This method can increase the stability and flexibility of the system.

[0052] Referring to Figure 1, this application exemplarily proposes a PCIe clock gating circuit, including: a link width control circuit 101, a link rate control circuit 102, and a link state control circuit 103. Wherein:

[0053] The link width control circuit 101 is used to output a clock control signal to shut down non-current width related modules when the current link width is less than the maximum width; the non-current width related modules include related modules of other channels other than the channel corresponding to the current link width, and related modules corresponding to other link widths other than the current link width;

[0054] The link rate control circuit 102 is used to output a control signal to shut down the clock of non-current rate related modules. The non-current rate related modules include related modules corresponding to other link rates other than the current link rate.

[0055] The link state control circuit 103 is used to output a control signal to shut down the clock of the abnormal working state related modules when the current link state is an abnormal working state. The abnormal working state related modules include related modules corresponding to other link states other than the current link state.

[0056] The link state control circuit 103 is also used to output a control signal to shut down the clock of the training stream sending module, the training stream receiving module, and the link training related modules during normal operation.

[0057] In some embodiments, when the current link width is less than the maximum width supported by the PCIe system, unused channels (i.e., channels other than the current channel) enter an electrically idle state. At this time, the logic of these other channels is not used, and the clocks of the corresponding modules (i.e., modules not related to the current width) can be turned off. It is understood that when the current link width is the maximum width, since all channels will be used, it is not necessary to turn off the clocks of the corresponding modules. For example, if the current link width is 4 and the maximum width is 16, then the related modules for other link widths can be modules that are only used when the other 4 channels (excluding the 4 channels corresponding to the current link width) are enabled.

[0058] In some optional implementations, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of the de-offset module, scrambling / descrambling module and message bus module corresponding to each other channel; the path related module includes the rate conversion module, message sending module and message receiving module corresponding to the other link width.

[0059] Referring to Figure 2, in some embodiments, the training stream (TS) related module, the deskew module (offset removal module), the scrambling / descrambling module, and the message bus module are instantiated in the PCIe system based on the number of channels; that is, each channel corresponds to the aforementioned modules. When the current link width is less than the maximum width, the link width control circuit can generate a clock control signal to shut down the corresponding module, thereby shutting down the aforementioned modules corresponding to other unused channels (i.e., the training stream (TS) related module, the deskew module (offset removal module), the scrambling / descrambling module, and the message bus module, where the training stream (TS) related module is the link training related module and is always shut down under normal operating conditions). These modules can be referred to as channel-related modules.

[0060] For example, the non-current width-related modules also include path-related modules. The 8b / 10b and 128b / 130b conversions in the data path are also instantiated based on the number of channels. When the current link width is less than the maximum width, the clocks corresponding to the rate conversion modules related to the 8b / 10b and 128b / 130b conversions of other channels can be turned off. These rate conversion modules for other channels are path-related modules.

[0061] For example, the sending and receiving of packets in the data path is related to the width of the current PCIe link. The current link width of the PCIe determines the position of the packet's symbol code (identifier code) and token code, and different link widths have different decoding logic. Therefore, the PCIe system only needs to turn on the clocks of the packet sending and receiving modules related to the current link width; the clocks of the packet sending and receiving modules for other link widths can be turned off. The packet sending or receiving modules corresponding to other link widths are path-dependent modules.

[0062] In some optional implementations, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of the following: a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5; and at least one of the following: a PAM4 encoding / decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6. When the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2. The module includes at least one of the following: a block, a message receiving and processing module, and a message sending and processing module; and at least one of the following: a PAM4 encoding / decoding module, a message receiving and processing module, and a message sending and processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related module includes at least one of the following: an 8b / 10b conversion module, a message receiving and processing module, and a message sending and processing module corresponding to Gen1 or Gen2; and at least one of the following: a 128b / 130b conversion module, a message receiving and processing module, a message sending and processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5.

[0063] Referring to Figure 3, exemplarily, when the current link rate is Gen1 or Gen2, the clocks of the training stream (TS) transmit / receive module, 8b / 10b conversion module, and data transmit / receive module corresponding to Gen1 or Gen2 are all turned on, while the clocks of these modules are turned off at other link rates. That is, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include the modules corresponding to Gen3, Gen4, or Gen5 and Gen6. The link rate control circuit outputs a clock-on control signal to the modules corresponding to Gen1 or Gen2, and a clock-off control signal to the modules corresponding to Gen3, Gen4, or Gen5 and Gen6.

[0064] When the current link rate is Gen3, Gen4, or Gen5, the clocks of the training stream (TS) transmit / receive module, 128b / 130b conversion module, message receive processing module, message transmit processing module, and precoding module (which only operates at Gen5) corresponding to Gen3, Gen4, or Gen5 are turned on. At other link rates, the clocks of these modules are turned off. In other words, when the current link rate is Gen3, Gen4, or Gen5, for modules not related to the current rate, including those corresponding to Gen1 or Gen2 and Gen6, the link rate control circuit outputs a clock-on control signal to the modules corresponding to Gen3, Gen4, or Gen5, and a clock-off control signal to the modules corresponding to Gen1 or Gen2 and Gen6.

[0065] When the current link rate is Gen6, the clocks of the PAM4 codec module, message receiving processing module, and message sending processing module corresponding to Gen6 are turned on, while the clocks of these modules are turned off at other link rates. In other words, when the current link rate is Gen6, for modules not related to the current rate, including those corresponding to Gen1 or Gen2 and Gen3, Gen4, or Gen5, the link rate control circuit outputs a clock-on control signal to the Gen6-related modules, and a clock-off control signal to the Gen1 or Gen2 and Gen3, Gen4, or Gen5-related modules.

[0066] In some optional implementations, abnormal operating states include: the link establishment phase, the link recovery phase, and the low-power state. The modules related to the abnormal operating states corresponding to the link establishment phase include modules other than the training stream sending module, the training stream receiving module, the link peer detection module, the link polling module, and the link equalization module. The modules related to the abnormal operating states corresponding to the link recovery phase include modules other than the training stream sending module, the training stream receiving module, the link rate switching module, and the link width switching module. The modules related to the abnormal operating states corresponding to the low-power state include modules other than the management module corresponding to the current low-power sub-state.

[0067] Referring to Figure 4, for example, during the link establishment (configuration) phase, the clocks of the training stream (TS) sending module, the training stream (TS) receiving module, the link peer detection module, the link polling module, and the link equalization module can be turned on, while the clocks of other modules can be turned off.

[0068] Currently, during the link recovery phase, the clocks of the training stream (TS) sending module, the training stream (TS) receiving module, and the link rate switching and link width switching related modules can be turned on, while the clocks of all other modules can be turned off.

[0069] Currently, in a low-power state, the clocks of the corresponding low-power sub-state related modules can be turned on according to the current LTSSM state. For example, the clock of the L1 related module can be turned on during L1ss, while the clocks of other modules can be turned off. For example, the low-power sub-state related modules include the L0s management module, the L0p management module, the L1ss management module, and the L2 management module.

[0070] The link establishment phase, link recovery phase, and low-power state described above are all abnormal operating states. All other states are normal operating states. In normal operating states, the clocks of link training-related modules can be turned off, such as the training stream (TS) transmitting module, the training stream (TS) receiving module, and other link training-related modules. It should be noted that the clocks of the three modules corresponding to the normal operating state shown in Figure 4 can be turned off. The shutdown of other modules is controlled by the link width control circuit and the link rate control circuit. That is, the control signals output by the link width control circuit and the link rate control circuit are valid in normal operating states but invalid in abnormal operating states. In abnormal operating states, the control signals output by the link state control circuit control the clocks of each module.

[0071] In some optional implementations, the PCIe clock gating circuit also includes: a logic OR gate;

[0072] The OR gate is used to perform a logical OR operation on multiple control signals to be output to the same clock.

[0073] For example, under normal operating conditions, the link width control circuit, link rate control circuit, and link state control circuit output control signals to the clocks of each module according to their respective logic. There may be multiple control signals output to the clock of the same module. Therefore, a logic OR gate can be placed before the clock of the same module, so that multiple control signals are logically ORed by the logic OR gate before being output to the clock. In this way, as long as there is a control signal to turn on the clock, the clock will be turned on; and if all control signals output to the same clock are turn-off signals, the clock will be turned off. It should also be noted that under normal operating conditions, the clocks of modules related to link training are all turned off.

[0074] In some optional implementations, the PCIe clock gating circuit also includes: a register enable signal output circuit;

[0075] The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the set register, so as to enable the control signal output to the clock.

[0076] Referring to Figure 5, exemplarily, the enable signal output by the register enable signal output circuit is also output to a logic OR gate to perform a logical OR operation with the control signals output by the aforementioned link width control circuit, link rate control circuit, and link status control circuit. The enable signal output by the register enable signal output circuit depends on the register's configuration information. If the configuration information enables the control signals output by the aforementioned link width control circuit, link rate control circuit, and link status control circuit, a low level is output, ensuring that the final control signal output to the clock is based on the control signals output by these circuits. Conversely, if the configuration information invalidates the control signals output by these circuits, a high level is output, ensuring that the final control signal output to the clock is always high and unaffected by the control signals output by these circuits.

[0077] The design of the PCIe clock gating circuit is described below with reference to Figure 5. Control circuit A represents a circuit including link width control, link speed control, and link status control. CLK Gate represents the clock signal. Modules A and B represent modules that need to be turned off or on.

[0078] ① Design control signals for clock enable in different scenarios based on PCIe link width, link speed, and link operating scenarios;

[0079] ② The configuration register generates an enable signal. When the enable signal is low, the hardware controls whether the clock gating is turned off; when the enable signal is high, the clock gating is always open.

[0080] ③ Generate dedicated clock gating circuits and package them into general-purpose clock gating component modules (CLK Gate CBB). These circuits are specifically optimized for clock gating and can provide better performance and lower leakage current.

[0081] ④ Connect the universal clock gating module using a control signal. When the control signal is valid, turn on the clock; when the control signal is invalid, turn off the clock and output the controlled gating clock. Finally, input the gating clock output to the controlled module.

[0082] The above describes the PCIe clock gating circuit proposed in this application. This circuit can effectively reduce the dynamic power consumption of the entire PCIe system. By differentiating the actual working modules through PCIe link width, link speed, and link operating scenario, shutting down the clock of inactive modules can significantly reduce clock and logic flips. Compared to clock gating that inserts registers in related technologies, the module-level clock module requires fewer hardware resources and is simpler to design.

[0083] In addition, the module-level clock gating circuit controls the clock opening and closing without software intervention; all control is completed automatically by hardware. At the same time, software can control the opening and closing of the clock gating, increasing the flexibility of the entire solution.

[0084] This application supports different versions of the PCIe protocol and can reduce the dynamic power consumption of the PCIe controller in various business scenarios. Simulation results show that in the PCIe controller's IDLE mode (L1ss), system power consumption can be reduced by 70%; in a single-channel (x1) scenario under normal business conditions (L0), system power consumption can be reduced by 30%; and in a full-channel (x16) scenario under normal business conditions (L0), system power consumption can be reduced by 10%.

[0085] Accordingly, referring to Figure 6, this application exemplarily provides a PCIe clock control method, including:

[0086] In step S601, when the current link width is less than the maximum width, the link width control circuit outputs a control signal to shut down the clock of modules not related to the current width; the modules not related to the current width include modules related to other channels other than the channel corresponding to the current link width, and modules related to other link widths other than the current link width.

[0087] In step S602, the link rate control circuit outputs a control signal to shut down the clock of non-current rate related modules. The non-current rate related modules include related modules corresponding to other link rates other than the current link rate.

[0088] In step S603, when the current link state is an abnormal working state, the link state control circuit outputs a control signal to shut down the clock of the abnormal working state related modules. The abnormal working state related modules include related modules corresponding to other link states other than the current link state.

[0089] In step S604, when the current link state is in normal working state, the link state control circuit outputs a control signal to shut down the clock of the training stream sending module, the training stream receiving module and the link training related modules.

[0090] In some optional implementations, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of the de-offset module, scrambling / descrambling module and message bus module corresponding to each other channel; the path related module includes the rate conversion module, message sending module and message receiving module corresponding to the other link width.

[0091] In some optional implementations, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of the following: a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5; and at least one of the following: a PAM4 encoding / decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6. When the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2. The module includes at least one of the following: a block, a message receiving and processing module, and a message sending and processing module; and at least one of the following: a PAM4 encoding / decoding module, a message receiving and processing module, and a message sending and processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related module includes at least one of the following: an 8b / 10b conversion module, a message receiving and processing module, and a message sending and processing module corresponding to Gen1 or Gen2; and at least one of the following: a 128b / 130b conversion module, a message receiving and processing module, a message sending and processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5.

[0092] In some optional implementations, abnormal operating states include: the link establishment phase, the link recovery phase, and the low-power state. The modules related to the abnormal operating states corresponding to the link establishment phase include modules other than the training stream sending module, the training stream receiving module, the link peer detection module, the link polling module, and the link equalization module. The modules related to the abnormal operating states corresponding to the link recovery phase include modules other than the training stream sending module, the training stream receiving module, the link rate switching module, and the link width switching module. The modules related to the abnormal operating states corresponding to the low-power state include modules other than the management module corresponding to the current low-power sub-state.

[0093] In some alternative implementations, the method further includes:

[0094] Multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate.

[0095] In some optional implementations, the multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate, including:

[0096] The register enable signal output circuit outputs an enable signal to the logic OR gate;

[0097] The enable signal and multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate.

[0098] The above-described PCIe clock control method can be implemented using the PCIe clock gating circuit provided in the above embodiments. For details on the implementation, please refer to the description of the PCIe clock gating circuit in the above embodiments, which will not be repeated here.

[0099] It is understood that the circuit structures, names, and parameters described in the above embodiments are merely examples. Those skilled in the art can also make readily conceived combinations and adjustments to the structural features of the above embodiments according to their needs, and the concept of this application should not be limited to the specific details of the above examples.

[0100] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A PCIe clock-gated circuit, characterized in that, include: Link width control circuit, link rate control circuit, and link status control circuit; among which, The link width control circuit is used to output a clock control signal to shut down non-current width related modules when the current link width is less than the maximum width; the non-current width related modules include related modules of other channels other than the channel corresponding to the current link width, and related modules corresponding to other link widths other than the current link width; The link rate control circuit is used to output a control signal to shut down the clock of modules that are not related to the current rate. The modules that are not related to the current rate include modules related to other link rates besides the current link rate. The link state control circuit is used to output a clock control signal to shut down the related modules of the abnormal working state when the current link state is an abnormal working state. The related modules of the abnormal working state include related modules corresponding to other link states other than the current link state. The link state control circuit is also used to output a control signal to shut down the clock of the training stream sending module, the training stream receiving module, and the link training related modules during normal operation.

2. The PCIe clock gating circuit according to claim 1, characterized in that, The non-current width related modules include channel related modules and path related modules; the channel related modules include at least one of the offset removal module, scrambling module and message bus module corresponding to each other channel; the path related modules include the rate conversion module, message sending module and message receiving module corresponding to the other link widths.

3. The PCIe clock gating circuit according to claim 1, characterized in that, When the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of the following: a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5; and at least one of the following: a PAM4 encoding / decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6. When the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module, a message receiving module, and a message sending processing module corresponding to Gen1 or Gen2. The non-current rate related modules include at least one of the processing module and the message sending processing module, and at least one of the PAM4 encoding / decoding module, message receiving processing module and message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of the 8b / 10b conversion module, message receiving processing module and message sending processing module corresponding to Gen1 or Gen2, and at least one of the 128b / 130b conversion module, message receiving processing module, message sending processing module and Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

4. The PCIe clock gating circuit according to claim 1, characterized in that, Abnormal operating states include: the link establishment phase, the link recovery phase, and the low-power state. The modules related to the abnormal operating states corresponding to the link establishment phase include modules other than the training stream sending module, training stream receiving module, link peer detection module, link polling module, and link equalization module. The modules related to the abnormal operating states corresponding to the link recovery phase include modules other than the training stream sending module, training stream receiving module, link rate switching module, and link width switching module. The modules related to the abnormal operating states corresponding to the low-power state include modules other than the management module corresponding to the current low-power sub-state.

5. The PCIe clock gating circuit according to any one of claims 1-4, characterized in that, Also includes: Logic OR gate; The OR gate is used to perform a logical OR operation on multiple control signals to be output to the same clock.

6. The PCIe clock gating circuit according to claim 5, characterized in that, Also includes: Register enable signal output circuit; The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the set register, so as to enable the control signal output to the clock.

7. A PCIe clock control method, characterized in that, include: When the current link width is less than the maximum width, the link width control circuit outputs a clock control signal to shut down modules that are not related to the current width; the modules that are not related to the current width include modules related to other channels other than the channel corresponding to the current link width, and modules related to other link widths other than the current link width. The link rate control circuit outputs a clock control signal to shut down modules related to non-current rates. These non-current rate related modules include modules related to other link rates besides the current link rate. When the current link state is in an abnormal working state, the link state control circuit outputs a clock control signal to shut down the modules related to the abnormal working state. The modules related to the abnormal working state include the modules corresponding to other link states other than the current link state. When the current link state is in normal working state, the link state control circuit outputs a control signal to shut down the clock of the training stream sending module, the training stream receiving module, and the link training related modules.

8. The PCIe clock control method according to claim 7, characterized in that, The non-current width related modules include channel related modules and path related modules; the channel related modules include at least one of the offset removal module, scrambling module and message bus module corresponding to each other channel; the path related modules include the rate conversion module, message sending module and message receiving module corresponding to the other link widths.

9. The PCIe clock control method according to claim 7, characterized in that, When the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of the following: a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5; and at least one of the following: a PAM4 encoding / decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6. When the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module, a message receiving module, and a message sending processing module corresponding to Gen1 or Gen2. The non-current rate related modules include at least one of the processing module and the message sending processing module, and at least one of the PAM4 encoding / decoding module, message receiving processing module and message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of the 8b / 10b conversion module, message receiving processing module and message sending processing module corresponding to Gen1 or Gen2, and at least one of the 128b / 130b conversion module, message receiving processing module, message sending processing module and Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

10. The PCIe clock control method according to claim 7, characterized in that, Abnormal operating states include: the link establishment phase, the link recovery phase, and the low-power state. The modules related to the abnormal operating states corresponding to the link establishment phase include modules other than the training stream sending module, training stream receiving module, link peer detection module, link polling module, and link equalization module. The modules related to the abnormal operating states corresponding to the link recovery phase include modules other than the training stream sending module, training stream receiving module, link rate switching module, and link width switching module. The modules related to the abnormal operating states corresponding to the low-power state include modules other than the management module corresponding to the current low-power sub-state.

11. The PCIe clock control method according to any one of claims 7-10, characterized in that, Also includes: Multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate.

12. The PCIe clock control method according to claim 11, characterized in that, The multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate, including: The register enable signal output circuit outputs an enable signal to the logic OR gate; The enable signal and multiple control signals to be output to the same clock are passed through a logic OR gate and then output to the clock by the logic OR gate.

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