Substrate for manufacturing a high-electron-mobility transistor

Abstract

The present invention relates to a substrate for manufacturing a high-electron-mobility transistor (HEMT), successively comprising: - a support substrate (10) made of monocrystalline silicon, - an intermediate layer (20) made of silicon nitride (Si3N4) with a thickness of between 0.5 and 3 µm, and - a seed layer (30) made of monocrystalline GaN, the intermediate layer (20) forming a bonding interface between the support substrate (10) and the seed layer (30).

Description

[0001] SUBSTRATE FOR THE FABRICATION OF A HIGH ELECTRON MOBILITY TRANSISTOR

[0002] FIELD OF INVENTION

[0003] The present invention relates to a substrate for the fabrication of a high-electron-mobility transistor, a transistor fabricated from such a substrate, and an integrated monolithic structure based on such a substrate. The invention also relates to a method for fabricating a substrate and a high-electron-mobility transistor.

[0004] STATE OF THE ART

[0005] High electron mobility transistors (HEMTs) are power transistors based on an III-V semiconductor, particularly gallium nitride (GaN). Since bulk gallium nitride substrates are unavailable, HEMTs are typically fabricated on a GaN layer deposited epitaxially onto a silicon substrate. A known HEMT is described, for example, in document EP2983195 A1.

[0006] Silicon exhibits different structural and mechanical properties than GaN, particularly in terms of its crystal lattice and coefficient of thermal expansion. This results in significant stress accumulation within GaN, which increases with the thickness of the GaN layer. To compensate for these differences, intermediate layers are added between the silicon substrate and the GaN layers. These intermediate layers typically consist of aluminum nitride (AIN) and gallium aluminum nitride (AIGaN). However, these intermediate layers have low thermal conductivity, negatively impacting the operation of the HEMT transistor. Furthermore, the thickness and crystal orientation of such a substrate preclude monolithic CMOS-type integration of electronic circuits for measuring and controlling HEMT power transistors on a single silicon substrate.

[0007] Figure 1 schematically illustrates a known HEMT. From its base to its surface, the HEMT comprises a silicon substrate 11 with a plurality of intermediate layers 21, a GaN buffer layer 31, a GaN channel 41, and an AIGaN barrier layer 51. The channel and barrier layer form a heterojunction, allowing the formation of a two-dimensional electron gas confined within the channel. The source electrode 61 and drain electrode 62 are formed on the channel 41. The gate electrode 63 is arranged on the barrier layer 51.

[0008] Furthermore, it is desirable to fabricate HEMTs on an integrated substrate that includes other components such as driver transistors, CMOS integrated circuits, and any other electronic components intended for use in the same device as the HEMT. Standard silicon substrates are particularly well-suited for mounting electronic components directly on their silicon top surface due to their semiconducting properties, which are well-suited to these applications, and the maturity of silicon microelectronics.

[0009] Furthermore, the switching on and off of HEMT transistors generates electromagnetic fields that can interfere with the operation of neighboring HEMT transistors, as well as with electronic measurement and control circuits. This interference, known as "crosstalk," increases with the proximity of the components. It is desirable to reduce the level of interference from electromagnetic fields in order to increase the integration density on the surface of a substrate.

[0010] Monolithic integration solutions for HEMTs on GaN and other electronic components on a Silicon On Insulator (SOI) substrate have also been proposed. An SOI substrate typically comprises a silicon support substrate, a buried oxide layer, and a thin silicon layer on which a gallium nitride layer is grown by heteroepitaxy. However, the oxide layer acts as a thermal barrier, making heat dissipation from the HEMT difficult. Consequently, the transistor can only operate with low currents or must have a large surface area to facilitate heat dissipation. A compromise must therefore be found between performance and integration density.

[0011] DESCRIPTION OF THE INVENTION

[0012] One aim of the invention is to provide a substrate for the manufacture of a gallium nitride-based HEMT exhibiting improved electrical and thermal performance, enabling in particular the integration of other components on the same substrate while ensuring electrical isolation of the HEMTs from these other components.

[0013] To this end, the invention proposes a substrate for the fabrication of a high electron mobility transistor, comprising successively:

[0014] • a monocrystalline silicon support substrate, • an intermediate silicon nitride layer with a thickness between 0.5 and 3 pm, and

[0015] • a seed layer made of single-crystal GaN,

[0016] the intermediate layer forming a bonding interface between the support substrate and the seed layer.

[0017] The intermediate layer simultaneously ensures adhesion of the seed layer to the substrate and provides electrical insulation of the HEMT within the volume, along the substrate's thickness. This electrical insulation, which can be combined with lateral insulation provided by an electrically insulating wall, prevents interference with the HEMT from electromagnetic fields generated by other components. Consequently, this allows for increased component integration density on a single substrate.

[0018] Advantageously, the substrate further comprises a first epitaxial layer of single-crystal GaN on the seed layer, the first epitaxial layer and the seed layer together forming a single-crystal GaN buffer layer.

[0019] Advantageously, the buffer layer has a thickness between 1 and 10 pm.

[0020] Preferably, the substrate further comprises a second epitaxial layer of unintentionally doped GaN, arranged on the buffer layer.

[0021] Advantageously, the intermediate layer and the buffer layer are in the form of at least one block extending over only a first region of the supporting substrate.

[0022] Particularly advantageously, the intermediate layer and the buffer layer are in the form of a plurality of blocks, each block being suitable for the manufacture of a respective high electron mobility transistor.

[0023] Preferably, the substrate further comprises at least one electronic component arranged on a second region of the support substrate distinct from the first region.

[0024] Advantageously, the substrate further comprises an electrically insulating wall made of a dielectric material in contact with the substrate support portion, said electrically insulating wall being arranged between each pad and an electronic component arranged on the second region of the substrate support.

[0025] In some embodiments, the support substrate comprises a first portion of monocrystalline silicon having a first electrical resistivity and a second portion of monocrystalline silicon extending over the first portion, said second portion comprising areas having a second electrical resistivity lower than the first electrical resistivity, at least one electronic component arranged on an area having the second electrical resistivity.

[0026] The invention also relates to a high electron mobility transistor, comprising

[0027] • a substrate as described above,

[0028] • a GaN channel arranged on the buffer layer,

[0029] • a barrier layer forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel,

[0030] • a source electrode and a drain electrode electrically connected to the channel,

[0031] • a grid electrode formed on the barrier layer so that the grid electrode is physically isolated from the channel.

[0032] The invention also relates to a method for manufacturing a substrate for a high electron mobility transistor as described above, said method comprising the following steps:

[0033] • the deposition of at least one intermediate layer of SiaN4 on a monocrystalline silicon support substrate and / or on a monocrystalline GaN donor substrate, the sum of the thicknesses of the respective intermediate layers being between 0.5 and 3 pm;

[0034] • the formation of a weakening zone by implantation of ionic species in the donor substrate in monocrystalline GaN so as to delimit a seed layer to be transferred;

[0035] • the bonding of the donor substrate to the support substrate via the intermediate layer;

[0036] • the detachment of the donor substrate along the embrittlement zone so as to transfer the seed layer of single-crystal GaN onto the support substrate.

[0037] Preferably, the process further includes a step of forming a first epitaxial layer of single-crystal GaN on at least a portion of the seed layer, the first epitaxial layer and the seed layer together forming a buffer layer.

[0038] Advantageously, the process further includes etching a portion of the intermediate layer and buffer layer so as to expose a region of the supporting substrate.

[0039] Particularly advantageously, the process further comprises the epitaxial deposition of a single-crystal silicon layer on at least part of the exposed region of the support substrate, the thickness of said silicon layer being equal to the sum of the thicknesses of the intermediate layer and the buffer layer.

[0040] Advantageously, the process further includes the fabrication of at least one electronic component on the region lacking the intermediate layer and the buffer layer.

[0041] The invention also relates to a method for manufacturing a high electron mobility transistor, comprising:

[0042] • the manufacture of a substrate by a process such as described above,

[0043] • the formation, by epitaxy, of a transistor channel on the buffer layer,

[0044] • the formation by epitaxy of a barrier layer forming a heterojunction with the canal,

[0045] • the formation of a cover layer on the barrier layer,

[0046] • the formation of a source electrode and a drain electrode electrically connected to the channel,

[0047] • the formation of a grid electrode on the cover layer.

[0048] The invention also relates to a method for manufacturing an integrated substrate comprising at least one high electron mobility transistor and at least one electronic component, comprising implementing the method as described above for forming the transistor on a first region of the substrate and implementing the method as described above for forming the electronic component on a second region of the substrate, said method further comprising forming an electrically insulating wall between the electronic component and the high electron mobility transistor, said electrically insulating wall being in contact with the substrate support portion.

[0049] BRIEF DESCRIPTION OF THE FIGURES

[0050] Figure 1 is a cross-sectional view of a known high-electron-mobility transistor. Figure 2A is a cross-sectional view of a high-electron-mobility transistor according to the invention.

[0051] Figure 2B is a cross-sectional view of an integrated substrate comprising two high electron mobility transistors according to the invention.

[0052] Figure 3 is a substrate for the fabrication of a high electron mobility transistor according to the invention.

[0053] Figure 4 illustrates a particular embodiment of the support substrate.

[0054] Figure 5A illustrates a first embodiment of the first step in substrate formation. Figure 5B illustrates a second embodiment of the first step in substrate formation.

[0055] Figure 6A illustrates a first embodiment of a second manufacturing step of a substrate according to the invention.

[0056] Figure 6B illustrates a second embodiment of the second manufacturing step of a substrate according to the invention.

[0057] Figure 6C illustrates a third manufacturing step of a substrate according to the invention.

[0058] Figure 6D illustrates a fourth manufacturing step of a substrate according to the invention.

[0059] Figure 7 illustrates a substrate with a GaN buffer layer.

[0060] Figure 8 illustrates a substrate comprising two high electron mobility transistors according to the invention.

[0061] Figure 9 illustrates a substrate comprising two high electron mobility transistors according to the invention and a silicon layer on an exposed portion of the top face of the support substrate.

[0062] Figure 10 illustrates a substrate comprising two high electron mobility transistors and a plurality of electronic components.

[0063] Figure 11 illustrates the substrate of Figure 10, which also includes dielectric barriers between the electronic components and the transistors.

[0064] DETAILED DESCRIPTION OF IMPLEMENTATION METHODS

[0065] A HEMT transistor is shown in Figure 2A. The transistor comprises, from its base to its surface, a substrate 10 made of single-crystal silicon, an intermediate layer 20 made of silicon nitride (SiN), a buffer layer 35 made of single-crystal gallium nitride (GaN), a channel 45 made of single-crystal GaN, and a barrier layer 50 typically made of Al₂₅Ga₇₅N over the channel and forming a heterojunction with the channel 40. A cover layer 70, typically a thin layer of gallium nitride or silicon nitride (SiN) with a thickness between one monolayer and 100 nm, can be arranged on the barrier layer 50. The cover layer 70 is a passivation layer and also prevents oxidation of the barrier layer 50.

[0066] Source electrodes 61, drain electrode 62 and grid electrode 63 are arranged on the channel 40. The grid electrode 63 is arranged on the cover layer 70 between the source electrode 61 and the drain electrode 62.

[0067] Due to the heterojunction, a two-dimensional electron gas forms at the interface between channel 45 and barrier layer 50. This two-dimensional electron gas serves as a conduction channel within the HEMT transistor. The buffer layer 35 has a thickness between 1 and 10 pm and can be doped according to the desired HEMT properties. The buffer layer 35 helps to limit lateral and vertical leakage currents in the transistor and to better confine the two-dimensional electron gas of the heterojunction.

[0068] In some embodiments, with reference to Figure 2B, one or more HEMTs are arranged on an integrated substrate. The integrated substrate has a single common support substrate 10 and may include one or more identical or different HEMTs 100A, 100B. Each HEMT comprises an intermediate layer 20a, 20b of respective silicon nitride arranged directly on the support substrate 10, and a buffer layer 35a, 35b of respective buffer layers arranged on each intermediate layer 20a, 20b. The channel, barrier layer, cover layer (not shown), and electrodes of each HEMT are arranged as described above for an isolated HEMT.

[0069] The integrated substrate further comprises one or more other electronic components 81, 82, 83 that can be arranged directly on the support substrate 10. Such electronic components are, for example, CMOS circuits such as HEMT gate control circuits, known as "drivers," circuits for measuring an electric current or the temperature of the HEMT, or any other electronic component that can be used in combination with or on the same device as the HEMT. Optionally, electrically insulating walls 90 can be arranged between the HEMTs and / or the respective other electronic components. The walls 90 can have a wide variety of geometries in the plane of the substrate, chosen according to the geometry of the components on the support substrate. The height of the walls 90 can also be chosen according to the electromagnetic fields that may be generated during the operation of the components on the integrated substrate.In general, each wall extends from the top face of the support substrate to a height greater than or equal to the height of the intermediate layer 20. Thus, the walls 90 ensure good electrical insulation between the electronic components and further suppress the cross talk phenomenon between the HEMTs and other components.

[0070] The HEMT transistor or the integrated substrate containing a HEMT is made from a substrate shown in Figure 3. The substrate comprises a support substrate 10, an intermediate layer 20 of silicon nitride (Sisl^U), and a seed layer 30 of single-crystal gallium nitride (GaN).

[0071] The substrate is made of monocrystalline silicon and typically has a thickness between 300 and 1100 µm. In a main embodiment, the substrate has an electrical resistivity between a few ohms and a few million ohms, enabling the fabrication of most electronic components and also the fabrication of HEMTs.

[0072] In a particular embodiment, as illustrated in Figure 4, the support substrate 10 comprises a first portion 10A made of monocrystalline silicon. The support substrate further comprises a second portion 10B made of monocrystalline silicon having areas 11A with a first high electrical resistivity similar to or equal to that of the first portion, and areas 11B with a lower electrical resistivity than the first. These areas 11B extend over a portion of the upper surface of the support substrate on which the electrical components will be fabricated. The areas 11B with low electrical resistivity allow the fabrication of certain electronic components requiring an electrically conductive substrate on an integrated substrate.Thanks to the different resistivities in the different areas of the substrate, electronic components such as CMOS circuits, for example the "drivers" of the HEMT or circuits allowing the control and / or measurement of parameters such as an electric current or the temperature of the HEMT, can be manufactured in monolithic integration with the HEMTs on a single substrate.

[0073] The intermediate layer 20 ensures the bonding of the seed layer 30 to the substrate support 10. Simultaneously, the intermediate layer 20 provides electrical insulation between the HEMT and other electronic components, such as drivers or CMOS circuits, which may be fabricated on the same substrate. Furthermore, the dielectric properties of the intermediate layer 20 ensure good HEMT performance, including a high blocking voltage of up to 1200 V, while also guaranteeing good thermal conductivity between the HEMT and the substrate. For example, the thermal conductivity of silicon nitride is approximately ten times higher than that of SiU2, used, for instance, in SOI-type substrates.

[0074] The intermediate layer 20 has a thickness between 0.5 and 3 µm. The chosen thickness depends on the blocking voltage required for the HEMT to be fabricated on the substrate. Typically, a thicker intermediate layer results in higher HEMT blocking voltages. A maximum thickness of 3 µm allows for a blocking voltage of approximately 650 V for a HEMT of known and commonly used dimensions.

[0075] The thickness of the intermediate layer can also be adjusted according to the electrical insulation required for the electronic components to be integrated on the same substrate and the intensity of any potential interference during HEMT operation. The seed layer 30 is a thin layer of single-crystal GaN, typically between 10 nm and 1 pm thick, for example, 300 nm. The seed layer 30 is bonded via the intermediate layer 20 to the top surface of the support substrate 10. The seed layer 30 is used for the epitaxial deposition of a GaN layer to form the buffer layer of the HEMT.

[0076] We will now describe the fabrication steps of such a HEMT transistor. We begin by providing a substrate support 10. Typically, the substrate support is a standard (100) single-crystal silicon substrate, as widely used in the semiconductor and electronics industries. The (100) notation refers to the crystallographic orientation of the substrate and indicates that the surface of the substrate support is parallel to the (100) crystal plane of the silicon crystal lattice.

[0077] In the case where the substrate includes 11B regions exhibiting low electrical resistivity, we start with a portion of the substrate 10A exhibiting a first electrical resistivity and we deposit, typically by epitaxial growth, a 10B portion onto the 10A portion. During this step, we carry out selective doping of silicon in one or more 11B regions in order to obtain low electrical resistivity in the selected regions as illustrated in Figure 4, and simultaneously deposit the 11A regions lacking such doping.

[0078] For the fabrication of the GaN seed layer 30, a donor substrate is provided from which the single-crystal GaN seed layer will be formed. The donor substrate is typically a heterosubstrate, for example, a single-crystal GaN substrate on sapphire or a single-crystal GaN substrate on SiC. Such heterosubstrates are easier to fabricate than bulk substrates, especially for substrate diameters greater than 4 inches (approximately 100 mm). Alternatively, a bulk single-crystal GaN substrate can be used.

[0079] An intermediate layer of SisN4 is deposited on the support substrate and / or on the donor substrate. Figure 5A illustrates such an intermediate layer 20 of SisN4 deposited on the donor substrate 300. Figure 5B illustrates a layer of SisN420 deposited on the support substrate 10. Typically, the SisN4 is deposited by chemical vapor deposition (CVD). In some embodiments, a single layer of SisN4 is deposited either on a main face of the support substrate 10 or on a main face of the donor substrate 300.

[0080] Alternatively, and not shown, a thick layer, with a thickness close to the final thickness of the intermediate layer to be fabricated, is deposited either on the support substrate or on the donor substrate. A thin layer of SisN4 is also deposited on the other substrate between the support and donor substrates. After bonding, the thick SiaN4 layer and the thin SiaN4 layer form a single intermediate layer of SiaN420. In other embodiments, layers of a certain thickness can be deposited on both the support and donor substrates. In all embodiments, the sum of the thicknesses of the respective intermediate layers corresponds to the thickness of the intermediate layer 20 and is between 0.5 and 3 µm.

[0081] Depositing SiaN4 on the top surface of the donor substrate has the advantage of encapsulating the GaN top surface of the donor substrate and protecting this surface against silicon migration. This advantage applies to SiaN4 layers regardless of their thickness.

[0082] Typically, a surface treatment of each substrate containing a SisN4 layer is carried out after the deposition of the SiaN4, for example polishing to reduce the roughness of the SiaN4 face.

[0083] To prepare for the transfer of the GaN seed layer 30 onto the support substrate 10, ionic species, such as hydrogen and / or helium, are implanted to form a weakening zone 31 in the donor substrate 300. If a SisN4 layer 20 is deposited on the donor substrate 300, as shown in Figure 6A, the implantation is carried out on the donor substrate 300 containing the SisN4 layer, so that the weakening zone 31 is inside the donor substrate 300. When the SisN4 layer is deposited only on the support substrate 10, the implantation is carried out directly in the donor substrate 300, as illustrated in Figure 6B.

[0084] With reference to figure 6C, the weakened donor substrate 300 is glued onto the support substrate 10, so that the SisN4 layer(s) are arranged at the interface between the support substrate 10 and the donor substrate 300, and form an intermediate layer of Si3N4.

[0085] This bonding can be performed with or without the addition of material, typically under vacuum. Preferably, the bonding is achieved by atomic diffusion bonding (ADB) with the addition of silicon or tungsten. For example, a thin layer of silicon can be deposited on both the donor and support substrates before bonding them.

[0086] With reference to Figure 6D, the donor substrate 300 is then detached along the embrittlement zone 31, which leads to the transfer of the seed layer 30 of single-crystal gallium nitride onto the support substrate 10. The layer(s) of SisN4 form a single intermediate layer 20 at the interface between the support substrate 10 and the seed layer 30.

[0087] The 301 residue of the donor substrate can be reused for the transfer of one or more other layers of single-crystal GaN onto other substrates.

[0088] Subsequently, with reference to Figure 7, a first epitaxial layer 40 of GaN is deposited on the seed layer 30. The first epitaxial layer 40 and the seed layer 30 together form a buffer layer 35 of single-crystal GaN.

[0089] To fabricate a single HEMT, a channel 45 is formed directly by depositing a second layer of single-crystal GaN via epitaxy. Generally, this layer is not intentionally doped. A barrier layer 50 is then deposited on the channel 45, as illustrated in Figure 2A. Thanks to this barrier layer 50, which forms a heterojunction with the channel, a two-dimensional electron gas is generated at the interface between the barrier 50 and the channel 45, enabling electron conduction within the transistor.

[0090] A cover layer (not shown) can then be deposited on the barrier layer 50. The cover layer is for example a p-doped GaN layer for a standard HEMT, or a thin layer of GaN and / or SisN4 for a HEMT for radio frequency applications.

[0091] In a manner known per se, the source electrodes 61 and drain electrodes 62 are deposited on the barrier layer 50 and the channel 40 or on either side of the barrier layer 50, for example by etching through a mask, and then are subjected to annealing to form an ohmic contact with said barrier layer 50. The grid electrode 63 is typically deposited on the cover layer on the upper face of the barrier layer 50.

[0092] In the case of manufacturing an integrated substrate, selective etching of the substrate is carried out after the deposition of the first epitaxial layer 40. The etching allows, with reference to figure 8, to expose a region 102 of the support substrate in order to make one or more electronic components directly in the support substrate 10 in monocrystalline silicon.

[0093] After selective etching, one or more blocks, each composed of an intermediate layer 20A, 20B, and a buffer layer 35A, 35B, are stored in a first region 101 of the substrate. Each block can be used to manufacture a HEMT. The geometry of each block in the principal plane of the substrate can be chosen according to the HEMTs and electronic components to be manufactured and can be arbitrary. The geometry of the blocks can therefore be complex and is not limited to rectangular, square, or round shapes. A second region 102 of the substrate lacks the intermediate layer and the buffer layer and can be used for manufacturing electronic components other than HEMTs.

[0094] When the substrate support includes 11B zones exhibiting low resistivity as illustrated in Figure 4, selective etching advantageously exposes at least said 11B zones.

[0095] To fabricate silicon electronic components on the top surface of the integrated substrate, a layer of monocrystalline silicon 80 can optionally be deposited over all or part of the second region 102 of the substrate 10, which lacks the intermediate and buffer layers. Such a layer of monocrystalline silicon 80 is illustrated in Figure 9. The deposited monocrystalline silicon can be doped to suit the electronic components to be manufactured. Advantageously, the thickness of the monocrystalline silicon layer is approximately equal to the thickness of each pad, i.e., the sum of the thicknesses of the intermediate SiaN4 layer 20 and the buffer layer 35. This allows all the electronic components of the integrated substrate to have the same surface height and facilitates substrate integration and electrical isolation between the different components.

[0096] With reference to Figure 10, electronic components 81, 82, 83 can now be made in the second exposed region 102, preferably in the silicon layer 80 deposited in said region 102. HEMT transistors can be made in one or more blocks according to the steps described above for the fabrication of a single HEMT.

[0097] Advantageously, before or after the formation of the HEMTs and other electronic components, one or more insulating walls 90 are deposited at least up to the height of the intermediate layer 20, as illustrated in Figure 11. Preferably, such walls are made by depositing a dielectric material onto an exposed region of the substrate, for example, silicon dioxide (SiO2) or silicon nitride (SiN). The size and shape of the walls 90 can be adapted to the geometry of the electronic components and, in particular, to the electrical voltages applied to the HEMTs during the operation of the integrated substrate. The insulating walls maximize the protection of the electronic components from disturbances caused by the electromagnetic fields generated during HEMT switching.Therefore, the presence of these insulating walls makes it possible to increase the density of components on the surface of an integrated substrate.

[0098] REFERENCES EP2983195 A1

Claims

DEMANDS 1. Substrate for the fabrication of a high electron mobility transistor (HEMT), comprising successively: o a monocrystalline silicon substrate support (10), o an intermediate layer (20) of silicon nitride (SisN^) having a thickness between 0.5 and 3 pm, and o a seed layer (30) in single-crystal GaN, the intermediate layer (20) forming a bonding interface between the support substrate (10) and the seed layer (30).

2. Substrate according to claim 1, further comprising a first epitaxial layer (40) of single-crystal GaN on the seed layer (30), the first epitaxial layer (40) and the seed layer (30) together forming a buffer layer (35, 35a, 35b) of single-crystal GaN.

3. Substrate according to claim 2, in which the buffer layer (35, 35a, 35b) has a thickness between 1 and 10 pm.

4. Substrate according to claim 2 or claim 3, further comprising a second epitaxial layer of unintentionally doped GaN, arranged on the buffer layer (35, 35a, 35b).

5. Substrate according to any one of claims 2 to 4, wherein the intermediate layer (20, 20a, 20b) and the buffer layer (35, 35a, 35b) are in the form of at least one block extending over only a first region (101) of the supporting substrate (10).

6. Substrate according to claim 5, wherein the intermediate layer (20, 20a, 20b) and the buffer layer (35, 35a, 35b) are in the form of a plurality of blocks, each block being adapted for the manufacture of a respective high electron mobility transistor.

7. Substrate according to claim 5 or claim 6, further comprising at least one electronic component (81, 82, 83) arranged on a second region (102) of the support substrate distinct from the first region (101).

8. Substrate according to claim 7, further comprising an electrically insulating wall (90) of a dielectric material in contact with the portion (102) of the support substrate, said electrically insulating wall (90) being arranged between each block (70) and an electronic component (81, 82, 83) arranged on the second region (102) of the support substrate.

9. Substrate according to claim 7 or claim 8, wherein the support substrate (10) comprises a first portion (10A) of monocrystalline silicon having a first electrical resistivity and a second portion (10B) of monocrystalline silicon extending over the first portion, said second portion (10B) comprising areas (11B) having a second electrical resistivity lower than the first electrical resistivity, at least one electronic component (81, 82, 83) arranged on an area (11B) having the second electrical resistivity.

10. High electron mobility transistor, comprising o a substrate according to any one of claims 3 to 9, o a GaN channel (45) arranged on the buffer layer (35), o a barrier layer (50) forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel, o a source electrode (61) and a drain electrode (62) electrically connected to the channel (45), o a grid electrode (63) formed on the barrier layer (50) so that the grid electrode (63) is physically isolated from the channel (45).

11. A method for manufacturing a substrate for a high electron mobility transistor according to any one of claims 1 to 9, said method comprising the following steps: o the deposition of at least one intermediate layer (20) in SiaN4 on a support substrate (10) in single-crystal silicon and / or on a donor substrate (300) in single-crystal GaN, the sum of the thicknesses of the respective intermediate layers (20) being between 0.5 and 3 pm; o the formation of a weakening zone (31) by implantation of ionic species in the donor substrate (300) in single-crystal GaN so as to delimit a seed layer to be transferred; o the bonding of the donor substrate (300) to the support substrate (10) via the intermediate layer (20); o the detachment of the donor substrate (300) along the embrittlement zone (31) so as to transfer the seed layer (30) of single-crystal GaN onto the support substrate.

12. Method of manufacturing a substrate according to claim 11, further comprising a step of forming a first epitaxial layer (40) of single-crystal GaN on at least a portion of the seed layer (20), the first epitaxial layer (40) and the seed layer (30) together forming a buffer layer (35).

13. Method of manufacturing a substrate according to claim 11 or claim 12, further comprising etching a portion of the intermediate layer (20) and the buffer layer (35) so as to expose a region (102) of the support substrate (10).

14. Method of manufacturing a substrate according to claim 13, further comprising the epitaxial deposition of a single-crystal silicon layer (80) on at least a part of the exposed region (102) of the support substrate (10), the thickness of said silicon layer (80) being equal to the sum of the thicknesses of the intermediate layer (20) and the buffer layer (35).

15. Method of manufacturing a substrate according to claim 13 or claim 14, further comprising manufacturing at least one electronic component (81, 82, 83) on the region (102) devoid of the intermediate layer (20) and the buffer layer (35).

16. A method for manufacturing a high electron mobility transistor, comprising: o the manufacture of a substrate by the process according to any one of claims 11 to 15, o the formation by epitaxy of a channel (45) of the transistor on the buffer layer (35), o the formation by epitaxy of a barrier layer (50) forming a heterojunction with the channel (45), o the formation of a coating layer on the barrier layer (70), o the formation of a source electrode (61) and a drain electrode (62) electrically connected to the channel (45), o the formation of a grid electrode (63) on the cover layer (70).

17. A method for manufacturing an integrated substrate comprising at least one high electron mobility transistor and at least one electronic component, comprising implementing the method according to claim 16 for forming the transistor on a first region (101) of the substrate and implementing the method according to claim 15 for forming the electronic component on a second region (102) of the substrate, said method further comprising forming an electrically insulating wall (90) between the electronic component (81, 82, 83) and the high electron mobility transistor, said electrically insulating wall (90) being in contact with the substrate support portion (102).

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