Electronic device and manufacturing method thereof

Abstract

This electronic device comprises: a circuit element layer including a scan driving unit and a pixel driving unit; and a display element layer including a light emitting element connected to the pixel driving unit, wherein the circuit element layer includes a first transistor included in the pixel driving unit, a second transistor included in the scan driving unit, and an insulating layer disposed between a first oxide semiconductor layer of the first transistor and a first gate of the first transistor, and wherein the insulating layer includes a lower oxide layer, an upper oxide layer disposed on the lower oxide layer, and a nitride layer disposed between the lower oxide layer and the upper oxide layer and having a hydrogen concentration higher than that of the upper oxide layer.

Description

Electronic device and method of manufacturing the same

[0001] The present invention relates to an electronic device and a method for manufacturing the same, and more specifically, to a display panel with improved display characteristics and a method for manufacturing the same.

[0002] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles may include a display device for displaying images. The display device may include a plurality of pixels, and each pixel may include a light-emitting element that generates light and a driving element connected to the light-emitting element.

[0003] Display devices equipped with organic light-emitting diodes among light-emitting devices are attracting attention as next-generation display devices due to their advantages such as wide viewing angles, fast response speeds, and low power consumption. However, as display devices become larger in area and higher in resolution, driving devices with improved characteristics are required.

[0004] The display panel may include a pixel comprising a light-emitting element and a pixel driver that drives the pixel, and a driver that drives the pixels. The driver may include a scan driver and a data driver. The scan driver may be provided mounted on a substrate together with the pixel.

[0005] An electronic device according to one embodiment of the present invention comprises a substrate, a circuit element layer disposed on the substrate and including a scan driving unit and a pixel driving unit, and a display element layer disposed on the circuit element layer and including a light-emitting element connected to the pixel driving unit, wherein the circuit element layer comprises a first transistor included in the pixel driving unit and including a first oxide semiconductor layer and a first gate, a second transistor included in the scan driving unit and disposed on a layer different from the first oxide semiconductor layer and including a second oxide semiconductor layer and a second gate, and an insulating layer disposed between the first oxide semiconductor layer and the first gate, wherein the insulating layer comprises a lower oxide layer, an upper oxide layer disposed on the lower oxide layer, and a nitride layer disposed between the lower oxide layer and the upper oxide layer and having a hydrogen concentration higher than that of the upper oxide layer.

[0006] The second oxide semiconductor layer may have a higher mobility than the first oxide semiconductor layer.

[0007] The second oxide semiconductor layer may include indium tin gallium zinc oxide.

[0008] The first oxide semiconductor layer may include indium gallium zinc oxide or indium gallium oxide.

[0009] The second oxide semiconductor layer can be in contact with the upper oxide layer.

[0010] The thickness of the upper oxide layer may be lower than the thickness of the nitride layer.

[0011] The thickness of the upper oxide layer may be 200 Å or less.

[0012] The above circuit element layer may further include a plurality of lower patterns disposed below the first oxide semiconductor layer.

[0013] Any one of the above lower patterns can be connected to the first oxide semiconductor layer.

[0014] Any one of the above lower patterns can constitute a capacitor included in the pixel driving unit.

[0015] An electronic device according to one embodiment of the present invention further comprises a buffer layer disposed between the lower patterns and the first oxide semiconductor layer, wherein the buffer layer may include a lower buffer oxide layer, an upper buffer oxide layer disposed between the lower buffer oxide layer and the first oxide semiconductor layer, and a buffer nitride layer disposed between the lower buffer oxide layer and the upper buffer oxide layer.

[0016] The thickness of the above nitride layer may be less than or equal to the thickness of the above buffer nitride layer.

[0017] The above nitride layer may include silicon nitride or silicon oxynitride.

[0018] An electronic device according to one embodiment of the present invention comprises a display panel, a processor for outputting data to the display panel, and a power module for providing power to the display panel, wherein the display panel comprises a light-emitting element, a pixel driving unit connected to the light-emitting element and comprising a first transistor, a scan driving unit comprising a second transistor, a gate line connecting the pixel driving unit and the scan driving unit, a data line connected to the pixel driving unit and insulatingly intersecting the gate line, and a plurality of insulating layers, wherein the insulating layers comprise a first insulating layer disposed below a first semiconductor layer of the first transistor, and a second insulating layer disposed between the first semiconductor layer and the first gate of the first transistor, wherein each of the first insulating layer and the second insulating layer comprises a lower oxide layer, an upper oxide layer disposed on the lower oxide layer, and

[0019] It includes a nitride layer disposed between the lower oxide layer and the upper oxide layer.

[0020] The second semiconductor layer of the second transistor is disposed on the second insulating layer, and the second semiconductor layer may include a material having a higher mobility than the first semiconductor layer.

[0021] The second semiconductor layer comprises indium tin gallium zinc oxide, and the first semiconductor layer may comprise indium gallium zinc oxide or indium gallium oxide.

[0022] An electronic device according to one embodiment of the present invention further includes a plurality of lower patterns disposed below the first insulating layer, and the first semiconductor layer is provided in a plurality, and any one of the lower patterns may be connected to the first semiconductor layer.

[0023] The upper oxide layer of the second insulating layer is in contact with the second semiconductor layer, and the thickness of the upper oxide layer of the second insulating layer may be about 200 Å or less.

[0024] The insulating layer further includes a gate insulating layer disposed between the second semiconductor layer and the second gate of the second transistor, and the gate insulating layer may be disposed between the second insulating layer and the first gate.

[0025] A method for manufacturing an electronic device according to an embodiment of the present invention comprises the steps of: forming a plurality of lower conductive patterns on a substrate; sequentially stacking a first lower oxide layer, a first nitride layer, and a first upper oxide layer on the lower conductive patterns to form a first insulating layer; forming a first semiconductor layer on the first insulating layer; sequentially stacking a second lower oxide layer, a second nitride layer, and a second upper oxide layer on the first insulating layer to form a second insulating layer; forming a second semiconductor layer on the second insulating layer; forming a first gate overlapping the first semiconductor layer and a second gate overlapping the second semiconductor layer; forming a third insulating layer covering the first gate and the second gate; and forming a plurality of connecting electrodes on the third insulating layer.

[0026] The step of forming the second insulating layer may include the step of forming the second lower oxide layer by depositing an oxide, the step of forming the second nitride layer by depositing a nitride on the second lower oxide layer, and the step of forming the second upper oxide layer by depositing an oxide on the second nitride layer.

[0027] According to the present invention, the integration density of the scan driving unit can be improved, so that an electronic device having a narrow bezel can be provided.

[0028] In addition, according to the present invention, an electronic device with improved reliability can be provided by improving the driving range and lifespan of the pixel transistor.

[0029] FIG. 1a is a perspective view of an electronic device according to one embodiment of the present invention.

[0030] FIG. 1b is a block diagram of an electronic device according to one embodiment of the present invention.

[0031] FIG. 2 is a diagram illustrating an exemplary cross-section of an electronic device shown in FIG. 1a.

[0032] FIG. 3 is a drawing exemplarily illustrating a cross-section of the display panel shown in FIG. 2.

[0033] Figure 4 is a block diagram of the electronic device shown in Figure 1.

[0034] FIG. 5 is an equivalent circuit diagram of any one of the pixels according to one embodiment of the present invention.

[0035] FIGS. 6a and FIGS. 6b are cross-sectional views of a display panel according to one embodiment of the present invention.

[0036] FIGS. 7a to 7e are graphs illustrating changes in the characteristics of a semiconductor layer according to the thickness of an insulating layer according to an embodiment of the present invention.

[0037] FIGS. 8a to 8i are cross-sectional views illustrating a method for manufacturing a display panel according to an embodiment of the present invention.

[0038] FIG. 9 is a block diagram of an electronic device according to one embodiment.

[0039] FIG. 10 is a schematic diagram of an electronic device according to various embodiments.

[0040] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0041] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content.

[0042] "And / or" includes all one or more combinations that the associated configurations can define.

[0043] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0044] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Additionally, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and may be explicitly defined herein unless interpreted in an ideal or overly formal sense.

[0046] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0047] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0048] FIG. 1a is a perspective view of an electronic device according to one embodiment of the present invention. FIG. 1b is a block diagram of an electronic device according to one embodiment of the present invention. The present invention will be described with reference to FIG. 1a and FIG. 1b.

[0049] As illustrated in FIG. 1a, the electronic device (DD) may include long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1). However, this is illustrated as an example, and the electronic device (DD) may include sides of equal length for each of the first direction (DR1) and the second direction (DR2), and is not limited to any one embodiment.

[0050] Hereinafter, the direction that intersects substantially perpendicularly with the plane defined by the first direction (DR1) and the second direction (DR2) is defined as the third direction (DR3). Additionally, in this specification, the meaning of "when viewed on a plane" is defined as the state viewed from the third direction (DR3).

[0051] The front surface of the electronic device (DD) can be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the electronic device (DD) can be provided to the user through the display surface (DS).

[0052] A display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) is an area where an image is displayed, and the non-display area (NDA) may be an area where an image is not displayed. The non-display area (NDA) may be adjacent to at least one side of the display area (DA). In this embodiment, the non-display area (NDA) may have a frame shape that surrounds the display area (DA). However, this is illustrated as an example, and in an electronic device (DD) of another embodiment of the present invention, the non-display area (NDA) may be omitted, and in this case, the display surface (DS) may consist only of the display area (DA).

[0053] The electronic device (DD) may detect inputs applied from outside the electronic device (DD). For example, the electronic device (DD) may detect a first input by touch (TC) and a second input by touch pen (PEN). The first input by touch (TC) may include various forms of external inputs, such as a part of the user's body, light, heat, or pressure. The touch pen (PEN) may be an active pen or an electromagnetic pen. The touch pen (PEN) includes active pens, passive pens, electromagnetic pens, etc., and is not limited to any one embodiment. The touch pen (PEN) may be defined as an input device, and the display area (DA) may provide the user with a sensing area capable of detecting input in addition to displaying an image.

[0054] Referring to FIG. 1b, the electronic device (DD) outputs various information through the display module (140) within the operating system. When the processor (110) executes an application stored in memory (120), the display module (140) provides application information to the user through the display panel (141).

[0055] The processor (110) obtains an external input through the input module (130) or the sensor module (161) and executes an application corresponding to the external input. For example, if a user selects a camera icon displayed on the display panel (141), the processor (110) obtains user input through the input sensor (161-2) and activates the camera module (171). The processor (110) transmits image data corresponding to the captured image obtained through the camera module (171) to the display module (140). The display module (140) can display an image corresponding to the captured image through the display panel (141).

[0056] The operation of the electronic device (DD) has been briefly described above. The configuration of the electronic device (DD) will be described in detail below. Some of the configurations of the electronic device (DD) described below may be integrated and provided as a single configuration, and a single configuration may be separated into two or more configurations.

[0057] Referring to FIG. 1b, the electronic device (DD) can communicate with an external electronic device (DD-A) through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device (DD) may include a processor (110), memory (120), an input module (130), a display module (140), a power module (150), an internal module (160), and an external module (170). According to one embodiment, at least one of the above-described components may be omitted, or one or more other components may be added to the electronic device (DD). According to one embodiment, some of the above-described components (e.g., a sensor module (161), an antenna module (162), or an acoustic output module (163)) may be integrated into another component (e.g., a display module (140)).

[0058] The processor (110) can execute software to control at least one other component (e.g., a hardware or software component) of an electronic device (DD) connected to the processor (110) and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (110) stores commands or data received from other components (e.g., an input module (130), a sensor module (161), or a communication module (173)) in a volatile memory (121), processes the commands or data stored in the volatile memory (121), and the resulting data can be stored in a non-volatile memory (122).

[0059] The processor (110) may include a main processor (111) and an auxiliary processor (112). The main processor (111) may include one or more of a central processing unit (111-1, CPU) or an application processor (AP). The main processor (111) may further include one or more of a graphic processing unit (111-2, GPU), a communication processor (CP), and an image signal processor (ISP). The main processor (111) may further include a neural processing unit (111-3, NPU). The neural processing unit is a processor specialized for processing artificial intelligence models, and the artificial intelligence model may be generated through machine learning. The artificial intelligence model may include a plurality of artificial neural network layers. An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially. At least two of the processing unit and processor described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0060] The auxiliary processor (112) may include a controller (112-1). The controller (112-1) may include an interface conversion circuit and a timing control circuit. The controller (112-1) receives a video signal from the main processor (111), converts the data format of the video signal to match the interface specifications with the display module (140), and outputs video data. The controller (112-1) may output various control signals required for driving the display module (140).

[0061] The auxiliary processor (112) may further include a data conversion circuit (112-2), a gamma correction circuit (112-3), a rendering circuit (112-4), etc. The data conversion circuit (112-2) receives image data from the controller (112-1) and can compensate the image data so that the image is displayed at a desired brightness according to the characteristics of the electronic device (DD) or the user's settings, etc., or can convert the image data to reduce power consumption or compensate for afterimages, etc. The gamma correction circuit (112-3) can convert image data or gamma reference voltage, etc. so that the image displayed on the electronic device (DD) has desired gamma characteristics. The rendering circuit (112-4) receives image data from the controller (112-1) and can render the image data by considering the pixel arrangement of the display panel (141) applied to the electronic device (DD). At least one of the data conversion circuit (112-2), gamma correction circuit (112-3), and rendering circuit (112-4) may be integrated into another component (e.g., main processor (111) or controller (112-1)). At least one of the data conversion circuit (112-2), gamma correction circuit (112-3), and rendering circuit (112-4) may also be integrated into the data driver (143) described later.

[0062] The memory (120) can store various data used by at least one component of the electronic device (DD) (e.g., a processor (110) or a sensor module (161)) and input or output data for related commands. The memory (120) may include at least one of a volatile memory (121) and a non-volatile memory (122).

[0063] The input module (130) can receive commands or data to be used for components of the electronic device (DD) (e.g., processor (110), sensor module (161) or sound output module (163)) from outside the electronic device (DD) (e.g., user or external electronic device (DD-A)).

[0064] The input module (130) may include a first input module (131) into which commands or data are input from a user, and a second input module (132) into which commands or data are input from an external electronic device (DD-A). The first input module (131) may include a microphone, a mouse, a keyboard, a key (e.g., a button), or a pen (e.g., a passive pen or an active pen). The second input module (132) may support a specified protocol that can be connected to the external electronic device (DD-A) via a wired or wireless connection. According to one embodiment, the second input module (132) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module (132) may include a connector that can be physically connected to the external electronic device (DD-A), such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0065] The display module (140) provides visual information to the user. The display module (140) may include a display panel (141), a scan driver (142), and a data driver (143). The display module (140) may further include a window, a chassis, and a bracket for protecting the display panel (141).

[0066] The display panel (141) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of the display panel (141) is not particularly limited. The display panel (141) may be a rigid type, or a flexible type that is rollable or foldable. The display module (140) may further include a supporter, a bracket, or a heat dissipation member that supports the display panel (141).

[0067] The scan driver (142) can be mounted on the display panel (141) as a driving chip. Additionally, the scan driver (142) can be integrated into the display panel (141). For example, the scan driver (142) may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT Gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) embedded in the display panel (141). The scan driver (142) receives a control signal from the controller (112-1) and outputs scan signals (or gate signals) to the display panel (141) in response to the control signal.

[0068] The display panel (141) may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel (141) in response to a control signal received from the controller (112-1). The light-emitting driver may be formed separately from the scan driver (142) or may be integrated into the scan driver (142).

[0069] The data driver (143) receives a control signal from the controller (112-1), converts the image data into an analog voltage (e.g., data voltage) in response to the control signal, and then outputs the data voltages to the display panel (141).

[0070] The data driver (143) may be integrated into other components (e.g., the controller (112-1)). The functions of the interface conversion circuit and the timing control circuit of the controller (112-1) described above may also be integrated into the data driver (143).

[0071] The display module (140) may further include a light-emitting driver and a voltage generating circuit, etc. The voltage generating circuit can output various voltages required for driving the display panel (141).

[0072] The power module (150) supplies power to the components of the electronic device (DD). The power module (150) may include a battery that charges the power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power module (150) may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and the modules described below. The power module (150) may include a wireless power transceiver electrically connected to the battery. The wireless power transceiver may include a plurality of coil-shaped antenna radiators.

[0073] The electronic device (DD) may further include an internal module (160) and an external module (170). The internal module (160) may include a sensor module (161), an antenna module (162), and an acoustic output module (163). The external module (170) may include a camera module (171), a light module (172), and a communication module (173).

[0074] The sensor module (161) can detect input by the user's body or input by a pen of the first input module (131) and generate an electrical signal or data value corresponding to the input. The sensor module (161) may include at least one of a fingerprint sensor (161-1), an input sensor (161-2), and a digitizer (161-3).

[0075] The fingerprint sensor (161-1) can generate a data value corresponding to the user's fingerprint. The fingerprint sensor (161-1) may include either an optical or capacitive fingerprint sensor.

[0076] The input sensor (161-2) can generate a data value corresponding to coordinate information of input by the user's body or input by a pen. The input sensor (161-2) generates a data value of the amount of change in capacitance due to the input. The input sensor (161-2) can detect input by a passive pen or transmit and receive data with an active pen.

[0077] The input sensor (161-2) may measure biosignals such as blood pressure, water content, or body fat. For example, if a user contacts a part of their body to the sensor layer or sensing panel and does not move for a certain period of time, the input sensor (161-2) may detect biosignals based on changes in the electric field caused by the part of the body and output information desired by the user to the display module (140).

[0078] The digitizer (161-3) can generate a data value corresponding to the coordinate information of the input by the pen. The digitizer (161-3) generates the amount of electromagnetic change caused by the input as a data value. The digitizer (161-3) can detect input by a passive pen or transmit and receive data with an active pen.

[0079] At least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be implemented as a sensor layer formed on the display panel (141) through a continuous process. The fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be positioned on the upper side of the display panel (141), and any one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3), such as the digitizer (161-3), may be positioned on the lower side of the display panel (141).

[0080] At least two of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) can be formed to be integrated into a single sensing panel through the same process. When integrated into a single sensing panel, the sensing panel can be positioned between the display panel (141) and a window positioned above the display panel (141). According to one embodiment, the sensing panel may be positioned on the window, and the position of the sensing panel is not particularly limited.

[0081] At least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be embedded in the display panel (141). That is, at least one of the fingerprint sensor (161-1), input sensor (161-2), and digitizer (161-3) may be formed simultaneously through a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel (141).

[0082] Additionally, the sensor module (161) may generate an electrical signal or data value corresponding to an internal or external state of the electronic device (DD). The sensor module (161) may further include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0083] The antenna module (162) may include one or more antennas for transmitting a signal or power to the outside or receiving it from the outside. According to one embodiment, the communication module (173) may transmit a signal to an external electronic device or receive it from an external electronic device through an antenna suitable for a communication method. The antenna pattern of the antenna module (162) may be integrated with one component of the display module (140) (e.g., a display panel (141)) or an input sensor (161-2), etc.

[0084] The sound output module (163) is a device for outputting a sound signal to the outside of the electronic device (DD), and may include, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for telephone reception. According to one embodiment, the receiver may be formed integrally with or separately from the speaker. The sound output pattern of the sound output module (163) may be integrated with the display module (140).

[0085] The camera module (171) can capture still images and video. According to one embodiment, the camera module (171) may include one or more lenses, image sensors, or image signal processors. The camera module (171) may further include an infrared camera capable of measuring the presence or absence of a user, the location of the user, the user's gaze, etc.

[0086] The light module (172) can provide light. The light module (172) may include a light-emitting diode or a xenon lamp. The light module (172) may operate in conjunction with the camera module (171) or operate independently.

[0087] The communication module (173) can support the establishment of a wired or wireless communication channel between an electronic device (DD) and an external electronic device (DD-A), and the performance of communication through the established communication channel. The communication module (173) may include one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a GNSS (global navigation satellite system) communication module, and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module (173) can communicate with the external electronic device (DD-A) through a short-range communication network such as Bluetooth, WiFi Direct, or IrDA (infrared data association), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN). The various types of communication modules (173) described above may be implemented as a single chip or each as a separate chip.

[0088] The input module (130), sensor module (161), camera module (171), etc., can be used to control the operation of the display module (140) in conjunction with the processor (110).

[0089] The processor (110) outputs commands or data to the display module (140), sound output module (163), camera module (171), or light module (172) based on input data received from the input module (130). For example, the processor (110) may generate image data in response to input data applied via a mouse or active pen, and output it to the display module (140), or generate command data in response to input data and output it to the camera module (171) or light module (172). If the processor (110) does not receive input data from the input module (130) for a certain period of time, it may switch the operating mode of the electronic device (DD) to a low-power mode or sleep mode to reduce the power consumed by the electronic device (DD).

[0090] The processor (110) outputs commands or data to the display module (140), sound output module (163), camera module (171), or light module (172) based on the sensing data received from the sensor module (161). For example, the processor (110) can compare the authentication data authorized by the fingerprint sensor (161-1) with the authentication data stored in the memory (120) and then execute an application based on the comparison result. The processor (110) can execute commands or output corresponding image data to the display module (140) based on the sensing data detected by the input sensor (161-2) or the digitizer (161-3). If the sensor module (161) includes a temperature sensor, the processor (110) receives temperature data regarding the temperature measured from the sensor module (161) and can further perform brightness correction, etc., on the image data based on the temperature data.

[0091] The processor (110) can receive measurement data regarding the presence or absence of a user, the location of the user, the user's gaze, etc. from the camera module (171). The processor (110) can further perform brightness correction on the image data based on the measurement data. For example, the processor (110), having determined the presence or absence of a user through input from the camera module (171), can output image data with corrected brightness to the display module (140) through the data conversion circuit (112-2) or the gamma correction circuit (112-3).

[0092] Some of the above components may be connected to each other via a communication method between peripheral devices, such as a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface), or UPI (Ultra path interconnect) link, to exchange signals (e.g., commands or data) with each other. The processor (110) may communicate with the display module (140) via an interface agreed upon with each other, and may, for example, use any of the communication methods described above, but is not limited to the communication methods described above.

[0093] The electronic device (DD) according to the various embodiments disclosed in this document may be of various forms. The electronic device (DD) may include, for example, at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device (DD) according to the embodiments of this document is not limited to the aforementioned devices.

[0094] FIG. 2 is a cross-sectional view of an electronic device illustrated in FIG. 1a. FIG. 3 is a cross-sectional view of a display panel illustrated in FIG. 2. The present invention will be described with reference to FIG. 2 and FIG. 3.

[0095] Referring to FIG. 2, the electronic device (DD) may include a display panel (DP), an input sensing unit (ISP), an anti-reflective layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2). The display panel (DP) corresponds to the display panel (141: see FIG. 1b) described above, and the input sensing unit (ISP) may correspond to the sensor module (161: see FIG. 1b) described above.

[0096] A display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel by way of example.

[0097] Referring to FIG. 3, the display panel (DP) may include a substrate (BS), a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE).

[0098] It may include a circuit element layer (DP-CL) disposed on a substrate (BS), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0099] The substrate (BS) may include glass or a flexible plastic material such as polyimide (PI).

[0100] A circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE) are sequentially disposed on a substrate (BS). Multiple pixels may be disposed on the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor disposed on the circuit element layer (DP-CL) and a light-emitting element disposed on the display element layer (DP-OLED) and connected to the transistor.

[0101] A thin film encapsulation layer (TFE) may be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) can protect pixels from moisture, oxygen, and external foreign substances. Meanwhile, although the thin film encapsulation layer (TFE) is illustrated as covering the entire area of ​​the substrate (SUB) in this embodiment, according to one embodiment of the present invention, the substrate (SUB) may include a portion of the area exposed from the thin film encapsulation layer (TFE). Alternatively, the area exposed from the thin film encapsulation layer (TFE) may be formed along the edge of the substrate (SUB), and is not limited to any one embodiment.

[0102] The input sensing unit (ISP) may be placed on the display panel (DP). The input sensing unit (ISP) may include a plurality of sensing units (not shown) for sensing external inputs in a capacitive manner. The input sensing unit (ISP) may be formed directly on the display panel (DP) during the manufacture of the electronic device (DD). Specifically, a conductive pattern or insulating layer constituting the input sensing unit (ISP) may be directly deposited or patterned on the display panel (DP). However, not limited thereto, the input sensing unit (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) via an adhesive layer, and is not limited to any one embodiment.

[0103] An anti-reflective layer (RPL) may be placed on an input sensing unit (ISP). The anti-reflective layer (RPL) can reduce the external light reflectivity of the electronic device (DD), thereby improving the visibility of the image displayed on the electronic device (DD). The anti-reflective layer (RPL) may include a phase delayer, a polarizer, a black matrix, a color filter, etc., and is not limited to any one embodiment. The anti-reflective layer (RPL) may be formed directly on the input sensing unit (ISP) through a coating or deposition process, or may be provided in the form of a film and attached to the input sensing unit (ISP) through an adhesive layer, and is not limited to any one embodiment.

[0104] The window (WIN) can be placed on the anti-reflective layer (RPL). The window (WIN) can protect the display panel (DP), the input sensing unit (ISP), and the anti-reflective layer (RPL) from external scratches and impacts.

[0105] A panel protection film (PPF) may be placed under a display panel (DP). The panel protection film (PPF) may support the display panel (DP) and protect the lower part of the display panel (DP). The panel protection film (PPF) may have insulating properties. For example, the panel protection film (PPF) may include resins such as polyethyleneterephthalate (PET), polyimide (PI), and polypropylene (PP), but is not limited thereto.

[0106] A first adhesive layer (AL1) is placed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded together by the first adhesive layer (AL1). A second adhesive layer (AL2) is placed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded together by the second adhesive layer (AL2).

[0107] FIG. 4 is a block diagram of the electronic device illustrated in FIG. 1. Referring to FIG. 4, the electronic device (DD) may include a display panel (DP), a timing controller (TC), a scan driver (SDV), a data driver (DDV), a light-emitting driver (EDV), and a voltage generator (VG). The display panel (DP), the timing controller (TC), the scan driver (SDV), the data driver (DDV), the light-emitting driver (EDV), and the voltage generator (VG) may correspond to the above-described display panel (141, see FIG. 1b), processor (110, see FIG. 1b), scan driver (142, see FIG. 1b), data driver (143, see FIG. 1b), light-emitting driver (not shown), and power module (150, see FIG. 1b), respectively.

[0108] The display panel (DP) may include a plurality of gate lines (GIL1~GILm, GWL1~GWLm, GRL1~GRLm, or scan lines), a plurality of light-emitting lines (EML1~EMLm), a plurality of data lines (DL1~DLn), and a plurality of pixels (PX). m and n are natural numbers.

[0109] Pixels (PX) can be electrically connected to gate lines (GIL1~GILm, GWL1~GWLm, GRL1~GRLm), light emission lines (EML1~EMLm), and data lines (DL1~DLn), respectively. Each pixel (PX) can be electrically connected to four corresponding gate lines, one corresponding data line, and one corresponding light emission line.

[0110] The gate lines (GIL1~GILm, GWL1~GWLm, GRL1~GRLm) may include a plurality of initialization gate lines (GIL1~GILm), a plurality of write gate lines (GWL1~GWLm), and a plurality of reset gate lines (GRL1~GRLm).

[0111] Each pixel (PX) can be connected to a corresponding one of the initialization gate lines (GIL1~GILm), a corresponding one of the write gate lines (GWL1~GWLm), and a corresponding one of the reset gate lines (GRL1~GRLm).

[0112] Gate lines (GIL1~GILm, GWL1~GWLm, GRL1~GRLm) are connected to a scan driver (SDV) and extend in a first direction (DR1) and can be arranged in a second direction (DR2). Light emission lines (EML1~EMLm) are connected to a light emission driver (EDV) and extend in a first direction (DR1) and can be arranged in a second direction (DR2). In this embodiment, the scan driver (SDV) and the light emission driver (EDV) may be spaced apart with pixels (PX) in between. However, this is illustrated as an example, and the scan driver (SDV) and the light emission driver (EDV) may be placed on the same side with respect to the pixels (PX) or may be formed as a single unit constituting a single driver. Alternatively, each of the scan driver (SDV) and the light emission driver (EDV) may include multiple divided drivers and is not limited to any one embodiment.

[0113] Meanwhile, in this embodiment, the scan driving unit (SDV) may be formed and provided on the display panel (DP). That is, the scan driving unit (SDV) and the pixels (PX) may be arranged on the same substrate and provided as a single display panel (DP).

[0114] Data lines (DL1~DLn) are connected to a data driver (DDV) and extend in a second direction (DR2) and can be arranged in a first direction (DR1). In this embodiment, the light-emitting driver (EDV) and the data driver (DDV) may be substantially placed on a display panel (DP). However, this is illustrated as an example, and at least one of the light-emitting driver (EDV) and the data driver (DDV) may be provided on a separate circuit board and electrically connected to the display panel (DP) to provide an electrical signal to the pixels (PX), and is not limited to any one embodiment.

[0115] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to match the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a gate control signal (SCS), a data control signal (DCS), and a light emission control signal (ECS).

[0116] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0117] The scan driver (SDV) can receive a gate control signal (SCS) from the timing controller (TC). The scan driver (SDV) can output gate signals to the gate lines (GIL1~GILm, GWL1~GWLm, GRL1~GRLm) in response to the gate control signal (SCS). The gate signals can be applied to pixels (PX) through the gate lines (GIL1~GILm, GWL1~GWLm, GRL1~GRLm).

[0118] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from the timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to pixels (PX) through data lines (DL1 to DLn).

[0119] The light-emitting driver (EDV) can receive a light-emitting control signal (ECS) from the timing controller (TC). The light-emitting driver (EDV) can output light-emitting signals to the light-emitting lines (EML1 to EMLm) in response to the light-emitting control signal (ECS). The light-emitting signals can be applied to pixels (PX) through the light-emitting lines (EML1 to EMLm).

[0120] Pixels (PX) can receive data voltages in response to gate signals. Pixels (PX) can display an image by emitting light of a brightness corresponding to the data voltages in response to light emission signals.

[0121] FIG. 5 is an equivalent circuit diagram of any one of the pixels according to an embodiment of the present invention. FIG. 5 shows a pixel (PXij) connected to the i-th gate lines (GWLi, GILi, GRLi), the j-th data line (DLj), and the i-th light emission line (EMLi). i and j are natural numbers. The present invention will be described below with reference to FIG. 5.

[0122] Referring to FIG. 5, a pixel (PXij) includes a light-emitting element (LD) and a pixel driver (PC). The light-emitting element (LD) is connected to a first power line (VDL) and the pixel driver (PC). The pixel driver (PC) can drive the light-emitting element (LD). The pixel driver (PC) may include a plurality of transistors (T1 to T7) and capacitors (C1, C2). The transistors (T1 to T7) and capacitors (C1, C2) can control the amount of current flowing to the light-emitting element (LD). The light-emitting element (LD) can generate light having a predetermined brightness according to the amount of current provided.

[0123] The pixel driver (PC) can be connected to the i-th gate lines (GWLi, GILi, GRLi), the i-th light emission lines (EMLi, EBLi), and the j-th data line (DLj). Additionally, the pixel (PXij) can be connected to power lines connected to the voltage generator (VG) to receive the first initialization voltage (VINT), the second initialization voltage (VAINT), the reference voltage (VREF), the first power supply voltage (ELVDD), and the second power supply voltage (ELVSS), respectively.

[0124] FIG. 5 illustrates signals transmitted to a pixel (PXij). The i-th write gate line (GWLi) receives the i-th write gate signal (GWi), and the i-th compensation gate line (GCLi) can receive the i-th compensation gate signal (GCi). The i-th initialization gate line (GILi) receives the i-th initialization gate signal (GIi), and the i-th reset gate line (GRLi) can receive the i-th reset gate signal (GRi). ​​The i-th light emission line (EMLi) receives the i-th light emission signal (EMi), and the i-th bias light emission line (EBLi) can receive the i-th bias light emission signal (EMBi). The j-th data line (DLj) receives the data voltage (Vdata). The first initialization line (VIL1) receives the first initialization voltage (VINT), and the second initialization line (VIL2) can receive the second initialization voltage (VAINT). The reference line (VRL) can receive the reference voltage (VREF). The first power line (PL1) can receive the first driving voltage (ELVDD), and the second power line (PL2) can receive the second driving voltage (ELVSS).

[0125] The pixel driver (PC) may include first to seventh transistors (T1, T2, T3, T4, T5, T6, T7), a first capacitor (C1), and a second capacitor (C2). Each of the transistors (T1 to T7) may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, for convenience in FIG. 5, either the source electrode or the drain electrode may be defined as the first electrode and the other may be described as the second electrode.

[0126] The transistors (T1 to T7) may include the first to seventh transistors (T1 to T7). In this embodiment, each of the first to seventh transistors (T1 to T7) may be a transistor comprising an oxide semiconductor. Each of the first to seventh transistors (T1 to T7) may be P-type or N-type.

[0127] The first transistor (T1) can be connected between the light-emitting control transistors (T5, T6) described later. The gate of the first transistor (T1) can be connected to the first node (N1). The first electrode of the first transistor (T1) can be connected to the fifth transistor (T5), and the second electrode can be connected to the second node (N2). The second electrode of the first transistor (T1) can be connected to the sixth transistor (T6), the seventh transistor (T7), the first capacitor (C1), and the second capacitor (C2) through the second node (N2). The first transistor (T1) can be a driving transistor. The first transistor (T1) can control the driving current flowing through the light-emitting element (LD) in response to the voltage of the first node (N1). At this time, the first power supply voltage (ELVDD) can be set to a voltage having a higher potential than the second power supply voltage (ELVSS).

[0128] Meanwhile, the first transistor (T1) may further include a bottom gate. That is, the first transistor (T1) may have a double gate structure. The bottom gate is connected to the second node (N2), and the second node (N2) may be connected to the second electrode of the first transistor (T1). That is, the bottom gate of the first transistor (T1) may form a source-sync structure. By having a source-sync structure, the first transistor (T1) according to the present invention can form a channel region with a secured driving range. Therefore, due to the widened driving range, the driving current can be finely controlled even in low grayscale, thereby providing an effect of improving image quality in low grayscale. A detailed explanation of this will be provided later.

[0129] A second transistor (T2) may be placed between the first transistor (T1) and the j-th data line (DLj) and connected to the first transistor (T1) and the j-th data line (DLj). The second transistor (T2) may include a gate connected to a write gate line (GWLi), a first electrode connected to a data line (DLj), and a second electrode connected to a first node (N1). The second transistor (T2) may supply a data voltage (Vdata) to the first node (N1) in response to an i-th write gate signal (GWi) transmitted through the write gate line (GWLi). The second transistor (T2) may be turned on when the i-th write gate signal (GWi) is received to electrically connect the data line (DLj) and the first node (N1).

[0130] The third transistor (T3) may be connected between the first node (N1) and a voltage line that receives the reference voltage (VREF). The first electrode of the third transistor (T3) receives the reference voltage (VREF), and the second electrode of the third transistor (T3) may be connected to the first node (N1). In this embodiment, the gate of the third transistor (T3) may receive the i-th reset gate signal (GRi). ​​When the reset gate signal (GRi) is supplied to the gate, the third transistor (T3) may be turned on to provide the reference voltage (VREF) to the first node (N1).

[0131] The fourth transistor (T4) can be connected between the light-emitting element (LD) and a power line that receives the second initialization voltage (VAINT). The first electrode of the fourth transistor (T4) is connected to the anode of the light-emitting element (LD) and the sixth transistor (T6), and the second electrode of the fourth transistor (T4) can receive the second initialization voltage (VAINT). The fourth transistor (T4) can be referred to as the first initialization transistor. The gate of the fourth transistor (T4) can receive the i-th initialization gate signal (GIi). The fourth transistor (T4) can be turned on when the i-th initialization gate signal (GIi) is supplied to the gate to provide the second initialization voltage (VAINT) to the anode of the light-emitting element (LD).

[0132] The fifth transistor (T5) can be connected between a power line receiving the first power supply voltage (ELVDD) and the third node (N3). The first electrode of the fifth transistor (T5) receives the first power supply voltage (ELVDD), and the second electrode of the fifth transistor (T5) is connected to the first electrode of the first transistor (T1). The gate of the fifth transistor (T5) can receive the i-th light emission signal (EMi). The fifth transistor (T5) may be referred to as the first light emission control transistor. When the i-th light emission signal (EMi) is supplied, the fifth transistor (T5) is turned on to electrically connect the first electrode of the first transistor (T1) and the power line receiving the first power supply voltage (ELVDD).

[0133] The sixth transistor (T6) can be connected between the first transistor (T1) and the light-emitting element (LD). Specifically, the first electrode of the sixth transistor (T6) can be connected to the second node (N2), and the second electrode can be connected to the anode of the light-emitting element (LD). The first electrode of the sixth transistor (T6) can be connected to the second electrode of the first transistor (T1), the first capacitor (C1), the seventh transistor (T7), and the second capacitor (C2) through the second node (N2). The gate of the sixth transistor (T6) can receive the i-th bias light-emitting signal (EMBi). The sixth transistor (T6) may be referred to as the second light-emitting control transistor. When the i-th light-emitting signal (EMBi) is supplied, the sixth transistor (T6) can be turned on to electrically connect the light-emitting element (LD) and the first transistor (T1).

[0134] Meanwhile, in this embodiment, the fifth transistor (T5) and the sixth transistor (T6) are shown to be turned on independently by different light emission signals (EMi, EMBi), but this is illustrated as an example, and the fifth transistor (T5) and the sixth transistor (T6) may be turned on by the same signal. In addition, in the pixel driving unit (PC) according to one embodiment of the present invention, either the fifth transistor (T5) or the sixth transistor (T6) may be omitted.

[0135] The seventh transistor (T7) can be connected between the second node (N2) and the power line where the first initialization voltage (VINT) is received. The first electrode of the seventh transistor (T7) can be connected to the first capacitor (C1), the first transistor (T1), the sixth transistor (T6), and the second capacitor (C2), respectively, through the second node (N2). The second electrode of the seventh transistor (T7) can receive the first initialization voltage (VINT). The seventh transistor (T7) can be referred to as the second initialization transistor. The gate of the seventh transistor (T7) can receive the i-th initialization gate signal (GIi). The seventh transistor (T7) can be turned on when the i-th initialization gate signal (GIi) is supplied to the gate to provide the first initialization voltage (VINT) to the first electrode of the first capacitor (C1) and the second electrode of the first transistor (T1).

[0136] Meanwhile, in this embodiment, the fourth transistor (T4) and the seventh transistor (T7) are shown as being turned on through the same gate signal (GIi), but this is illustrated as an example, and the fourth transistor (T4) and the seventh transistor (T7) may each be turned on independently through distinct gate signals.

[0137] The first capacitor (C1) may be placed between the first node (N1) and the second node (N2). The first capacitor (C1) may store the voltage difference between the first node (N1) and the second node (N2). The first capacitor (C1) may be referred to as a storage capacitor.

[0138] The second capacitor (C2) can be placed between the second node (N2) and the power line where the first power supply voltage (ELVDD) is received. That is, one electrode of the second capacitor (C2) receives the first power supply voltage (ELVDD), and the other electrode of the second capacitor (C2) can be connected to the first transistor (T1), the sixth transistor (T6), the seventh transistor (T7), and the first capacitor (C1) through the second node (N2). The second capacitor (C2) can store a charge corresponding to the voltage difference between the first power supply voltage (ELVDD) and the second node (N2). The second capacitor (C2) may be referred to as a hold capacitor. The second capacitor (C2) can have a higher storage capacity compared to the first capacitor (C1). Accordingly, the second capacitor (C2) can minimize the voltage change of the third node (N3) in response to the voltage change of the first node (N1).

[0139] Meanwhile, the number of transistors and the connection relationships of capacitors constituting the pixel driving unit (PC) according to one embodiment of the present invention may be varied and are not limited to any one embodiment.

[0140] FIGS. 6A and 6B are cross-sectional views of a display panel according to one embodiment of the present invention. FIGS. 6A and 6B illustrate a cross-section taken along I-I' shown in FIG. 4 and an embodiment in which a scan driving unit (SDV) is mounted on a display panel (DP). FIGS. 6A and 6B illustrate cross-sectional views of other embodiments. Hereinafter, the present invention will be described with reference to FIGS. 6A and 6B.

[0141] FIG. 6a illustrates a substrate (BS), a circuit element layer (DP-CL), and a display element layer (DP-OLED). The substrate (BS) may include a glass substrate, a sapphire substrate, a plastic film, or an organic / inorganic laminated film. The substrate (BS) may have a multilayer or single-layer structure. For example, the substrate (BS) may have a laminated structure of multiple plastic films bonded by an adhesive, or a laminated structure of a glass substrate and a plastic film bonded by an adhesive. The substrate (BS) may have flexibility. For example, the substrate (BS) may include polyimide (PI). However, this is described by way of example, and the substrate (BS) may be provided in a rigid state and is not limited to any one embodiment.

[0142] The circuit element layer (DD-CL) is disposed on the substrate (SUB). The circuit element layer (DD-CL) may include driving elements and a plurality of insulating layers (10, 20, 30, 40, 50, 60). The driving elements may include one transistor (TRp, hereinafter pixel transistor) among the transistors constituting the pixel driving unit (PC: see FIG. 5), one capacitor, and one transistor (TRd, hereinafter driving unit transistor) constituting the scan driving unit (SDV: see FIG. 4). The insulating layers (10, 20, 30, 40, 50, 60) may include first to sixth insulating layers (10, 20, 30, 40, 50, 60) sequentially stacked on the substrate (BS), but this is illustrated as an example and the number of insulating layers constituting the circuit element layer (DD-CL) can be varied and is not limited to any one embodiment.

[0143] A first sublayer may be disposed on a substrate (BS). The first sublayer may include a plurality of first sublayer patterns (BL1a, BL1b). The first sublayer patterns (BL1a, BL1b) may be disposed and may form a pixel (PX). The first sublayer patterns (BL1a, BL1b) may include a conductive material and may include a metal. Alternatively, the first sublayer patterns (BL1a, BL1b) may include a light-blocking material. The first sublayer patterns (BL1a, BL1b) may include the same material, but are not limited thereto and may include different materials and are not limited to any one embodiment.

[0144] The first insulating layer (10) is placed on the substrate (BS) and covers the first lower patterns (BL1a, BL1b).

[0145] A second lower layer may be disposed on the first insulating layer (10). The second lower layer may include a plurality of second lower patterns (BL2a, BL2b, BL2c).

[0146] Two of the second sub-patterns (BL2a, BL2b) among the second sub-patterns (BL2a, BL2b) shown in FIG. 6a can be placed superimposed on the first sub-patterns (BL1a, BL1b), respectively. The two second sub-patterns (BL2a, BL2b) can form a pixel (PX). One of the two second sub-patterns (BL2a, BL2b) (BL2a) can function as the bottom gate of a pixel transistor (TRp) and be connected to the pixel transistor (TRp). The other of the two second sub-patterns (BL2a, BL2b) (BL2b) can be one electrode of a capacitor (C1).

[0147] The remaining lower pattern (BL2c) among the second lower patterns (BL2a, BL2b, BL2c) shown in FIG. 6a may constitute a scan drive unit (SDV). The second lower patterns (BL2a, BL2b, BL2c) may include a conductive material and may include a metal. The second lower patterns (BL2a, BL2b, BL2c) may include the same material, but are not limited thereto and may include different materials and are not limited to any one embodiment.

[0148] The second insulating layer (20) is disposed on the first insulating layer (10) and covers the second lower patterns (BL2a, BL2b, BL2c). The second insulating layer (20) can cover the entire substrate (BS). The second insulating layer (20) may include a buffer layer. That is, the second insulating layer (20) can reduce the surface energy of the surface on which the circuit element layer (DP-CL) is formed so that it can be stably formed on the transistors (TRp, TRd) or the capacitor substrate (SUB).

[0149] Meanwhile, the second insulating layer (20) may include a first lower oxide layer (21), a first nitride layer (22), and a first upper oxide layer (23) stacked sequentially. That is, the second insulating layer (20) may include three insulating layers stacked sequentially.

[0150] The first lower oxide layer (21) may be a low-hydrogen layer with a low hydrogen content. The first lower oxide layer (21) may include silicon oxide. That is, the first lower oxide layer (21) may be formed from a material having the chemical formula SiOx. For example, the first lower oxide layer (21) may include silicon oxide (SiO2).

[0151] The first nitride layer (22) may have a higher hydrogen content than the first lower oxide layer (21). The first nitride layer (22) may include silicon nitride or silicon oxynitride. That is, the first nitride layer (22) may have a relatively higher nitrogen specific gravity than the first lower oxide layer (21) or the first upper oxide layer (23). The first nitride layer (22) may be formed from a material having the chemical formula SiNx or SiON.

[0152] The first upper oxide layer (23) may be a low-hydrogen layer with a low hydrogen content. The first upper oxide layer (23) may include silicon oxide. That is, the first upper oxide layer (23) may be formed from a material having the chemical formula SiOx. For example, the first upper oxide layer (23) may include silicon oxide (SiO2). In this embodiment, the first upper oxide layer (23) may be formed from the same material as the first lower oxide layer (21). However, this is described as an example, and the first upper oxide layer (23) and the first lower oxide layer (21) may be formed from independent materials and may be formed from different materials, and are not limited to any one embodiment.

[0153] A pixel transistor (TRp) may be disposed on the second insulating layer (20). The pixel transistor (TRp) is exemplarily illustrated as the first transistor (T1: see FIG. 5) shown in FIG. 5. However, this is exemplarily illustrated, and the pixel transistor (TRp) may correspond to the second to seventh transistors (T2 to T7) shown in FIG. 5 in common and is not limited to any one embodiment.

[0154] A pixel transistor (TRp) may include a gate (G1, hereinafter referred to as the first gate) and a semiconductor layer (A1, hereinafter referred to as the first semiconductor layer). The first semiconductor layer (A1) may be disposed on a second insulating layer (20). The first semiconductor layer (A1) may include an oxide semiconductor. For example, the first semiconductor layer (A1) may include at least one of indium, gallium, and zinc. In the present embodiment, the first semiconductor layer (A1) may include indium gallium zinc oxide (IGZO) or indium gallium oxide (IGO).

[0155] The first semiconductor layer (A1) can be divided into a source region, a drain region, and a channel region according to conductivity. Specifically, the channel region may be a region with relatively lower conductivity compared to the source region and the drain region, and may overlap with the first gate (G1).

[0156] The source and drain regions may be regions separated by the channel region, and each may be a region with conductive properties. The source and drain regions can each be formed through doping or reduction. For example, in an oxide semiconductor pattern, the reduced region may have higher conductivity compared to the unreduced region. Since the metal oxide constituting the oxide semiconductor pattern is deposited as metal through a reduction process, the regions where the metal oxide is reduced become the source and drain regions, and the remaining region can become the channel region.

[0157] The third insulating layer (30) is placed on the second insulating layer (20) and covers the first semiconductor layer (A1). The third insulating layer (30) is placed between the first semiconductor layer (A1) and the first gate (G1). The third insulating layer (30) may be a gate insulating film of a pixel transistor (TRp). That is, the pixel transistor (TRp) may have a top-gate structure.

[0158] The third insulating layer (30) according to the present embodiment may include a second lower oxide layer (31), a second nitride layer (32), and a second upper oxide layer (33) stacked sequentially. That is, the third insulating layer (30) may include three insulating layers stacked sequentially.

[0159] The second lower oxide layer (31) may be a low-hydrogen layer with a low hydrogen content. The second lower oxide layer (31) may include silicon oxide. That is, the second lower oxide layer (31) may be formed from a material having the chemical formula SiOx. For example, the second lower oxide layer (31) may include silicon oxide (SiO2).

[0160] The second nitride layer (32) may have a higher hydrogen content than the second lower oxide layer (31). The second nitride layer (32) may include silicon nitride or silicon oxynitride. That is, the second nitride layer (32) may have a relatively higher nitrogen specific gravity than the second lower oxide layer (31) or the second upper oxide layer (33). The second nitride layer (32) may be formed from a material having the chemical formula SiNx or SiON.

[0161] The thickness of the second nitride layer (32) may be less than or equal to the thickness of the first nitride layer (22). For example, the thickness of the second nitride layer (32) may be approximately 100 Å or more and 2000 Å or less. The second nitride layer (32) may serve to provide hydrogen to the first semiconductor layer (A1). Therefore, if the thickness of the second nitride layer (32) is less than 100 Å, it may be difficult to provide sufficient hydrogen to the first semiconductor layer (A1). Additionally, if the thickness of the second nitride layer (32) is greater than 100 Å, hydrogen may be excessively provided, and it may become difficult to control the channel region by the first gate (G1).

[0162] The second upper oxide layer (33) may be a low-hydrogen layer with a low hydrogen content. The second upper oxide layer (33) may include silicon oxide. That is, the second upper oxide layer (33) may be formed from a material having the chemical formula SiOx. For example, the second upper oxide layer (33) may include silicon oxide (SiO2). In this embodiment, the second upper oxide layer (33) may be formed from the same material as the second lower oxide layer (31). However, this is described as an example, and the second upper oxide layer (33) and the second lower oxide layer (31) may be formed from independent materials and may be formed from different materials, and are not limited to any one embodiment.

[0163] The thickness of the second upper oxide layer (33) may be smaller than the thickness of the second nitride layer (32). The third insulating layer (30) according to the present invention may be disposed between the first semiconductor layer (A1) and the first gate (G1) described later and function as a gate insulating film for a pixel transistor (TRp). The third insulating layer (30) can sufficiently secure the spacing distance between the first gate (G1) and the first semiconductor layer (A1) by sufficiently securing the thickness of the second nitride layer (32). Accordingly, the thickness of the second upper oxide layer (33) can be designed in various ways, and by forming it to be smaller than the thickness of the second nitride layer (32), the influence on the configuration formed on the second nitride layer (32) can be reduced. For example, the thickness of the second upper oxide layer (33) may be 200 Å or less, but is not limited thereto and may be provided in various embodiments as long as it is smaller than the thickness of the second nitride layer (32), and is not limited to any one embodiment.

[0164] The display panel (DP) according to the present invention includes a second nitride layer (32) so as to be able to stably supply hydrogen required for the first semiconductor layer (A1). As described above, the first semiconductor layer (A1) includes indium gallium zinc oxide, which may be a material requiring a gate insulating layer with a high hydrogen concentration. Since the second nitride layer (32) has a high hydrogen content, it can stably provide the hydrogen required for the first semiconductor layer (A). Accordingly, the driving range of the first semiconductor layer (A1) can be secured and reliability can be improved.

[0165] The driving transistor (TRd) may be placed on the third insulating layer (30). The driving transistor (TRd) may include a gate (G2, hereinafter the second gate) and a semiconductor layer (A2, hereinafter the second semiconductor layer). The second semiconductor layer (A2) may be placed on the third insulating layer (30). That is, the driving transistor (TRd) may have a top-gate structure.

[0166] The second semiconductor layer (A2) may include an oxide semiconductor. For example, the second semiconductor layer (A2) may include at least one of indium, gallium, and zinc. The second semiconductor layer (A2) may include a material different from the first semiconductor layer (A1) and may include a material with higher mobility than the first semiconductor layer (A1). In this embodiment, the second semiconductor layer (A2) may include indium tin gallium zinc oxide (ITGZO).

[0167] The second semiconductor layer (A2), like the first semiconductor layer (A1), can be divided into a source region, a drain region, and a channel region according to conductivity. Specifically, the channel region may be a region with relatively lower conductivity compared to the source region and the drain region, and may overlap with the second gate (G2). The source region and the drain region may be regions separated by the channel region, and each may be a region having conductive properties. The source region and the drain region may be regions containing metal precipitates formed by the reduction of metal oxides.

[0168] The second semiconductor layer (A2) can come into contact with the second upper oxide layer (33) of the third insulating layer (30). The third insulating layer (30) can provide sufficient hydrogen to the first semiconductor layer (A1) by including the second nitride layer (32). That is, the thickness required to provide hydrogen to the first semiconductor layer (A1) can be secured through the second nitride layer (32), so that even if the thickness of the second upper oxide layer (33) is reduced, the impact on the hydrogen supplied to the second semiconductor layer (A2) can be reduced.

[0169] The third insulating layer (30) can reduce the thickness of the second upper oxide layer (33) in contact with the second semiconductor layer (A2), thereby preventing the threshold voltage (Vth) of the second semiconductor layer (A2) from shifting in the negative direction due to the second upper oxide layer (33). According to the present invention, by including a second upper oxide layer (33) with a low thickness, the threshold voltage of the second semiconductor layer (A2) can be shifted in the positive direction, and the reliability of the driving transistor (TRd) can be improved.

[0170] A plurality of insulating patterns (40a, 40b, 40c) may be disposed on the second semiconductor layer (A2). A plurality of gate electrode patterns (G1, G2, CC) may be disposed on the insulating patterns (40a, 40b, 40c). The gate electrode patterns (G1, G2, CC) may include a first gate (G1), a second gate (G2), and a capacitor electrode (CC). The insulating patterns (40a, 40b, 40c) may be formed by patterning using the gate electrode patterns (G1, G2, CC) as a mask.

[0171] Two of the insulating patterns (40a, 40b, 40c), specifically 40a and 40b, can be placed in a pixel (PX). One of the two insulating patterns (40a, 40b), 40a, is placed between the first semiconductor layer (A1) and the first gate (G1) and can function as a gate insulating film for a pixel transistor (TRp). The other of the two insulating patterns (40a, 40b), 40b, is placed between the second lower pattern (BL2b) and the capacitor electrode (CC) and can function as a dielectric layer for the first capacitor (C1). The remaining one (40c) of the insulating patterns (40a, 40b, 40c) is placed in the scan driver (SDV) and is placed between the second semiconductor layer (A2) and the second gate (G2) to function as a gate insulating film of the driver transistor (TRd).

[0172] The fifth insulating layer (50) is disposed on the third insulating layer (30) and can cover insulating patterns (40a, 40b, 40c) and gate electrode patterns (G1, G2, CC). The fifth insulating layer (50) may include an organic layer or may include an organic layer and an inorganic layer.

[0173] Electrode patterns (CNa, CNb, CNc, CNd) may be disposed on the fifth insulating layer (50). Among the electrode patterns (CNa, CNb, CNc, CNd), the electrode patterns (CNa, CNb) constituting the pixel (PX) may penetrate the fifth insulating layer (50) and be connected to the source region and drain region of the first semiconductor layer (A1), respectively. Among the electrode patterns (CNa, CNb, CNc, CNd), the electrode patterns (CNc, CNd) constituting the scan driving unit (SDV) may penetrate the fifth insulating layer (50) and be connected to the source region and drain region of the second semiconductor layer (A2), respectively.

[0174] Meanwhile, one of the electrode patterns (CNa, CNb) constituting the pixel (PX) (CNb) may be connected to the second lower pattern (BL2a). In this case, the second lower pattern (BL2a) acts as a bottom gate for the first semiconductor layer (A1), and the pixel transistor (TRp) may have a dual gate structure including a top gate (G1) and a bottom gate (BL2a). The pixel transistor (TRp) may have a source-sync structure, and in this case, the pixel transistor (TRp) illustrated in FIG. 6a may correspond to the first transistor (T1) illustrated in FIG. 5. Meanwhile, this is illustrated as an example, and the electrode patterns (CNa, CNb, CNc, CNd) may not be connected to the second lower patterns (BL2a, BL2b) and are not limited to any one embodiment.

[0175] The sixth insulating layer (60) can be disposed on the fifth insulating layer (50) to cover electrode patterns (CNa, CNb, CNc, CNd). A display element layer (DP-OLED) can be disposed on the sixth insulating layer (60).

[0176] The display element layer (DP-OLED) may include a light-emitting element (LD) and a seventh insulating layer (70). The seventh insulating layer (70) is disposed on the sixth insulating layer (60) and may provide a predetermined opening to the pixel (PX). The seventh insulating layer (70) may function as a pixel defining film.

[0177] The light-emitting element (LD) may include an anode (AE), a light-emitting layer (EM), and a cathode (CE). The seventh insulating layer (70) exposes at least a portion of the anode (AE) through an opening. The light-emitting layer (EM) may be placed at the opening and between the anode (AE) and the cathode (CE). The cathode (CE) may be placed on the seventh insulating layer (70) and may cover the entire display area. In this embodiment, the cathode (CE) is shown as extending to the scan driver (SDV), but is not limited thereto, and the cathode (CE) may not overlap with the scan driver (SDV) and is not limited to any one embodiment.

[0178] Meanwhile, referring to FIG. 6b, in a display panel (DP) according to one embodiment of the present invention, the fourth insulating layer (40) may be provided as a layer having a single shape. The fourth insulating layer (40) is disposed on the third insulating layer (30) and completely covers the upper surface of the second upper oxide layer (33).

[0179] At this time, the first semiconductor layer (A1) and the second semiconductor layer (A2) can each be divided into a channel region, a source region, and a drain region through a doping process. That is, in each of the first semiconductor layer (A1) and the second semiconductor layer (A2), regions having a high dopant concentration through the doping process become the source region / drain region, and the remaining region overlapping with the gates (G1, G2) can become the channel region. Meanwhile, a low-doping region with a dopant concentration higher than that of the channel region but lower than that of the source region or drain region may be further formed between the source region or drain region and the channel region, and is not limited to any one embodiment.

[0180] Even if the fourth insulating layer (40) is formed with patterns (40a, 40b, 40c) as shown in FIG. 6a or formed integrally as shown in FIG. 6b, the third insulating layer (30) may not be affected by the fourth insulating layer (40). Accordingly, a display panel according to one embodiment of the present invention includes a third insulating layer (30) composed of a second lower oxide layer (31), a second nitride layer (32), and a second upper oxide layer (33), thereby supplying sufficient hydrogen to the first semiconductor layer (A1) while shifting the threshold voltage of the second semiconductor layer (A2) in a positive direction. Therefore, all characteristics required for the first semiconductor layer (A1) and the second semiconductor layer (A2), which are made of different materials, can be satisfied through a single insulating layer (30), thereby simplifying the process and design.

[0181] FIGS. 7a to 7e are graphs illustrating changes in the characteristics of a semiconductor layer according to the thickness of an insulating layer according to an embodiment of the present invention. In FIGS. 7a to 7e, the X-axis represents the change in thickness of the second upper oxide layer (33, see FIG. 6a), and the Y-axis represents the threshold voltage (Vth), driving range, mobility, and on-current (I) of the semiconductor layer. onIt refers to a change in characteristics such as the characteristic. Specifically, FIG. 7a illustrates the change in threshold voltage (Vth) according to the thickness of the second upper oxide layer (33), and is illustrated for each of the three embodiments (R1, R2, R3). FIG. 7b illustrates the change in driving range of the first embodiment (R1) according to the thickness of the second upper oxide layer (33), and FIG. 7c illustrates the change in mobility of the second embodiment (R2) according to the thickness of the second upper oxide layer (33). FIG. 7d illustrates the change in on-current of the second embodiment (R2) according to the thickness of the second upper oxide layer (33), and FIG. 7e illustrates the change in on-current of the third embodiment (R3) according to the thickness of the second upper oxide layer (33). Hereinafter, the present invention will be described with reference to FIG. 7a to 7e.

[0182] Among the three embodiments (R1, R2, R3), the first embodiment (R1) corresponds to the case where the first semiconductor layer (A1) of the pixel transistor (TRp, see FIG. 6a) has a bottom gate and a source-sink structure. Among the three embodiments (R1, R2, R3), the second embodiment (R2) corresponds to the case where the second semiconductor layer (A2) of the driving transistor (TRd, see FIG. 6a) has a bottom gate and a gate-sink structure. Among the three embodiments (R1, R2, R3), the third embodiment (R3) corresponds to the case where the first semiconductor layer (A1) of the pixel transistor (TRp, see FIG. 6a) has a structure where the bottom gate is omitted.

[0183] Referring to FIG. 7a, it can be seen that as the thickness of the second upper oxide layer (33) adjacent to the semiconductor layer increases, the threshold voltage of the semiconductor layer tends to shift in the negative direction. Among the three embodiments (R1, R2, R3), the third embodiment (R3) shows the most rapid shift, while the second embodiment (R2) shows relatively less shift but not a large deviation. However, the graph for the first embodiment (R1) among the three embodiments (R1, R2, R3) shows that no shift in the negative direction occurred relatively.

[0184] Additionally, referring to FIG. 7b, it can be seen that as the thickness of the second upper oxide layer (33) in the first embodiment (R1) decreases, the driving range of the semiconductor layer (A1) increases. In particular, a driving range of 0.31 or more can be secured even in a thickness range of 600 Å or less, which has a positive value based on the first embodiment (R1) and has a small change in the threshold voltage (Vth).

[0185] That is, referring to FIGS. 7a and 7b, when a pixel transistor (TRp) is formed in a source-synchronized structure through a bottom gate as in the first embodiment (R1), the shift in the negative direction of the threshold voltage (Vth) due to changes in the thickness of the insulating layer may be reduced, thereby securing a driving range and enabling stable driving.

[0186] Referring again to FIG. 7a, it can be seen that for the second embodiment (R2) and the third embodiment (R3), the deviation of the shift in the threshold voltage (Vth) is larger around a thickness of 400 Å. It can be seen that when the thickness of the second upper oxide layer (33) is 400 Å, the degree of shift in the negative direction of the threshold voltage (Vth) of the first semiconductor layer (A1) may be relatively low, and in the 400 Å range, a shift of -1 or less is observed.

[0187] Referring to FIGS. 7c and 7d, as the thickness of the second upper oxide layer (33) increases, the mobility and on-current (I) in the second embodiment (R2) on It can be seen that the mobility or on-current (I) shows an increasing trend. At this time, the thickness of the second upper oxide layer (33) is around 500 Å, and the mobility or on-current (I on It appears that the deviation is large.

[0188] That is, referring to FIGS. 7a, 7c, and 7d, in the case of a driving transistor (TRd) comprising a second semiconductor layer (A2) disposed on a second upper oxide layer (33) as in the second embodiment (R2), if the thickness of the second upper oxide layer (33) is secured to be 200 Å or less, excessive shift in the negative direction of the threshold voltage (Vth) of the second semiconductor layer (A2) does not occur, thereby facilitating the control of the driving transistor (TRd) and improving reliability. At this time, the mobility or on-current (I) of the driving transistor (TRd) on The current characteristics are improved and the scan drive unit (SDV) for driving a high-resolution display panel can be stably designed by appropriately controlling the number of units so as not to increase excessively while having sufficient mobility. According to the present invention, by forming the drive unit transistor (TRd) as a high-mobility semiconductor layer, the area of ​​the scan drive unit (SDV) can be reduced, and an electronic device with a reduced bezel area can be provided while applying a high-resolution circuit design.

[0189] Additionally, referring to FIGS. 7a and 7e, it can be seen that in the third embodiment (R3), as in the second embodiment (R2), the on-current increases as the thickness of the second upper oxide layer (33) increases, and the on-current (I) in the second embodiment (R2) on It can be seen that the value is relatively lower than that of ), but the deviation is not large, and the pattern of increase is similar to that of Fig. 7d.

[0190] According to the present invention, by including a second nitride layer (32), hydrogen can be sufficiently supplied even if the semiconductor layer (A1) of the pixel transistor (TRp) has a relatively low mobility, thereby ensuring a driving range and improving reliability, an electronic device having a pixel driving unit (PC) can be provided.

[0191] FIGS. 8a to 8i are cross-sectional views illustrating a method for manufacturing a display panel according to an embodiment of the present invention. FIGS. 8a to 8i exemplarily illustrate a method for manufacturing an embodiment illustrated in FIG. 6a. Hereinafter, the present invention will be described with reference to FIGS. 8a to 8i. Meanwhile, the same reference numerals are assigned to configurations identical to those described in FIGS. 1a to 7, and redundant descriptions are omitted.

[0192] Referring to FIG. 8a, a first sublayer may be formed on a base substrate (BS, or substrate). The first sublayer may include a plurality of first sublayer patterns (BL1a, BL1b). The first sublayer patterns (BL1a, BL1b) may be formed by forming a conductive layer on the substrate (BS) through deposition or coating and then patterning the layer.

[0193] Referring to FIG. 8b thereafter, a first insulating layer (10) and a second lower layer may be formed sequentially. After forming the first lower patterns (BL1a, BL1b), an insulating material is deposited or coated on a substrate (BS) to form the first insulating layer (10). The insulating material may be an inorganic insulating material. After depositing or coating a conductive material on the first insulating layer (10), a plurality of second lower patterns (BL2a, BL2b, BL2c) may be formed by patterning the material.

[0194] Referring to FIG. 8c thereafter, a second insulating layer (20) may be formed. The second insulating layer (20) may be formed by sequentially stacking a first lower oxide layer (21), a first nitride layer (22), and a first upper oxide layer (23). Each of the first lower oxide layer (21), the first nitride layer (22), and the first upper oxide layer (23) may be formed on the front surface of the substrate (BS). The first lower oxide layer (21) and the first upper oxide layer (23) may be formed from a material including silicon oxide. The first lower oxide layer (21) and the first upper oxide layer (23) may be formed from the same or different material. The first nitride layer (22) may be formed from a material including silicon nitride or silicon oxynitride.

[0195] The second insulating layer (20) may be formed by sequentially depositing or coating the first lower oxide layer (21), the first nitride layer (22), and the first upper oxide layer (23). For example, each of the first lower oxide layer (21), the first nitride layer (22), and the first upper oxide layer (23) may be formed through a chemical vapor deposition process. Each of the first lower oxide layer (21), the first nitride layer (22), and the first upper oxide layer (23) may be sequentially deposited within the same chamber using different deposition sources, or may be formed independently in different chambers, and is not limited to any one embodiment.

[0196] Referring to FIG. 8d thereafter, a first semiconductor layer (A1) may be formed on the second insulating layer (20). The first semiconductor layer (A1) may be formed by depositing or coating a first semiconductor material on the second insulating layer (20) and then patterning it. The first semiconductor material may include an oxide semiconductor. For example, the first semiconductor material may include indium gallium zinc oxide (IGZO) or indium gallium oxide (IGO).

[0197] Referring to FIG. 8e, a third insulating layer (30) may be formed thereafter. The third insulating layer (30) is formed on the second insulating layer (20) and covers the first semiconductor layer (A1). The third insulating layer (30) may be formed by sequentially stacking a second lower oxide layer (31), a second nitride layer (32), and a second upper oxide layer (33).

[0198] Each of the second lower oxide layer (31), the second nitride layer (32), and the second upper oxide layer (33) can be formed on the front surface of the substrate (BS). Each of the second lower oxide layer (31), the second nitride layer (32), and the second upper oxide layer (33) can be formed by depositing or coating an insulating material. Each of the second lower oxide layer (31) and the second upper oxide layer (33) can be formed from a material including silicon oxide (SiOx). However, this is described as an example, and a low-hydrogen oxide layer, for example, about The oxide layer having a hydrogen concentration below is not limited to any one of the embodiments.

[0199] The second nitride layer (32) may be formed from a material including silicon oxide (SiOx) or silicon oxynitride (SiON). However, this is described as an example, and the second nitride layer (32) may include various materials as long as it has a higher hydrogen concentration than the second lower oxide layer (31) and the second upper oxide layer (33), and is not limited to any one embodiment.

[0200] The third insulating layer (30) may be formed by sequentially depositing or coating the second lower oxide layer (31), the second nitride layer (32), and the second upper oxide layer (33). For example, each of the second lower oxide layer (31), the second nitride layer (32), and the second upper oxide layer (33) may be formed through a chemical vapor deposition process. Each of the second lower oxide layer (31), the second nitride layer (32), and the second upper oxide layer (33) may be sequentially deposited within the same chamber using different deposition sources, or may be formed independently in different chambers, and is not limited to any one embodiment.

[0201] The second nitride layer (32) can supply hydrogen to the first semiconductor layer (A1). By supplying the hydrogen contained in the second nitride layer (32) to the first semiconductor layer (A1), the mobility of the first semiconductor layer (A1) can be improved. Accordingly, the driving range of the first semiconductor layer (A1) is widened and the constant current stress (CCS) is improved, thereby forming a first semiconductor layer (A1) with improved reliability.

[0202] The second nitride layer (32) may be formed with a thickness not greater than that of the first nitride layer (22). For example, when the first nitride layer (22) is formed with a thickness of about 2000 Å, the second nitride layer (32) may be formed with a thickness of about 100 Å or more and 2000 Å or less. According to the present invention, by designing the thickness of the second nitride layer (32) to be within an appropriate range, hydrogen supplied to the first semiconductor layer (A1) can be easily controlled, and the channel region of the first semiconductor layer (A1) by the first gate (G1) can be easily controlled.

[0203] The second upper oxide layer (33) can be formed with a thickness lower than that of the second nitride layer (32). For example, the second upper oxide layer (33) can be formed with a thickness of 200 Å or less.

[0204] Subsequently, referring to FIG. 8f, a second semiconductor layer (A2) may be formed on the third insulating layer (30). The second semiconductor layer (A2) may be formed by depositing or coating a second semiconductor material on the third insulating layer (30) and then patterning it. The second semiconductor layer (A2) may be formed in an area where a scan driving unit (SDV) is placed. The second semiconductor material may be an oxide semiconductor material that is different from the first semiconductor material and has a higher mobility than the first semiconductor material. For example, when the first semiconductor material is indium gallium zinc oxide (IGZO), the second semiconductor material may include indium tin gallium zinc oxide (ITGZO).

[0205] According to the present invention, by forming the second upper oxide layer (33) thinly, the phenomenon in which the threshold voltage of the second semiconductor layer (A2) shifts in a negative direction due to the second upper oxide layer (33) can be prevented. According to the present invention, the threshold voltage of the second semiconductor layer (A2) can be formed to a value greater than 0, and the on current (Ion) can be easily secured.

[0206] Referring to FIG. 8g thereafter, a plurality of insulating patterns (40a, 40b, 40c) and a plurality of gate patterns (G1, G2, CC) may be formed. An insulating material layer is formed by depositing or coating an insulating material so that the second semiconductor layer (A2) is covered on the third insulating layer (30). Then, a conductive material is deposited or coated to form a conductive layer. Then, the conductive layer is patterned to form a first gate (G1), a second gate (G2), and a capacitor electrode (CC), and insulating patterns (40a, 40b, 40c) may be formed by etching the insulating material layer using these as a mask.

[0207] Meanwhile, the region covered by the insulating patterns (40a, 40b, 40c) of the second semiconductor layer (A2) can be reduced to form a source region and a drain region, respectively. Accordingly, the source region and the drain region of the second semiconductor layer (A2) can be self-aligned with the second gate (G2).

[0208] Referring to FIG. 8h, a fifth insulating layer (50) may be formed, and a plurality of connecting electrodes (CNa, CNb, CNc, CNd) may be formed. The fifth insulating layer (50) may be formed by depositing or coating an insulating material. Subsequently, through holes may be formed in the fifth insulating layer (50) or in the third insulating layer (30) and the fifth insulating layer (50). The connecting electrodes (CNa, CNb, CNc, CNd) may be formed by patterning after forming a conductive layer. The connecting electrodes (CNa, CNb, CNc, CNd) may be filled into corresponding through holes and connected to the source region and drain region of the first semiconductor layer (A1) and the source region and drain region of the second semiconductor layer (A2).

[0209] Referring to FIG. 8i, a display element layer (DP-OLED) can be formed by forming a seventh insulating layer (70) and a light-emitting element (LD). The anode (AE) can be formed by depositing a conductive material to form a conductive layer and then patterning it. Subsequently, an insulating material layer is formed by depositing or coating an insulating material, and then an opening is formed to form the seventh insulating layer (70). Subsequently, a light-emitting layer (EM) and a cathode (CE) can be formed sequentially to form a light-emitting element (LD).

[0210]

[0211] FIG. 9 is a block diagram of an electronic device according to one embodiment. Referring to FIG. 9, an electronic device (EDE) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0212] The display module (11) can display an image. The image may include a still image as well as a dynamic image. The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The processor (12) may be configured to control the operation of the display module (11).

[0213] The memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal are transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen.

[0214] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (EDE).

[0215] FIG. 10 is a schematic diagram of an electronic device according to various embodiments.

[0216] Referring to FIG. 10, various electronic devices to which a display device according to embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a Center Information Display (CID) and a room mirror display placed on the instrument panel, center fascia, and dashboard of a car. The electronic device of FIG. 10 may include the configurations illustrated in FIG. 9. For example, a smartphone (10_1a) may include a display module (11), a processor (12), a memory (13), and a power module (14) illustrated in FIG. 9. The smartphone (10_1a) may further include a communication module and a battery device. Power provided by the battery device may be converted through a power module (14) and provided to a processor (12), memory (13), and display module (11). In one embodiment, the display device applied to the smartphone (10_1a) includes a display module (11) and may further include a power module (14). The processor (12) and memory (13) may be provided in the form of chips mounted on a motherboard, which is an external device, but are not limited thereto.

[0217] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0218] According to the present invention, an electronic device having a narrow bezel area can be provided. Accordingly, the present invention is industrially applicable.

Claims

1. Substrate; A circuit element layer disposed on the above substrate and comprising a scan driving unit and a pixel driving unit; and It includes a display element layer comprising a light-emitting element disposed on the circuit element layer and connected to the pixel driving unit, and The above circuit element layer is, A first transistor included in the pixel driving unit and comprising a first oxide semiconductor layer and a first gate; A second transistor including a second oxide semiconductor layer and a second gate, which are included in the scan driving unit and disposed on a layer different from the first oxide semiconductor layer; and It includes an insulating layer disposed between the first oxide semiconductor layer and the first gate, and The above insulating layer is, Lower oxide layer; An upper oxide layer disposed on the lower oxide layer; and An electronic device comprising a nitride layer disposed between the lower oxide layer and the upper oxide layer and having a higher hydrogen concentration than the upper oxide layer.

2. In Paragraph 1, The electronic device having a second oxide semiconductor layer with higher mobility than the first oxide semiconductor layer.

3. In Paragraph 2, The above second oxide semiconductor layer is an electronic device comprising indium tin gallium zinc oxide.

4. In Paragraph 3, The above first oxide semiconductor layer comprises indium gallium zinc oxide or indium gallium oxide in an electronic device.

5. In Paragraph 2, The above second oxide semiconductor layer is an electronic device in contact with the above upper oxide layer.

6. In Paragraph 5, An electronic device in which the thickness of the upper oxide layer is lower than the thickness of the nitride layer.

7. In Paragraph 6, An electronic device having an upper oxide layer with a thickness of 200 Å or less.

8. In Paragraph 1, The above circuit element layer further comprises a plurality of lower patterns disposed below the first oxide semiconductor layer, in an electronic device.

9. In Paragraph 8, Any one of the above lower patterns is an electronic device connected to the first oxide semiconductor layer.

10. In Paragraph 8, Any one of the above lower patterns is an electronic device constituting a capacitor included in the pixel driving unit.

11. In Paragraph 8, It further includes a buffer layer disposed between the above lower patterns and the first oxide semiconductor layer, and The above buffer layer is, Lower buffer oxide layer; An upper buffer oxide layer disposed between the lower buffer oxide layer and the first oxide semiconductor layer; and An electronic device comprising a buffer nitride layer disposed between the lower buffer oxide layer and the upper buffer oxide layer.

12. In Paragraph 11, An electronic device in which the thickness of the above nitride layer is less than or equal to the thickness of the above buffer nitride layer.

13. In Paragraph 1, The above nitride layer is an electronic device comprising silicon nitride or silicon oxynitride.

14. Display panel; A processor that outputs data to the above display panel; and It includes a power module that provides power to the above-mentioned display panel, and The above display panel is, Light-emitting element; A pixel driving unit connected to the above-mentioned light-emitting element and including a first transistor; Scan driving unit including a second transistor; A gate line connecting the pixel driving unit and the scan driving unit; A data line connected to the pixel driving unit and insulatingly intersecting with the gate line; and It includes a plurality of insulating layers, The above insulating layers are, A first insulating layer disposed below the first semiconductor layer of the first transistor; and It includes a second insulating layer disposed between the first semiconductor layer and the first gate of the first transistor, and Each of the above first insulating layer and the above second insulating layer is, Lower oxide layer; An upper oxide layer disposed on the lower oxide layer; and An electronic device comprising a nitride layer disposed between the lower oxide layer and the upper oxide layer.

15. In Paragraph 14, The second semiconductor layer of the second transistor is disposed on the second insulating layer, and An electronic device comprising a material having a higher mobility than the first semiconductor layer in the second semiconductor layer.

16. In Paragraph 15, The second semiconductor layer comprises indium tin gallium zinc oxide, and The above first semiconductor layer comprises an indium gallium zinc oxide or indium gallium oxide in an electronic device.

17. In Paragraph 14, It further includes a plurality of lower patterns disposed below the first insulating layer, and The above first semiconductor layer is provided in multiple numbers, and Any one of the above lower patterns is an electronic device connected to the first semiconductor layer.

18. In Paragraph 17, The upper oxide layer of the second insulating layer is in contact with the second semiconductor layer. An electronic device in which the thickness of the upper oxide layer of the second insulating layer is about 200 Å or less.

19. In Paragraph 14, The insulating layer further includes a gate insulating layer disposed between the second semiconductor layer and the second gate of the second transistor, and The above gate insulating layer is an electronic device disposed between the above second insulating layer and the above first gate.

20. A step of forming a plurality of lower conductive patterns on a substrate; A step of sequentially stacking a first lower oxide layer, a first nitride layer, and a first upper oxide layer on the lower conductive patterns to form a first insulating layer; A step of forming a first semiconductor layer on the first insulating layer; A step of forming a second insulating layer by sequentially stacking a second lower oxide layer, a second nitride layer, and a second upper oxide layer on the first insulating layer; A step of forming a second semiconductor layer on the second insulating layer; A step of forming a first gate overlapping the first semiconductor layer and a second gate overlapping the second semiconductor layer; A step of forming a third insulating layer covering the first gate and the second gate; and A method for manufacturing an electronic device comprising the step of forming a plurality of connecting electrodes on the third insulating layer.

21. In Paragraph 20, The step of forming the second insulating layer is, A step of forming the second lower oxide layer by depositing an oxide; A step of forming a second nitride layer by depositing a nitride on the second lower oxide layer; and A method for manufacturing an electronic device comprising the step of depositing an oxide on the second nitride layer to form the second upper oxide layer.

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