Semiconductor memory device for HBM and manufacturing method therefor

Abstract

The present invention is a semiconductor memory device for high bandpass memory (HBM), the device comprising a base and a silicon semiconductor memory element formed on the base. The base includes a first base section made of silicon and a second base section located above the first base section and made of 3C-SiC, or the base is composed solely of 3C-SiC. This configuration makes it possible to provide a semiconductor memory device for HBM, in which cracking is successfully suppressed and heat dissipation characteristics are improved.

Description

Semiconductor memory device for HBM and method for manufacturing the same

[0001] This invention relates to a semiconductor memory device for High Bandpass Memory (HBM) and a method for manufacturing the same, and more particularly to a semiconductor memory device for HBM installed inside a GPU used in a server for generating AI, and a method for manufacturing the same.

[0002] In the 2000s, the demand for AI servers exploded, driven by advancements such as machine learning on large amounts of data on servers to dramatically improve image recognition accuracy. Furthermore, in recent years, generative AI, which generates data based on machine learning-generated data, has become mainstream. While it was previously possible to output search results based on machine learning results, generative AI, which is attracting attention in the future, outputs new results. An example of this is the recent case at SoftBank (registered trademark) where an overwhelming number of patents were filed in a short period of time, demonstrating how it can significantly transform the existing social structure (Non-Patent Literature 1).

[0003] Furthermore, since the content of the data used for learning naturally differs between machine learning and generative AI, the importance of AI servers, which replace conventional general-purpose servers, is expected to increase even more in the future (the age of artificial intelligence).

[0004] The GPU used in AI servers has a structure in which the processor's main core and the HBM are connected by a silicon interposer. For thermal management, heat sinks are installed on top of the processor and HBM. For this reason, the height of the HBM must be the same as that of the processor (Non-Patent Literature 2).

[0005] HBMs have a stacked structure of DRAM (Dynamic Random Access Memory) chips (DRAM dies). To improve performance, the number of stacks needs to be increased, but due to height constraints, the height of individual DRAM chips must be reduced (thinner). As mentioned in Non-Patent Literature 2 above, as the DRAM chips become thinner, the substrate strength at the DRAM chip decreases, leading to problems such as cracking defects due to crack formation and bonding defects due to warping.

[0006] Furthermore, the issue of heat generation associated with high-speed operation has been pointed out (Non-Patent Literature 2). Stacking deteriorates heat dissipation characteristics. This deterioration in heat dissipation characteristics also requires further consideration and countermeasures as the number of stacked layers increases.

[0007] Nomura Research Institute Future Creation Center Research Report Vol. 10 "The Future Landscape Transformed by Generative AI: What You Should Know About the Suddenly Appearing 'Generative AI'" December 2023 ADMETAPlus 2024, Tutorial "Metallization for Memory Devices - Challenging High Bandwidth Memory" Micron Memory Japan, K. K. Yokoi Naoki

[0008] The present invention was made to solve the above problems and aims to provide a semiconductor memory device for HBMs that can suppress cracking and has improved heat dissipation characteristics.

[0009] To achieve the above objective, the present invention provides a semiconductor memory device for HBMs, comprising a substrate portion and a semiconductor memory element portion made of silicon on the substrate portion, wherein the substrate portion comprises a first substrate portion made of silicon and a second substrate portion made of 3C-SiC on the first substrate portion, or is made of 3C-SiC only.

[0010] In the HBM semiconductor memory device of the present invention, the substrate portion (which comprises a first substrate portion made of silicon and a second substrate portion made of 3C-SiC, or which consists only of 3C-SiC) includes at least a portion made of 3C-SiC as described above. In this way, by utilizing (1) the prevention of cracking due to 3C-SiC, which has a higher Young's modulus than silicon, and (2) the heat dissipation effect due to the high thermal conductivity of 3C-SiC compared to silicon, it is possible to achieve both crack suppression and improved heat dissipation characteristics in an HBM semiconductor memory device. As a result, the HBM semiconductor memory device can be made even thinner without causing problems such as cracking, and it becomes possible to improve the performance of the HBM (increase in the number of layers of HBM semiconductor memory devices).

[0011] In this case, the second substrate portion made of 3C-SiC, or the substrate portion made solely of 3C-SiC, may have a thickness of 100 nm or more.

[0012] If the 3C-SiC portion has the above thickness, cracking can be suppressed more reliably and effectively, and heat dissipation characteristics can be improved.

[0013] The present invention also provides a method for manufacturing a semiconductor memory device for HBMs, comprising forming a silicon layer on a silicon substrate by epitaxial growth, forming a semiconductor memory element on the silicon layer, and subjecting it to a thin-film treatment, wherein in the formation of the silicon layer, a 3C-SiC layer is first formed on the silicon substrate by epitaxial growth, and then the silicon layer is formed on the 3C-SiC layer, and in the thin-film treatment, part or all of the silicon substrate is removed.

[0014] With the manufacturing method for HBM semiconductor memory devices of the present invention, by forming a 3C-SiC layer as described above, it is possible to manufacture an HBM semiconductor memory device that can achieve both crack suppression and improved heat dissipation characteristics. Consequently, it is possible to thin the HBM semiconductor memory device without causing problems such as cracking, increase the number of layers in the HBM, and improve the performance of the HBM.

[0015] In this case, when forming the 3C-SiC layer, the thickness of the formed film can be 100 nm or more.

[0016] By setting the thickness of the 3C-SiC layer to the above-mentioned thickness, cracking can be suppressed more reliably and effectively, and heat dissipation characteristics can be improved.

[0017] Furthermore, when forming the silicon layer, the thickness of the formed film can be adjusted according to the thickness of the semiconductor memory device for the HBM being manufactured.

[0018] In HBM fabrication, when attempting to increase the number of stacked semiconductor memory devices for the HBM while considering the thickness limitations of the HBM, it is necessary to reduce the thickness of each individual HBM semiconductor memory device. Therefore, it is best to appropriately adjust the thickness of the silicon layer based on the required thickness of the HBM semiconductor memory device.

[0019] The present invention provides a semiconductor memory device for HBMs and a method for manufacturing the same, which utilizes 3C-SiC, a material with a high Young's modulus and high thermal conductivity compared to silicon, resulting in improved heat dissipation. This allows for thinner films than conventional HBMs, increasing the number of layers in the HBM and thereby improving the performance of the HBM.

[0020] This is a schematic diagram illustrating an example of a semiconductor memory device for HBMs according to the present invention. This is a graph showing the results of a bending test (relationship between displacement and applied stress) for a silicon substrate (without 3C-SiC film) and a silicon substrate (with 3C-SiC film). This is a schematic diagram illustrating another example of the semiconductor memory device for HBMs according to the present invention. This is a process flow diagram illustrating an example of a manufacturing method for the semiconductor memory device for HBMs according to the present invention.

[0021] The present invention will be described in detail below with reference to the figures as an example of an embodiment, but the present invention is not limited thereto. As mentioned above, there is a demand for thinning of individual DRAM chips (semiconductor memory devices for HBMs) and an increase in the number of stacked layers in HBMs, but cracking due to thinning and deterioration of heat dissipation characteristics due to stacking are challenges.

[0022] Therefore, the inventors conducted diligent research and discovered that if a semiconductor memory device for HBMs has a substrate and a semiconductor memory element made of silicon on the substrate, and the substrate comprises a first substrate made of silicon and a second substrate made of 3C-SiC on the first substrate, or is made of 3C-SiC alone, then it is possible to suppress cracking and improve heat dissipation characteristics by utilizing the heat dissipation effect due to the high Young's modulus and high thermal conductivity of 3C-SiC, and thus completed the present invention.

[0023] Furthermore, the present invention was completed by finding that an HBM semiconductor memory device can be obtained that exhibits the above-mentioned excellent effects if, in the method of manufacturing an HBM semiconductor memory device, a silicon layer is formed on a silicon substrate by epitaxial growth, a semiconductor memory element is formed on the silicon layer, and a thin-film treatment is performed, in which, in the silicon layer formation, a 3C-SiC layer is first formed on the silicon substrate by epitaxial growth, the silicon layer is formed on the 3C-SiC layer, and in the thin-film treatment, part or all of the silicon substrate is removed, thereby obtaining an HBM semiconductor memory device that exhibits the above-mentioned excellent effects.

[0024] Figure 1 shows an example of a semiconductor memory device for HBMs according to the present invention. As shown in Figure 1, the semiconductor memory device for HBMs (hereinafter also simply referred to as memory device) 1 of the present invention has a substrate 2 and a semiconductor memory element 3. The substrate 2 comprises a first substrate 2A made of silicon and a second substrate 2B made of 3C-SiC located on the first substrate 2A. The semiconductor memory element 3 is also made of silicon. More specifically, a desired semiconductor memory element is formed on a silicon layer. The semiconductor memory element can be a capacitor, a transistor, or any other element that performs an appropriate role as a DRAM, and is not particularly limited.

[0025] Here, we will explain the significance of the second substrate part 2B, which is made of 3C-SiC. The Young's modulus of 3C-SiC is 450 GPa (Proceedings of the 2016 Spring Meeting of the Japan Society for Precision Engineering, 723 (2016)). On the other hand, the Young's modulus of silicon (for example, a silicon single crystal with a (100) orientation) is 130 GPa (The Science of Silicon, p. 989 (1996)). Thus, in terms of Young's modulus, 3C-SiC has a higher rigidity and durability than silicon.

[0026] Therefore, the following test was conducted to assess the effectiveness of the rigidity of 3C-SiC. First, two identical silicon substrates (300 mm in diameter) were prepared. One silicon substrate was left as is, while 3C-SiC was epitaxially grown on the other silicon substrate to a thickness of 100 nm. For each substrate, a bending test was performed at a temperature of 22°C, with the left and right sides of the substrate supported, and the center of the substrate was pressed down from above with an indenter. The relationship between the displacement and the applied stress was then measured. The test results are shown in Figure 2. The solid line represents the results for the substrate with the 3C-SiC film, and the dashed line represents the results for the substrate without the 3C-SiC film. The substrate with the 3C-SiC film showed a smaller displacement for the same amount of stress, confirming that its rigidity was increased. Therefore, 3C-SiC is effective in preventing cracking.

[0027] Furthermore, regarding thermal conductivity, 3C-SiC has a thermal conductivity of 500 Wm². －１ K －１ (Z. Cheng et al., Nature communications, 13, 7201 (2022)) However, the thermal conductivity of silicon with a (100) orientation is 67 Wm². －１ K －１ (Silicon Science, pp. 992, 1005 (1996)). Thus, 3C-SiC has a much higher thermal conductivity than silicon. Therefore, when assembled in the manufacturing of HBM, heat can be effectively transferred to the heat sink through the bump metal via the 3C-SiC, making it an effective thermal management tool.

[0028] As described above, 3C-SiC has a higher Young's modulus and higher thermal conductivity compared to silicon. Therefore, the memory device 1 of the present invention, which has a part made of 3C-SiC such as the second substrate part 2B, can suppress the occurrence of cracks and has improved heat dissipation characteristics, making it extremely superior. It can adequately address the challenges associated with further thinning and an increase in the number of layers that have been required in recent years.

[0029] The thickness of the substrate portion 2 and the semiconductor memory element portion 3 is not particularly limited and can be determined as appropriate. For example, the thickness of each portion can be determined according to the overall thickness of the memory device 1 in accordance with the requirement for thin film reduction. The thinner the material, the thinner the overall thickness of the memory device 1 becomes, which is preferable because it allows for an increase in the number of layers in the manufacturing of the HBM.

[0030] Furthermore, the thickness of the second substrate portion 2B made of 3C-SiC is not particularly limited, but a thickness of 100 nm or more is preferable because it is more effective in suppressing cracking and improving heat dissipation characteristics. If necessary, it can be, for example, 125 nm or more, or even 150 nm or more. As an upper limit, a value of about 200 nm is generally considered sufficient, but it is not limited to this, and can be determined while comparing the above effects with the overall thickness of the memory device 1, etc.

[0031] Furthermore, Figure 3 shows an example of another embodiment of the semiconductor memory device for HBM of the present invention. As shown in Figure 3, in this embodiment of the memory device 10, the substrate portion 20 is made only of 3C-SiC. To put it another way, in comparison to Figure 1, in Figure 3 there is no equivalent to the substrate portion 2A (silicon) in Figure 1, and it is composed only of the equivalent to the second substrate portion 2B (3C-SiC) in Figure 1. Therefore, the memory device 10 in the embodiment of Figure 3 can be made even thinner overall than the memory device 1 in the embodiment of Figure 1. The effectiveness of 3C-SiC in the substrate portion 20 is as described above, and the same crack resistance and heat dissipation characteristics as in the embodiment of Figure 1 can be obtained.

[0032] Next, the method for manufacturing a semiconductor memory device for HBMs according to the present invention will be described. Figure 4 shows an example of the process flow of the manufacturing method according to the present invention. As shown in Figure 4, the process consists of (Step 1) preparation of a silicon substrate, (Step 2) hydrogen baking, (Step 3) deposition of a 3C-SiC layer, (Step 4) deposition of a silicon layer, (Step 5) formation of a semiconductor memory element, and (Step 6) thin-film processing. Each step will be described in detail below.

[0033] (Step 1) Preparation of the silicon substrate First, a single-crystal silicon substrate is prepared. A silicon ingot can be manufactured by methods such as the Czochralski method or the floating zone method, and then cut into wafers and subjected to various processes such as grinding, etching, and polishing to prepare this silicon substrate. The diameter size and surface orientation are not particularly limited.

[0034] (Step 2) Hydrogen baking Next, prepare a reduced-pressure CVD apparatus (an apparatus similar to the one used conventionally can be prepared), place a single-crystal silicon substrate inside the apparatus, and perform a hydrogen bake (H) on the native oxide film on the surface. ２ It is removed by annealing. By removing the native oxide film on the surface of the single-crystal silicon substrate in advance so that no residue remains, SiC nucleation on the single-crystal silicon substrate can be performed more reliably in the next step. ２ Annealing is preferably carried out under temperature conditions of, for example, 1000°C to 1200°C, H ２ There are no particular restrictions on the annealing pressure or time, as long as it is sufficient to remove the native oxide film.

[0035] (Step 3) Deposition of the 3C-SiC layer Next, the 3C-SiC layer is formed by epitaxial growth (SiC nucleation and formation of the 3C-SiC layer). This formed 3C-SiC layer corresponds to the second substrate part 2B in Figure 1 (substrate part 20 in Figure 3). SiC nucleation is performed on a single-crystal silicon substrate in a reduced-pressure CVD apparatus by setting the temperature to, for example, 300°C to 1100°C and introducing monomethylsilane or trimethylsilane as a raw material gas for SiC. SiC nucleation can be performed on the surface of a single-crystal silicon substrate if the pressure is 100 Torr or less (13332 Pa or less) and the temperature is 300°C or higher.

[0036] Also, in order to efficiently perform epitaxial growth of SiC, it is preferable to set the temperature to 800°C or higher. Also, by setting the temperature at the time of SiC nucleation to 800°C or higher, SiC nucleation and 3C-SiC single crystal layer formation can be performed under the same conditions. The growth pressure during 3C-SiC single crystal layer formation is preferably, for example, 100 Torr or less (13332 Pa or less). This is to effectively prevent the polycrystallization of 3C-SiC. On the other hand, under the condition that the pressure is 10 Torr or less (1333 Pa or less), more preferably 1 Torr or less (133 Pa or less), voids are formed directly under the 3C-SiC single crystal layer, and the effect of relaxing the stress of the entire epitaxial layer can be obtained.

[0037] At this time, since the film thickness to be formed depends on the pressure and temperature, the film formation time is appropriately set based on the pressure and temperature conditions set to achieve the target film thickness. Although the film formation thickness of the 3C-SiC single crystal layer is not particularly limited, it can preferably be 100 nm or more. This is because, as described above, it is more effective in suppressing cracking and improving heat dissipation characteristics of the finally manufactured memory device. Furthermore, for example, it can be 125 nm or more, 150 nm or more, and a thickness of about 200 nm is also sufficient.

[0038] (Step 4) Film formation of the silicon layer On the 3C-SiC single crystal layer grown as described above, silicon is grown using a CVD apparatus to form a single crystal silicon layer. At this time, there is no restriction whether it is a reduced pressure CVD apparatus or an atmospheric pressure CVD apparatus, but particularly when growing thicker than 3C-SiC, the atmospheric pressure CVD apparatus is more suitable because the growth rate is higher. At this time, by introducing, for example, monosilane or trichlorosilane into the CVD apparatus and setting the temperature to about 1000°C or higher and 1200°C or lower, the above single crystal silicon layer can be formed.

[0039] At this time, by considering in advance the final overall thickness of the memory device, it is advisable to appropriately adjust the film formation thickness of the silicon layer so that it falls within the range of the overall thickness after the thinning process in the subsequent steps.

[0040] (Step 5) Formation of semiconductor memory elements Then, the desired semiconductor memory elements are formed on the deposited single-crystal silicon layer. Using techniques such as photolithography, a DRAM consisting of capacitors that serve as memory elements and transistors that serve as switches can be fabricated. The fabrication of this DRAM itself can be carried out in basically the same way as in the past. The silicon layer on which the semiconductor memory elements have been formed in this way corresponds to the semiconductor memory element section 3 in Figure 1 (semiconductor memory element section 30 in Figure 3).

[0041] (Step 6) Thinning treatment Then, part or all of the silicon substrate is removed. The removal method itself is not particularly limited and can be carried out as appropriate using grinding, polishing, etching, etc., and may be the same as conventional methods. If only a part is removed, the remaining part of the silicon substrate corresponds to the first substrate part 2A in Figure 1. The part that combines this remaining part of the silicon substrate (corresponding to the first substrate part 2A) and the aforementioned 3C-SiC layer (corresponding to the second substrate part 2B) corresponds to the substrate part 2 in Figure 1. Furthermore, the entire remaining part after this thinning treatment corresponds to the memory device 1 in Figure 1. On the other hand, if the entire silicon substrate is removed, as mentioned above, the 3C-SiC layer corresponds to the substrate part 20 consisting only of 3C-SiC in Figure 3. The entire remaining part after the thinning treatment corresponds to the memory device 10 in Figure 3. Removing the entire silicon substrate allows for even thinner film, making it possible to thin the HBM by one layer or increase the number of stacked DRAM chips, which is more preferable.

[0042] As described above, the manufacturing method of the present invention makes it possible to manufacture a memory device that has both crack suppression and improved heat dissipation characteristics by utilizing the properties of 3C-SiC (high Young's modulus and heat dissipation effect due to high thermal conductivity). For this reason, even if the memory device is made thinner than conventional devices, it is less likely to crack and less likely to warp. In addition, even if the number of stacked memory devices is increased in the manufacturing of HBMs, deterioration of heat dissipation characteristics can be prevented. Therefore, it is possible to increase the number of stacked devices to improve the performance of the HBM.

[0043] In the production of HBM, the semiconductor memory device for HBM of the present invention is diced into chips (DRAM chips), and a plurality of DRAM chips (memory dies) thus prepared are stacked vertically and connected to each other by through electrodes to manufacture HBM. Then, this HBM is connected to a silicon interposer, and a processor is connected to the silicon interposer, which can be used in an AI server or the like.

[0044] Hereinafter, the present invention will be described more specifically with reference to examples of the present invention, but the present invention is not limited thereto. (Example) The semiconductor memory device 1 for HBM of the present invention was manufactured as follows according to the flow of FIG. 4. A normal resistance single crystal silicon substrate with a diameter of 300 mm, a thickness of 750 μm, a plane orientation of (100), and boron doping was prepared (Step 1). The single crystal silicon substrate prepared on the susceptor in the reactor of a commercially available general low-pressure CVD apparatus was placed, and annealing was performed at 1080° C. for 1 minute (Step 2). Subsequently, trimethylsilane gas was introduced with a growth temperature of 900° C. and a growth pressure of 5 Torr (667 Pa) to perform a nucleation process of SiC and an epitaxial growth of a 3C-SiC single crystal layer. Growth was performed for 20 minutes to form a 3C-SiC single crystal layer with a film thickness of 100 nm (Step 3). ２ Thereafter, annealing was performed at 1130° C. for 1 minute in a commercially available general atmospheric pressure epitaxial growth furnace. Subsequently, trichlorosilane gas was introduced with a growth temperature of 1080° C., and a silicon epitaxial layer was grown by 2 μm (Step 4). ２ A semiconductor memory element (DRAM) was formed on this silicon epitaxial layer using photolithography (Step 5). Thereafter, for HBM, the single crystal silicon substrate was polished to a thickness of about 78 μm to thin the film so that the overall thickness became 80 μm (Step 6), and the semiconductor memory device 1 for HBM of the present invention was obtained.

[0045] After that, a plurality of DRAM chips were obtained by dicing. Then, bumps were formed on the back surface, and four DRAM chips were bonded together, but no cracks occurred.

[0046] After that, a plurality of DRAM chips were obtained by dicing. Then, bumps were formed on the back surface, and four DRAM chips were bonded together, but no cracks occurred.

[0047] (Comparative Example) A conventional resistance single crystal silicon substrate with a diameter of 300 mm, a thickness of 750 μm, a crystal orientation (100), and boron doping was prepared. In the same atmospheric pressure epitaxial growth furnace as in the example, it was subjected to H2O2 at 1130°C for 1 minute. ２ Annealing was performed. Subsequently, a 2 μm silicon epitaxial layer was grown by introducing trichlorosilane gas at a growth temperature of 1080°C. A semiconductor memory element (DRAM) was formed on this silicon epitaxial layer using photolithography. Then, for use in HBMs, a single-crystal silicon substrate was polished to a thickness of approximately 78 μm to thin it, resulting in an overall thickness of 80 μm, thus obtaining a semiconductor memory device for HBMs. In this way, the semiconductor memory device for HBMs was manufactured in the same manner as in the example, except that a 3C-SiC single-crystal layer was not formed.

[0048] Afterward, multiple DRAM chips were obtained by dicing. Then, bumps were formed on the back surface and four DRAM chips were bonded together. In this case, cracks occurred in all chips, starting from the bumps.

[0049] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that has substantially the same technical idea as described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention.

Claims

1. A semiconductor memory device for HBMs, comprising a substrate and a semiconductor memory element portion made of silicon on the substrate, wherein the substrate comprises a first substrate portion made of silicon and a second substrate portion made of 3C-SiC on the first substrate portion, or is made of 3C-SiC only.

2. The semiconductor memory device for HBM according to claim 1, characterized in that the second substrate portion made of 3C-SiC, or the substrate portion made solely of 3C-SiC, has a thickness of 100 nm or more.

3. A method for manufacturing a semiconductor memory device for HBMs, comprising forming a silicon layer on a silicon substrate by epitaxial growth, forming a semiconductor memory element on the silicon layer, and performing a thin-film treatment, wherein, in the formation of the silicon layer, a 3C-SiC layer is first formed on the silicon substrate by epitaxial growth, and then the silicon layer is formed on the 3C-SiC layer, and in the thin-film treatment, part or all of the silicon substrate is removed.

4. The method for manufacturing a semiconductor memory device for HBM according to claim 3, characterized in that when the 3C-SiC layer is formed, the thickness of the formed film is 100 nm or more.

5. The method for manufacturing a semiconductor memory device for an HBM according to claim 3 or 4, characterized in that when forming the silicon layer, the thickness of the formed film is adjusted according to the thickness of the semiconductor memory device for an HBM to be manufactured.

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