Laminate, semiconductor element, and method for producing laminate

Abstract

Provided is a laminate having excellent heat dissipation properties, electrical conductivity properties and the like. This laminate comprises a semiconductor layer, a silicon carbide layer, and an intermediate layer disposed between the semiconductor layer and the silicon carbide layer, wherein the intermediate layer is composed of 3C-SiC crystals.

Description

Laminate, semiconductor element, and method for manufacturing a laminate

[0001] The present invention relates to a laminate, a semiconductor element, and a method for manufacturing a laminate.

[0002] Active development is underway for semiconductor devices using various compound semiconductor materials. For compound semiconductor materials such as Group III element nitrides, laminates have been proposed that combine substrates with different properties to utilize the characteristics of both, as described in Patent Document 1, for example. For example, since silicon carbide substrates can have excellent thermal conductivity, a laminate obtained by combining a silicon carbide substrate with a compound semiconductor material can have excellent heat dissipation properties.

[0003] Patent No. 4458116

[0004] However, further quality improvements may be desired in the above-mentioned laminate. For example, further improvements in heat dissipation, conductivity, etc., may be desired in the above-mentioned laminate.

[0005] In view of the above, the primary objective of the present invention is to provide a laminate with excellent quality in terms of heat dissipation, conductivity, and other properties.

[0006] 1. A laminate according to an embodiment of the present invention comprises a semiconductor layer, a silicon carbide layer, and an intermediate layer disposed between the semiconductor layer and the silicon carbide layer, wherein the intermediate layer is composed of 3C-SiC crystal. 2. In the intermediate layer of the laminate described in 1 above, the single crystal region composed of the 3C-SiC crystal may occupy 50% or more. 3. In the laminate described in 1 or 2 above, the thickness of the intermediate layer may be 5 nm or less. 4. In the laminate described in any of 1 to 3 above, the thermal resistance of the intermediate layer is 1 × 10⁻⁶ －８ I understand ２10. In the laminate described in any of 1 to 4 above, the silicon carbide layer may be composed of 4H-SiC crystals or 6H-SiC crystals. 11. In the laminate described in 5 above, the off-angle of the silicon carbide layer may be 1° or less. 22. In the laminate described in any of 1 to 6 above, the thickness of the silicon carbide layer may be 100 μm or more and 1000 μm or less. 33. In the laminate described in any of 1 to 7 above, the semiconductor layer may be a compound semiconductor layer. 23. In the laminate described in any of 1 to 8 above, the compound semiconductor layer may be composed of a III-V compound semiconductor. 34. In the laminate described in any of 1 to 9 above, the thickness of the semiconductor layer may be 0.1 μm or more and 20 μm or less. 35. In the laminate described in any of 1 to 9 above, the dislocation density of the semiconductor layer is 1 × 10 ７ cm －２ The following may also be applied: 12. A semiconductor element according to another embodiment of the present invention comprises a laminate described in any of 1 to 11 above and a functional layer provided on the laminate. 13. A method for manufacturing a laminate according to yet another embodiment of the present invention is a method for manufacturing a laminate described in any of 1 to 11 above, comprising, in this order, activating the surface of the semiconductor layer precursor and the surface of the silicon carbide layer precursor, joining the semiconductor layer precursor and the silicon carbide layer precursor to obtain a bond in which an amorphous layer containing silicon carbide is formed, and heat-treating the bond, wherein the heat treatment is performed in a hydrogen-containing atmosphere.

[0007] According to embodiments of the present invention, it is possible to provide a laminate with excellent quality in terms of heat dissipation, conductivity, and other properties.

[0008] This is a schematic cross-sectional view showing the general structure of a laminate according to one embodiment of the present invention. This is a diagram showing the manufacturing process of a laminate according to one embodiment of the present invention. This is a diagram following Figure 2A. This is a diagram following Figure 2B. This is a diagram following Figure 2C. This is a diagram following Figure 2D. This is a diagram following Figure 2E. This is a schematic cross-sectional view showing the general structure of a semiconductor element according to one embodiment of the present invention. This is a TEM image (magnification: 4 million times) of the laminate of Example 1. This is a TEM image (magnification: 10 million times) of the laminate of Example 1. This is an ADF-STEM image of the area enclosed by a rectangle in Figure 4B. This is a TEM image (magnification: 4 million times) of the laminate of Comparative Example 4. This is a TEM image (magnification: 10 million times) of the laminate of Example 4.

[0009] The embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited to these embodiments. In order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] A. Figure 1 of the laminate is a schematic cross-sectional view showing the general configuration of a laminate according to one embodiment of the present invention. The laminate 100 has a semiconductor layer 10, a silicon carbide layer 20, and an intermediate layer 30 disposed between the semiconductor layer 10 and the silicon carbide layer 20. In one embodiment, the semiconductor layer 10 is a compound semiconductor layer. Hereinafter, it may be referred to as the compound semiconductor layer 10. The compound semiconductor layer 10 has a first main surface 11 and a second main surface 12 that face each other, and the intermediate layer 30 and the silicon carbide layer 20 are disposed on the second main surface 12 side of the compound semiconductor layer 10. For example, a functional layer (device layer) is formed on the compound semiconductor layer 10, and the laminate 100 can be used as a semiconductor element.

[0011] Although not shown in the figures, the laminate 100 may have additional layers of any kind. The type, function, number, combination, and arrangement of such layers can be appropriately determined according to the purpose.

[0012] The laminate 100 can be manufactured in any suitable shape. In one embodiment, it can be manufactured in the form of a so-called wafer. The size of the laminate 100 can be appropriately set according to the purpose. For example, the diameter of the wafer is 50 mm to 200 mm. The laminate 100 may have an orientation flat or a notch formed in a part thereof to indicate the crystal orientation (e.g., the crystal orientation of the wafer).

[0013] [Semiconductor layer (Compound semiconductor layer)] The thickness of the semiconductor layer (compound semiconductor layer) 10 can be set to any appropriate value, for example, according to the use of the laminate 100. The thickness of the semiconductor layer (compound semiconductor layer) 10 is, for example, 0.1 μm or more, preferably 0.5 μm or more, and may be 1 μm or more. On the other hand, the thickness of the semiconductor layer (compound semiconductor layer) 10 is, for example, 20 μm or less, preferably 10 μm or less, and more preferably 5 μm or less.

[0014] Typically, the compound semiconductor layer 10 is composed of a single crystal. The compound semiconductor layer 10 is composed of any appropriate compound semiconductor according to the use of the laminate 100. Examples of the compound semiconductor that can form the compound semiconductor layer 10 include III-V group compound semiconductors. Specific examples of III-V group compound semiconductors include III group element nitrides, indium phosphide, gallium arsenide, etc. As the III group element constituting the III group element nitride, for example, aluminum (Al), gallium (Ga), indium (In) are used. These can be used alone or in combination of two or more. Specific examples of III group element nitrides include aluminum nitride (Al ｘ N), gallium nitride (Ga ｙ N), indium nitride (In ｚ N), aluminum gallium nitride (Al ｘ Ga ｙ N), gallium indium nitride (Ga ｙ In ｚ N), aluminum indium nitride (Al ｘ In ｚ N), aluminum gallium indium nitride (Al ｘ Ga ｙ In ｚN) is an example. Other compound semiconductors that can constitute the compound semiconductor layer 10 include, for example, gallium oxide (e.g., Ga ２ O ３ ), aluminum gallium oxide ((Al ｘ Ga ｙ ) ２ O ３ Examples include oxides of Group III elements such as ). In each chemical formula in parentheses, x + y + z = 1 is typical.

[0015] The crystal constituting the compound semiconductor layer 10 may have a hexagonal wurtzite-type crystal structure. In such a crystal (typically a group III element nitride crystal), typically the <0001> direction is the c-axis direction, the <1-100> direction is the m-axis direction, and the <11-20> direction is the a-axis direction. Furthermore, a crystal plane perpendicular to the c-axis is a c-plane, a crystal plane perpendicular to the m-axis is an m-plane, and a crystal plane perpendicular to the a-axis is an a-plane. In one embodiment, the thickness direction of the compound semiconductor layer 10 composed of a group III element nitride crystal is parallel to or substantially parallel to the c-axis. In this case, the first main surface 11 may be a group III element polarity plane on the (0001) plane side, and the second main surface 12 may be a nitrogen polarity plane on the (000-1) plane side. Specifically, the first main surface 11 may be parallel to the (0001) plane, or it may be inclined with respect to the (0001) plane. The inclination angle of the first main surface 11 with respect to the (0001) plane is, for example, 10° or less, may be 5° or less, may be 2° or less, or may be 1° or less. The second main surface 12 may be parallel to the (000-1) plane, or it may be inclined with respect to the (000-1) plane. The inclination angle of the second main surface 12 with respect to the (000-1) plane is, for example, 10° or less, may be 5° or less, may be 2° or less, or may be 1° or less. Conversely, the second main surface 12 may be the Group III element polar plane on the (0001) plane side, and the first main surface 11 may be the nitrogen polar plane on the (000-1) plane side.

[0016] The compound semiconductor constituting the compound semiconductor layer 10 may contain a dopant. As the dopant, for example, transition elements such as zinc (Zn), iron (Fe), manganese (Mn), vanadium (V), chromium (Cr), cobalt (Co), nickel (Ni), etc. are used. Also, carbon (C) can be used as a dopant. These can be used alone or in combination of two or more.

[0017] The semiconductor layer (compound semiconductor layer) 10 may have any appropriate resistivity, for example, according to the use of the laminate 100. Specifically, the semiconductor layer (compound semiconductor layer) 10 may be conductive or semi-insulating. In this specification, "being semi-insulating" means that the resistivity is, for example, 1×10 ５ Ω·cm or more, preferably 1×10 ６ Ω·cm or more and 1×10 １４ Ω·cm or less, and more preferably 1×10 ７ Ω·cm or more and 1×10 １４ Ω·cm or less. In this specification, "being conductive" means that the resistivity is, for example, 100 mΩ·cm or less, preferably 0.1 mΩ·cm or more and 10 mΩ·cm or less, and more preferably 0.1 mΩ·cm or more and 1 mΩ·cm or less.

[0018] Resistivity can be measured by any suitable method. Examples of resistivity measurement methods include the capacitance method, the two-terminal method, the double-ring electrode method, and the eddy current method. In one embodiment, the capacitance method is preferably used. According to the capacitance method, resistivity can be determined without damaging the object to be measured. Specifically, the object to be measured is inserted into a capacitor consisting of a probe and a stage, a pulse voltage is applied, the time change in the charge amount of the object to be measured is measured, and resistivity is calculated from the measured value. In this case, since the probe does not come into contact with the object to be measured, resistivity can be determined without forming an ohmic contact electrode. The spatial resolution of the probe may be about 1 mm to 10 mm. For more information on how to determine resistivity, see, for example, the non-patent document "R. Stibal et al., “Contactless evaluation of semi-insulating GaAs wafer resistivity using the time-dependent charge measurement” Semiconductor Science and Technology 6 p995 (1991)".

[0019] The dislocation density of the semiconductor layer (compound semiconductor layer) 10 is 1 × 10⁻⁶ ７ cm －２ The following may be true, preferably 5 × 10 ６ cm －２ The following, more preferably 1 × 10 ６ cm －２ The following applies. By having such a compound semiconductor layer 10 (in particular, a compound semiconductor layer 10 composed of a group III element nitride), for example, a functional layer can be formed well. The lower limit of the dislocation density of the semiconductor layer (compound semiconductor layer) 10 is, for example, 1 × 10⁻⁶. １ cm －２ This is possible. The dislocation density of the compound semiconductor layer 10, which is composed of group III element nitrides, is, for example, 1 × 10⁻⁶. ４ cm －２ That's fine too.

[0020] [Silicon Carbide Layer] The silicon carbide layer 20, which is composed of silicon carbide, tends to have a higher thermal conductivity than the compound semiconductor layer 10. Therefore, by combining the silicon carbide layer 20 with the compound semiconductor layer 10, it is possible to achieve high heat dissipation that cannot be achieved with the compound semiconductor layer 10 alone.

[0021] The thickness of the silicon carbide layer 20 can be set to any appropriate value. The silicon carbide layer 20 can function as a support substrate for the compound semiconductor layer 10. The thickness of the silicon carbide layer 20 is, for example, 100 μm or more and 1000 μm or less, preferably 200 μm or more.

[0022] The silicon carbide layer 20 is preferably composed of a crystalline material, and more preferably of a single crystal. The silicon carbide layer 20 may be composed of 4H-SiC crystals or 6H-SiC crystals.

[0023] When the silicon carbide layer 20 is composed of a single crystal, for example, the thickness direction of the silicon carbide layer 20 may be parallel to or substantially parallel to the c-axis. The off-angle of the silicon carbide layer 20 is, for example, 5° or less, preferably 3° or less, more preferably 1° or less, and even more preferably 0.5° or less. Note that the off-angle of the silicon carbide layer 20 refers to the inclination angle of the silicon carbide layer 20 in the thickness direction with respect to the reference crystal axis (e.g., the c-axis). Furthermore, the main surface of the silicon carbide layer 20 located on the intermediate layer 30 side may be the Si polar surface side or the C polar surface side. In the laminate 100, the crystal orientation of the compound semiconductor layer 10 and the crystal orientation of the silicon carbide layer 20 can be any appropriate arrangement.

[0024] The silicon carbide layer 20 may have any appropriate resistivity depending on the application of the laminate 100. Specifically, the silicon carbide layer 20 may be conductive or semi-insulating. In one embodiment, the compound semiconductor layer 10 is conductive, and the silicon carbide layer 20 is also conductive. In another embodiment, the compound semiconductor layer 10 is semi-insulating, and the silicon carbide layer 20 is also semi-insulating. For example, the silicon carbide layer 20 may contain impurities. The silicon carbide layer 20 may contain, for example, donor impurities such as nitrogen (N) and phosphorus (P), and donor compensating impurities such as vanadium (V). These may be used alone or in combination of two or more.

[0025] [Intermediate Layer] The intermediate layer 30 is composed of 3C-SiC crystals. Preferably, the single-crystal region composed of 3C-SiC crystals occupies 50% or more of the intermediate layer 30, more preferably 60% or more, and may be 70% or more, or 80% or more. The thickness of the intermediate layer 30 is preferably 5 nm or less, and may be 2 nm or less. On the other hand, the thickness of the intermediate layer 30 is, for example, 0.5 nm or more. The presence or absence of the intermediate layer 30 and the thickness of the intermediate layer 30 can be confirmed, for example, by observation using a transmission electron microscope (TEM).

[0026] In the laminate 100, an intermediate layer 30 composed of 3C-SiC crystals is formed, which allows the high thermal conductivity of the silicon carbide layer 20 to be effectively utilized, and the laminate 100 can have extremely excellent heat dissipation properties. The thermal resistance of the intermediate layer 30 is, for example, 1 × 10⁻⁶. －８ I understand ２ It may be less than or equal to kW, preferably 8 × 10 －９ I understand ２ It is less than kW and 6 x 10 －９ I understand ２ It may be less than or equal to K / W. The thermal resistance of the intermediate layer 30 may correspond to the interfacial thermal resistance (TBR) between the compound semiconductor layer 10 and the silicon carbide layer 20.

[0027] Because an intermediate layer 30 composed of 3C-SiC crystal is formed in the laminate 100, the laminate 100 can have excellent conductivity.

[0028] The intermediate layer 30 may contain elements other than carbon and silicon. For example, argon may be present in the intermediate layer 30. Specifically, when the compound semiconductor layer 10 is composed of gallium nitride, the amount of Ar present in the intermediate layer 30, when the total amount of C, N, O, Si, Ga, and Ar in the intermediate layer 30 is 100 atom%, is, for example, 0.1 atom% or more, and may be 2.0 atom% or more. On the other hand, the amount of Ar present in the intermediate layer 30, when the total amount of C, N, O, Si, Ga, and Ar in the intermediate layer 30 is 100 atom%, is, for example, 15.0 atom% or less. The amounts of various elements in the intermediate layer 30 can be determined, for example, by compositional analysis using energy-dispersive X-ray spectroscopy (EDX).

[0029] Furthermore, for example, elements constituting the compound semiconductor layer 10 may be present in the intermediate layer 30. Specifically, when the compound semiconductor layer 10 is composed of gallium nitride, the amount of N present when the total amount of C, N, O, Si, Ga, and Ar in the intermediate layer 30 is 100 atom% is, for example, 5 atom% or more and 25 atom% or less, preferably 15 atom% or less. Also, when the compound semiconductor layer 10 is composed of gallium nitride, the amount of Ga present when the total amount of C, N, O, Si, Ga, and Ar in the intermediate layer 30 is 100 atom% is, for example, 10 atom% or more and 50 atom% or less, preferably 30 atom% or less.

[0030] B. Manufacturing method The laminate can be obtained, for example, by heat-treating a bonded body obtained by joining a plate-shaped compound semiconductor layer precursor and a silicon carbide layer precursor.

[0031] Figures 2A to 2F show the manufacturing process of a laminate according to one embodiment of the present invention. As shown in Figure 2A, a semiconductor layer precursor 1 and a silicon carbide layer precursor 2 are prepared and a laminate 100 is obtained by directly joining them. In one embodiment, the semiconductor layer precursor 1 is a compound semiconductor layer precursor. Hereinafter, it may be referred to as the compound semiconductor layer precursor 1. When directly joining, it is preferable that the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the silicon carbide layer precursor 2 are each activated by an appropriate activation treatment. Specifically, it is preferable that the bonding surface (main surface) of the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the bonding surface (main surface) of the silicon carbide layer precursor 2 are each activated by an appropriate activation treatment.

[0032] When the silicon carbide layer precursor 2 is composed of a single crystal, for example, the thickness direction of the silicon carbide layer precursor 2 may be parallel to or substantially parallel to the c-axis. The bonding surface to which the activation treatment is applied may be on the Si polar surface side or the C polar surface side. The off-angle of the silicon carbide layer precursor 2 is, for example, 5° or less, preferably 3° or less, more preferably 1° or less, and even more preferably 0.5° or less. By using a silicon carbide layer precursor 2 having such an off-angle, an intermediate layer composed of the 3C-SiC crystal can be formed well. Note that the off-angle of the silicon carbide layer precursor 2 refers to the inclination angle of the main surface of the silicon carbide layer precursor 2 with respect to the reference crystal plane (e.g., the c-plane).

[0033] A doping layer may be formed at the thickness-direction end of the silicon carbide layer precursor 2 on the bonding surface side. The formation of the doping layer allows for adjustment of the resistivity of the formed intermediate layer 30, for example. The doping layer can be formed, for example, by ion implantation. Specifically, the doping layer may be an ion-implanted layer. Examples of ions to be implanted include nitrogen ions, phosphorus ions, and vanadium ions. The doping element concentration of the ion-implanted layer is, for example, 1 × 10⁻⁶. １７ cm －２ The above is preferable to 1 × 10 １９ cm －２That concludes the explanation. The concentration of doping elements can be confirmed, for example, by secondary ion mass spectrometry (SIMS).

[0034] The above activation treatment is typically performed by irradiating with a neutralizing beam. Preferably, a neutralizing beam is generated using an apparatus such as the one described in Japanese Patent Application Publication No. 2014-086400, and the activation treatment is performed by irradiating with this beam. Specifically, a saddle-field type fast atomic beam (FAB) source is used as the beam source, an inert gas such as argon or xenon is introduced into the chamber, and a high voltage is applied to the electrodes from a DC power supply. As a result, electrons move due to the saddle-field type electric field generated between the electrode (positive electrode) and the housing (negative electrode), and a beam of atoms and ions from the inert gas is generated. Of the beam that reaches the grid, the ion beam is neutralized at the grid, so a beam of neutral atoms is emitted from the fast atomic beam source. The voltage during the activation treatment by beam irradiation is preferably 0.5 kV to 2.0 kV. The current during the activation treatment by beam irradiation is preferably 50 mA to 200 mA.

[0035] Since the semiconductor layer precursor 1 and the silicon carbide layer precursor 2 may have different resistances to activation treatment, it is preferable to perform the activation treatment so that an amorphous layer containing silicon carbide can be formed near the bonding interface after bonding. In one embodiment, the activation treatment can be performed in multiple stages (for example, three stages). Figure 2B shows the state in which the first activation treatment has been applied to the bonding surface 1a of the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the bonding surface 2a of the silicon carbide layer precursor 2, respectively. Typically, the activation of the bonding surface 1a of the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the bonding surface 2a of the silicon carbide layer precursor 2 can be performed simultaneously. The time of the first activation treatment (for example, the irradiation time of the beam) is, for example, 20 seconds to 200 seconds.

[0036] Figure 2C shows the second activation treatment. In the second activation treatment, the junction surface 2a of the silicon carbide layer precursor 2 is further irradiated with a beam. In the second activation treatment, the semiconductor layer precursor (compound semiconductor layer precursor) 1 is substantially not irradiated with a beam. For example, the second activation treatment is performed by irradiating the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the silicon carbide layer precursor 2 with a beam in the first activation treatment, then stopping the beam irradiation to the semiconductor layer precursor (compound semiconductor layer precursor) 1, and continuing the beam irradiation to the silicon carbide layer precursor 2 for a predetermined time. As a result of the second activation treatment, an amorphous region (not shown) may be formed on the junction surface 2a side of the silicon carbide precursor 2. Also, as a result of the second activation treatment, a deposited layer 4 containing the components constituting the silicon carbide layer precursor 2 may be formed on the surface of the semiconductor layer precursor (compound semiconductor layer precursor) 1. The time of the second activation treatment (for example, the beam irradiation time) is, for example, 10 to 120 seconds.

[0037] Figure 2D shows the third activation treatment. In the third activation treatment, the junction surface 1a of the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the junction surface 2a of the silicon carbide layer precursor 2 are further irradiated with a beam. For example, the third activation treatment is performed by, in the second activation treatment, after irradiating the silicon carbide layer precursor 2 with a beam, restarting the beam irradiation to the semiconductor layer precursor (compound semiconductor layer precursor) 1 and continuing the beam irradiation to the silicon carbide layer precursor 2 for a predetermined time. The third activation treatment removes the deposited layer 4 formed on the surface of the semiconductor layer precursor (compound semiconductor layer precursor) 1, and the junction surface 1a of the semiconductor layer precursor (compound semiconductor layer precursor) 1 can be activated. The duration of the third activation treatment (for example, the beam irradiation time) is, for example, 20 seconds to 200 seconds.

[0038] After activation treatment, the bonding surface 1a of the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the bonding surface 2a of the silicon carbide layer precursor 2 can be brought into contact and directly bonded by applying pressure. By direct bonding, a bonded body 101 is obtained as shown in Figure 2E. It is preferable to perform the contact and pressurization of the bonding surfaces in a vacuum atmosphere. The temperature at this time is typically room temperature. Specifically, it is preferably 20°C to 40°C, and more preferably 25°C to 30°C. The pressure applied is preferably 100N to 20000N. An amorphous layer 3 containing silicon carbide may be formed near the bonding interface of the bonded body 101.

[0039] During bonding, it is preferable that the bonding surface 1a of the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the bonding surface 2a of the silicon carbide layer precursor 2 are flat surfaces. Specifically, the arithmetic mean roughness Ra of the bonding surface 1a of the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the bonding surface 2a of the silicon carbide layer precursor 2 is preferably 1 nm or less, more preferably 0.7 nm or less, even more preferably 0.5 nm or less, and particularly preferably 0.3 nm or less. Methods for planarizing the surfaces of each precursor include, for example, mirror polishing by chemical mechanical polishing (CMP) or lapping.

[0040] When joining, it is preferable that the joining surfaces be cleaned, for example, to remove abrasive residue. Examples of cleaning methods include wet cleaning, dry cleaning, and scrubbing. Among these, scrubbing is preferred because it is simple and efficient. A specific example of scrubbing is a method in which a cleaning agent (for example, Lion Corporation's Sunwash series) is used, followed by cleaning with a solvent (for example, a mixed solution of acetone and isopropyl alcohol (IPA)) using a scrubbing machine.

[0041] Next, the bonded body 101 of the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the silicon carbide layer precursor 2 is subjected to heat treatment. In the illustrated example, as shown in Figure 2F, the bonded body 101, which has been thinned by grinding, polishing, etc., is subjected to heat treatment. By heat treating the bonded body 101, the amorphous layer 3 is crystallized and an intermediate layer 30 can be formed. In this way, a laminated body 100 is obtained.

[0042] The heat treatment for forming the intermediate layer 30 is preferably carried out under a hydrogen atmosphere. The heat treatment atmosphere may contain gases other than hydrogen gas. The heat treatment atmosphere preferably contains a noble gas such as argon and an inert gas such as nitrogen. Furthermore, the heat treatment atmosphere may contain other gases depending on the constituent components of the semiconductor layer precursor (compound semiconductor layer precursor) 1. For example, if the compound semiconductor layer precursor 1 is composed of nitride, the heat treatment atmosphere may contain ammonia gas. The heat treatment temperature is, for example, 700°C to 1100°C, preferably 800°C or higher, and may also be 900°C or higher. The heat treatment time is preferably 5 to 60 minutes.

[0043] Although not shown in the figures, a protective film may be provided on the surface of the semiconductor layer precursor (compound semiconductor layer precursor) 1 during the heat treatment of the bonded body 101. By providing a protective film, for example, deterioration of the semiconductor layer precursor (compound semiconductor layer precursor) 1 due to heat treatment can be prevented. The protective film may be composed of, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, etc. The thickness of the protective film is preferably 0.01 μm to 1 μm. The protective film can be removed by any appropriate method after the heat treatment of the bonded body 101.

[0044] The bonded body 101 (laminated body 100) can be subjected to any appropriate processing. Unlike the illustrated example, the thinning of the semiconductor layer precursor (compound semiconductor layer precursor) 1 may be performed after the heat treatment of the bonded body 101. However, if the thermal expansion coefficient of the semiconductor layer precursor (compound semiconductor layer precursor) 1 is greater than that of the silicon carbide layer precursor 2, it is preferable to thin the semiconductor layer precursor (compound semiconductor layer precursor) 1 before the heat treatment of the bonded body 101, as shown in the illustration. This is because it is possible to suppress the occurrence of defects such as cracks and fractures in the resulting semiconductor layer (compound semiconductor layer) 10. In the illustrated example, the semiconductor layer precursor (compound semiconductor layer precursor) 1 is thinned, but for example, if the semiconductor layer precursor (compound semiconductor layer precursor) 1 and the silicon carbide precursor 2 are bonded together, which are previously integrated on another substrate (not shown), the thinning of the semiconductor layer precursor (compound semiconductor layer precursor) 1 can be omitted.

[0045] C. Applications The above laminate can typically be applied to any suitable semiconductor element. Specifically, any suitable functional layer can be formed on the laminate. Figure 3 is a schematic cross-sectional view showing the general configuration of a semiconductor element (substrate for element) according to one embodiment of the present invention. The semiconductor element (substrate for element) 200 has a laminate 100 and a functional layer 40 formed on the first main surface 11 of the semiconductor layer (compound semiconductor layer) 10 of the laminate 100. The functional layer 40 is typically formed by epitaxial growth of a crystal by any suitable growth method. The functional layer 40 can function as, for example, a light-emitting layer, a rectifier element layer, a switching element layer, or a power semiconductor layer. For example, since the laminate 100 can have excellent heat dissipation, the semiconductor element 200 can have excellent device operation characteristics and reliability.

[0046] D. Modifications In the embodiments described above, the case where the semiconductor layer 10 is a compound semiconductor layer is described in detail. However, in the present invention, the semiconductor layer is not limited to a compound semiconductor layer. The semiconductor layer 10 may be an elemental semiconductor layer composed of a single element. The elemental semiconductor layer is described in the same way as the compound semiconductor layer described above, except for the material that constitutes the semiconductor layer. Therefore, the description of the elemental semiconductor layer will be omitted as appropriate. Examples of elemental semiconductor layers include a silicon (Si) layer and a germanium (Ge) layer. In one embodiment, the semiconductor layer 10 is a silicon (Si) layer. The silicon layer is typically composed of single-crystal silicon. Single-crystal silicon may have a cubic diamond-type crystal structure.

[0047] The present invention will be specifically described below with reference to examples, but the present invention is not limited to these examples. The arithmetic mean roughness Ra and dislocation density are values ​​measured by the following measurement methods. <Arithmetic Mean Roughness Ra> The arithmetic mean roughness Ra of the substrate was measured in a 10 μm × 10 μm field of view using an atomic force microscope (Hitachi High-Technologies Corporation, "AFM5400L"). <Dislocation Density 1> The dislocation density of the group III element nitride substrate was determined by obtaining a CL image by cathodoluminescence (CL) observation and calculating the density of dark spots, which are defect locations. A scanning electron microscope with a MiniCL system from Gatan (Hitachi High-Technologies Corporation, "S-3400N") was used for observation. Under the conditions of an acceleration voltage of 15 kV, a probe current of 90 μA, and a working distance (WD) of 15 mm, a photomultiplier tube (PMT) was used as the detector to acquire a monochrome CL image (magnification 1200x). Observation was performed with the detector inserted between the sample and the objective lens. Five fields of view of 78 μm × 105 μm were observed, the number of dark spots in each image was counted, and the average value was calculated. <Dislocation Density 2> For substrates other than Group III element nitride substrates, the dislocation density was determined by the etch pit density. Specifically, it was determined in accordance with SEMI M36-0699.

[0048] [Example 1] (Substrate) A semi-insulating single-crystal silicon carbide substrate (vanadium-doped 6H-SiC substrate) with a diameter of 4 inches, a thickness of 400 μm, and an off-angle of 0.05°, and a substrate with a diameter of 4 inches, a thickness of 400 μm, and a dislocation density of 2 × 10 ６ cm －２ Next, semi-insulating gallium nitride substrates were prepared. The surfaces (bonding surfaces) of these substrates were subjected to chemical mechanical polishing, and the arithmetic mean roughness Ra was 0.2 nm.

[0049] (Bonding) Next, the silicon carbide substrate and the gallium nitride substrate were directly bonded. Specifically, after cleaning the bonding surface (Si polar side) of the silicon carbide substrate and the bonding surface (N polar side) of the gallium nitride substrate, both substrates were placed in a vacuum chamber and 10 －６ The system was evacuated to a Pa level. Then, the bonding surfaces of both substrates were irradiated with a high-speed atomic beam for 50 seconds under the conditions of an acceleration voltage of 1 kV and an Ar flow rate of 27 sccm. After that, only the bonding surface of the silicon carbide substrate was irradiated with the high-speed atomic beam under the same conditions for 20 seconds, and then the bonding surfaces of both substrates were irradiated with the high-speed atomic beam under the same conditions for another 50 seconds. After irradiation, the beam-irradiated surfaces of both substrates were superimposed and pressed with 10,000 N for 2 minutes to bond the two substrates and obtain a bonded body. Subsequently, the gallium nitride substrate of the obtained bonded body was ground and polished to obtain a gallium nitride layer with a thickness of 3 μm.

[0050] (Heat Treatment) Next, the bonded body was subjected to heat treatment. The heat treatment was carried out at 1000°C for 20 minutes under a mixed gas atmosphere of ammonia, hydrogen, and nitrogen (gas flow rate ratio of ammonia:hydrogen:nitrogen = 1:3:2). In this way, a laminate was obtained.

[0051] [Example 2] As substrates to be bonded, a conductive single-crystal silicon carbide substrate (nitrogen-doped 4H-SiC substrate) with a diameter of 4 inches, a thickness of 350 μm, and an off-angle of 4°, and a substrate with a diameter of 4 inches, a thickness of 400 μm, and a dislocation density of 1 × 10⁻¹⁶ ６ cm －２ Then, a laminate was obtained in the same manner as in Example 1, except that a conductive gallium nitride substrate was used.

[0052] [Example 3] As substrates to be bonded, a semi-insulating single-crystal silicon carbide substrate (undoped 4H-SiC substrate) with a diameter of 4 inches, a thickness of 350 μm, and an off-angle of 0.05° was used, and a substrate with a diameter of 4 inches, a thickness of 600 μm, and a dislocation density of 1 × 10⁻¹⁶ ３ cm －２ The following describes the use of a semi-insulating indium phosphide substrate, the heat treatment performed at 800°C under a mixed gas atmosphere of hydrogen and nitrogen (gas flow rate ratio of hydrogen:nitrogen = 2:1), and the application of a 100 nm thick silicon dioxide (SiO₂) protective film to the surface of the indium phosphide substrate of the bonded structure before the heat treatment (after polishing the indium phosphide substrate). ２ A laminate was obtained in the same manner as in Example 1, except that the film was formed by sputtering and the protective film was removed using a hydrofluoric acid etching solution after heat treatment.

[0053] [Example 4] As substrates to be bonded, a semi-insulating single-crystal silicon carbide substrate (undoped 4H-SiC substrate) with a diameter of 4 inches, a thickness of 350 μm, and an off-angle of 0.05° was used, and a substrate with a diameter of 4 inches, a thickness of 500 μm, and a dislocation density of 1 × 10 １ cm －２ A laminate was obtained in the same manner as in Example 1, except that a silicon substrate of less than 1 μm was used, and the silicon substrate of the bonded body was ground and polished to form a silicon layer with a thickness of 1 μm.

[0054] [Comparative Example 1] A laminate was obtained in the same manner as in Example 1, except that the high-speed atomic beam irradiation was not performed in three stages during bonding, and the bonding surface of the silicon carbide substrate and the gallium nitride substrate was irradiated with a high-speed atomic beam for 120 seconds under the conditions of an acceleration voltage of 1 kV and an Ar flow rate of 27 sccm, and no heat treatment was performed after polishing the gallium nitride substrate of the bonded body.

[0055] [Comparative Example 2] (Substrate) A semi-insulating single-crystal silicon carbide substrate (undoped 4H-SiC substrate) with a diameter of 4 inches, a thickness of 400 μm, and an off-angle of 0.05°, and a substrate with a diameter of 4 inches, a thickness of 400 μm, and a dislocation density of 2 × 10 ６ cm －２Next, semi-insulating gallium nitride substrates were prepared. The surfaces (bonding surfaces) of these substrates were subjected to chemical mechanical polishing, and the arithmetic mean roughness Ra was 0.2 nm.

[0056] (Bonding) Next, the silicon carbide substrate and the gallium nitride substrate were directly bonded. Specifically, after cleaning the bonding surface (Si polar side) of the silicon carbide substrate and the bonding surface (N polar side) of the gallium nitride substrate, both substrates were placed in a vacuum chamber and 10 －６ The system was evacuated to a Pa level. Then, the bonding surfaces of both substrates were irradiated with a high-speed atomic beam for 50 seconds under the conditions of an acceleration voltage of 1 kV and an Ar flow rate of 27 sccm. After that, only the bonding surface of the silicon carbide substrate was irradiated with the high-speed atomic beam under the same conditions for 20 seconds, and then the bonding surfaces of both substrates were irradiated with the high-speed atomic beam under the same conditions for another 50 seconds. After irradiation, the beam-irradiated surfaces of both substrates were superimposed and pressed with 10,000 N for 2 minutes to bond the two substrates and obtain a bonded body. Subsequently, the gallium nitride substrate of the obtained bonded body was ground and polished to a thickness of 3 μm from its original thickness to obtain a laminate.

[0057] [Comparative Example 3] The gallium nitride substrate of the bonded body obtained in Comparative Example 2 was ground and polished to a thickness of 3 μm from its original thickness, and then the bonded body was heat-treated. Specifically, the treatment was carried out at 1000°C for 20 minutes under a nitrogen atmosphere. In this way, a laminated body was obtained.

[0058] [Comparative Example 4] As substrates to be bonded, a conductive single-crystal silicon carbide substrate (nitrogen-doped 4H-SiC substrate) with a diameter of 4 inches, a thickness of 350 μm, and an off-angle of 4°, and a substrate with a diameter of 4 inches, a thickness of 400 μm, and a dislocation density of 1 × 10⁻¹⁶ ６ cm －２ Then, a laminate was obtained in the same manner as in Comparative Example 2, except that a conductive gallium nitride substrate was used.

[0059] [Comparative Example 5] As substrates to be bonded, a semi-insulating single-crystal silicon carbide substrate (undoped 4H-SiC substrate) with a diameter of 4 inches, a thickness of 350 μm, and an off-angle of 0.05° was used, and a substrate with a diameter of 4 inches, a thickness of 600 μm, and a dislocation density of 1 × 10⁻¹⁶ ３ cm －２In the following, a laminate was obtained in the same manner as in Comparative Example 2, except that a semi-insulating indium phosphide substrate was used.

[0060] <Evaluation> The laminates obtained in the examples and comparative examples were evaluated as follows: 1. Cross-sectional TEM observation A scanning transmission electron microscope (JEOL Ltd., "JEM-ARM200F") was used to confirm the presence or absence of an intermediate layer in the laminate and to evaluate the crystallinity of the intermediate layer. Samples for STEM observation were obtained by thinning using the FIB method. When the intermediate layer was composed of single crystals, the proportion of the single-crystal region in the intermediate layer (single-crystal area ratio) was determined. Specifically, in the cross-sectional TEM observation area of ​​the intermediate layer (a region of thickness × width of 45 nm in the cross-sectional TEM image observed at 4 million times magnification), the region in which the 3C-SiC lattice arrangement was confirmed was defined as the single-crystal region, and the other regions (regions in which the lattice arrangement was not confirmed) were defined as the non-single-crystal region, and the proportion occupied by the single-crystal region was determined. When observing the lattice image, the observation resolution was increased as needed by high-angle annular dark-field observation (ADF-STEM) with spherical aberration correction. The observation results are summarized in Table 3. Furthermore, as representative examples, TEM images of the laminate of Example 1 are shown in Figures 4A and 4B, a TEM image of the laminate of Comparative Example 4 is shown in Figure 5, and a TEM image of the laminate of Example 4 is shown in Figure 6. In addition, the ADF-STEM image of the area enclosed by a rectangle in Figure 4B is shown in Figure 4C. In the intermediate layer of the laminates of each example, the arrangement of silicon atoms belonging to 3C-SiC crystals (cubic system) was confirmed, as shown by the white dotted line in Figure 4C. In the intermediate layer of the laminate of Example 4, one period (3ML) of 3C-SiC crystals (cubic system) was formed. The thickness of this intermediate layer was 0.75 nm. Furthermore, elemental analysis was performed using STEM-EDX observation with respect to the composition at the analysis sites shown in Figure 4A (Example 1) and Figure 5 (Comparative Example 4), using an energy-dispersive X-ray analyzer (JEOL Ltd., JED-2300T) with an acceleration voltage of 200 kV, a beam diameter of approximately 0.2 nmΦ, an energy resolution of approximately 140 eV, and an acquisition time of 30 seconds. The results for Example 1 are summarized in Table 1, and the results for Comparative Example 4 are summarized in Table 2.

[0061]

[0062]

[0063] 2. Interfacial Thermal Resistance A 10 mm x 10 mm test specimen was cut from the obtained laminate, and the interfacial thermal resistance between the gallium nitride layer, indium phosphide layer, or silicon layer and the silicon carbide substrate was measured by time-domain thermoreflectance (TDTR) method. Specifically, a 100 nm thick molybdenum film was deposited as a reflective film on the surface of the test specimen (the surface on the gallium nitride layer, indium phosphide layer, or silicon layer side), and then a temperature history curve (phase signal) was obtained by surface heating / surface temperature measurement using picosecond pulsed light with a pulsed laser. The obtained temperature history curve was fitted using time response analysis to calculate the interfacial thermal resistance. The surface heating conditions using the heating laser were a pulse width of 0.5 ps, a wavelength of 1550 nm, and a beam diameter of 45 μm, and the temperature measurement conditions using the measurement laser were a pulse width of 0.5 ps, a wavelength of 775 nm, and a beam diameter of 25 μm. The measurement results are summarized in Table 3.

[0064]

[0065] 3. Conductivity in the longitudinal direction (thickness direction) was evaluated for the laminate of Conductive Example 2 and the laminate of Comparative Example 4. A 1 cm × 1 cm test piece was cut from the obtained laminate using a dicing device. After cleaning the silicon carbide substrate surface of the test piece with a 10% hydrofluoric acid solution, metal films of Ti and Ni were sequentially deposited on the silicon carbide substrate surface via a metal mask using vacuum deposition with thicknesses of 50 nm and 200 nm, respectively, to form a 200 μm diameter electrode with a laminated structure. Subsequently, the electrode was heated in an infrared lamp annealing device under nitrogen atmosphere at 1000°C for 2 minutes to alloy the electrode. Next, metal films of Ti, Al, Ni, and Au were sequentially deposited on the gallium nitride layer surface of the test piece via a metal mask using vacuum deposition with thicknesses of 15 nm, 220 nm, 40 nm, and 75 nm, respectively, to form a 200 μm diameter electrode with a laminated structure. Subsequently, the electrodes were heated in an infrared lamp annealing apparatus under a nitrogen atmosphere at 700°C for 30 seconds to alloy the electrodes. The current-voltage characteristics were evaluated by applying a voltage from -2V to +2V to the formed electrodes using an I-V prober and measuring the current value. The electrical resistance (differential resistance) of the laminate was calculated from the obtained I-V curve slope, and it was 3.4Ω for Example 2 and 10.4Ω for Comparative Example 4. Therefore, it can be said that a laminate with excellent conductivity can be obtained by forming an intermediate layer composed of 3C-SiC crystals between the conductive compound semiconductor layer and the silicon carbide substrate (silicon carbide layer).

[0066] The laminate according to the embodiment of the present invention can be applied, for example, to a semiconductor device.

[0067] 1 Semiconductor layer precursor (compound semiconductor layer precursor), 2 Silicon carbide layer precursor, 3 Amorphous layer, 4 Deposition layer, 10 Semiconductor layer (compound semiconductor layer), 11 First main surface, 12 Second main surface, 20 Silicon carbide layer, 30 Intermediate layer, 40 Functional layer, 100 Laminate, 101 Bonded structure, 200 Semiconductor device (device substrate).

Claims

1. A laminate comprising a semiconductor layer, a silicon carbide layer, and an intermediate layer disposed between the semiconductor layer and the silicon carbide layer, wherein the intermediate layer is composed of 3C-SiC crystal.

2. The laminate according to claim 1, wherein in the intermediate layer, the single crystal region composed of the 3C-SiC crystal accounts for 50% or more.

3. The laminate according to claim 1, wherein the thickness of the intermediate layer is 5 nm or less.

4. The thermal resistance of the intermediate layer is 1 × 10 －８ I understand ２ The laminate according to claim 1, wherein the wattage is less than or equal to kW.

5. The laminate according to claim 1, wherein the silicon carbide layer is composed of 4H-SiC crystals or 6H-SiC crystals.

6. The laminate according to claim 5, wherein the off-angle of the silicon carbide layer is 1° or less.

7. The laminate according to claim 1, wherein the thickness of the silicon carbide layer is 100 μm or more and 1000 μm or less.

8. The laminate according to claim 1, wherein the semiconductor layer is a compound semiconductor layer.

9. The laminate according to claim 8, wherein the compound semiconductor layer is composed of a group III-V compound semiconductor.

10. The laminate according to claim 1, wherein the thickness of the semiconductor layer is 0.1 μm or more and 20 μm or less.

11. The dislocation density of the semiconductor layer is 1 × 10⁻⁶ ７ cm －２ The laminate according to claim 1, which is as follows:

12. A semiconductor element comprising a laminate according to any one of claims 1 to 11 and a functional layer provided on the laminate.

13. A method for manufacturing a laminate according to any one of claims 1 to 11, comprising, in this order: activating the surface of a semiconductor layer precursor and the surface of a silicon carbide layer precursor; joining the semiconductor layer precursor and the silicon carbide layer precursor to obtain a bonded body in which an amorphous layer containing silicon carbide is formed; and heat-treating the bonded body, wherein the heat-treating is performed in a hydrogen-containing atmosphere.

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