Laminate, semiconductor element, and method for producing laminate

Abstract

Provided is a laminate having excellent thermal conductivity and electrical conductivity. This laminate has a semiconductor layer, a support substrate, and an intermediate layer disposed between the semiconductor layer and the support substrate. Each of the semiconductor layer and the support substrate exhibits electrical conductivity, the thermal conductivity of the support substrate is higher than the thermal conductivity of the semiconductor layer, and the intermediate layer exhibits crystallinity.

Description

Laminate, semiconductor device, and method for manufacturing laminate

[0001] The present invention relates to a laminate, a semiconductor device, and a method for manufacturing a laminate.

[0002] Development of semiconductor devices using various compound semiconductor materials has been actively carried out. For compound semiconductor materials such as group III element nitrides, for example, as described in Patent Document 1, a laminate that combines substrates with different properties and can utilize the characteristics of both has been proposed.

[0003] Japanese Patent No. 4458116

[0004] However, in the above laminate, further improvement in quality may be desired. For example, further improvement in thermal conductivity and electrical conductivity in the above laminate may be desired.

[0005] In view of the above, a main object of the present invention is to provide a laminate having excellent thermal conductivity and electrical conductivity.

[0006] 1. A laminate according to an embodiment of the present invention includes a semiconductor layer, a support substrate, and an intermediate layer disposed between the semiconductor layer and the support substrate. Each of the semiconductor layer and the support substrate has conductivity, the thermal conductivity of the support substrate is higher than the thermal conductivity of the semiconductor layer, and the intermediate layer has crystallinity. 2. In the laminate according to 1 above, each of the semiconductor layer, the support substrate, and the intermediate layer may contain donor impurities. The concentration of donor impurities in the intermediate layer may be higher than the concentration of donor impurities in the semiconductor layer and the concentration of donor impurities in the support substrate. 3. In the laminate according to 2 above, the concentration of donor impurities in the intermediate layer is 1×10 ２０ atoms / cm ３7. In the laminate described in any one of items 1 to 3 above, the intermediate layer may contain the constituent material of the semiconductor layer and / or the constituent material of the support substrate. 8. In the laminate described in any one of items 1 to 4 above, the intermediate layer may contain Ar. 9. In the laminate described in item 5 above, the proportion of Ar in the intermediate layer may be 5 atom% or less when the total amount of elements contained in the intermediate layer is 100 atom%. 10. In the laminate described in any one of items 1 to 6 above, the intermediate layer may contain 3C-SiC crystal. In the intermediate layer, the single crystal region composed of the 3C-SiC crystal may occupy 50% or more. 11. In the laminate described in any one of items 1 to 7 above, the dislocation density of the semiconductor layer may be 1 × 10 ７ cm －２ The following may also apply: 9. In the laminate described in any one of items 1 to 8 above, the thickness of the intermediate layer may be 5 nm or less. 10. In the laminate described in any one of items 1 to 9 above, the thermal resistance of the intermediate layer may be 1 × 10 －８ I understand ２It may be below K / W. 11. In the laminate according to any one of 1 to 10 above, the support substrate may contain 4H-SiC crystal or 6H-SiC crystal. 12. In the laminate according to 11 above, the off-angle of the support substrate may be 1° or less. 13. In the laminate according to any one of 1 to 12 above, the thickness of the support substrate may be 100 μm or more and 1000 μm or less. 14. In the laminate according to any one of 1 to 13 above, the semiconductor layer may be a compound semiconductor layer. 15. In the laminate according to 14 above, the compound semiconductor layer may contain a group III-V compound semiconductor. 16. In the laminate according to any one of 1 to 15 above, the thickness of the semiconductor layer may be from 0.1 μm to 20 μm. 17. A semiconductor device according to another aspect of the present invention has a laminate according to any one of 1 to 16 above and a functional layer provided on the laminate. 18. A method for manufacturing a laminate according to yet another aspect of the present invention is a method for manufacturing a laminate according to any one of 1 to 16 above, which includes performing an activation treatment on each of the surface of a semiconductor layer precursor and the surface of a support substrate precursor, joining the semiconductor layer precursor and the support substrate precursor to obtain a joined body in which an amorphous layer is formed, and performing a heat treatment on the joined body in this order, and the heat treatment is performed in an atmosphere containing hydrogen.

[0007] According to an embodiment of the present invention, a laminate having excellent thermal conductivity and electrical conductivity can be provided.

[0008] It is a schematic cross-sectional view showing a schematic configuration of a laminate according to one embodiment of the present invention. It is a view showing a manufacturing process of a laminate according to one embodiment of the present invention. It is a view following FIG. 2A. It is a view following FIG. 2B. It is a view following FIG. 2C. It is a view following FIG. 2D. It is a view following FIG. 2E. It is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to one embodiment of the present invention.

[0009] The embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited to these embodiments. In order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the embodiments, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] A. Figure 1 of the laminate is a schematic cross-sectional view showing the general configuration of a laminate according to one embodiment of the present invention. The laminate 100 has a semiconductor layer 10, a support substrate 20, and an intermediate layer 30 disposed between the semiconductor layer 10 and the support substrate 20. The semiconductor layer 10 has a first main surface 11 and a second main surface 12 that are spaced apart from each other in the thickness direction, and the intermediate layer 30 and the support substrate 20 are disposed on the second main surface 12 side of the semiconductor layer 10. For example, a functional layer (device layer) is formed on the semiconductor layer 10, and the laminate 100 can be used as a semiconductor element.

[0011] Although not shown in the diagram, the laminate 100 may have additional layers of any kind. The type, function, number, combination, and arrangement of such layers can be appropriately determined according to the purpose.

[0012] The laminate 100 can be manufactured in any suitable shape. In one embodiment, it can be manufactured in the form of a so-called wafer. The size of the laminate 100 can be appropriately set depending on the purpose. For example, the diameter of the wafer is 50 mm to 200 mm. The laminate 100 may have orientation flats or notches formed in part to indicate the crystal orientation (e.g., the crystal orientation of the wafer).

[0013] [Semiconductor Layer] The thickness of the semiconductor layer 10 can be set to any appropriate value depending on the application of the laminate 100. The thickness of the semiconductor layer 10 is, for example, 0.1 μm or more, preferably 0.5 μm or more, and may be 1 μm or more. On the other hand, the thickness of the semiconductor layer 10 is, for example, 20 μm or less, preferably 10 μm or less, and more preferably 5 μm or less.

[0014] The semiconductor layer 10 typically has crystallinity. In this specification, "crystallinity" means a state in which the atoms constituting each layer or the substrate are arranged regularly. The semiconductor layer 10 preferably contains a single crystal of a semiconductor material. The content ratio of the semiconductor material in the semiconductor layer 10 is, for example, 95% to 100% by mass. Examples of the semiconductor layer 10 include an elemental semiconductor layer and a compound semiconductor layer. The elemental semiconductor layer contains a single element as the semiconductor material. Examples of the element that can constitute the elemental semiconductor layer include silicon (Si) and germanium (Ge). These can be used alone or in combination. The compound semiconductor layer contains a compound semiconductor composed of a plurality of elements as the semiconductor material. Examples of the compound semiconductor that can constitute the compound semiconductor layer include III-V compound semiconductors. Specific examples of the III-V compound semiconductors include group III element nitrides, indium phosphide, gallium arsenide, etc. Examples of the group III element used to constitute the group III element nitride include aluminum (Al), gallium (Ga), and indium (In). These can be used alone or in combination. Specific examples of the group III element nitride include aluminum nitride (Al ｘ N), gallium nitride (Ga ｙ N), indium nitride (In ｚ N), aluminum gallium nitride (Al ｘ Ga ｙ N), gallium indium nitride (Ga ｙ In ｚ N), aluminum indium nitride (Al ｘ In ｚ N), aluminum gallium indium nitride (Al ｘ Ga ｙ In ｚ N). Examples of the compound semiconductor that can constitute the compound semiconductor layer also include, for example, gallium oxide (e.g., Ga ２ O ３ ), aluminum gallium oxide ((Al ｘ Ga ｙ ) ２ O ３Examples include oxides of Group III elements such as ). In each chemical formula in parentheses, x + y + z = 1 is typical.

[0015] In one embodiment, the semiconductor layer 10 is a compound semiconductor layer. The crystal constituting the compound semiconductor layer may have a hexagonal wurtzite-type crystal structure. In such a crystal (typically a group III element nitride crystal), typically the <0001> direction is the c-axis direction, the <1-100> direction is the m-axis direction, and the <11-20> direction is the a-axis direction. Furthermore, a crystal plane perpendicular to the c-axis is a c-plane, a crystal plane perpendicular to the m-axis is an m-plane, and a crystal plane perpendicular to the a-axis is an a-plane. In one embodiment, the thickness direction of the compound semiconductor layer composed of a group III element nitride crystal is parallel to or substantially parallel to the c-axis. In this case, the first main surface 11 may be a group III element polarity plane on the (0001) plane side, and the second main surface 12 may be a nitrogen polarity plane on the (000-1) plane side. Specifically, the first main surface 11 may be parallel to the (0001) plane, or it may be inclined with respect to the (0001) plane. The inclination angle of the first main surface 11 with respect to the (0001) plane is, for example, 10° or less, may be 5° or less, may be 2° or less, or may be 1° or less. The second main surface 12 may be parallel to the (000-1) plane, or it may be inclined with respect to the (000-1) plane. The inclination angle of the second main surface 12 with respect to the (000-1) plane is, for example, 10° or less, may be 5° or less, may be 2° or less, or may be 1° or less. Conversely, the second main surface 12 may be the Group III element polar plane on the (0001) plane side, and the first main surface 11 may be the nitrogen polar plane on the (000-1) plane side.

[0016] The semiconductor layer 10 is conductive. In this specification, "having conductivity" means that the resistivity is, for example, 100 mΩ·cm or less, preferably 0.1 mΩ·cm or more and 10 mΩ·cm or less, and more preferably 0.1 mΩ·cm or more and 1 mΩ·cm or less.

[0017] Resistivity can be measured by any suitable method. Examples of resistivity measurement methods include the capacitance method, the two-terminal method, the double-ring electrode method, and the eddy current method. In one embodiment, the capacitance method is preferably used. According to the capacitance method, resistivity can be determined without damaging the object to be measured. Specifically, the object to be measured is inserted into a capacitor consisting of a probe and a stage, a pulse voltage is applied, the time change in the charge amount of the object to be measured is measured, and resistivity is calculated from the measured value. In this case, since the probe does not come into contact with the object to be measured, resistivity can be determined without forming an ohmic contact electrode. The spatial resolution of the probe may be about 1 mm to 10 mm. For information on how to determine resistivity, see, for example, the non-patent document "R. Stibal et al., “Contactless evaluation of semi-insulating GaAs wafer resistivity using the time-dependent charge measurement” Semiconductor Science and Technology 6 p995 (1991)".

[0018] The semiconductor layer 10 may contain a dopant. The dopant may be a donor impurity or an acceptor impurity. In one embodiment, the semiconductor layer 10 contains a donor impurity. This can impart excellent conductivity to the semiconductor layer. Examples of donor impurities include the elements of groups 14 to 16 of the periodic table (IUPAC Periodic Table of the Elements (version date 4 May 2022)). Specific examples of group 14 elements include carbon (C), silicon (Si), germanium (Ge), and tin (Sn). Specific examples of group 15 elements include nitrogen (N), phosphorus (P), and arsenic (As). Specific examples of group 16 elements include oxygen (O) and sulfur (S). Donor impurities may be used alone or in combination. The semiconductor layer 10 preferably contains silicon (Si), germanium (Ge), nitrogen (N), phosphorus (P), sulfur (S), or a combination thereof, and more preferably contains silicon (Si), germanium (Ge), sulfur (S), or a combination thereof. This allows for stable improvement of the conductivity of the semiconductor layer.

[0019] The concentration of donor impurities in the semiconductor layer 10 is, for example, 1 × 10⁻⁶ １６ atoms / cm ３ The above is preferable to 1 × 10 １８ atoms / cm ３ That is all, more preferably 3 × 10 １８ atoms / cm ３ This concludes the explanation. When the concentration of donor impurities in the semiconductor layer is above this lower limit, the conductivity of the semiconductor layer can be further and stably improved. The concentration of donor impurities can be measured, for example, by Hall effect measurement, C-V measurement, or secondary ion mass spectrometry (SIMS).

[0020] The dislocation density of the semiconductor layer 10 is 1 × 10⁻⁶ ７ cm －２ The following may be true, preferably 5 × 10 ６ cm －２The following, more preferably 1 × 10 ６ cm －２ The following applies. By having such a semiconductor layer 10 (in particular, a compound semiconductor layer composed of a group III element nitride), a functional layer can be formed well, for example. The lower limit of the dislocation density of the semiconductor layer 10 is, for example, 1 × 10⁻⁶. １ cm －２ This is possible. The dislocation density of a compound semiconductor layer composed of Group III element nitrides is, for example, 1 × 10⁻⁶. ４ cm －２ That's fine too.

[0021] The thermal conductivity of the semiconductor layer 10 at room temperature (25°C) is, for example, 1 W / K·m or more, preferably 8 W / K·m or more. On the other hand, the thermal conductivity of the semiconductor layer 10 is, for example, 350 W / K·m or less, preferably 250 W / K·m or less. The thermal conductivity is measured, for example, by the laser flash method or the heat flow meter method.

[0022] [Support Substrate] The support substrate 20 supports the semiconductor layer 10 via the intermediate layer 30. The thermal conductivity of the support substrate 20 is higher than that of the semiconductor layer 10. Therefore, by combining the support substrate with the semiconductor layer, the thermal conductivity of the laminate can be improved, and a high level of heat dissipation that cannot be achieved with the semiconductor layer alone can be achieved.

[0023] At room temperature (25°C), the thermal conductivity of the support substrate 20 is, for example, 1.1 times or more, preferably 2.0 times or more, than that of the semiconductor layer 10. The thermal conductivity of the support substrate 20 at room temperature (25°C) is, for example, 270 W / K·m or more, preferably 490 W / K·m or more. When the support substrate has such thermal conductivity, the thermal conductivity of the laminate can be stably improved.

[0024] The thickness of the support substrate 20 can be set to any appropriate value. For example, the thickness of the support substrate 20 is 100 μm or more and 1000 μm or less, preferably 200 μm or more.

[0025] The support substrate 20 is typically crystalline. The support substrate 20 preferably contains crystalline inorganic material, and more preferably contains single crystals of inorganic material. The inorganic material content in the support substrate 20 is, for example, 95% to 100% by mass. Examples of inorganic materials that can constitute the support substrate 20 include inorganic carbides such as silicon carbide (SiC); and aluminum oxide (Al ２ O ３ ), sapphire, quartz, spinel (MgAl ２ O ４ ), mullite (3Al ２ O ３ ・2SiO ２ , 2Al ２ O ３ 3SiO ２ Examples include inorganic oxides such as ), inorganic nitrides such as aluminum nitride (AlN), and the compound semiconductors mentioned above. Inorganic materials can be used alone or in combination. Among such inorganic materials, inorganic carbides and compound semiconductors are preferred, inorganic carbides are preferred, and silicon carbide (SiC) is even more preferred.

[0026] In one embodiment, the support substrate 20 contains a 4H-SiC crystal or a 6H-SiC crystal. This allows the thermal conductivity of the support substrate to be stably adjusted to the above range. When the support substrate 20 contains a single crystal of an inorganic material, for example, the thickness direction of the support substrate 20 may be parallel or substantially parallel to the c-axis. The off-angle of the support substrate 20 is, for example, 5° or less, preferably 3° or less, more preferably 1° or less, and even more preferably 0.5° or less. Note that the off-angle of the support substrate 20 refers to the inclination angle of the support substrate 20 in the thickness direction with respect to the reference crystal axis (e.g., the c-axis). Furthermore, when the support substrate 20 contains a 4H-SiC crystal or a 6H-SiC crystal, the main surface of the support substrate 20 located on the intermediate layer 30 side may be the Si polarity side or the C polarity side. In the laminate 100, the crystal orientation of the semiconductor layer 10 and the crystal orientation of the support substrate 20 can be any appropriate arrangement.

[0027] The support substrate 20 is conductive. In other words, in one embodiment, both the semiconductor layer 10 and the support substrate 20 are conductive. Therefore, the conductivity of the laminate can be sufficiently improved. The resistivity of the support substrate 20 is preferably 0.1 mΩ·cm or more and 30 mΩ·cm or less, and more preferably 0.1 mΩ·cm or more and 20 mΩ·cm or less.

[0028] The support substrate 20 may contain a dopant. The dopant may be a donor impurity or an acceptor impurity. In one embodiment, the support substrate 20 contains a donor impurity. This can impart excellent conductivity to the support substrate. Examples of donor impurities that the support substrate 20 may contain are the same as those that the semiconductor layer 10 may contain. The support substrate 20 preferably contains silicon (Si), germanium (Ge), nitrogen (N), phosphorus (P), sulfur (S), or a combination thereof, and more preferably nitrogen (N). This can stably improve the conductivity of the support substrate.

[0029] The concentration of donor impurities in the support substrate 20 may be higher than or lower than the concentration of donor impurities in the semiconductor layer 10. In one embodiment, the concentration of donor impurities in the support substrate 20 is lower than the concentration of donor impurities in the semiconductor layer 10. The concentration of donor impurities in the support substrate 20 is, for example, 1 × 10⁻¹⁶. １６ atoms / cm ３ The above is preferable to 1 × 10 １８ atoms / cm ３ That concludes the explanation. When the concentration of donor impurities in the support substrate is above this lower limit, the conductivity of the support substrate can be improved more stably.

[0030] [Intermediate Layer] The intermediate layer 30 is located between the semiconductor layer 10 and the support substrate 20, and joins them together. The intermediate layer 30 typically contains the constituent material of the semiconductor layer 10 and / or the constituent material of the support substrate 20, and preferably contains the constituent material of the support substrate 20 (i.e., the inorganic material described above). This can improve the bonding strength between the semiconductor layer and the support substrate. The inorganic material content in the intermediate layer 30 is, for example, 95% to 100% by mass. The intermediate layer 30 is crystalline. Preferably, the intermediate layer 30 contains crystalline bodies of the same inorganic material as the support substrate 20, and more preferably, contains single crystal bodies of the same inorganic material as the support substrate 20.

[0031] In one embodiment, when the support substrate 20 contains silicon carbide (SiC), the intermediate layer 30 contains 3C-SiC crystals. Preferably, in the intermediate layer 30, single-crystal regions composed of 3C-SiC crystals occupy 50% or more, more preferably 60% or more, and may be 70% or more, or 80% or more. The thickness of the intermediate layer 30 is preferably 5 nm or less, and may be 2 nm or less. On the other hand, the thickness of the intermediate layer 30 is, for example, 0.5 nm or more. The presence or absence of the intermediate layer and the thickness of the intermediate layer can be confirmed, for example, by observation with a transmission electron microscope (TEM). By forming an intermediate layer composed of 3C-SiC crystals in the laminate, the high thermal conductivity of the support substrate can be effectively utilized, and the laminate can have extremely excellent heat dissipation properties.

[0032] The thermal resistance of the intermediate layer 30 is, for example, 1 × 10⁻⁶ －８ I understand ２ It may be less than or equal to kW, preferably 8 × 10 －９ I understand ２ It is less than kW and 6 x 10 －９ I understand ２ It may be less than or equal to kW. The thermal resistance of the intermediate layer 30 may correspond to the interfacial thermal resistance (TBR) between the compound semiconductor layer 10 and the support substrate 20.

[0033] The intermediate layer 30 may contain a dopant. The dopant may be a donor impurity or an acceptor impurity. In one embodiment, the intermediate layer 30 contains a donor impurity. This can narrow the potential barrier width at the junction interface of the laminate, and improve conductivity through the tunneling effect, etc. Examples of donor impurities that the intermediate layer 30 may contain are the same as those that the semiconductor layer 10 may contain. The intermediate layer 30 preferably contains silicon (Si), germanium (Ge), nitrogen (N), phosphorus (P), sulfur (S), or a combination thereof, and more preferably contains nitrogen (N) and / or phosphorus (P).

[0034] In one embodiment, the concentration of donor impurities in the intermediate layer 30 is higher than the concentration of donor impurities in the semiconductor layer 10 and the concentration of donor impurities in the support substrate 20. This can further narrow the potential barrier width at the bonding interface of the laminate. The concentration of donor impurities in the intermediate layer 30 is, for example, 100 times or more, preferably 1000 times or more, and more preferably 2000 times or more, compared to the concentration of donor impurities in the semiconductor layer 10. On the other hand, the concentration of donor impurities in the intermediate layer 30 is, for example, 10000 times or less, preferably 5000 times or less, and more preferably 3000 times or less, compared to the concentration of donor impurities in the semiconductor layer 10. The concentration of donor impurities in the intermediate layer 30 is, for example, 100 times or more, preferably 1000 times or more, more preferably 2000 times or more, and even more preferably 4000 times or more, compared to the concentration of donor impurities in the support substrate 20. On the other hand, the concentration of donor impurities in the intermediate layer 30 is, for example, 10,000 times or less, preferably 8,000 times or less, and more preferably 6,000 times or less, compared to the concentration of donor impurities in the support substrate 20.

[0035] The concentration of donor impurities in the intermediate layer 30 is, for example, 1 × 10⁻⁶ １９ atoms / cm ３ The above is preferable to 1 × 10 ２０ atoms / cm ３That concludes the explanation. If the concentration of donor impurities in the intermediate layer is above this lower limit, the conductivity of the laminate can be sufficiently improved. On the other hand, the concentration of donor impurities in the intermediate layer 30 is, for example, 3 × 10⁻⁶. ２２ atoms / cm ３ The following applies, and also, for example, 2 × 10 ２２ atoms / cm ３ The following applies:

[0036] The intermediate layer 30 may contain elements other than the constituent materials of the semiconductor layer 10, the constituent materials of the support substrate 20, and the dopant. For example, the intermediate layer 30 may further contain argon (Ar). The proportion of Ar in the intermediate layer 30 may be, for example, 0.1 atom% or more, and 2.0 atom% or more, when the total amount of elements contained in the intermediate layer 30 is taken as 100 atom%. On the other hand, the proportion of Ar in the intermediate layer 30 may be, for example, 15.0 atom% or less, preferably 5 atom% or less, when the total amount of elements contained in the intermediate layer 30 is taken as 100 atom%. As a specific example, when the semiconductor layer 10 contains gallium nitride, the proportion of Ar in the intermediate layer 30 will be within the above range when the sum of C, N, O, Si, Ga, and Ar in the intermediate layer 30 is taken as 100 atom%. The relative abundance of various elements in the intermediate layer can be determined, for example, by compositional analysis using energy-dispersive X-ray spectroscopy (EDX).

[0037] B. Manufacturing method The laminate can be obtained, for example, by heat-treating a bonded body obtained by joining a plate-shaped semiconductor layer precursor and a support substrate precursor.

[0038] Figures 2A to 2F show the manufacturing process of a laminate according to one embodiment of the present invention. As shown in Figure 2A, a semiconductor layer precursor 1 and a support substrate precursor 2 are prepared, and a laminate 100 is obtained by directly joining them. When directly joining, it is preferable that the semiconductor layer precursor 1 and the support substrate precursor 2 are each activated by an appropriate activation treatment. Specifically, it is preferable that the bonding surface (main surface) of the semiconductor layer precursor 1 and the bonding surface (main surface) of the support substrate precursor 2 are each activated by an appropriate activation treatment.

[0039] When the support substrate precursor 2 contains a single crystal of an inorganic material, for example, the thickness direction of the support substrate precursor 2 may be parallel to or substantially parallel to the c-axis. Also, when the support substrate precursor 2 contains a 4H-SiC crystal or a 6H-SiC crystal, the bonding surface to which the activation treatment is applied may be on the Si polar surface side or the C polar surface side. Furthermore, the off-angle of the support substrate precursor 2 is, for example, 5° or less, preferably 3° or less, more preferably 1° or less, and even more preferably 0.5° or less. By using a support substrate precursor having such an off-angle, the above-described intermediate layer can be formed well. Note that the off-angle of the support substrate precursor 2 refers to the inclination angle of the main surface of the support substrate precursor 2 with respect to the reference crystal plane (e.g., the c-plane).

[0040] A doping layer may be formed at the thickness-direction end of the support substrate precursor 2 on the bonding surface side. The formation of the doping layer allows, for example, the concentration of donor impurities in the formed intermediate layer to be stably adjusted within the above-mentioned range, thereby suitably adjusting the resistivity of the intermediate layer. The doping layer can be formed, for example, by ion implantation. Specifically, the doping layer may be an ion-implanted layer. Examples of ions to be implanted include nitrogen ions and phosphorus ions. The doping element concentration of the ion-implanted layer is, for example, 1 × 10⁻⁶. ２０ cm －２ The above is preferable to 1 × 10 ２１ cm －２ That concludes the explanation. The concentration of doping elements can be confirmed, for example, by secondary ion mass spectrometry (SIMS).

[0041] The above activation treatment is typically performed by irradiating with a neutralizing beam. Preferably, a neutralizing beam is generated using an apparatus such as the one described in Japanese Patent Application Publication No. 2014-086400, and the activation treatment is performed by irradiating with this beam. Specifically, a saddle-field type fast atomic beam (FAB) source is used as the beam source, an inert gas such as argon or xenon is introduced into the chamber, and a high voltage is applied to the electrodes from a DC power supply. As a result, electrons move due to the saddle-field type electric field generated between the electrode (positive electrode) and the housing (negative electrode), and a beam of atoms and ions from the inert gas is generated. Of the beam that reaches the grid, the ion beam is neutralized at the grid, so a beam of neutral atoms is emitted from the fast atomic beam source. The voltage during the activation treatment by beam irradiation is preferably 0.5 kV to 2.0 kV. The current during the activation treatment by beam irradiation is preferably 50 mA to 200 mA.

[0042] Since the semiconductor layer precursor 1 and the support substrate precursor 2 may have different resistances to activation treatment, it is preferable to perform the activation treatment so that an amorphous layer can be formed near the bonding interface after bonding. In one embodiment, the activation treatment can be performed in multiple stages (for example, three stages). Figure 2B shows the state in which the first activation treatment has been applied to the bonding surface 1a of the semiconductor layer precursor 1 and the bonding surface 2a of the support substrate precursor 2, respectively. Typically, the activation of the bonding surface 1a of the semiconductor layer precursor 1 and the bonding surface 2a of the support substrate precursor 2 can be performed simultaneously. The time of the first activation treatment (for example, the irradiation time of the beam) is, for example, 20 seconds to 200 seconds.

[0043] Figure 2C shows the second activation treatment. In the second activation treatment, the junction surface 2a of the support substrate precursor 2 is further irradiated with a beam. In the second activation treatment, the semiconductor layer precursor 1 is substantially not irradiated with a beam. For example, the second activation treatment is performed by irradiating the semiconductor layer precursor 1 and the support substrate precursor 2 with a beam in the first activation treatment, stopping the beam irradiation to the semiconductor layer precursor 1, and continuing the beam irradiation to the support substrate precursor 2 for a predetermined time. As a result of the second activation treatment, an amorphous region (not shown) may be formed on the junction surface 2a side of the support substrate precursor 2. Also, as a result of the second activation treatment, a deposited layer 4 containing the components constituting the support substrate precursor 2 may be formed on the surface of the semiconductor layer precursor 1. The time of the second activation treatment (for example, the beam irradiation time) is, for example, 10 to 120 seconds.

[0044] Figure 2D shows the third activation treatment. In the third activation treatment, the junction surface 1a of the semiconductor layer precursor 1 and the junction surface 2a of the support substrate precursor 2 are further irradiated with a beam. For example, the third activation treatment is performed by, in the second activation treatment, irradiating the support substrate precursor 2 with a beam, then restarting the beam irradiation to the semiconductor layer precursor 1, and continuing the beam irradiation to the support substrate precursor 2 for a predetermined time. The third activation treatment removes the deposited layer 4 formed on the surface of the semiconductor layer precursor 1, and the junction surface 1a of the semiconductor layer precursor 1 can be activated. The duration of the third activation treatment (for example, the beam irradiation time) is, for example, 20 seconds to 200 seconds.

[0045] After activation treatment, the bonding surface 1a of the semiconductor layer precursor 1 and the bonding surface 2a of the support substrate precursor 2 can be brought into contact and directly bonded by applying pressure. By direct bonding, a bonded body 101 is obtained as shown in Figure 2E. It is preferable to perform the contact and pressurization of the bonding surfaces in a vacuum atmosphere. The temperature at this time is typically room temperature. Specifically, it is preferably 20°C to 40°C, and more preferably 25°C to 30°C. The pressure applied is preferably 100N to 20000N. An amorphous layer 3 as a precursor for the intermediate layer 30 can be formed near the bonding interface of the bonded body 101.

[0046] During bonding, it is preferable that the bonding surface 1a of the semiconductor layer precursor 1 and the bonding surface 2a of the support substrate precursor 2 are flat surfaces. Specifically, the arithmetic mean roughness Ra of the bonding surface 1a of the semiconductor layer precursor 1 and the bonding surface 2a of the support substrate precursor 2 is preferably 1 nm or less, more preferably 0.7 nm or less, even more preferably 0.5 nm or less, and particularly preferably 0.3 nm or less. Methods for planarizing the surfaces of each precursor include, for example, mirror polishing by chemical mechanical polishing (CMP) or lapping.

[0047] When joining, it is preferable that the joining surfaces be cleaned, for example, to remove abrasive residue. Examples of cleaning methods include wet cleaning, dry cleaning, and scrubbing. Among these, scrubbing is preferred because it is simple and efficient. A specific example of scrubbing is a method in which a cleaning agent (for example, Lion Corporation's Sunwash series) is used, followed by cleaning with a solvent (for example, a mixed solution of acetone and isopropyl alcohol (IPA)) using a scrubbing machine.

[0048] Next, the bonded body 101 of the semiconductor layer precursor 1 and the support substrate precursor 2 is subjected to heat treatment. In the illustrated example, as shown in Figure 2F, the bonded body 101, which has been thinned by grinding, polishing, etc., is subjected to heat treatment. By heat-treating the bonded body 101, the amorphous layer 3 can be crystallized and an intermediate layer 30 can be formed. At this time, elements that can function as donor impurities among the elements constituting the semiconductor layer precursor 1 and / or the elements constituting the support substrate precursor 2 may diffuse into the intermediate layer 30. In this way, a laminated body 100 is obtained.

[0049] The heat treatment atmosphere is arbitrarily and appropriately selected depending on the composition of the amorphous layer 3. Examples of heat treatment atmospheres include a hydrogen atmosphere and a phosphine atmosphere. It is preferable to perform the heat treatment for forming the intermediate layer 30 under a hydrogen atmosphere. The heat treatment atmosphere may contain gases other than hydrogen gas and phosphine. It is preferable that the heat treatment atmosphere contains a noble gas such as argon and an inert gas such as nitrogen. Furthermore, the heat treatment atmosphere may contain other gases depending on the constituent components of the semiconductor layer precursor 1. For example, if the semiconductor layer precursor 1 is composed of nitride, the heat treatment atmosphere may contain ammonia gas. The heat treatment temperature is, for example, 700°C to 1100°C, preferably 800°C or higher, and may also be 900°C or higher. The heat treatment time is preferably 5 to 60 minutes. When the heat treatment temperature and / or heat treatment time are within this range, elements that can function as donor impurities can be stably diffused from the semiconductor layer precursor and / or support substrate precursor to the intermediate layer.

[0050] Although not shown in the figures, a protective film may be provided on the surface of the semiconductor layer precursor 1 during the heat treatment of the bonded body 101. By providing a protective film, for example, deterioration of the semiconductor layer precursor 1 due to heat treatment can be prevented. The protective film may be composed of, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, etc. The thickness of the protective film is preferably 0.01 μm to 1 μm. The protective film can be removed by any appropriate method after the heat treatment of the bonded body 101.

[0051] The bonded body 101 (laminated body 100) can be subjected to any appropriate processing. Unlike the illustrated example, the thinning of the semiconductor layer precursor 1 may be performed after the heat treatment of the bonded body 101. However, if the thermal expansion coefficient of the semiconductor layer precursor 1 is greater than that of the support substrate precursor 2, it is preferable to thin the semiconductor layer precursor 1 before the heat treatment of the bonded body 101, as shown in the illustration. This is because it is possible to suppress the occurrence of defects such as cracks and fractures in the resulting semiconductor layer 10. In the illustrated example, the semiconductor layer precursor 1 is thinned, but for example, if the semiconductor layer precursor 1 and the support substrate precursor 2 are bonded together after being integrated with another substrate (not shown) in advance, the thinning of the semiconductor layer precursor 1 can be omitted.

[0052] C. Applications The above laminate can typically be applied to any suitable semiconductor device. Specifically, any suitable functional layer can be formed on the laminate. Figure 3 is a schematic cross-sectional view showing the general configuration of a semiconductor device (device substrate) according to one embodiment of the present invention. The semiconductor device (device substrate) 200 has a laminate 100 and a functional layer 40 formed on the first main surface 11 of the semiconductor layer 10 of the laminate 100. The functional layer 40 is typically formed by epitaxial growth of a crystal by any suitable growth method. The functional layer 40 can function as, for example, a light-emitting layer, a rectifier layer, a switching element layer, or a power semiconductor layer. For example, since the laminate can have excellent heat dissipation, the semiconductor device can have excellent device operation characteristics and reliability.

[0053] The present invention will be specifically described below with reference to examples, but the present invention is not limited to these examples. The arithmetic mean roughness Ra and dislocation density are values ​​measured by the following measurement methods. <Arithmetic mean roughness Ra> The arithmetic mean roughness Ra of the substrate was measured using an atomic force microscope (Hitachi High-Technologies Corporation, "AFM5400L") in a field of view of 10 μm × 10 μm. <Dislocation density> The dislocation density of the group III element nitride substrate was determined by obtaining a CL image by cathodoluminescence (CL) observation and calculating the density of dark spots, which are defect locations. A scanning electron microscope with a MiniCL system from Gatan (Hitachi High-Technologies Corporation, "S-3400N") was used for observation. Under conditions of an acceleration voltage of 15 kV, a probe current of 90 μA, and a working distance (WD) of 15 mm, a photomultiplier tube (PMT) was used as the detector to acquire a monochrome CL image (magnification 1200x). Observation was performed with the detector inserted between the sample and the objective lens. Five fields of view of 78 μm × 10⁵ μm were observed, the number of dark spots in each image was counted, and the average value was calculated.

[0054] (Preparation Example 1) A conductive single-crystal silicon carbide substrate was prepared. The silicon carbide substrate had a diameter of 4 inches, a thickness of 350 μm, and an off-angle of 4°. The silicon carbide substrate contained 4H-SiC crystals as the main component and nitrogen (N) as a donor impurity.

[0055] (Preparation Example 2) A conductive gallium nitride substrate was prepared. The gallium nitride substrate had a diameter of 4 inches, a thickness of 400 μm, and a dislocation density of 1 × 10⁻¹⁶. ６ cm －２ The gallium nitride substrate contained gallium nitride (GaN) as its main component and silicon (Si) as a donor impurity.

[0056] (Preparation Example 3) A conductive gallium nitride substrate was prepared. The gallium nitride substrate had a diameter of 4 inches, a thickness of 400 μm, and a dislocation density of 1 × 10⁻¹⁶. ６ cm －２ The gallium nitride substrate contained gallium nitride (GaN) as its main component and germanium (Ge) as a donor impurity.

[0057] (Preparation Example 4) A conductive indium phosphide substrate was prepared. The indium phosphide substrate had a diameter of 4 inches, a thickness of 600 μm, and a dislocation density of 1 × 10⁻¹⁶. ３ cm －２ The indium phosphide substrate contained indium phosphide (InP) as its main component and sulfur (S) as a donor impurity.

[0058] [Example 1] (Substrate) The single-crystal silicon carbide substrate (N-doped 4H-SiC substrate) from Preparation Example 1 was used as the support substrate precursor, and the gallium nitride substrate (Si-doped GaN substrate) from Preparation Example 2 was used as the semiconductor layer precursor. The surfaces (bonding surfaces) of these substrates were subjected to chemical mechanical polishing, and the arithmetic mean roughness Ra was 0.2 nm.

[0059] (Bonding) Next, the silicon carbide substrate and the gallium nitride substrate were directly bonded. Specifically, after cleaning the bonding surface (Si polar side) of the silicon carbide substrate and the bonding surface (N polar side) of the gallium nitride substrate, both substrates were placed in a vacuum chamber and 10 －６ The system was evacuated to a Pa level. Then, the bonding surfaces of both substrates were irradiated with a high-speed atomic beam for 50 seconds under the conditions of an acceleration voltage of 1 kV and an Ar flow rate of 27 sccm. After that, only the bonding surface of the silicon carbide substrate was irradiated with the high-speed atomic beam under the same conditions for 20 seconds, and then the bonding surfaces of both substrates were irradiated with the high-speed atomic beam under the same conditions for another 50 seconds. After irradiation, the beam-irradiated surfaces of both substrates were superimposed and pressed with 10,000 N for 2 minutes to bond the two substrates and obtain a bonded body. Subsequently, the gallium nitride substrate of the obtained bonded body was ground and polished to form a gallium nitride layer (semiconductor layer) with a thickness of 3 μm.

[0060] (Heat Treatment) Next, the bonded body was subjected to heat treatment. The heat treatment was carried out at 1000°C for 20 minutes under a mixed gas atmosphere of ammonia, hydrogen, and nitrogen (gas flow rate ratio of ammonia:hydrogen:nitrogen = 1:3:2). In this way, a laminate was obtained.

[0061] [Example 2] A laminate was obtained in the same manner as in Example 1, except that the gallium nitride substrate (Ge-doped GaN substrate) from Preparation Example 3 was used as the semiconductor layer precursor, and phosphorus (P) was ion-implanted as a donor impurity into the surface (Si polar surface) of the silicon carbide substrate before bonding.

[0062] [Example 3] A laminate was obtained in the same manner as in Example 1, except that the indium phosphide substrate (S-doped InP substrate) from Preparation Example 4 was used as the semiconductor layer precursor.

[0063] <Evaluation> The laminates obtained in the examples were evaluated as follows: 1. Cross-sectional TEM observation A scanning transmission electron microscope (JEOL Ltd., "JEM-ARM200F") was used to confirm the presence or absence of an intermediate layer in the laminate and to evaluate the crystallinity of the intermediate layer. Samples for STEM observation were obtained by thinning using the FIB method. For lattice image observation, the observation resolution was increased as needed by high-angle annular dark-field observation (ADF-STEM) with spherical aberration correction. In the intermediate layer of the laminates obtained in the examples, it was confirmed that the atoms were arranged in a regular manner, indicating that a crystalline intermediate layer was formed. Specifically, in the intermediate layer of the laminates of Examples 1 to 3, the arrangement of silicon atoms belonging to 3C-SiC crystal (cubic crystal system) was confirmed. When the intermediate layer was composed of a single crystal, the proportion of the single-crystal region in the intermediate layer (single-crystal area ratio) was determined. Specifically, in the cross-sectional TEM observation area of ​​the intermediate layer (a region with a thickness of the intermediate layer × width of 45 nm in the cross-sectional TEM image observed at 4 million times magnification), the region where the 3C-SiC lattice arrangement was confirmed was defined as the single-crystal region, and the other regions (regions where the lattice arrangement was not confirmed) were defined as the non-single-crystal region, and the proportion occupied by the single-crystal region was determined. The results are shown in Table 1. Furthermore, regarding the composition of the intermediate layer of the laminate of Example 1, elemental analysis was performed by STEM-EDX observation using an energy-dispersive X-ray spectrometer (JEOL Ltd., JED-2300T) with an acceleration voltage of 200 kV, a beam diameter of approximately 0.2 nmΦ, an energy resolution of approximately 140 eV, and an acquisition time of 30 seconds. This allowed for the measurement of the proportion of Ar in the intermediate layer of the laminate of Example 1. The results are shown in Table 1.

[0064] 2. Concentration of donor impurities in each layer of the laminate The concentration of donor impurities in the semiconductor layer and the support substrate was measured from the surface side using a quadrupole secondary ion mass spectrometer (D-SIMS). The concentration of donor impurities in the intermediate layer was measured by STEM-EDX observation, similar to the measurement of the abundance of Ar described above: composition [atom%] [atoms / cm³] ３ The calculation was performed by converting to [composition obtained by STEM-EDX] × [electron number density per unit cell of 3C-SiC = 9.65 × 10⁻¹⁰]. More specifically, [composition obtained by STEM-EDX] × [electron number density per unit cell of 3C-SiC = 9.65 × 10⁻¹⁰]. ２２ atom / cm３ The donor impurity concentration of the intermediate layer was calculated using the following method. For example, in the intermediate layer of the laminate of Example 1, the nitrogen concentration (composition) obtained by STEM-EDX was 10 atom%, and the donor impurity concentration obtained by conversion was 9.65 × 10 ２１ atoms / cm ３ The results are shown in Table 1.

[0065] 3. Resistivity of the semiconductor layer and support substrate of the laminate The sheet resistance [Ω / □] of the substrates prepared in each preparation example was measured by the eddy current method (device: NC-80MAP manufactured by Napson Corporation), and the resistivity [Ω・cm] was calculated by sheet resistance × thickness. The calculated resistivity of the substrate is shown in Table 1 as the resistivity of the corresponding semiconductor layer or support substrate.

[0066]

[0067] The laminate according to the embodiment of the present invention can be applied, for example, to a semiconductor device.

[0068] 1 Semiconductor layer precursor, 2 Support substrate precursor, 3 Amorphous layer, 4 Deposition layer, 10 Semiconductor layer, 11 First main surface, 12 Second main surface, 20 Support substrate, 30 Intermediate layer, 40 Functional layer, 100 Laminate, 101 Bonded structure, 200 Semiconductor device (device substrate).

Claims

1. A laminate comprising a semiconductor layer, a support substrate, and an intermediate layer disposed between the semiconductor layer and the support substrate, wherein each of the semiconductor layer and the support substrate is electrically conductive, the thermal conductivity of the support substrate is higher than the thermal conductivity of the semiconductor layer, and the intermediate layer is crystalline.

2. The laminate according to claim 1, wherein each of the semiconductor layer, the support substrate, and the intermediate layer contains a donor impurity, and the concentration of the donor impurity in the intermediate layer is higher than the concentration of the donor impurity in the semiconductor layer and the concentration of the donor impurity in the support substrate.

3. The concentration of donor impurities in the intermediate layer is 1 × 10⁻⁶ ２０ atoms / cm ３ The laminate according to claim 2.

4. The laminate according to claim 1, wherein the intermediate layer comprises the constituent material of the semiconductor layer and / or the constituent material of the support substrate.

5. The laminate according to claim 1, wherein the intermediate layer contains Ar.

6. The laminate according to claim 5, wherein the proportion of Ar in the intermediate layer is 5 atom% or less, when the total amount of elements contained in the intermediate layer is 100 atom%.

7. The laminate according to claim 1, wherein the intermediate layer contains a 3C-SiC crystal, and in the intermediate layer, a single-crystal region composed of the 3C-SiC crystal accounts for 50% or more.

8. The dislocation density of the semiconductor layer is 1 × 10⁻⁶ ７ cm －２ The laminate according to claim 1, which is as follows:

9. The laminate according to claim 1, wherein the thickness of the intermediate layer is 5 nm or less.

10. The thermal resistance of the intermediate layer is 1 × 10 －８ I understand ２ The laminate according to claim 1, wherein the wattage is less than or equal to kW.

11. The laminate according to claim 1, wherein the support substrate includes a 4H-SiC crystal or a 6H-SiC crystal.

12. The laminate according to claim 11, wherein the off-angle of the support substrate is 1° or less.

13. The laminate according to claim 1, wherein the thickness of the support substrate is 100 μm or more and 1000 μm or less.

14. The laminate according to claim 1, wherein the semiconductor layer is a compound semiconductor layer.

15. The laminate according to claim 14, wherein the compound semiconductor layer comprises a group III-V compound semiconductor.

16. The laminate according to claim 1, wherein the thickness of the semiconductor layer is 0.1 μm or more and 20 μm or less.

17. A semiconductor element comprising a laminate according to any one of claims 1 to 16 and a functional layer provided on the laminate.

18. A method for manufacturing a laminate according to any one of claims 1 to 16, comprising, in this order: activating the surface of a semiconductor layer precursor and the surface of a support substrate precursor; joining the semiconductor layer precursor and the support substrate precursor to obtain a bonded body in which an amorphous layer is formed; and subjecting the bonded body to heat treatment, wherein the heat treatment is performed in a hydrogen-containing atmosphere.

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