Array substrate and display apparatus
By designing an overlapping structure of compensation transistors and scanning signal lines on the array substrate, the parasitic capacitance is increased, which solves the image retention problem in AMOLED display devices, reduces power consumption, and improves display effect and stability.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-10-13
- Publication Date
- 2026-05-15
AI Technical Summary
Image retention is a problem in AMOLED displays, especially on array substrates using low-temperature polycrystalline silicon technology, which affects display performance and reliability.
By designing the gate of the compensation transistor on the array substrate to be coupled to the first scan signal line, and setting the first conductive region in the conductive connection portion so that it partially overlaps with the first scan signal line, the parasitic capacitance is increased, the maximum value of the data voltage of the data signal line is reduced, and the state difference of the driving transistor before and after charging is reduced.
It improves the display ghosting problem, reduces display power consumption, enhances display effect and stability, and strengthens product competitiveness.
Smart Images
Figure CN2025127396_15052026_PF_FP_ABST
Abstract
Description
Array substrate and display device
[0001] Cross-reference to related applications
[0002] This application claims priority to Chinese Patent Application No. 202411589754.5, filed on November 8, 2024, entitled "Array Substrate and Display Device", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This invention relates to the field of display technology, and in particular to array substrates and display devices. Background Technology
[0004] Active-matrix organic light-emitting diodes (AMOLEDs) are characterized by fast response times, high contrast ratios, and wide viewing angles, and are currently widely used. With the development of AMOLED technology, its advantages such as wide color gamut, low power consumption, and flexibility are becoming increasingly apparent. However, limitations imposed by factors such as the lifespan of the light-emitting materials, device structure, and manufacturing processes can lead to image retention issues in AMOLEDs. This is particularly noticeable in products using low-temperature polysilicon (LTPS) array substrates, thus affecting display quality and reliability. Summary of the Invention
[0005] The array substrate provided in this embodiment of the invention includes: a substrate and a pixel circuit disposed on the substrate;
[0006] The pixel circuit includes a driving transistor and a compensation transistor; the gate of the compensation transistor is coupled to a first scan signal line, the first electrode of the compensation transistor is coupled to the gate of the driving transistor through a first conductive connection portion, and the second electrode of the compensation transistor is coupled to the second electrode of the driving transistor.
[0007] The first conductive connection portion extends along a first direction, and the first scan signal line extends along a second direction; the first conductive connection portion has a first conductive area, and the orthographic projection of the first conductive area on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate.
[0008] The spacing of the first conductive area along the second direction is greater than the spacing of the areas in the first conductive connection portion other than the first conductive area along the second direction.
[0009] In some possible implementations, the overlapping area of the first conductive region and the first scan signal line in the orthographic projection of the substrate is the first overlapping area;
[0010] The spacing of the first overlapping regions along the first direction is smaller than the spacing of the first conductive regions along the first direction.
[0011] In some possible implementations, the compensation transistor further includes: a first compensation transistor and a second compensation transistor connected in series;
[0012] The first scan signal line extending along the second direction overlaps with the orthographic projection of the active layer of the first compensation transistor onto the substrate.
[0013] The first scan signal line has a first branch protruding along the first direction, and the first branch overlaps with the orthographic projection of the active layer of the second compensation transistor onto the substrate.
[0014] In some possible implementations, the first conductive connection portion further includes: a second conductive region;
[0015] The second conductive region is coupled to the first electrode of the second compensation transistor through the first via, and the orthographic projection of the second conductive region on the substrate covers the orthographic projection of the first via on the substrate.
[0016] In some possible implementations, the spacing of the second conductive region along the first direction is greater than the spacing of the first via along the first direction.
[0017] In some possible implementations, the spacing of the second conductive region along the second direction is equal to the spacing of the first via along the second direction;
[0018] The spacing of the second conductive region along the second direction is smaller than the spacing of the first conductive region along the second direction.
[0019] In some possible implementations, the orthographic projection of the second conductive region onto the substrate does not overlap with the orthographic projection of the first scan signal line onto the substrate.
[0020] In some possible implementations, the orthographic projection of the second conductive region onto the substrate covers the orthographic projection of the channel region of the second compensation transistor onto the substrate.
[0021] In some possible implementations, it further includes: an anode, which is coupled to the second electrode of the driving transistor;
[0022] The orthographic projection of the anode onto the substrate at least partially overlaps with the orthographic projection of the first compensation transistor onto the substrate.
[0023] In some possible implementations, the orthogonal projection of the anode onto the substrate overlaps with the orthogonal projection portion of at least one of the second compensation transistors onto the substrate.
[0024] In some possible implementations, the orthogonal projection of the anode onto the substrate covers the orthogonal projection of at least one of the second compensation transistors onto the substrate.
[0025] In some possible implementations, the pixel circuit includes: an adjacent first pixel circuit and a second pixel circuit; the first pixel circuit is electrically connected to the anode.
[0026] The orthographic projection of the anode onto the substrate at least partially overlaps with the first conductive connection portion in the first pixel circuit;
[0027] The orthographic projection of the anode onto the substrate at least partially overlaps with the first conductive connection in the second pixel circuit.
[0028] In some possible implementations, the first conductive connection portion further includes: a third conductive region, wherein the first conductive region is located between the second conductive region and the third conductive region;
[0029] The third conductive region is coupled to the gate of the driving transistor through the second via, and the orthographic projection of the third conductive region on the substrate overlaps with the orthographic projection of the second via on the substrate.
[0030] In some possible implementations, the spacing of the third conductive region along the second direction is smaller than the spacing of the second conductive region along the second direction.
[0031] In some possible implementations, the first conductive connection portion further includes: a fourth conductive region, the fourth conductive region being located between the third conductive region and the first conductive region;
[0032] The spacing of the fourth conductive region along the second direction is smaller than the spacing of the third conductive region along the second direction.
[0033] In some possible implementations, the first conductive region in the first conductive connection portion protrudes in a direction away from the first compensation transistor.
[0034] In some possible implementations, the orthogonal projection of the anode onto the substrate covers at least one third conductive region in the first conductive connection portion;
[0035] The orthographic projection of the anode onto the substrate overlaps with the orthographic projection portions of the first conductive region, the second conductive region, and the fourth conductive region in at least one of the first conductive connections onto the substrate.
[0036] In some possible implementations, the first pixel circuit and the second pixel circuit are arranged in a mirror-symmetric manner.
[0037] In some possible implementations, the pixel circuit further includes a first initialization signal line; the first initialization signal line extends along the second direction;
[0038] The first initialization signal line and the first scan signal line are spaced apart along the first direction;
[0039] The protruding area in the first conductive region does not overlap with the orthographic projection of the first initialization signal line onto the substrate.
[0040] The present invention provides a display device including the array substrate described above. Attached Figure Description
[0041] Figure 1 is a schematic diagram of some layout structures of the array substrate provided in an embodiment of the present invention;
[0042] Figure 2 is a schematic diagram of some structures of the pixel circuit provided in an embodiment of the present invention;
[0043] Figure 3 is a schematic diagram of some layout structures of the semiconductor layer provided in an embodiment of the present invention;
[0044] Figure 4 is a schematic diagram of some layout structures of the first conductive layer provided in an embodiment of the present invention;
[0045] Figure 5 is a schematic diagram of some layout structures of the second conductive layer provided in an embodiment of the present invention;
[0046] Figure 6 is a schematic diagram of some layout structures of the third conductive layer provided in an embodiment of the present invention;
[0047] Figure 7 is a schematic diagram of some layout structures of the overlapping first and third conductive layers provided in an embodiment of the present invention;
[0048] Figure 8 is a schematic diagram of some layout structures of the overlapping semiconductor layer and the first conductive layer provided in an embodiment of the present invention;
[0049] Figure 9 is a schematic diagram of some layout structures of the overlapping semiconductor layer, the first conductive layer and the third conductive layer provided in an embodiment of the present invention;
[0050] Figure 10 is a schematic diagram of some other layout structures of the array substrate provided in an embodiment of the present invention;
[0051] Figure 11 is a schematic diagram of some layout structures of the anode provided in an embodiment of the present invention;
[0052] Figure 12 is a schematic diagram of some layout structures of the array substrate provided in the embodiment of the present invention;
[0053] Figure 13 is a simulation curve provided by an embodiment of the present invention;
[0054] Figure 14 is a schematic diagram of some layout structures of the array substrate provided in the embodiment of the present invention;
[0055] Figure 15 is a schematic diagram of some other layout structures of the third conductive layer provided in an embodiment of the present invention;
[0056] Figure 16 is a schematic diagram of some layout structures of the array substrate provided in the embodiment of the present invention;
[0057] Figure 17 is a schematic diagram of some other layout structures of the anode provided in an embodiment of the present invention. Detailed Implementation
[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0059] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.
[0060] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0061] For example, the array substrate may include a display area and a non-display area (i.e., the area in the array substrate other than the area surrounded by the display area). The display area may include multiple pixel units arranged in an array. For example, each pixel unit may include sub-pixels of the same color or sub-pixels of multiple different colors. For instance, a pixel unit may include red, green, and blue sub-pixels, allowing for color mixing to achieve a color display. Alternatively, a pixel unit may include red, green, blue, and white sub-pixels, also allowing for color mixing to achieve a color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following explanation uses a pixel unit including red, green, and blue sub-pixels as an example.
[0062] For example, each sub-pixel may include a pixel circuit and a light-emitting device, with the pixel circuit driving the light-emitting device in the corresponding sub-pixel to emit light.
[0063] The array substrate provided in this embodiment of the invention, as shown in FIG1, includes: a substrate 100 and a pixel circuit 200 disposed on the substrate;
[0064] The pixel circuit 200 includes: a driving transistor T0 and a compensation transistor T1; the gate of the compensation transistor T1 is coupled to the first scan signal line GA1, the first terminal of the compensation transistor T1 is coupled to the gate of the driving transistor T0 through the first conductive connection N1, and the second terminal of the compensation transistor T1 is coupled to the second terminal of the driving transistor T0.
[0065] The first conductive connection portion N1 extends along the first direction F1, and the first scan signal line GA1 extends along the second direction F2; the first conductive connection portion N1 has a first conductive region N1-1, and the orthographic projection of the first conductive region N1-1 on the substrate 100 overlaps with the orthographic projection of the first scan signal line GA1 on the substrate 100.
[0066] The spacing of the first conductive region N1-1 along the second direction F2 is greater than the spacing of the regions in the first conductive connection part N1 other than the first conductive region N1-1 along the second direction F2.
[0067] This invention, through its embodiment, couples the gate of a compensation transistor to a first scan signal line, couples the first electrode of the compensation transistor to the gate of a driving transistor via a first conductive connection, and couples the second electrode of the compensation transistor to the second electrode of the driving transistor. Furthermore, by having the first conductive connection have a first conductive region, the orthographic projection of the first conductive region onto the substrate overlaps with the orthographic projection of the first scan signal line onto the substrate. The spacing of the first conductive region along the second direction is greater than the spacing of the areas in the first conductive connection excluding the first conductive region along the second direction. This maximizes the overlap area between the orthographic projection of the first conductive connection and the first scan signal line onto the substrate, thereby increasing the parasitic capacitance between the first conductive connection and the first scan signal line. Consequently, the maximum value of the data voltage of the data signal line in the pixel circuit is reduced, which decreases the state difference of the driving transistor before and after charging, thus improving the display ghosting problem, enhancing display effect and stability. Moreover, because the maximum value of the data voltage of the data signal line in the pixel circuit is reduced, display power consumption is significantly reduced, i.e., the power consumption of the chip IC is reduced, improving product competitiveness.
[0068] For example, as shown in Figures 1 and 2, the pixel circuit further includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor Cst; wherein, the gate of the second transistor T2 is coupled to the reset signal line RE, the first terminal of the second transistor T2 is coupled to the first node n1 (which can be equivalent to the first conductive connection N1), and the second terminal of the second transistor T2 is coupled to the first initialization signal line Vin1; the gate of the third transistor T3 is coupled to the first scan signal line GA1, the first terminal of the third transistor T3 is coupled to the first terminal of the driving transistor T0, and the second terminal of the third transistor T3 is coupled to the data signal line DA; the gate of the fourth transistor T4 is coupled to the first light emission control signal line EM1, the first terminal of the fourth transistor T4 is coupled to the first power supply signal line VDD, and the fourth transistor T4's... The second electrode of the fifth transistor T5 is coupled to the first electrode of the driving transistor T0; the gate of the fifth transistor T5 is coupled to the first light-emitting control signal line EM1, the first electrode of the fifth transistor T5 is coupled to the second electrode of the driving transistor T0, and the second electrode of the fifth transistor T5 is coupled to the anode of the light-emitting device L; the gate of the sixth transistor T6 is coupled to the second light-emitting control signal line EM2, the first electrode of the sixth transistor T6 is coupled to the anode of the light-emitting device L, and the second electrode of the sixth transistor T6 is coupled to the second initialization signal line Vin2; the gate of the seventh transistor T7 is coupled to the second light-emitting control signal line EM2, the first electrode of the seventh transistor T7 is coupled to the first electrode of the driving transistor T0, and the second electrode of the seventh transistor T7 is coupled to the third initialization signal line Vin3; the first electrode of the capacitor Cst is coupled to the first power supply signal line VDD, and the second electrode of the capacitor Cst is coupled to the gate of the driving transistor T0.
[0069] For example, compensation transistor T1 and third transistor T3 can be turned on under the control of the effective level of the first scan signal transmitted on the first scan signal line GA1, and can be turned off under the control of the ineffective level of the first scan signal. For instance, compensation transistor T1 and third transistor T3 can be configured as N-type transistors, in which case the effective level of the first scan signal is high and the ineffective level of the first scan signal is low. Alternatively, compensation transistor T1 and third transistor T3 can be configured as P-type transistors, in which case the effective level of the first scan signal is low and the ineffective level of the first scan signal is high.
[0070] For example, the second transistor T2 can be turned on under the control of the effective level of the reset signal transmitted on the reset signal line RE, and can be turned off under the control of the ineffective level of the reset signal. For instance, the second transistor T2 can be configured as an N-type transistor, in which case the effective level of the reset signal is high and the ineffective level of the reset signal is low. Alternatively, the second transistor T2 can be configured as a P-type transistor, in which case the effective level of the reset signal is low and the ineffective level of the reset signal is high.
[0071] For example, the fourth transistor T4 and the fifth transistor T5 can be turned on under the control of the effective level of the first light-emitting control signal transmitted on the first light-emitting control signal line EM1, and can be turned off under the control of the ineffective level of the first light-emitting control signal. For instance, the fourth transistor T4 and the fifth transistor T5 can be configured as N-type transistors, in which case the effective level of the first light-emitting control signal is high and the ineffective level of the first light-emitting control signal is low. Alternatively, the fourth transistor T4 and the fifth transistor T5 can be configured as P-type transistors, in which case the effective level of the first light-emitting control signal is low and the ineffective level of the first light-emitting control signal is high.
[0072] For example, the sixth transistor T6 and the seventh transistor T7 can be turned on under the control of the effective level of the second light-emitting control signal transmitted on the second light-emitting control signal line EM2, and can be turned off under the control of the ineffective level of the second light-emitting control signal. For instance, the sixth transistor T6 and the seventh transistor T7 can be configured as N-type transistors, in which case the effective level of the second light-emitting control signal is high and the ineffective level of the second light-emitting control signal is low. Alternatively, the sixth transistor T6 and the seventh transistor T7 can be configured as P-type transistors, in which case the effective level of the second light-emitting control signal is low and the ineffective level of the second light-emitting control signal is high.
[0073] For example, as shown in FIG3, a semiconductor layer 110 is disposed on the substrate in the embodiment of the present invention, wherein the semiconductor layer 110 includes: an active layer of driving transistor T0, an active layer of compensation transistor T1, an active layer of second transistor T2, an active layer of third transistor T3, an active layer of fourth transistor T4, an active layer of fifth transistor T5, an active layer of sixth transistor T6, and an active layer of seventh transistor T7.
[0074] For example, the semiconductor layer can be formed by patterning a semiconductor material. The semiconductor layer can be made of semiconductor materials such as low-temperature poly-silicon (LTPS), and there is no limitation herein.
[0075] It should be noted that the active layer of each transistor includes a source region, a drain region, and a channel region located between the source and drain regions. The source region can be the first electrode of the transistor, and the drain region can be the second electrode; alternatively, the source region can be the second electrode, and the drain region can be the first electrode. No specific limitation is made here. The source and drain regions can be conductive regions formed by doping with n-type or p-type impurities.
[0076] For example, as shown in FIG4, the embodiment of the present invention further includes a first conductive layer 120 located on the side of the semiconductor layer away from the substrate. The first conductive layer 120 includes a first scan signal line GA1, a reset signal line RE, a first light emission control signal line EM1, a second light emission control signal line EM2, and a second electrode of capacitor Cst. It should be noted that the first scan signal line GA1 can be reused as the gate of compensation transistor T1 and third transistor T3, the reset signal line RE can be reused as the gate of second transistor T2, the first light emission control signal line EM1 can be reused as the gate of fourth transistor T4 and fifth transistor T5, the second light emission control signal line EM2 can be reused as the gate of sixth transistor T6 and seventh transistor T7, and the second electrode of capacitor Cst can be reused as the gate of driving transistor T0.
[0077] For example, as shown in FIG5, the embodiment of the present invention further includes a second conductive layer 130 located on the side of the first conductive layer away from the substrate; wherein, the second conductive layer 130 includes: a first initialization signal line Vin1, a third initialization signal line Vin3 and a first power signal line VDD; wherein, the first power signal line VDD can be reused as the first electrode of capacitor Cst.
[0078] As exemplarily shown in FIG6, the embodiment of the present invention further includes a third conductive layer 140 located on the side of the second conductive layer away from the substrate; wherein, the third conductive layer 140 includes a first conductive connection portion N1 and a second initialization signal line Vin2.
[0079] For example, the first conductive layer, the second conductive layer, and the third conductive layer can be conductive materials. For instance, conductive materials can include metals or alloys such as aluminum, molybdenum, and titanium, or metal oxides such as indium tin oxide (ITO). The embodiments of the present invention do not specifically limit the materials of the above-mentioned films.
[0080] It should be noted that a first insulating layer is disposed between the semiconductor layer and the first conductive layer; a second insulating layer is disposed between the first conductive layer and the second conductive layer; and a third insulating layer is disposed between the second conductive layer and the third conductive layer. Exemplarily, the first, second, and third insulating layers are all formed of insulating materials. Depending on the requirements, organic insulating materials, such as polyimide and resin materials, can be selected, or inorganic insulating materials, such as silicon oxide, silicon nitride, and silicon oxynitride, can be selected. This embodiment of the invention does not specifically limit the materials of the above-mentioned film layers.
[0081] In some embodiments of the present invention, as shown in FIG7, the overlapping area of the first conductive region N1-1 and the first scanning signal line GA1 on the substrate 100 is the first overlapping region J1; the spacing L2 of the first overlapping region J1 along the first direction F1 is smaller than the spacing L1 of the first conductive region N1-1 along the first direction F1.
[0082] In some embodiments of the present invention, as shown in FIG8, the compensation transistor T1 includes: a first compensation transistor T1-1 and a second compensation transistor T1-2 connected in series; wherein, a first scan signal line GA1 extending along the second direction F2 overlaps with the orthographic projection of the active layer of the first compensation transistor T1-1 on the substrate 100; the first scan signal line GA1 has a first branch Z1 protruding along the first direction F1, and the first branch Z1 overlaps with the orthographic projection of the active layer of the second compensation transistor T1-2 on the substrate 100.
[0083] In some embodiments of the present invention, as shown in FIG9, the first conductive connection portion N1 further includes a second conductive region N1-2; wherein the second conductive region N1-2 is coupled to the first pole of the second compensation transistor T1-2 through a first via, and the orthogonal projection of the second conductive region N1-2 on the substrate 100 covers the orthogonal projection of the first via on the substrate 100.
[0084] In some embodiments of the present invention, as shown in FIG9, the spacing L3 of the second conductive region N1-2 along the first direction F1 is greater than the spacing L4 of the first via along the first direction.
[0085] In some embodiments of the present invention, as shown in FIG9, the spacing of the second conductive region N1-2 along the second direction F2 is equal to the spacing of the first via along the second direction F2.
[0086] In some embodiments of the present invention, as shown in FIG6, the spacing H2 of the second conductive region N1-2 along the second direction F2 is smaller than the spacing H1 of the first conductive region N1-1 along the second direction F2.
[0087] In some embodiments of the present invention, as shown in FIG9, the orthographic projection of the second conductive region N1-2 on the substrate 100 does not overlap with the orthographic projection of the first scanning signal line GA1 on the substrate 100.
[0088] In some embodiments of the present invention, as shown in FIG10, it further includes: an anode 150, the anode 150 being coupled to the second pole of the driving transistor T0; the orthographic projection of the anode 150 on the substrate 100 at least partially overlaps with the orthographic projection of the first compensation transistor T1-1 on the substrate 100.
[0089] For example, as shown in Figure 11, the anode 150 is the anode of the light-emitting device; wherein, as shown in Figure 2, the anode of the light-emitting device L is coupled to the second terminal of the driving transistor T0 through the fifth transistor T5, and the cathode of the light-emitting device L is coupled to the second power signal line VSS; for example, the light-emitting device L can be an electroluminescent diode. For example, the light-emitting device L can include at least one of the following: organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED), micro light-emitting diode (Micro LED), and mini light-emitting diode (Mini LED). For example, the light-emitting device L can include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the specific structure of the light-emitting device L can be determined according to the needs of the actual application, and is not limited here.
[0090] In some embodiments of the present invention, as shown in FIG10, the orthographic projection of the anode 150 on the substrate 100 overlaps with the orthographic projection portion of at least one second compensation transistor T1-2 on the substrate 100.
[0091] In some embodiments of the present invention, as shown in FIG12, the pixel circuit includes: an adjacent first pixel circuit 200-1 and a second pixel circuit 200-2; the first pixel circuit 200-1 is electrically connected to the anode 150;
[0092] The orthographic projection of the anode 150 onto the substrate 100 at least partially overlaps with the first conductive connection portion N1 in the first pixel circuit 200-1;
[0093] The orthographic projection of the anode 150 onto the substrate 100 at least partially overlaps with the first conductive connection N1 in the second pixel circuit 200-2.
[0094] In some embodiments of the present invention, as shown in FIG6 and FIG9, the first conductive connection portion N1 further includes: a third conductive region N1-3, wherein the first conductive region N1-1 is located between the second conductive region N1-2 and the third conductive region N1-3; the third conductive region N1-3 is coupled to the gate of the driving transistor T0 through a second via, and the orthographic projection of the third conductive region N1-3 on the substrate 100 overlaps with the orthographic projection of the second via on the substrate 100.
[0095] In some embodiments of the present invention, as shown in FIG6, the spacing H3 of the third conductive region N1-3 along the second direction F2 is smaller than the spacing H1 of the first conductive region N1-2 along the second direction F2.
[0096] In some embodiments of the present invention, as shown in FIG6 and FIG9, the first conductive connection portion N1 further includes: a fourth conductive region N1-4, the fourth conductive region N1-4 being located between the third conductive region N1-3 and the first conductive region N1-1; the spacing H4 of the fourth conductive region N1-4 along the second direction F2 is smaller than the spacing H3 of the third conductive region N1-3 along the second direction F2.
[0097] In some embodiments of the present invention, as shown in FIG9, the first conductive region N1-1 in the first conductive connection portion N1 protrudes in a direction away from the first compensation transistor T1-1.
[0098] In some embodiments of the present invention, as shown in FIG10, the orthogonal projection of the anode 150 onto the substrate 100 covers at least one third conductive region N1-3 in the first conductive connection portion N1.
[0099] The orthographic projection of the anode 150 onto the substrate 100 overlaps with the orthographic projection portions of the first conductive region N1-1, the second conductive region N1-2, and the fourth conductive region N1-4 in at least one first conductive connection portion N1 onto the substrate 100.
[0100] In some embodiments of the present invention, as shown in FIG12, the first pixel circuit 200-1 and the second pixel circuit 200-2 are arranged in a mirror-symmetric manner.
[0101] In some embodiments of the present invention, as shown in FIG12, the pixel circuit further includes a first initialization signal line Vin1; the first initialization signal line Vin1 extends along a second direction F2;
[0102] The first initialization signal line Vin1 and the first scan signal line GA1 are spaced apart along the first direction F1;
[0103] The protruding area in the first conductive region N1-1 does not overlap with the orthographic projection of the first initialization signal line Vin1 onto the substrate 100.
[0104] Simulation experiments were conducted on the array substrate shown in FIG12 provided in the embodiments of the present invention to obtain the values of the parasitic capacitance between the first conductive connection portion and the first scan signal line, as shown in Table 1 below.
[0105] Table 1
[0106] For example, the capacitance value of the 2D capacitor formed between the first conductive connection N1_G and the first scan signal line GA1 in the pixel circuit of the green sub-pixel is 0.801fF, the capacitance value of the 3D capacitor formed between the first conductive connection N1_G and the first scan signal line GA1 in the pixel circuit of the green sub-pixel is 2.430fF, the capacitance value of the 2D capacitor formed between the first conductive connection N1_R and the first scan signal line GA1 in the pixel circuit of the red sub-pixel is 0.801fF, and the capacitance value of the 3D capacitor formed between the first conductive connection N1_R and the first scan signal line GA1 in the pixel circuit of the red sub-pixel is 2.434fF.
[0107] In general, the first conductive connection portion of the array substrate in related technologies is designed as a straight line with a fixed linewidth. Simulation experiments on the array substrate in these technologies yielded the values of the parasitic capacitance between the first conductive connection portion and the first scan signal line, as shown in Table 2 below.
[0108] Table 2
[0109] For example, the capacitance value of the 2D capacitor formed between the first conductive connection N1_G and the first scan signal line GA1 in the pixel circuit of the green sub-pixel is 0.330fF, the capacitance value of the 3D capacitor formed between the first conductive connection N1_G and the first scan signal line GA1 in the pixel circuit of the green sub-pixel is 1.707fF, the capacitance value of the 2D capacitor formed between the first conductive connection N1_R and the first scan signal line GA1 in the pixel circuit of the red sub-pixel is 0.330fF, and the capacitance value of the 3D capacitor formed between the first conductive connection N1_R and the first scan signal line GA1 in the pixel circuit of the red sub-pixel is 1.707fF.
[0110] For example, by substituting the values in Tables 1 and 2 above into the model of the pixel circuit shown in Figure 2 for simulation experiments, the simulation curve shown in Figure 13 can be obtained; where S1 represents the simulation curve in the related technology, and S2 represents the simulation curve in the embodiment of the present invention; the horizontal axis represents the voltage value of VGMP, in volts (V); the vertical axis represents the current value IL of the light-emitting device, in amperes (A); when the current value IL of the light-emitting device is 1 PA, the voltage value of VGMP required for the pixel circuit on the array substrate in the related technology is 6.92V, and the voltage value of VGMP required for the pixel circuit on the array substrate in the embodiment of the present invention is 6.76V. It can be seen that the voltage value of VGMP required in the embodiment of the present invention is less than the voltage value of VGMP required in the related technology.
[0111] It should be noted that the VGMP voltage value is the maximum value of the data signal line voltage in the pixel circuit; the VGMP voltage value is provided by the chip IC, which provides VGMP to the data signal line in the pixel circuit.
[0112] In the embodiments of the present invention, the voltage value of VGMP required for the pixel circuit in the array substrate is relatively small, so the state difference of the driving transistor in the pixel circuit before and after charging is small, thereby improving the problem of image retention and significantly reducing display power consumption, that is, reducing the power consumption of the chip IC and improving the competitiveness of the product.
[0113] This disclosure provides other structural schematic diagrams of an array substrate, as shown in FIG14, which are modifications of the embodiments described above. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.
[0114] In some other embodiments of the present invention, as shown in FIG14, the orthogonal projection of the second conductive region N1-2 on the substrate 100 covers the orthogonal projection of the channel region of the second compensation transistor T1-2 on the substrate 100.
[0115] As shown in Figure 15, the area of the first conductive connection portion N1 in the third conductive layer 140 of the present invention is larger than that of the first conductive connection portion N1 in Figure 6. Furthermore, the spacing between the first conductive region N1-1 and the second conductive region N1-2 of the first conductive connection portion N1 in the present invention along the second direction F2 is larger than that between the first conductive region N1-1 and the second conductive region N1-2 of the first conductive connection portion N1 in Figure 6. This can further increase the overlap area of the first conductive connection portion and the first scanning signal line in the orthogonal projection on the substrate, that is, further increase the parasitic capacitance between the first conductive connection portion and the first scanning signal line, thereby further reducing the maximum value of the data voltage of the data signal line in the pixel circuit, thus improving the image retention problem more effectively and with lower power consumption.
[0116] Furthermore, in this embodiment of the invention, the orthogonal projection of the second conductive region onto the substrate covers the orthogonal projection of the channel region of the second compensation transistor onto the substrate, which can block the undesirable phenomenon of strong light emission caused by the sensitive characteristics of the second compensation transistor. In addition, the third conductive layer is closer to the second compensation transistor, so the blocking effect is better than that of using an anode blocking effect.
[0117] In some other embodiments of the present invention, as shown in FIG15, the spacing of the third conductive region N1-3 along the second direction F2 is smaller than the spacing of the second conductive region N1-2 along the second direction F2.
[0118] In an embodiment of the present invention, as shown in FIG16, the orthographic projection of the anode 150-1 on the substrate 100 overlaps with the orthographic projection of the second compensation transistor T1-2 on the substrate 100.
[0119] Since the second conductive area in the first conductive connection portion of the present invention can block the second compensation transistor, when designing the pattern of the anode, it is not necessary to add a pattern to repeatedly block the second compensation transistor, thereby reducing the area of the anode, significantly reducing the proportion of metal, and improving the transmittance of the display panel.
[0120] For example, the anode in this embodiment of the invention is shown in FIG17. The anode shown in FIG17 has a smaller area than the anode shown in FIG11. This reduces the amount of metal material occupied by the anode, thereby increasing the transmittance of the display panel and further improving the display effect.
[0121] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the array substrate described above in the embodiments of the present invention. The principle by which this display device solves the problem is similar to that of the aforementioned array substrate; therefore, the implementation of this display device can refer to the implementation of the aforementioned array substrate, and the repeated parts will not be described again here.
[0122] In specific implementations, in the embodiments of the present invention, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present invention.
[0123] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0124] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.
Claims
1. An array substrate, wherein, include: Substrate and pixel circuitry disposed on the substrate; The pixel circuit includes a driving transistor and a compensation transistor; the gate of the compensation transistor is coupled to a first scan signal line, the first electrode of the compensation transistor is coupled to the gate of the driving transistor through a first conductive connection portion, and the second electrode of the compensation transistor is coupled to the second electrode of the driving transistor. The first conductive connection portion extends along a first direction, and the first scan signal line extends along a second direction; the first conductive connection portion has a first conductive area, and the orthographic projection of the first conductive area on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate. The spacing of the first conductive area along the second direction is greater than the spacing of the areas in the first conductive connection portion other than the first conductive area along the second direction.
2. The array substrate as claimed in claim 1, wherein, The first overlapping region is the area where the first conductive region and the first scanning signal line overlap in the orthographic projection of the substrate. The spacing of the first overlapping regions along the first direction is smaller than the spacing of the first conductive regions along the first direction.
3. The array substrate as described in claim 2, wherein, Also includes: The compensation transistor includes: a first compensation transistor and a second compensation transistor connected in series; The first scan signal line extending along the second direction overlaps with the orthographic projection of the active layer of the first compensation transistor onto the substrate. The first scan signal line has a first branch protruding along the first direction, and the first branch overlaps with the orthographic projection of the active layer of the second compensation transistor onto the substrate.
4. The array substrate as claimed in claim 3, wherein, The first conductive connection portion further includes: a second conductive region; The second conductive region is coupled to the first electrode of the second compensation transistor through the first via, and the orthographic projection of the second conductive region on the substrate covers the orthographic projection of the first via on the substrate.
5. The array substrate as claimed in claim 4, wherein, The spacing of the second conductive area along the first direction is greater than the spacing of the first via along the first direction.
6. The array substrate as claimed in claim 4, wherein, The spacing of the second conductive area along the second direction is equal to the spacing of the first via along the second direction; The spacing of the second conductive region along the second direction is smaller than the spacing of the first conductive region along the second direction.
7. The array substrate as claimed in claim 4, wherein, The orthographic projection of the second conductive region onto the substrate does not overlap with the orthographic projection of the first scan signal line onto the substrate.
8. The array substrate as claimed in claim 4, wherein, The orthographic projection of the second conductive region onto the substrate covers the orthographic projection of the channel region of the second compensation transistor onto the substrate.
9. The array substrate according to any one of claims 3-8, wherein, Also includes: Anode, which is coupled to the second terminal of the driving transistor; The orthographic projection of the anode onto the substrate at least partially overlaps with the orthographic projection of the first compensation transistor onto the substrate.
10. The array substrate as claimed in claim 9, wherein, The orthographic projection of the anode onto the substrate overlaps with the orthographic projection portion of at least one of the second compensation transistors onto the substrate.
11. The array substrate as claimed in claim 9, wherein, The orthogonal projection of the anode onto the substrate covers the orthogonal projection of at least one of the second compensation transistors onto the substrate.
12. The array substrate as claimed in claim 9, wherein, The pixel circuit includes: an adjacent first pixel circuit and a second pixel circuit; the first pixel circuit is electrically connected to the anode. The orthographic projection of the anode onto the substrate at least partially overlaps with the first conductive connection portion in the first pixel circuit; The orthographic projection of the anode onto the substrate at least partially overlaps with the first conductive connection in the second pixel circuit.
13. The array substrate according to any one of claims 10-12, wherein, The first conductive connection portion further includes: a third conductive region, wherein the first conductive region is located between the second conductive region and the third conductive region; The third conductive region is coupled to the gate of the driving transistor through the second via, and the orthographic projection of the third conductive region on the substrate overlaps with the orthographic projection of the second via on the substrate.
14. The array substrate as claimed in claim 13, wherein, The spacing of the third conductive region along the second direction is smaller than the spacing of the second conductive region along the second direction.
15. The array substrate according to any one of claims 10-12, wherein, The first conductive connection portion further includes: a fourth conductive region, the fourth conductive region being located between the third conductive region and the first conductive region; The spacing of the fourth conductive region along the second direction is smaller than the spacing of the third conductive region along the second direction.
16. The array substrate according to any one of claims 10-12, wherein, The first conductive region in the first conductive connection portion protrudes in a direction away from the first compensation transistor.
17. The array substrate as claimed in claim 16, wherein, The orthogonal projection of the anode onto the substrate covers at least one third conductive region in the first conductive connection portion; The orthographic projection of the anode onto the substrate overlaps with the orthographic projection portions of the first conductive region, the second conductive region, and the fourth conductive region in at least one of the first conductive connections onto the substrate.
18. The array substrate as claimed in claim 16, wherein, The first pixel circuit and the second pixel circuit are set up in a mirror-symmetric manner.
19. The array substrate as claimed in claim 16, wherein, The pixel circuit further includes a first initialization signal line; the first initialization signal line extends along the second direction; The first initialization signal line and the first scan signal line are spaced apart along the first direction; The protruding area in the first conductive region does not overlap with the orthographic projection of the first initialization signal line onto the substrate.
20. A display device, wherein, Includes the array substrate as described in any one of claims 1-19.