Light detection device

Abstract

Provided is a light detection device comprising: a photoelectric conversion element that is disposed on a first substrate and that converts light into an electric charge; and a pixel circuit that converts the electric charge into a pixel signal. The pixel circuit: is disposed on a second substrate on which the first substrate is laminated; is electrically connected to the photoelectric conversion element; and is configured to include a transistor having three terminals disposed on a first surface side of the second substrate. A first wiring is disposed on a second surface side of the second substrate facing the first surface, and at least one of the three terminals of the transistor is electrically connected to the first wiring via a first through wiring penetrating at least a part of the second substrate in the thickness direction.

Description

Light detection device

[0001] This disclosure relates to a photodetector.

[0002] Patent Document 1 discloses a solid-state imaging device. In this solid-state imaging device, the first substrate, second substrate, and third substrate are sequentially bonded together and stacked. The first substrate comprises a first semiconductor substrate on which pixel portions with arranged pixels are formed, and a first multilayer wiring layer stacked on this first semiconductor substrate. The second substrate comprises a second semiconductor substrate on which circuits are formed, and a second multilayer wiring layer stacked on this second semiconductor substrate. The third substrate comprises a third semiconductor substrate on which circuits are formed, and a third multilayer wiring layer stacked on this third semiconductor substrate.

[0003] Here, the first substrate is bonded to the second substrate with the electrodes of the uppermost layer of the first multilayer wiring layer in direct contact with the electrodes of the uppermost layer of the second multilayer wiring layer. The third substrate is bonded to the second substrate with the third multilayer wiring layer in contact with the second semiconductor substrate.

[0004] Japanese Patent Publication No. 2023-57137

[0005] In the above-described solid-state imaging device, electrodes, wiring, circuits, etc., are concentrated on the first substrate side of the second substrate. Therefore, the layout of electrodes, wiring, and circuits is constrained, and there has been a need for the development of an optical detection device that can overcome these design rule constraints.

[0006] Furthermore, as the electrode size increases, the parasitic capacitance added to the floating diffusion also increases. Therefore, there has been a need for the development of a photodetector that can effectively reduce parasitic capacitance and improve photoelectric conversion efficiency.

[0007] A photodetector according to a first embodiment of the present disclosure comprises a photoelectric conversion element disposed on a first substrate that converts light into electric charge, and a pixel circuit that converts electric charge into a pixel signal. The pixel circuit is disposed on a second substrate on which the first substrate is stacked, and the pixel circuit is electrically connected to the photoelectric conversion element. The pixel circuit includes a transistor having three terminals disposed on the first surface side of the second substrate, and a first wiring is disposed on the second surface side of the second substrate facing the first surface. At least one of the three terminals of the transistor is electrically connected to the first wiring through a first through-wiring that penetrates at least a portion of the second substrate in the thickness direction.

[0008] In the photodetector according to the second embodiment of the present disclosure, the second substrate is configured to include at least a semiconductor layer, and an insulator thicker than the thickness of the gate insulating film of the transistor is disposed between the first through-wiring and the semiconductor layer.

[0009] In the photodetector according to the third embodiment of the present disclosure, the photodetector according to the first embodiment further comprises a second wiring arranged on the first surface side of the second substrate and electrically connected to one of the three terminals of the transistor, wherein the first wiring is electrically connected to the transistor through the first through wiring and the second wiring.

[0010] In the photodetector according to the fourth embodiment of the present disclosure, in the photodetector according to the third embodiment, the pixel circuit is constructed to include an amplification transistor, a reset transistor and a selection transistor, or further to include a floating diffusion conversion gain switching transistor, and the second wiring is a shared wiring that electrically connects the amplification transistor and the reset transistor.

[0011] In the photodetector according to the fifth embodiment of the present disclosure, in the photodetector according to the third embodiment, the pixel circuit is constructed to include an amplification transistor, a reset transistor and a selection transistor, or further to include a floating diffusion conversion gain switching transistor, and the second wiring is a lead wire drawn out from the selection transistor and electrically connecting the selection transistor and the vertical signal line.

[0012] In the photodetector according to the sixth embodiment of the present disclosure, the photodetector according to the third embodiment further comprises a capacitive element in which a first through-wiring electrically connected to the reset transistor or the floating diffusion conversion gain switching transistor through a second wiring is used as the first electrode, a dielectric is interposed in the first through-wiring, and a second through-wiring penetrating the second substrate in the thickness direction is used as the second electrode.

[0013] The photodetector according to the seventh embodiment of the present disclosure comprises a photoelectric conversion element disposed on a first substrate and converting light into electric charge, and a pixel circuit disposed on a second substrate on which the first substrate is stacked and electrically connected to the photoelectric conversion element and converting electric charge into a pixel signal, wherein the second substrate is composed of a semiconductor layer, and the pixel circuit is composed of a transistor disposed on the semiconductor layer on the first surface side of the second substrate facing the first substrate, and on the second surface side of the second substrate facing the first surface, a contact region having the same conductivity type as the semiconductor layer and a higher impurity density than the semiconductor layer is disposed on the semiconductor layer, and a first power supply wiring electrically connected to the semiconductor layer through the contact region is disposed on the second surface side of the second substrate.

[0014] A photodetector according to the eighth embodiment of the present disclosure comprises a first substrate including a first semiconductor layer having a photoelectric conversion element and a floating diffusion region; a second substrate including a second semiconductor layer, which is stacked with the first substrate such that the surface of the first semiconductor layer faces the back surface of the second semiconductor layer opposite to the first surface; a first transistor having a first gate electrode provided on the side of the second semiconductor layer opposite to the first surface; a second transistor having a second gate electrode provided on the first surface side of the second semiconductor layer; and wiring connected between the floating diffusion region and the first gate electrode.

[0015] Figure 1 is a schematic system diagram of a photodetector according to the first-first embodiment of this disclosure. Figure 2 is a schematic exploded plan view of the photodetector shown in Figure 1. Figure 3 is a circuit diagram of the pixels and pixel circuits of the photodetector shown in Figure 1. Figure 4 is a schematic cross-sectional view of the stacked state of the first substrate having pixels, the second substrate having pixel circuits, and the third substrate having logic circuits of the photodetector shown in Figure 1. Figure 5 is an enlarged cross-sectional view of the second substrate of the photodetector shown in Figure 4 (a cross-sectional view including the portion cut along the A-A cutting line shown in Figure 6). Figure 6 is a plan view of the main part of the pixel circuit of the photodetector shown in Figure 5. Figure 7 is a perspective view of the transistors that make up the pixel circuit shown in Figure 6. Figure 8 is a further enlarged cross-sectional view of the main part of the pixel circuit shown in Figure 6 (a cross-sectional view cut along the A-A cutting line shown in Figure 6). Figure 9 is a first process cross-sectional view illustrating the manufacturing method of the photodetector according to the first-first embodiment. Figure 10 is a second process cross-sectional view. Figure 11 is a cross-sectional view of the third process. Figure 12 is a cross-sectional view of the fourth process. Figure 13 is a cross-sectional view of the fifth process. Figure 14 is a cross-sectional view of the sixth process. Figure 15 is a cross-sectional view of the seventh process. Figure 16 is a plan view of the main part of the pixel circuit of the photodetector according to the first-second embodiment of the present disclosure, corresponding to Figure 6. Figure 17 is a plan view of the main part of the pixel circuit of the photodetector according to the first-third embodiment of the present disclosure, corresponding to Figure 6. Figure 18 is a cross-sectional view of the main part of the photodetector according to the first-fourth embodiment of the present disclosure, corresponding to Figure 8, which is an enlarged view of the main part of the photodetector. Figure 19 is a cross-sectional view of the main part of the photodetector according to the first-fifth embodiment of the present disclosure, corresponding to Figure 8, which is an enlarged view of the main part of the photodetector. Figure 20 is a cross-sectional view of the main part of the photodetector according to the first-sixth embodiment of the present disclosure, corresponding to Figure 5, which is an enlarged view of the main part of the photodetector. Figure 21 is a plan view of the main part of the pixel circuit of the photodetector shown in Figure 20. Figure 22 is a cross-sectional view corresponding to Figure 8, which is an enlarged view of the main part of the pixel circuit shown in Figure 20 (a cross-sectional view cut along the B-B cutting line shown in Figure 21). Figure 23 is a cross-sectional view corresponding to Figure 5, which is an enlarged view of the main part of the light detection device according to the first to seventh embodiments of this disclosure. Figure 24 is a circuit diagram of the pixel circuit shown in Figure 23.Figure 25 is a cross-sectional view corresponding to Figure 5, showing an enlarged view of the main part of the photodetector according to the first to eighth embodiments of this disclosure. Figure 26 is a cross-sectional view corresponding to Figure 5, showing an enlarged view of the main part of the photodetector according to the first to ninth embodiments of this disclosure. Figure 27 is a plan view of the main part of the pixel circuit of the photodetector shown in Figure 26. Figure 28 is a cross-sectional view corresponding to Figure 8, showing an enlarged view of the main part of the pixel circuit shown in Figure 26 (a cross-sectional view cut along the C-C cutting line shown in Figure 27). Figure 29 is a cross-sectional view corresponding to Figure 5, showing an enlarged view of the main part of the photodetector according to the first to tenth embodiments of this disclosure. Figure 30 is a plan view of the main part of the pixel circuit of the photodetector shown in Figure 29. Figure 31 is a cross-sectional view corresponding to Figure 8, showing an enlarged view of the main part of the pixel circuit shown in Figure 30 (a cross-sectional view cut along the D-D cutting line shown in Figure 30). Figure 32 is an enlarged cross-sectional view of the main part of the pixel circuit of a photodetector according to a modified example of the first to tenth embodiments (corresponding to the cross-sectional view cut along the E-E cutting line shown in Figure 30). Figure 33 is a circuit diagram of the pixels and pixel circuit of a photodetector according to the second to first embodiment of the present disclosure, corresponding to Figure 3. Figure 34 is a plan view of the main part of the pixel circuit of the photodetector shown in Figure 33, corresponding to Figure 6. Figure 35 is an enlarged cross-sectional view of the main part of the pixel circuit shown in Figure 34, corresponding to Figure 8 (a cross-sectional view cut along the F-F cutting line shown in Figure 34). Figure 36 is a plan view of the main part of the pixel circuit of the photodetector shown in Figure 34, viewed from the back side. Figure 37 is a plan view of the main part of the pixel circuit of a photodetector according to the second to second embodiment of the present disclosure, corresponding to Figure 6. Figure 38 is an enlarged cross-sectional view of the main part of the pixel circuit shown in Figure 37, corresponding to Figure 8 (a cross-sectional view cut along the G-G cutting line shown in Figure 37). Figure 39 is a plan view of the main part of the pixel circuit of the light detection device shown in Figure 37, viewed from the back side. Figure 40 is a plan view of the main part of the pixel circuit of the light detection device according to the second to third embodiments of the present disclosure, corresponding to Figure 6. Figure 41 is an enlarged cross-sectional view of the main part of the pixel circuit shown in Figure 40, corresponding to Figure 8 (a cross-sectional view cut along the H-H cutting line shown in Figure 40). Figure 42 is an enlarged cross-sectional view of the main part of the pixel circuit shown in Figure 40 (a cross-sectional view cut along the I-I cutting line shown in Figure 40).Figure 43 is a plan view of the main components of the pixel circuit of the photodetector shown in Figure 40, viewed from the back side. Figure 44 is a schematic longitudinal cross-sectional view of the entire photodetector, comprising a second substrate having the pixel circuit shown in Figure 40, a first substrate having pixels, and a third substrate having a logic circuit. Figure 45 is a schematic plan view of the entire photodetector, including the pixel region (pixel array), according to the second-fourth embodiment of this disclosure. Figure 46 is a schematic longitudinal cross-sectional view of the entire photodetector, corresponding to Figure 44 (a cross-sectional view cut along the J-J cutting line shown in Figure 45), according to the photodetector shown in Figure 45. Figure 47 is a plan view of the main components of the pixel circuit of the photodetector, corresponding to Figure 6, according to the second-fifth embodiment of this disclosure. Figure 48 is a cross-sectional view corresponding to Figure 8, which is an enlarged view of the main components of the pixel circuit shown in Figure 47 (a cross-sectional view cut along the K-K cutting line shown in Figure 47). Figure 49 is a plan view of the main components of the pixel circuit of the photodetector, shown in Figure 47, viewed from the back side. Figure 50 is a plan view of the main part of the pixel circuit of a photodetector according to the second-sixth embodiment of the present disclosure, corresponding to Figure 6. Figure 51 is a cross-sectional view corresponding to Figure 8, which is an enlarged view of the main part of the pixel circuit shown in Figure 50 (a cross-sectional view cut along the L-L cutting line shown in Figure 50). Figure 52 is a cross-sectional view corresponding to Figure 8, which is an enlarged view of the main part of a photodetector according to the second-seventh embodiment of the present disclosure. Figure 53 is a plan view of the connection portion between the electrode connected to the pixel shown in Figure 52 and the electrode connected to the pixel circuit. Figure 54 is a plan view of the main part of the pixel circuit of a photodetector according to the second-eighth embodiment of the present disclosure, corresponding to Figure 6. Figure 55 is a cross-sectional view corresponding to Figure 8, which is an enlarged view of the main part of the pixel circuit shown in Figure 54 (a cross-sectional view cut along the M-M cutting line shown in Figure 54). Figure 56 is a cross-sectional view corresponding to Figure 8, which is an enlarged view of the main part of the pixel circuit shown in Figure 54 (a cross-sectional view cut along the N-N cutting line shown in Figure 54). Figure 57 is a cross-sectional diagram corresponding to Figure 8, which is an enlarged view of the main part of the pixel circuit shown in Figure 54 (a cross-sectional view cut along the O-O cutting line shown in Figure 54). Figure 58 is a cross-sectional diagram corresponding to Figure 8, which is an enlarged view of the main part of the pixel circuit shown in Figure 54 (a cross-sectional view cut along the P-P cutting line shown in Figure 54).Figure 59 is a schematic cross-sectional view corresponding to Figure 4 of a photodetector according to the third-first embodiment of this disclosure. Figure 60 is a plan view of the main part of the pixel circuit shown in Figure 59, corresponding to Figure 6. Figure 61 is a cross-sectional view illustrating one step of the manufacturing method of the photodetector shown in Figure 59. Figure 62 is a cross-sectional view illustrating one step of the manufacturing method of a photodetector according to the third-second embodiment of this disclosure. Figure 63 is a schematic cross-sectional view corresponding to Figure 59 of a photodetector according to the third-third embodiment of this disclosure. Figure 64 is a schematic cross-sectional view corresponding to Figure 59 of a photodetector according to the third-fourth embodiment of this disclosure. Figure 65 is a schematic cross-sectional view corresponding to Figure 59 of a photodetector according to the third-fifth embodiment of this disclosure. Figure 66 is a schematic cross-sectional view corresponding to Figure 59 of a photodetector according to the third-sixth embodiment of this disclosure. Figure 67 is a schematic cross-sectional view corresponding to Figure 59 of a photodetector according to the third-seventh embodiment of this disclosure. Figure 68 is a schematic cross-sectional diagram corresponding to Figure 59 of a photodetector according to the third to eighth embodiment of the present disclosure. Figure 69 is a diagram showing an example of a schematic cross-sectional configuration of a photodetector according to the fourth embodiment of the present disclosure. Figure 70 is a diagram showing an example of an enlarged cross-sectional configuration of the second substrate of the photodetector according to the fourth embodiment of the present disclosure. Figure 70 is a diagram showing an example of a planar configuration of a part of the pixel circuit of the photodetector according to the fourth embodiment of the present disclosure. Figure 72A is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure. Figure 72B is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure. Figure 72C is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure. Figure 72D is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure. Figure 72E is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure. Figure 72F is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure. Figure 72G is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of the present disclosure. Figure 72H is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of this disclosure.Figure 72I is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of this disclosure. Figure 72J is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of this disclosure. Figure 72K is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of this disclosure. Figure 72L is a diagram illustrating an example of a method for manufacturing a photodetector according to the fourth embodiment of this disclosure. Figure 73 is a diagram showing an example of an enlarged cross-sectional configuration of the second substrate of a photodetector according to Modification 1 of the fourth embodiment of this disclosure. Figure 74 is a diagram showing an example of a planar configuration of a part of the pixel circuit of a photodetector according to Modification 1 of the fourth embodiment of this disclosure. Figure 75 is a diagram showing an example of an enlarged cross-sectional configuration of the second substrate of a photodetector according to Modification 2 of the fourth embodiment of this disclosure. Figure 76 is a diagram showing an example of a planar configuration of a part of the pixel circuit of a photodetector according to Modification 2 of the fourth embodiment of this disclosure. Figure 77 is a diagram showing an example of an enlarged cross-sectional configuration of the second substrate of a photodetector according to Modification 3 of the fourth embodiment of this disclosure. Figure 78 is a diagram showing an example of a planar configuration of a part of the pixel circuit of a photodetector according to Modification 3 of the fourth embodiment of this disclosure. Figure 79 is a diagram showing an example of an enlarged cross-sectional configuration of the second base of a photodetector according to Modification 4 of the fourth embodiment of this disclosure. Figure 80 is a diagram showing an example of a planar configuration of a part of the pixel circuit of a photodetector according to Modification 4 of the fourth embodiment of this disclosure. Figure 81 is a diagram showing another example of an enlarged cross-sectional configuration of the second base of a photodetector according to Modification 4 of the fourth embodiment of this disclosure. Figure 82 is a diagram showing another example of a planar configuration of a part of the pixel circuit of a photodetector according to Modification 4 of the fourth embodiment of this disclosure. Figure 83 is a diagram showing an example of an enlarged cross-sectional configuration of the second base of a photodetector according to Modification 5 of the fourth embodiment of this disclosure. Figure 84 is a diagram showing an example of a planar configuration of a part of the pixel circuit of a photodetector according to Modification 5 of the fourth embodiment of this disclosure. Figure 85 is a diagram showing an example of an enlarged cross-sectional configuration of the second base of a photodetector according to Modification 6 of the fourth embodiment of this disclosure. Figure 86 is a diagram showing an example of a planar configuration of a part of the pixel circuit of a photodetector according to Modification 6 of the fourth embodiment of this disclosure. Figure 87 is a block diagram showing an example of a schematic configuration of a vehicle control system.Figure 88 is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit. Figure 89 is a block diagram showing an example of a schematic configuration of the internal body information acquisition system.

[0016] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 1. Embodiment 1-1 Embodiment 1-1 describes a first example in which the present technology is applied to a photodetector. In this technology, the photodetector is constructed by a solid-state imaging device, or equipped with a solid-state imaging device. Embodiment 1-1 describes the overall configuration of the photodetector, the configuration of the pixels, and the configuration of the pixel circuit. Furthermore, Embodiment 1 describes a method for manufacturing the photodetector. 2. Embodiment 1-2 Embodiment 1-2 describes a second example in which the connection structure between the transistors and wiring that constitute the pixel circuit is changed in the photodetector according to Embodiment 1-1. 3. Embodiment 1-3 Embodiment 1-3 describes a third example in which the connection structure between the transistors and wiring that constitute the pixel circuit is changed in the photodetector according to Embodiment 1-1. 4. Embodiment 1-4 Embodiment 1-4 describes a fourth example in which the connection structure between the transistors and wiring that constitute the pixel circuit is changed in the photodetector according to Embodiment 1-1. 5. 1. Embodiment 1-5 Embodiment 1-5 describes a fifth example in which the connection structure between the transistors and wiring that constitute the pixel circuit is changed in the photodetector according to Embodiment 1-1. 6. Embodiment 1-6 Embodiment 1-6 describes a sixth example in which the structure of the element isolation region of the transistors that constitute the pixel circuit is changed in the photodetector according to Embodiment 1-1. 7. Embodiment 1-7 Embodiment 1-7 describes a seventh example in which the connection structure between the transistors and wiring that constitute the pixel circuit is changed in the photodetector according to Embodiment 1-1. 8. Embodiment 1-8 Embodiment 1-8 describes an eighth example in which the connection structure between the transistors and wiring that constitute the pixel circuit is changed in the photodetector according to Embodiment 1-1. 9. Embodiment 1-9 Embodiment 1-9 describes a ninth example in which the structure of the transistors that constitute the pixel circuit is changed in the photodetector according to Embodiment 1-6. 10. Embodiment 1-10 Embodiment 1-10 describes a tenth example that combines the photodetector according to Embodiment 1-8 and the photodetector according to Embodiment 1-9.

[0017] 11. Embodiment 2-1 Embodiment 2-1 describes an eleventh example in which the connection structure between the transistors and wiring that make up the pixel circuit is changed in the photodetector according to Embodiment 1-7. Embodiment 2-1 changes the configuration of the pixel circuit. 12. Embodiment 2-2 Embodiment 2-2 describes a twelfth example in which the connection structure between the transistors and wiring that make up the pixel circuit is changed in the photodetector according to Embodiment 2-1. 13. Embodiment 2-3 Embodiment 2-3 describes a thirteenth example in which the connection structure between the transistors and wiring that make up the pixel circuit is changed in the photodetector according to Embodiment 2-1. 14. Embodiment 2-4 Embodiment 2-4 describes a fourteenth example in which the wiring structure is changed in the photodetector according to Embodiment 2-1. 15. Embodiment 2-5 Embodiment 2-5 describes a fifteenth example in which the connection structure between the transistors and wiring that make up the pixel circuit is changed in the photodetector according to Embodiment 2-1. 16. 17. Embodiment 2-6 Embodiment 2-6 describes a 16th example in which the connection structure between the transistors and wiring that make up the pixel circuit is changed in the photodetector according to Embodiment 2-1. 18. Embodiment 2-7 Embodiment 2-7 describes a 17th example in which the connection structure between the photoelectric conversion element and the transistors that make up the pixel circuit is changed in the photodetector according to Embodiment 2-1. 19. Embodiment 2-8 Embodiment 2-8 describes a 18th example in which the connection structure between the transistors and wiring that make up the pixel circuit is changed in the photodetector according to Embodiment 2-1. Here, an example of constructing a capacitive element using the connection structure is described.

[0018] 19. Embodiment 3-1 Embodiment 3-1 is the 19th example describing the connection structure between the semiconductor layer and the wiring that constitutes the pixel circuit in any of the optical detection devices according to Embodiments 1-1 to 2-8. 20. Embodiment 3-2 Embodiment 3-2 describes the 20th example in which the manufacturing method of the contact region disposed on the semiconductor layer is changed in the optical detection device according to Embodiment 3-1. 21. Embodiment 3-3 Embodiment 3-3 describes the 21st example in which the connection structure between the semiconductor layer and the wiring that supplies potential to the semiconductor layer is changed in the optical detection device according to Embodiment 3-1. 22. Embodiment 3-4 Embodiment 3-4 describes the 22nd example in which the connection structure between the semiconductor layer and the wiring that supplies potential to the semiconductor layer is changed in the optical detection device according to Embodiment 3-1. 23. Embodiment 3-5 Embodiment 3-5 describes the 23rd example in which the connection structure between the semiconductor layer and the wiring that supplies potential to the semiconductor layer is changed in the optical detection device according to Embodiment 3-4. 24. 3-6 Embodiment The 3-6 embodiment describes a 24th example in which the photodetector according to the 3-1 embodiment and the photodetector according to the 3-4 embodiment are combined. 25. 3-7 Embodiment The 3-7 embodiment describes a 25th example in which the connection structure between the semiconductor layer and the wiring that supplies potential to the semiconductor layer is changed in the photodetector according to the 3-1 embodiment. 26. 3-8 Embodiment The 3-8 embodiment describes a 26th example in which the connection structure between the semiconductor layer and the wiring that supplies potential to the semiconductor layer is changed in the photodetector according to the 3-1 embodiment.

[0019] 27. Fourth Embodiment

[0020] 28. Application Examples to Mobile Devices This application example describes an example of applying this technology to a vehicle control system, which is an example of a mobile device control system. 29. Application to Internal Body Information Acquisition Systems This application example describes an example of applying this technology to an internal body information acquisition system. 30. Other Embodiments

[0021] <1. First-First Embodiment> The photodetector 1 and the method for manufacturing the photodetector 1 according to the first-first embodiment of the present disclosure will be explained with reference to Figures 1 to 15.

[0022] Here, the arrow X direction shown as appropriate in the figure indicates one planar direction of the light detection device 1 placed on a plane for convenience. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. The arrow Z direction indicates the upward direction, perpendicular to both the arrow X and arrow Y directions. In other words, the arrow X, arrow Y, and arrow Z directions coincide exactly with the X-axis, Y-axis, and Z-axis directions of the three-dimensional coordinate system, respectively. Note that these directions are shown for convenience to aid in understanding the explanation and do not limit the directions of this technology.

[0023] [Configuration of Photodetection Device 1] (1) Overall Configuration Diagram 1 of the photodetection device 1 shows an example of the system configuration of the photodetection device 1 according to the first embodiment. The photodetection device 1 is constructed by a solid-state imaging device, or equipped with a solid-state imaging device. In this case, the photodetection device 1 is constructed as a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device. In the solid-state imaging device, light L (see Figure 4) incident from the outside is detected, and this detected light L is converted into an electric charge, and image information such as still images or moving images is generated based on the converted electric charge.

[0024] The light detection device 1 comprises a pixel region 100 having a plurality of pixels 10 arranged regularly in two dimensions within a plane in the directions of arrows X and Y, and peripheral circuits arranged around the pixel region 100. The pixel region 100 is a pixel array.

[0025] As will be explained later, the pixel 10 includes a photoelectric conversion element PD (see Figure 3) and a transfer transistor TR (see Figure 3). The photoelectric conversion element PD is composed of, for example, a photodiode. The photoelectric conversion element PD converts light L into electric charge. The transfer transistor TR transfers the charge converted by the photoelectric conversion element PD. A pixel circuit 20 (see Figure 3) is also electrically connected to the pixel 10. The pixel circuit 20 reads the charge converted in the pixel 10 and generates a pixel signal (image information).

[0026] The peripheral circuitry is constructed with a vertical drive circuit VD, a column signal processing circuit CS, a horizontal drive circuit HD, an output circuit Out, a control circuit CC, and the like.

[0027] The control circuit CC receives the input clock and data that commands the operating mode, etc., and outputs data such as internal information of the light detection device 1. In other words, the control circuit CC generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. These signals are then input to the vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, etc.

[0028] The vertical drive circuit VD is composed of, for example, a shift register. The vertical drive circuit VD selects a pixel drive wiring Ld and supplies pulses to the selected pixel drive wiring Ld to drive the pixel 10. The pixels 10 are driven row by row. That is, the vertical drive circuit VD sequentially selects and scans each pixel 10 of the pixel region 100 vertically row by row. The signal charge generated in the photoelectric conversion element PD of each pixel 10 according to the amount of light received is supplied to the column signal processing circuit CS as a pixel signal through the vertical signal line Lv.

[0029] The column signal processing circuit CS is arranged for each column of pixels 10, for example. In the column signal processing circuit CS, signal processing such as noise reduction is performed on the signal output from one row of pixels 10 for each pixel column. That is, the column signal processing circuit CS performs signal processing such as CDS (Correlated Double Sampling) to remove fixed pattern noise specific to the pixels 10, signal amplification, and AD (Analog Digital) conversion. A horizontal selection switch (not shown) is connected between the output stage of the column signal processing circuit CS and the horizontal signal line Lh.

[0030] The horizontal drive circuit HD is composed of, for example, a shift register. The horizontal drive circuit HD sequentially outputs horizontal scanning pulses, thereby sequentially selecting each of the column signal processing circuits CS, and outputting pixel signals from each of the column signal processing circuits CS to the horizontal signal line Lh.

[0031] The output circuit Out processes the signals sequentially supplied from each column signal processing circuit CS through the horizontal signal line Lh and outputs them. For example, the output circuit Out may perform only buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal In handles signal exchange between the light detection device 1 and the outside world.

[0032] (2) Diagram 2 of the device configuration of the photodetector 1 shows an example of a schematic exploded view of the photodetector 1 shown in Figure 1. The photodetector 1 has a three-layer structure in which the first substrate 1A, the second substrate 1B, and the third substrate 1C are stacked and bonded to each other. Here, the third substrate 1C, the second substrate 1B, and the first substrate 1A are stacked sequentially in the direction of arrow Z. In the first embodiment and subsequent embodiments, the photodetector 1 has a three-layer structure. The present disclosure is not limited to a three-layer structure, and for example, the photodetector 1 may be constructed with a two-layer structure in which the second substrate 1B and the third substrate 1C are made into a single substrate. Furthermore, in the present disclosure, the photodetector 1 may be constructed with a four-layer structure by adding a fourth substrate to the first substrate 1A, the second substrate 1B, and the third substrate 1C.

[0033] The first substrate 1A is formed in a rectangular shape when viewed from the direction of arrow Z or the direction opposite to arrow Z (hereinafter simply referred to as "in a plan view"). More specifically, the first substrate 1A is formed in a square shape. The first substrate 1A includes a semiconductor layer formed of, for example, single-crystal silicon. In this disclosure, the term semiconductor layer is used to include a semiconductor substrate cut from a semiconductor wafer and separated into individual pieces by a dicing process, and a well region formed by introducing specific impurities into this semiconductor substrate. The components of the semiconductor layer will be described in Figure 4 and subsequent figures.

[0034] The semiconductor layer of the first substrate 1A is provided with photoelectric conversion elements PD and transfer transistors TR (see Figure 3) for constructing pixels 10. A pixel region 100 is provided over substantially the entire area of ​​the first substrate 1A. As described above, multiple pixels 10 are arranged in the pixel region 100. In other words, the first substrate 1A constitutes a light detection surface that serves as an imaging surface for capturing images.

[0035] The semiconductor layer of the first substrate 1A further contains at least some of the pixel transistors (not shown) that constitute the pixel circuit 20. In the first embodiment, the transfer transistor TR among the pixel transistors is disposed on the first substrate 1A (see Figures 3 and 4).

[0036] The second substrate 1B is formed in a rectangular shape similar to that of the first substrate 1A in a plan view, and has a planar size similar to that of the first substrate 1A. The second substrate 1B, like the first substrate 1A, includes a semiconductor layer (see Figure 4, etc.) formed of, for example, single-crystal silicon.

[0037] Here, in the semiconductor layer of the second substrate 1B, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL for constructing the pixel circuit 20 are arranged. In addition to these pixel transistors, the pixel circuit 20 may be constructed to include a floating diffusion conversion gain switching transistor (hereinafter simply referred to as "FD conversion gain switching transistor") FDG (see FIG. 33). At least a part of the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL for constructing the pixel circuit 20 may be arranged on the first substrate 1A.

[0038] In particular, the number of arrangements is not limited, but in the first embodiment, one pixel circuit 20 is arranged for four pixels 10. The configuration of the plurality of pixel transistors for constructing the pixel circuit 20 will be described later. Also, on the second substrate 1B, a pixel driving wiring Ld that overlaps the pixel region 100 in plan view and extends the pixel region 100 in the arrow X direction and a vertical signal line Lv that extends in the arrow Y direction are arranged.

[0039] The third substrate 1C is formed in a rectangular shape similar to the first substrate 1A in plan view and has a plane size similar to the plane size of the first substrate 1A. The third substrate 1C includes a semiconductor layer formed of, for example, single crystal silicon, similar to the first substrate 1A (see FIG. 4). A peripheral circuit is arranged in the semiconductor layer of the third substrate 1C. As described above, the peripheral circuit includes a vertical drive circuit VD, a column signal processing circuit CS, a horizontal drive circuit HD, an output circuit Out, a control circuit CC, and the like.

[0040] In the first embodiment, each circuit of the peripheral circuit is a logic circuit. The logic circuit is constructed to include one or more semiconductor elements selected from transistors, capacitors, and resistors. At least a part of the logic circuit includes a CMOS circuit.

[0041] For the transistors that construct the aforementioned pixel circuit 20, logic circuit, etc., insulated gate field effect transistors (IGFET: Insulated Gate Field Effect Transistor) are used. IGFETs include MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) and MISFETs (Metal Insulator Semiconductor Field Effect Transistor). Therefore, the aforementioned CMOS circuit is one embodiment of the present disclosure, and the present disclosure includes CMIS (Complementary Metal Insulator Semiconductor) circuits.

[0042] (3) Circuit Configuration Diagram 3 of Pixel 10 and Pixel Circuit 20 shows an example of the circuit configuration of pixel 10 and pixel circuit 20 of the photodetection device 1. In the first embodiment, four pixels 10 are electrically connected to one pixel circuit 20, and the four pixels 10 share one pixel circuit 20. That is, the charges converted from light L in each of the four pixels 10 are read out in one pixel circuit 20.

[0043] Pixel 10 includes a photoelectric conversion element PD and a transfer transistor TR, and is composed of a series circuit of both. Specifically, the photoelectric conversion element PD is composed of a photodiode here. The photodiode includes an anode region and a cathode region. On the other hand, the transfer transistor TR is an IGFET. The IGFET includes a pair of main electrodes (source region and drain region) and a gate electrode.

[0044] The anode region of the photoelectric conversion element PD is electrically connected to the reference voltage GND. Also, the cathode region is electrically connected to one of the main electrodes of the transfer transistor TR. The other main electrode of the transfer transistor TR is electrically connected to one end of the floating diffusion FD. And a control signal for controlling conduction or non-conduction is input to the gate electrode.

[0045] As mentioned above, four pixels 10 are arranged in one pixel circuit 20. Therefore, each of the four pixels 10 is distinguished from the others by adding an identification number 1, 2, 3, or 4 to the end of the code of the components within the pixel 10. For example, one of the four pixels 10 is composed of a photoelectric conversion element PD1 and a transfer transistor TR1. In cases where there is no need to distinguish from each other, no identification number is assigned, and no further explanation is given.

[0046] The pixel circuit 20 is constructed from multiple pixel transistors. Here, the pixel transistor comprises a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. Each of the pixel transistors is composed of a lateral IGFET. The pixel transistor also has three terminals: a gate electrode and a pair of main electrodes (source region and drain region).

[0047] One main electrode of the reset transistor RST (e.g., the source region) is electrically connected to the other end of the floating diffusion FD, and the other main electrode is electrically connected to the power supply voltage VDD. A reset signal is input to the gate electrode. When the reset transistor RST becomes conductive, it resets the floating diffusion FD to a potential corresponding to the power supply voltage VDD.

[0048] One main electrode of the amplification transistor AMP is electrically connected to one main electrode of the selection transistor SEL, and the other main electrode is electrically connected to the power supply voltage VDD. The gate electrode is electrically connected to one main electrode of the reset transistor RST and the other end of the floating diffusion FD. The amplification transistor AMP constitutes a source follower type amplifier. In other words, the amplification transistor AMP generates a pixel signal (pixel information) corresponding to the charge transferred through the floating diffusion FD.

[0049] The other main electrode of the selection transistor SEL is electrically connected to the vertical signal line Lv. The selection signal is input to the gate electrode. The selection transistor SEL outputs the generated pixel signal to the vertical signal line Lv.

[0050] Furthermore, the pixel circuit 20 may include an FD conversion gain switching transistor FDG. In this case, one main electrode of the FD conversion gain switching transistor FDG is electrically connected to the floating diffusion FD, and the other main electrode is electrically connected to one main electrode (for example, the source region) of the reset transistor RST. For a detailed configuration, please refer to Figure 33. In addition, one pixel circuit 20 may be provided for two pixels 10, eight pixels 10, etc., and the charge from these pixels 10 may be read out by one pixel circuit 20.

[0051] (4) Device Configuration of Pixel 10 The following describes in detail each component of the light detection device 1. Figure 4 shows an example of a schematic cross-sectional configuration in the stacked state of the first substrate 1A having the pixel 10, the second substrate 1B having the pixel circuit 20, and the third substrate 1C having the logic circuit 60 of the light detection device 1. Figure 5 shows an example of an enlarged cross-sectional configuration of the second substrate 1B of the light detection device 1 shown in Figure 4. Figure 6 shows an example of a planar configuration of the main part of the pixel circuit 20 of the light detection device 1 shown in Figure 5. Figure 7 shows an example of a view of the pixel transistors that make up the pixel circuit 20 shown in Figure 6 from an oblique direction. Figure 8 shows an example of a further enlarged cross-sectional configuration of the main part of the pixel circuit 20 shown in Figure 6.

[0052] As described above, the light detection device 1 according to the first embodiment has a three-layer structure. The pixels 10 are disposed in the semiconductor layer 30 that forms the first substrate 1A which constructs the three-layer structure. The pixel circuit 20 is disposed in the semiconductor layer 40 that forms the second substrate 1B.

[0053] (4-1) As shown in the apparatus configuration diagram 4 of the first substrate 1A, the first substrate 1A comprises a semiconductor layer 30 having a first surface 30A in the direction of arrow Z and a second surface 30B facing the opposite direction of arrow Z, and a wiring layer 35 disposed on the second surface 30B side of the semiconductor layer 30. As mentioned above, the semiconductor layer 30 is made of a semiconductor substrate formed of, for example, single-crystal silicon.

[0054] As shown in Figures 1, 2, and 4 above, the pixel 10 is formed in a square shape in a plan view, for example, with sides of equal length in the X-direction and Y-direction. A pixel separation region 31 is provided around the side of the pixel 10. Note that the planar shape of the pixel 10 is not limited to a square. For example, the planar shape of the pixel 10 may be rectangular.

[0055] The pixel isolation region 31 is configured to surround at least the side of the photoelectric conversion element PD. The pixel isolation region 31 electrically and optically separates adjacent pixels 10. The pixel isolation region 31 is composed of a groove 311 and an embedded member 312. The groove 311 is formed by deeply excavating in the thickness direction of the semiconductor layer 30 from the first surface 30A toward the second surface 30B of the semiconductor layer 30.

[0056] Furthermore, the grooves 311 extend in the direction of arrow X and are arranged at regular intervals in the direction of arrow Y, and also extend in the direction of arrow Y and are arranged at regular intervals in the direction of arrow X. In other words, in a plan view, the grooves 311 are formed in a grid shape. The embedded members 312 are filled into the grooves 311. The embedded members 312 contain, for example, SiO2, which can separate optically and electrically adjacent pixels 10. ２ Insulating materials such as the above are used.

[0057] Each pixel 10 comprises a photoelectric conversion element PD and a transfer transistor TR. Figure 4 shows a unit pixel. That is, as shown in Figure 3 above, four pixels 10 electrically connected to one pixel circuit 20 are considered a unit pixel. The four pixels 10 consist of two pixels 10 arranged in the direction of arrow X and two pixels 10 arranged in the direction of arrow Y (not shown). These four pixels 10 are formed in a symmetrical shape with respect to a center line (not shown) passing between adjacent pixels 10.

[0058] (4-2) Apparatus configuration of the photoelectric conversion element PD The photoelectric conversion element PD is disposed inside the semiconductor layer 30 within a region surrounded by pixel separation regions 31 in the directions of arrows X and Y. Although a detailed diagram of the configuration is omitted, the photoelectric conversion element PD comprises a p-type semiconductor region as the anode region and an n-type semiconductor region as the cathode region. In addition, a pinning region (not shown) formed by a p-type semiconductor region with a high impurity density is disposed on the surface portion of the semiconductor layer 30 along the pixel separation region 31.

[0059] (4-3) Device configuration of the transfer transistor TR The transfer transistor TR is located within the pixel separation region 31 on the second surface 30B opposite to the direction of arrow Z from the photoelectric conversion element PD. The transfer transistor TR mainly comprises a channel formation region (not shown), a gate insulating film 321, a gate electrode 322, and a pair of main electrodes (source region and drain region).

[0060] In a transfer transistor TR, the gate insulating film 321 is disposed between the semiconductor layer 30 and the gate electrode 322. The gate insulating film 321 is made of, for example, SiO ２ It is formed from insulating materials such as the above. The gate electrode 322 is formed from a gate electrode material such as polycrystalline silicon. When polycrystalline silicon is used as the gate electrode material, impurities that reduce the resistance value are added to the polycrystalline silicon.

[0061] One of the pair of main electrodes is electrically connected to the cathode region of the photoelectric conversion element PD. In other words, the cathode region is used as one of the main electrodes of the transfer transistor TR. The other of the pair of main electrodes is electrically connected to an n-type semiconductor region 323. Here, the n-type semiconductor region 323 is arranged overlapping the pixel separation region 31 in a plan view and is shared as the main electrode of the transfer transistor TR of multiple adjacent pixels 10. The n-type semiconductor region 323 is also used as part of the floating diffusion FD.

[0062] (4-4) Device Configuration of Wiring Layer 35 The wiring layer 35 comprises wiring 351, plug wiring 352, electrodes 353, and an insulating layer 355. The wiring 351 is arranged in multiple layers by employing a multilayer wiring structure. The wiring 351 is formed of, for example, Cu or a metal material or metal alloy material mainly composed of Cu. The plug wiring 352 electrically connects the multiple layers of wiring 351. The plug wiring 352 is formed of, for example, a metal material or metal alloy material such as W, Co, or WSi. The electrodes 353 are electrically connected to the wiring 351 and are arranged in the uppermost layer of the wiring layer 35. The electrodes 353 are used for the electrical connection between the wiring 351 of the first substrate 1A and the wiring 451 of the second substrate 1B when the first substrate 1A and the second substrate 1B are bonded together and laminated. The electrode 353 is formed of, for example, a metallic material or metal alloy material with Cu or Cu as its main composition.

[0063] The insulating layer 355 is actually formed between multiple layers of wiring 351 and is made up of multiple layers of insulating film. The insulating film is made of, for example, SiO ２ It is formed from insulating materials such as the above.

[0064] (5) Device configuration of the pixel circuit 20 As shown in Figures 4 to 8, the pixel circuit 20 is arranged on the second substrate 1B. As described above, the pixel circuit 20 is constructed of a plurality of pixel transistors. That is, in the first embodiment, the pixel circuit 20 comprises an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL.

[0065] (5-1) Apparatus configuration of the second substrate 1B The second substrate 1B comprises a semiconductor layer 40 having a first surface 40A in the direction of arrow Z and a second surface 40B facing the opposite direction of arrow Z, a wiring layer 45 disposed on the first surface 40A side of the semiconductor layer 40, and a wiring layer 46 disposed on the second surface 40B side of the semiconductor layer 40. Similar to the semiconductor layer 30, a semiconductor substrate formed of, for example, single-crystal silicon is used for the semiconductor layer 40. The semiconductor layer 40 is formed in a p-type configuration here. The first surface 40A of the semiconductor layer 40 and the second surface 30B of the semiconductor layer 30 face each other, and the second substrate 1B is laminated by bonding the first substrate 1A to it.

[0066] (5-2) Device Configuration of Amplifier Transistor AMP As shown in Figures 4 to 6, the amplifier transistor AMP is arranged on the first surface 40A side of the semiconductor layer 40, surrounded by an element isolation region 41. Here, the element isolation region 41 electrically isolates adjacent pixel transistors. The element isolation region 41 is composed of a groove 411 and an embedded member 412. The groove 411 is formed by excavating in the thickness direction of the semiconductor layer 40 from the first surface 40A toward the second surface 40B of the semiconductor layer 40. The embedded member 412 is filled in the groove 411. The embedded member 412 contains, for example, SiO ２ Insulating materials such as the above are used. In the first embodiment, the element isolation region 41 is formed by an STI (Shallow Trench Isolation) structure.

[0067] The amplification transistor AMP comprises a channel formation region, a gate insulating film 421a, a gate electrode 422, and a pair of main electrodes 423 as its main components. Here, the gate insulating film 421a will be described simply as "gate insulating film 421" unless otherwise specified for other transistors. Also, in figures other than Figures 4 and 5, the gate insulating film 421a is simply denoted by the reference numeral "421". The channel formation region is formed on the first surface 40A side of the semiconductor layer 40, which is surrounded by the element isolation region 41. The gate insulating film 421 is formed on the first surface 40A of the semiconductor layer 40. The gate insulating film 421 is made of, for example, SiO ２It is formed from insulating materials such as the above. The gate electrode 422 is formed on the gate insulating film 421. The gate electrode 422 is formed from a gate electrode material such as polycrystalline silicon.

[0068] A pair of main electrodes 423 are arranged in the semiconductor layer 40 on both sides of the gate length direction of the gate electrode 422, with the gate electrode 422 at its center. This pair of main electrodes 423 is formed from n-type semiconductor regions. In other words, the amplification transistor AMP is composed of n-channel IGFETs. Although not indicated by symbols, sidewall spacers are formed on the side walls of the gate electrode 422 of the amplification transistor AMP.

[0069] (5-3) Device Configuration of Reset Transistor RST The reset transistor RST, like the amplification transistor AMP, is arranged on the first surface 40A side of the semiconductor layer 40, surrounded by an element isolation region 41. The reset transistor RST mainly comprises a channel formation region, a gate insulating film 421, a gate electrode 422, and a pair of main electrodes 423. The reset transistor RST is composed of an n-channel IGFET. The connection structure between the gate electrode 422 of the reset transistor RST and the electrodes (wiring) 463 of the wiring layer 46 will be described later.

[0070] (5-4) Device Configuration of the Selective Transistor SEL The selective transistor SEL, like the amplifying transistor AMP, is arranged on the first surface 40A side of the semiconductor layer 40, surrounded by an element isolation region 41. The selective transistor SEL mainly comprises a channel formation region, a gate insulating film 421s, a gate electrode 422, and a pair of main electrodes 423. The selective transistor SEL is composed of an n-channel IGFET. Here, the gate insulating film 421s will be described simply as "gate insulating film 421" in the same way as "gate insulating film 421a" unless it is specifically differentiated from transistors other than the selective transistor SEL. Also, in figures other than Figures 4 and 5, the gate insulating film 421s is simply denoted by the reference numeral "421".

[0071] (5-5) Device Configuration of Wiring Layer 45 As shown in Figures 4 and 5, the wiring layer 45, like the wiring layer 35, comprises wiring 451, plug wiring 452, electrodes 453, and an insulating layer 455. The wiring 451 is arranged in multiple layers by employing a multilayer wiring structure. The plug wiring 452 electrically connects the multiple layers of wiring 451. The electrodes 453 are electrically connected to the wiring 451 and are arranged in the uppermost layer of the wiring layer 45. The electrodes 453 are used for electrical connection between the wiring 351 of the first substrate 1A and the wiring 451 of the second substrate 1B when the first substrate 1A and the second substrate 1B are bonded together and laminated. Here, each of the electrodes 353 of the first substrate 1A and the electrodes 453 of the second substrate 1B is formed of, for example, Cu, and the connection structure between the electrodes 353 and the electrodes 453 is a Cu-Cu connection structure. The insulating layer 455 is actually formed between multiple layers of wiring 451 and is made up of multiple layers of insulating film.

[0072] In this first embodiment, except for the gate electrode 422 of the reset transistor RST, the gate electrodes 422 of the amplification transistor AMP and the selection transistor SEL, and the main electrodes 423 of the amplification transistor AMP, the reset transistor RST and the selection transistor SEL are electrically connected to the wiring 451 of the wiring layer 45.

[0073] (5-6) Device Configuration of Wiring Layer 46 As shown in Figures 4, 5, and 8, the wiring layer 46 comprises wiring 463, through-wiring 464, and an insulating layer 465. The wiring 463 is not particularly limited, but here it is formed by a single-layer wiring structure. Since the wiring 463 is formed in the uppermost layer of the wiring layer 46, it is also used as an "electrode" to electrically connect the second substrate 1B and the third substrate 1C when the second substrate 1B and the third substrate 1C are bonded together and laminated. The wiring 463 is formed of a metallic material or an alloy material, for example, similar to the electrode 453 described above. Here, the wiring 463 corresponds to the "first wiring" according to this disclosure.

[0074] The through-wiring 464 is arranged so as to partially penetrate the second substrate 1B in the thickness direction. This will be explained in detail. The through-wiring 464 is arranged with an insulator 43 interposed in a through-hole 42 that penetrates the entire semiconductor layer 40 in the thickness direction, and is further arranged so as to penetrate a part of the wiring layer 46. In the first embodiment, one end of the through-wiring 464 is electrically connected to the gate electrode 422 of the selection transistor SEL. The other end of the through-wiring 464 is electrically connected to the wiring 463. In other words, the gate electrode 422 of the selection transistor SEL is electrically connected to the wiring 463 through the through-wiring 464. The through-wiring 464 is formed of, for example, a metal material or a metal alloy material, similar to the plug wiring 452. Here, the through-wiring 464 corresponds to the "first through wiring" according to this disclosure.

[0075] The insulator 43 electrically separates the semiconductor layer 40 and the through-hole wiring 464 within the through-hole 42. The insulator 43 is made of, for example, SiO ２ It is formed from insulating materials such as the above. Here, the insulator 43 is formed to a thick tox1 for purposes such as improving the dielectric breakdown voltage between the semiconductor layer 40 and the through-wiring 464. For example, when the thickness tox2 of the gate insulating film 421 of the selected transistor SEL is formed to be between 2 nm and 10 nm, the thickness tox1 of the insulator 43 is formed to be equal to or greater than the thickness tox2 in order to maintain the dielectric breakdown voltage. For example, the thickness tox1 is formed to be between 2 nm and 200 nm.

[0076] (5-7) Connection structure between through-wiring 464 and selection transistor SEL As shown in Figures 4 to 8, in the first embodiment, the gate electrode 422 of the selection transistor SEL has an extension portion 422E that extends across the element isolation region 41 in the gate width direction intersecting the gate length direction from one main electrode 423 to the other main electrode 423. In other words, the element isolation region 41 is disposed between the channel formation region of the selection transistor SEL and the extension portion 422E. The extension portion 422E is formed integrally with the gate electrode 422. One end of the through-wiring 464 penetrates the gate insulating film 421 on the back surface side of the extension portion 422E on the second surface 40B side and is electrically connected to the extension portion 422E.

[0077] (6) As shown in the device configuration diagram 4 of the logic circuit 60, the logic circuit 60 that constructs the peripheral circuit is arranged on the third substrate 1C. The logic circuit 60 is equipped with a CMOS circuit (or CMIS circuit). That is, the logic circuit 60 is equipped with an n-channel IGFET Qn and a p-channel IGFET Qp.

[0078] (6-1) Apparatus configuration of the third substrate 1C The third substrate 1C comprises a semiconductor layer 50 having a first surface 50A in the direction of arrow Z and a second surface 50B facing the opposite direction of arrow Z, and a wiring layer 55 disposed on the first surface 50A side of the semiconductor layer 50. Similar to the semiconductor layer 30, the semiconductor layer 50 uses a semiconductor substrate made of, for example, single-crystal silicon. The semiconductor layer 50 is formed in a p-type configuration. Furthermore, an n-type well region 501 is disposed in the semiconductor layer 50 as a semiconductor layer. The third substrate 1C is laminated by bonding the second substrate 1B to the first surface 50A of the semiconductor layer 50 and the second surface 40B of the semiconductor layer 40 facing each other.

[0079] (6-2) Device configuration of n-channel IGFET Qn The n-channel IGFET Qn is arranged on the first surface 50A side of the semiconductor layer 50, surrounded by an element isolation region 51. Here, the element isolation region 51 electrically isolates adjacent n-channel IGFET Qn and p-channel IGFET Qp, etc. The element isolation region 51 is composed of a groove 511 and an embedded member 512. The groove 511 is formed by excavating in the thickness direction of the semiconductor layer 50 from the first surface 50A toward the second surface 50B of the semiconductor layer 50. The embedded member 512 is filled in the groove 511. The embedded member 512 contains, for example, SiO ２ Insulating materials such as the above are used. In the first embodiment, the element isolation region 51 is formed by an STI structure.

[0080] The n-channel IGFET Qn comprises a channel formation region, a gate insulating film 521, a gate electrode 522, and a pair of main electrodes 523 as its main components. The channel formation region is formed on the first surface 50A side of the semiconductor layer 50, which is surrounded by an element isolation region 51. The gate insulating film 521 is formed on the first surface 50A of the semiconductor layer 50. The gate insulating film 521 is made of, for example, SiO ２ It is formed from insulating materials such as the above. The gate electrode 522 is formed on the gate insulating film 521. The gate electrode 522 is formed from a gate electrode material such as polycrystalline silicon.

[0081] A pair of main electrodes 523 are arranged in the semiconductor layer 50 on both sides of the gate length direction of the gate electrode 522, with the gate electrode 522 at its center. This pair of main electrodes 523 is formed from n-type semiconductor regions. Although not indicated by reference numerals, sidewall spacers are formed on the side walls of the gate electrode 522 of the n-channel IGFET Qn.

[0082] (6-3) Device Structure of p-Channel IGFET Qp The p-channel IGFET Qp is disposed in the n-type well region 501 and includes a channel formation region, a gate insulating film 521, a gate electrode 522, and a pair of main electrodes 524 as main components. The channel formation region is formed on the first surface 50A side of the n-type well region 501 surrounded by the element isolation region 51. The gate insulating film 521 is formed on the first surface 50A of the semiconductor layer 50. The gate insulating film 521 is formed of an insulating material such as SiO ２ etc. The gate electrode 522 is formed on the gate insulating film 521. The gate electrode 522 is formed of a gate electrode material such as polycrystalline silicon.

[0083] The pair of main electrodes 524 are disposed in the n-type well region 501 on both sides in the gate length direction of the gate electrode 522 with the gate electrode 522 as the center. This pair of main electrodes 524 is formed of a p-type semiconductor region. Also, although not shown, sidewall spacers are formed on the sidewalls of the gate electrode 522 of the p-channel IGFET Qp.

[0084] (6-4) Device Structure of Wiring Layer 55 Similar to the wiring layer 35, the wiring layer 55 includes a wiring 551, a plug wiring 552, an electrode 553, and an insulating layer 555. The wiring 551 is arranged in multiple layers here by adopting a multilayer wiring structure. The plug wiring 552 electrically connects between the multiple layers of wirings 551. The electrode 553 is electrically connected to the wiring 551 and is disposed on the uppermost layer of the wiring layer 55. The electrode 553 is used for the electrical connection between the wiring 451 of the second substrate 1B and the wiring 551 of the third substrate 1C when the second substrate 1B and the third substrate 1C are bonded and laminated. Here, each of the electrodes (for example, wiring 463 or electrode 453) of the second substrate 1B and the electrode 553 of the third substrate 1C is formed of, for example, Cu, and the connection structure between the electrode of the second substrate 1B and the electrode 553 is a Cu-Cu connection structure. The insulating layer 555 is actually formed between the multiple layers of wirings 551 and is formed of multiple layers of insulating films.

[0085] (7) Configuration of the optical filter 7 As shown in Figure 4, in the pixel 10, the optical filter 7 and the optical lens 8 are sequentially arranged on the first surface 30A of the semiconductor layer 30 with a protective film (not shown) interposed between them. The optical filter 7 is formed as, for example, a red color filter that transmits light L in the red light band, a green color filter that transmits light L in the green light band, or a blue color filter that transmits light L in the blue light band. The optical filter 7 may also be a filter that transmits near-infrared light. The optical filter 7 is formed from, for example, a resin material to which an organic pigment has been added. As the resin material, acrylic resin, styrene resin, etc. can be used.

[0086] (8) Configuration of the optical lens 8 The optical lens 8 is arranged for each pixel 10 or for each set of pixels 10 in a side view. The optical lens 8 is formed in a curved shape that protrudes in the direction of arrow Z in a side view. The optical lens 8 is made of, for example, a light-transmitting resin material. Although not shown in the illustrations and detailed description, an anti-reflective coating may be formed on the optical lens 8. The optical lens 8 is connected to other adjacent optical lenses 8, and a set of optical lenses 8 are formed as a single unit. The optical lens 8 is configured as an on-chip lens.

[0087] [Manufacturing Method for Photodetector 1] Figures 9 to 15 show examples of cross-sectional views illustrating the manufacturing method for the photodetector 1 step by step. The manufacturing method for the photodetector 1 according to the first embodiment mainly describes a manufacturing method in which the connection structure between the gate electrode 422 of the selection transistor SEL of the pixel circuit 20 and the wiring 463 is formed in the second substrate 1B. The manufacturing method is as follows.

[0088] As shown in Figure 9, the first substrate 1A is bonded to the second substrate 1B, and the first substrate 1A is joined to the second substrate 1B. A Cu-Cu junction structure is used for joining, with the electrode 353 of the first substrate 1A and the electrode 453 of the second substrate 1B. Prior to joining, the first substrate 1A already has the photoelectric conversion element PD and transfer transistor TR for constructing the pixel 10 fabricated. The second substrate 1B also already has the pixel transistor for constructing the pixel circuit 20 fabricated.

[0089] Next, the second surface 40B side of the semiconductor layer 40 of the second substrate 1B is partially removed using a polishing or etching method, and the semiconductor layer 40 is thinned (see Figure 10). As shown in Figure 10, an insulating layer 465 is formed on the second surface 40B of the semiconductor layer 40. The insulating layer 465 forms the wiring layer 46 of the second substrate 1B. The insulating layer 465 is formed, for example, using the CVD (Chemical Vapor Deposition) method, where SiO ２ It is formed by.

[0090] As shown in Figure 11, a through-hole 42 is formed in the region of the selected transistor SEL, penetrating the semiconductor layer 40 in the thickness direction, including the insulating layer 465. The through-hole 42 is formed using an etching method with a mask formed on the second surface 40B side of the semiconductor layer 40 (not shown). The mask is formed using, for example, photolithography. Anisotropic etching such as RIE (Reactive Ion Etching) is used as the etching method. The through-hole 42 penetrates the semiconductor layer 40 and reaches the gate electrode 422 of the selected transistor SEL. In other words, the surface on the second surface 40B side of the gate electrode 422 is exposed within the through-hole 42.

[0091] As shown in Figure 12, an insulator 43 is formed that covers at least the inner wall of the through hole 42. The insulator 43 is formed, for example, using the CVD method, and here SiO ２ It is formed by this. For this reason, the insulator 43 is also formed on the surface of the gate electrode 422, which is the bottom surface of the through hole 42, and on the surface of the insulating layer 465.

[0092] As shown in Figure 13, the insulator 43 is left only on the inner wall of the through-hole 42, and the rest of the insulator 43 is removed. Anisotropic etching, such as RIE, is used to remove the insulator 43.

[0093] As shown in Figure 14, through-holes 42 are interposed with an insulator 43 to form through-holes 42, creating through-wiring 464. Through-holes 464 are formed by depositing a film using, for example, CVD or sputtering, and then removing the excess material outside of the through-holes 42. For this removal, for example, CMP (Chemical Mechanical Polishing) is used.

[0094] As shown in Figure 15, wiring 463 is formed in the insulating layer 465. The wiring 463 is electrically connected to the gate electrode 422 of the selection transistor SEL through through wiring 464.

[0095] Once the above steps are completed, the first substrate 1A and the second substrate 1B are finished, and when the third substrate 1C is further stacked, the light detection device 1 shown in Figure 4 above is completed.

[0096] [Effects] As described above, the photodetector 1 according to the first embodiment comprises a photoelectric conversion element PD and a pixel circuit 20, as shown in Figures 4 to 8. The photoelectric conversion element PD is disposed on the first substrate 1A and converts light into electric charge. The pixel circuit 20 is disposed on the second substrate 1B on which the first substrate 1A is stacked, and is electrically connected to the photoelectric conversion element PD to convert the electric charge into a pixel signal. Here, the pixel circuit 20 is configured to include a pixel transistor having three terminals disposed on the first surface 40A side of the second substrate 1B. Here, the pixel transistor is a selection transistor SEL. Wiring (first wiring) 463 is disposed on the second surface 40B side of the second substrate 1B facing the first surface 40A. At least one of the three terminals of the pixel transistor, i.e., the gate electrode 422 of the selection transistor SEL, is electrically connected to the wiring 463 through a through-wiring (first through-wiring) 464 that penetrates at least a portion of the second substrate 1B in the thickness direction. With the photodetector 1 configured in this way, the wiring 463 connected to the pixel transistor of the pixel circuit 20 is arranged on a wiring layer 46 on the second surface 40B side, separate from the wiring layer 45 on the first surface 40A side of the second substrate 1B. Therefore, the constraints on the wiring layout of the wiring layer 45 are relaxed, and the constraints of the design rules can be eliminated.

[0097] Furthermore, in the photodetector 1, the signal path from the select transistor SEL of the pixel circuit 20 to the gate electrode 422 is moved away from the floating diffusion FD because the wiring 463 is relocated to the wiring layer 46. As a result, the parasitic capacitance added to the floating diffusion FD can be effectively reduced, and the photoelectric conversion efficiency can be improved.

[0098] Furthermore, in the photodetector 1, as shown in Figures 6 to 8, in the selection transistor SEL of the pixel circuit 20, a gate electrode 422 extends in the gate width direction intersecting the gate length direction from one main electrode 423 to the other main electrode 423, and a through-wiring 464 is electrically connected to the extended portion 422E of this gate electrode 422. With the photodetector 1 configured in this way, the through-wiring 464 is connected to the gate electrode 422 at a position away from the channel formation region of the selection transistor SEL, so the characteristics of the selection transistor SEL are not impaired.

[0099] Furthermore, as shown in Figures 6 to 8, the photodetector 1 further includes an element isolation region 41 in the selection transistor SEL of the pixel circuit 20, which electrically isolates the pair of main electrodes 423 and the through-wiring 464. With the photodetector 1 configured in this way, the channel formation region of the selection transistor SEL and the through-wiring 464 are electrically isolated, so the characteristics of the selection transistor SEL are not impaired. In other words, there is no variation in the channel width dimension of the channel formation region of the selection transistor SEL.

[0100] Furthermore, in the photodetector 1, as shown in Figure 8, the second substrate 1B is configured to include at least a semiconductor layer 40, and an insulator 43 having a thickness tox1, which is thicker than, for example, the thickness tox2 of the gate insulating film 421 of the selection transistor SEL, is disposed between the through-wiring 464 and the semiconductor layer 40. Therefore, the parasitic capacitance formed by the through-wiring 464, the insulator 43, and the semiconductor layer 40 and added to the through-wiring 464 can be effectively reduced. In other words, the capacitance value of the parasitic capacitance can be effectively reduced. Consequently, the parasitic capacitance added to the floating diffusion FD can be effectively reduced, and the photoelectric conversion efficiency can be improved.

[0101] <2. First-Second Embodiment> The photodetector 1 according to the first-second embodiment of the present disclosure will be described with reference to Figure 16. The first-second embodiment describes a second example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 according to the first-first embodiment. In the first-second embodiment and subsequent embodiments, the same reference numerals are used for components that are the same as or substantially the same as components of the photodetector 1 according to the first-first embodiment, and redundant explanations are omitted.

[0102] [Device Configuration of Photodetector 1] Figure 16 shows an example of the main planar configuration of the pixel circuit 20 of the photodetector 1 according to the first and second embodiments. As shown in Figure 16, in the photodetector 1, instead of the selection transistor SEL of the pixel circuit 20, the gate electrode 422 of the reset transistor RST is electrically connected to the wiring (first wiring) 463 through the through wiring (first through wiring) 464. The gate electrode 422 of the reset transistor RST is located on the first surface 40A side of the semiconductor layer 40. The wiring 463 is located on the second surface 40B side of the semiconductor layer 40.

[0103] The components of the first and second embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first embodiment.

[0104] [Effects and Effects] According to the first and second embodiments of the photodetector 1, the same effects and effects as those obtained with the first and first embodiments of the photodetector 1 can be obtained.

[0105] <3. First-Third Embodiments> The first-third embodiment of the photodetector 1 of the present disclosure will be described with reference to Figure 17. The first-third embodiment describes a third example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 of the first-first embodiment.

[0106] [Device Configuration of Photodetector 1] Figure 17 shows an example of the main planar configuration of the pixel circuit 20 of the photodetector 1 according to the first to third embodiments. As shown in Figure 17, in the photodetector 1, in addition to the selection transistor SEL of the pixel circuit 20, the gate electrode 422 of the reset transistor RST is electrically connected to the wiring (first wiring) 463 through the through wiring (first through wiring) 464. The gate electrodes 422 of the selection transistor SEL and the reset transistor RST are arranged on the first surface 40A side of the semiconductor layer 40. The wiring 463 is arranged on the second surface 40B side of the semiconductor layer 40.

[0107] The components of the first to third embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first to first embodiment and the first to second embodiment.

[0108] [Effects] According to the first to third embodiments of the photodetector 1, it is possible to obtain effects that combine the effects obtained by the photodetector 1 according to the first to first embodiment and the effects obtained by the photodetector 1 according to the first to second embodiment.

[0109] <4. First-Fourth Embodiments> The photodetector 1 according to the first-fourth embodiment of the present disclosure will be described with reference to Figure 18. The first-fourth embodiment describes a fourth example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector according to the first-first embodiment.

[0110] [Device Configuration of Photodetector 1] Figure 18 shows an example of an enlarged cross-sectional configuration of the main part of the pixel circuit 20 of the photodetector 1 according to the first to fourth embodiments. As shown in Figure 18, in the photodetector 1, through wiring 464 is arranged overlapping the element isolation region 41 in the second substrate 1B. This will be explained in detail.

[0111] The groove 411 of the element isolation region 41 formed on the first surface 40A side of the semiconductor layer 40 is connected at its bottom to a through hole 42 formed on the second surface 40B side of the semiconductor layer 40. A portion of the through wiring 464 is disposed in the groove 411 with an embedded member 412 interposed therebetween, and the remaining portion of the through wiring 464 is disposed in the through hole 42 with an insulator 43 interposed therebetween. Similar to the photodetector 1 according to the first embodiment, one end of the through wiring 464 is electrically connected to the gate electrode 422 of the selection transistor SEL, as described above. The other end of the through wiring 464 is electrically connected to wiring 463.

[0112] The components of the first to fourth embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first to first embodiment.

[0113] [Effects and Effects] According to the first to fourth embodiments of the photodetector 1, the same effects and effects as those obtained with the first to first embodiment of the photodetector 1 can be obtained.

[0114] Furthermore, in the photodetector 1, as shown in Figure 18, the through-wiring 464 is arranged overlapping the element isolation region 41, so the area where the through-wiring 464 is formed can be effectively eliminated. As a result, the constraints on the wiring layout of the through-wiring 464 are relaxed, and the constraints on the design rules can be eliminated.

[0115] <5. First to Fifth Embodiments> The first to fifth embodiment of the photodetector 1 of this disclosure will be described with reference to Figure 19. The first to fifth embodiment describes a fifth example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 of the first to first embodiment. The first to fifth embodiment is also an application example of the photodetector 1 of the first to fourth embodiment.

[0116] [Device Configuration of Photodetector 1] Figure 19 shows an example of an enlarged cross-sectional configuration of the main part of the pixel circuit 20 of the photodetector 1 according to the first to fifth embodiments. As shown in Figure 19, in the photodetector 1, through wiring 464 is arranged overlapping the element isolation region 41 in the second substrate 1B. This will be explained in detail.

[0117] The element isolation region 41 is disposed to penetrate the semiconductor layer 40 in the thickness direction. That is, the element isolation region 41 comprises a groove 411 penetrating from the first surface 40A to the second surface 40B of the semiconductor layer 40, and an embedded member 412 embedded in the groove 411. The through-wiring 464 is disposed within a through-hole 42 formed in the embedded member 412 of the element isolation region 41. When the embedded member 412 is formed of an insulating material, the insulator 43 is not formed. Similar to the photodetector 1 according to the first embodiment, one end of the through-wiring 464 is electrically connected to the gate electrode 422 of the selection transistor SEL, as described above. The other end of the through-wiring 464 is electrically connected to the wiring 463.

[0118] The components of the first to fifth embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first to fifth embodiment.

[0119] [Effects and Effects] The photodetector 1 according to the first to fifth embodiments can obtain the same effects and effects as those obtained by the photodetector 1 according to the first to first embodiment. Furthermore, the photodetector 1 according to the first to fifth embodiments can obtain the same effects and effects as those obtained by the photodetector 1 according to the first to fourth embodiment.

[0120] <6. First-sixth Embodiment> The photodetector 1 according to the first-sixth embodiment of the present disclosure will be described with reference to Figures 20 to 22. The first-sixth embodiment describes a sixth example in which the structure of the element isolation region 41 of the pixel transistor that constructs the pixel circuit 20 is changed in the photodetector 1 according to the first-first embodiment.

[0121] [Device Configuration of Photodetector 1] Figure 20 shows an example of an enlarged cross-sectional configuration of the second base 1B of the photodetector 1 according to the first to sixth embodiments. Figure 21 shows an example of a planar configuration of the main part of the pixel circuit 20 of the photodetector 1 shown in Figure 20. Figure 22 shows an example of a further enlarged cross-sectional configuration of the main part of the pixel circuit 20.

[0122] As shown in Figures 20 to 22, in the photodetector 1, in the second substrate 1B, an extension portion 422E is provided on the gate electrode 422 of the selection transistor SEL, but an element isolation region 41 is not provided between the effective channel formation region and the through-wiring 464.

[0123] The components of the first to sixth embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first to sixth embodiment.

[0124] [Effects and Effects] According to the photodetector 1 of the 1st to 6th embodiments, the same effects and effects as those obtained with the photodetector 1 of the 1st to 1st embodiment can be obtained.

[0125] <7. First to Seventh Embodiments> The photodetector 1 according to the first to seventh embodiment of the present disclosure will be described with reference to Figures 23 and 24. The first to seventh embodiment describes a seventh example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 according to the first to first embodiment. Furthermore, the photodetector 1 according to the first to seventh embodiment is also an example of combining the photodetector 1 according to the first to first embodiment and the photodetector 1 according to the first to fifth embodiment.

[0126] [Device Configuration of Photodetector 1] Figure 23 shows an example of an enlarged cross-sectional configuration of the second base 1B of the photodetector 1 according to the first to seventh embodiments. Figure 24 shows an example of the circuit configuration of the pixel 10 and the pixel circuit 20.

[0127] First, as shown in Figure 24, in the pixel circuit 20, the terminals enclosed by the solid lines of the pixel transistors are electrically connected to the wiring 463 through the through wiring 464. This will be explained in detail.

[0128] As shown in Figures 23 and 24, the gate electrode 422 of the reset transistor RST is electrically connected to the wiring 463 through the through wiring 464, similar to the photodetector 1 according to the first embodiment described above. A control signal (for example, a reset signal) is transmitted to this wiring 463.

[0129] On the other hand, the main electrode 423 of the reset transistor RST is electrically connected to the wiring 463 through the wiring 425 and the through-wiring 464. The through-wiring 464 is arranged overlapping the element isolation region 41, similar to the photodetector 1 according to the first to fifth embodiments described above. The wiring 425 is arranged on the first surface 40A side of the semiconductor layer 40, with one end electrically connected to the main electrode 423 and the other end electrically connected to the through-wiring 464. The power supply voltage VDD is supplied to the wiring 463. The wiring 425 may also share connections with terminals of other adjacent pixel transistors and is formed as "shared wiring". The wiring 425 is formed of, for example, a compound of one or more metals selected from Ti, Mo, Ni, Co, and Pt and Si, or of Si. Here, the wiring 425 corresponds to the "second wiring" according to this disclosure.

[0130] The gate electrode 422 of the selection transistor SEL is electrically connected to the wiring 463 through the through wiring 464, similar to the photodetector 1 according to the first embodiment described above. A control signal (for example, a selection signal) is transmitted to this wiring 463.

[0131] On the other hand, the main electrode 423 of the selection transistor SEL is electrically connected to the wiring 463 through the wiring 425 and the through-wiring 464. The through-wiring 464 is arranged overlapping the element isolation region 41, similar to the photodetector 1 according to the first to fifth embodiments described above. The wiring 425 is arranged on the first surface 40A side of the semiconductor layer 40, with one end electrically connected to the main electrode 423 and the other end electrically connected to the through-wiring 464. The wiring 463 is used, for example, as a vertical signal line Lv.

[0132] The main electrode 423 of the amplification transistor AMP is electrically connected to the wiring 463 through the wiring 425 and the through-wiring 464. The through-wiring 464 is arranged overlapping the element isolation region 41, similar to the photodetector 1 according to the first to fifth embodiments described above. The wiring 425 is arranged on the first surface 40A side of the semiconductor layer 40, with one end electrically connected to the main electrode 423 and the other end electrically connected to the through-wiring 464. The power supply voltage VDD is supplied to the wiring 463.

[0133] The components of the first to seventh embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first to first embodiment or the photodetector 1 according to the first to fifth embodiment.

[0134] [Effects] According to the photodetector 1 of the first to seventh embodiments, it is possible to obtain effects that combine the effects obtained by the photodetector 1 of the first to first embodiment and the effects obtained by the photodetector 1 of the first to fifth embodiments.

[0135] Furthermore, in the photodetector 1, as shown in Figures 23 and 24, the terminals of most of the pixel transistors in the pixel circuit 20 are electrically connected to the wiring 463 arranged on the second surface 40B of the semiconductor layer 40 through through-wiring 464. As a result, the constraints on the wiring layout of the wiring layer 45 are further relaxed, and the constraints on design rules can be eliminated.

[0136] Furthermore, in the photodetector 1, as shown in Figures 23 and 24, the terminals of most of the pixel transistors in the pixel circuit 20 are electrically connected to the wiring 463 arranged on the second surface 40B of the semiconductor layer 40 through through-wiring 464. As a result, the parasitic capacitance added to the floating diffusion FD can be effectively reduced, and the photoelectric conversion efficiency can be further improved.

[0137] <8. First to Eighth Embodiment> The first to eighth embodiment of the present disclosure of the photodetector 1 will be described with reference to Figure 25. The first to eighth embodiment describes an eighth example in which the connection structure between the pixel transistors and wiring that constitute the pixel circuit 20 is changed in the photodetector 1 according to the first to first embodiment.

[0138] [Device Configuration of Photodetector 1] Figure 25 shows an example of an enlarged cross-sectional configuration of the second substrate 1B of the photodetector 1 according to the first to eighth embodiments. As shown in Figure 25, in the photodetector 1, some of the pixel transistors of the pixel circuit 20 are arranged on the second surface 40B side of the second substrate 1B. Here, as an example, the reset transistor RST is arranged on the second surface 40B side of the second substrate 1B. This will be explained in detail.

[0139] The semiconductor layer 40 of the second substrate 1B is thinned. The gate insulating film 421 and gate electrode 422 of the reset transistor RST are disposed on the second surface 40B of the semiconductor layer 40. A pair of main electrodes 423 are disposed in the thickness direction from the second surface 40B to the first surface 40A of the semiconductor layer 40.

[0140] Furthermore, the main electrode 423 of the reset transistor RST is electrically connected to the wiring 451 through the plug wiring 452 of the wiring layer 45, which is disposed on the first surface 40A side of the semiconductor layer 40.

[0141] In other words, the second surface 40B of the second substrate 1B can be replaced with the "first surface" according to this disclosure, and it can be considered that a pixel transistor is disposed on the "first surface (second surface 40B)" of the second substrate 1B. Furthermore, the first surface 40A of the second substrate 1B can be replaced with the "second surface" according to this disclosure, the plug wiring 452 of the wiring layer 45 can be replaced with the "first through wiring" according to this disclosure, and the wiring 451 can be replaced with the "first wiring" according to this disclosure. In other words, the terminal (main electrode 423) of the pixel transistor can be considered to be electrically connected to the "first wiring (wiring 451)" through the "first through wiring (plug wiring 452)" which penetrates a part of the wiring layer 45 of the second substrate 1B.

[0142] The components of the first to eighth embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first to first embodiment.

[0143] [Effects] The photodetector 1 according to the first to eighth embodiment can obtain the same effects as those obtained with the photodetector 1 according to the first to first embodiment.

[0144] <9. First to Ninth Embodiments> The photodetector 1 according to the first to ninth embodiment of the present disclosure will be described using Figures 26 to 28. The first to ninth embodiment describes a ninth example in which the structure of the pixel transistors that make up the pixel circuit 20 is changed in the photodetector 1 according to the first to sixth embodiment.

[0145] [Device Configuration of Photodetector 1] Figure 26 shows an example of an enlarged cross-sectional configuration of the second base 1B of the photodetector 1 according to the first to ninth embodiments. Figure 27 shows an example of a planar configuration of the main part of the pixel circuit 20 of the photodetector 1 shown in Figure 26. Figure 28 shows an example of a further enlarged cross-sectional configuration of the main part of the pixel circuit 20.

[0146] As shown in Figures 26 to 28, in the light detection device 1, the pixel transistors or a part thereof of the pixel circuit 20 are equipped with a fin-type gate structure. Here, for example, the selection transistor SEL is equipped with a fin-type gate structure. This will be explained in detail.

[0147] A portion of the gate electrode 422 of the selection transistor SEL extends from the first surface 40A to the second surface 40B of the semiconductor layer 40 of the second substrate 1B. In other words, the gate width dimension of the gate electrode 422 is extended in the thickness direction of the semiconductor layer 40. Here, two locations in the gate width direction of the gate electrode 422 extend in the thickness direction of the semiconductor layer 40. Note that a similar structure can be adopted for pixel transistors other than the selection transistor SEL in the pixel circuit 20.

[0148] The components of the first to ninth embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first to sixth embodiments.

[0149] [Effects] The photodetector 1 according to the first to ninth embodiments can obtain the same effects as those obtained with the photodetector 1 according to the first to sixth embodiments.

[0150] Furthermore, in the photodetector 1, as shown in Figures 26 to 28, a fin-type gate structure is employed for the pixel transistors of the pixel circuit 20. In other words, the gate width dimension of the pixel transistors is expanded. As a result, the transconductance (gm) of the pixel transistors can be improved, and thus the modulation characteristics can be effectively improved.

[0151] <10. First-to-Tenth Embodiments> The photodetector 1 according to the first-to-tenth embodiment of this disclosure will be described using Figures 29 to 31. The first-to-tenth embodiment describes a tenth example that combines the photodetector 1 according to the first-to-eighth embodiment and the photodetector 1 according to the first-to-ninth embodiment.

[0152] [Device Configuration of Photodetector 1] Figure 29 shows an example of an enlarged cross-sectional configuration of the second base 1B of the photodetector 1 according to the first to tenth embodiments. Figure 30 shows an example of a planar configuration of the main part of the pixel circuit 20 of the photodetector 1 shown in Figure 29. Figure 31 shows an example of a further enlarged cross-sectional configuration of the main part of the pixel circuit 20.

[0153] As shown in Figures 29 to 31, in the light detection device 1, the pixel transistors of the pixel circuit 20, or a part thereof, are equipped with a fin-type gate structure. Here, for example, the reset transistor RST is equipped with a fin-type gate structure. This will be explained in detail.

[0154] A portion of the gate electrode 422 of the reset transistor RST extends from the second surface 40B of the semiconductor layer 40 of the second substrate 1B toward the first surface 40A. In other words, the gate width dimension of the gate electrode 422 is extended in the thickness direction of the semiconductor layer 40. Here, two locations in the gate width direction of the gate electrode 422 extend in the thickness direction of the semiconductor layer 40. Note that a similar structure can be adopted for pixel transistors other than the reset transistor RST in the pixel circuit 20.

[0155] The components of the first to tenth embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first to eighth embodiment or the photodetector 1 according to the first to ninth embodiment.

[0156] [Effects] According to the first to tenth embodiments of the photodetector 1, it is possible to obtain effects that combine the effects obtained by the photodetector 1 according to the first to eighth embodiments and the effects obtained by the photodetector 1 according to the first to ninth embodiments.

[0157] [Modified Example] Figure 32 shows an example of a cross-sectional configuration (corresponding to the cross-sectional configuration in Figure 31) that further enlarges the main part of the pixel circuit 20 of the light detection device 1 according to a modified example of the first to tenth embodiments. As shown in Figure 32, in the light detection device 1, the pixel transistors of the pixel circuit 20 or a part thereof are equipped with a fin-type gate structure. Here, for example, the reset transistor RST is equipped with a fin-type gate structure. This will be explained in detail.

[0158] A portion of the gate electrode 422 of the reset transistor RST extends from the second surface 40B of the semiconductor layer 40 of the second substrate 1B toward the first surface 40A. In other words, the gate width dimension of the gate electrode 422 is extended in the thickness direction of the semiconductor layer 40. Here, one point in the center of the gate width direction of the gate electrode 422 extends in the thickness direction of the semiconductor layer 40. Note that a similar structure can be adopted for pixel transistors other than the reset transistor RST in the pixel circuit 20.

[0159] Other components of the modified example are the same as or substantially the same as the components of the photodetector 1 according to the first to tenth embodiments.

[0160] [Effects and Effects] According to the photodetector 1 modified from the first to tenth embodiments, the same effects and effects as those obtained with the photodetector 1 according to the first to tenth embodiments can be obtained.

[0161] <11. Second-First Embodiment> The light detection device 1 according to the second-first embodiment of the present disclosure will be described using Figures 33 to 36. The second-first embodiment describes an eleventh example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the light detection device 1 according to the first-seventh embodiment. The second-first embodiment changes the configuration of the pixel circuit 20.

[0162] [Circuit Configuration of Pixel 10 and Pixel Circuit 20] Figure 33 shows an example of the circuit configuration of the pixel 10 and pixel circuit 20 of the photodetector 1 according to the second-first embodiment. As shown in Figure 33, the pixel circuit 20 of the photodetector 1 further includes an FD conversion gain switching transistor FDG. One main electrode of the FD conversion gain switching transistor FDG is electrically connected to a floating diffusion FD, and the other main electrode is electrically connected to one main electrode of a reset transistor RST. A control signal is input to the gate electrode.

[0163] [Device Configuration of Light Detection Device 1] Figure 34 shows an example of the planar configuration of the main part of the pixel circuit 20 of the light detection device 1 according to the second-first embodiment. Figure 35 shows an example of a cross-sectional configuration of the main part of the pixel circuit 20, which is further enlarged.

[0164] As shown in Figures 34 and 35, in the photodetector 1, the FD conversion gain switching transistor FDG of the pixel circuit 20 is arranged on the first surface 40A side of the semiconductor layer 40 of the second substrate 1B, similar to the amplification transistor AMP. The FD conversion gain switching transistor FDG, similar to the amplification transistor AMP, has a channel formation region, a gate insulating film 421, a gate electrode 422, and a pair of main electrodes 423 as its main components (see Figures 4 and 5).

[0165] In the second-first embodiment, the main electrode 423 of the amplification transistor AMP and the main electrode 423 of the reset transistor RST are electrically connected to the wiring 463 through the wiring 425 and the through-wiring 464.

[0166] Similar to the photodetector 1 according to the first to seventh embodiments described above, the main electrode 423 of the amplification transistor AMP and the main electrode 423 of the reset transistor RST are arranged on the first surface 40A side of the semiconductor layer 40. The wiring 425 is arranged on the first surface 40A side of the semiconductor layer 40 as described above and is configured as a "shared wiring". The through-wiring 464 is arranged to penetrate the semiconductor layer 40 in the thickness direction and overlaps with the element isolation region 41. One end of the through-wiring 464 is electrically connected to the wiring 425. The other end of the through-wiring 464 is electrically connected to the wiring 463. The wiring 463 is arranged on the second surface 40B side of the semiconductor layer 40. The power supply voltage VDD is supplied to the wiring 463.

[0167] Figure 36 shows an example of the main planar configuration of the pixel circuit 20 as viewed from the second surface 40B side of the semiconductor layer 40. The wiring 463 arranged on the second surface 40B side of the semiconductor layer 40 is formed in a ring shape along the contour of the pixel 10, which is shown by the dashed line. The wiring 463 of adjacent pixels 10 are formed integrally. In other words, as a whole for the pixel region 100 (see Figures 1 and 2), the wiring 463 is formed in a lattice shape, extending in the direction of arrow X, spaced apart at regular intervals in the direction of arrow Y, and further extending in the direction of arrow Y and spaced apart at regular intervals in the direction of arrow X.

[0168] The components of the second-first embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first-seventh embodiments.

[0169] [Effects and Effects] According to the second-first embodiment of the photodetector 1, the same effects and effects as those obtained by the photodetector 1 according to the first-seventh embodiments can be obtained.

[0170] Furthermore, in the photodetector 1, as shown in Figure 36 in particular, on the second surface 40B side of the second substrate 1B, the wiring 463 is formed in a ring shape along the contour of the pixel 10, and the entire pixel region 100 is formed in a grid shape. The power supply voltage VDD is supplied to the wiring 463. With the photodetector 1 configured in this way, the area of ​​the wiring 463 can be increased, so the resistance of the wiring 463 can be reduced and the voltage drop of the power supply voltage VDD can be reduced.

[0171] <12. Second-Second Embodiment> The photodetector 1 according to the second-second embodiment of the present disclosure will be described using Figures 37 to 39. The second-second embodiment describes a twelfth example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 according to the second-first embodiment.

[0172] [Device Configuration of Light Detection Device 1] Figure 37 shows an example of the planar configuration of the main part of the pixel circuit 20 of the light detection device 1 according to the second-second embodiment. Figure 38 shows an example of a cross-sectional configuration of the main part of the pixel circuit 20, which is further enlarged.

[0173] As shown in Figures 37 and 38, in the light detection device 1, the main electrode 423 of the selection transistor SEL of the pixel circuit 20 is electrically connected to the wiring 463. The main electrode 423 of the selection transistor SEL is electrically connected to the through-wiring 464 through wiring 425, and this through-wiring 464 is further electrically connected to wiring 463.

[0174] In the second-second embodiment, the wiring 425 is arranged on the first surface 40A side of the semiconductor layer 40 and is arranged as a drawer wiring that is drawn out from the main electrode 423 of the selected transistor SEL to the element isolation region 41. The wiring 425 corresponds to the "drawer wiring" according to the present disclosure.

[0175] Figure 39 shows an example of the main planar configuration of the pixel circuit 20 as viewed from the second surface 40B side of the semiconductor layer 40. The wiring 463 arranged on the second surface 40B side of the semiconductor layer 40 extends in the direction of arrow Y and is arranged at predetermined intervals in the direction of arrow X. In other words, the wiring 463 is formed in a stripe shape. Here, the wiring 463 is used as a power supply wiring to which the reference voltage GND is supplied, and as a vertical signal line Lv, respectively.

[0176] The components of the second-second embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the second-first embodiment.

[0177] [Effects and Effects] According to the second-second embodiment of the photodetector 1, the same effects and effects as those obtained with the second-first embodiment of the photodetector 1 can be obtained.

[0178] <13. Second- and Third Embodiments> The photodetector 1 according to the second- and third embodiment of the present disclosure will be described using Figures 40 to 44. The second- and third embodiment describes a thirteenth example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 according to the second- and first embodiment.

[0179] [Device Configuration of Light Detection Device 1] Figure 40 shows an example of the planar configuration of the main part of the pixel circuit 20 of the light detection device 1 according to the second and third embodiments. Figures 41 and 42 show examples of the cross-sectional configuration of the main part of the pixel circuit 20, which is further enlarged.

[0180] As shown in Figures 40 to 42, in the light detection device 1, a shared wiring (second wiring) 425 is provided, electrically connected to the main electrode 423 of the amplification transistor AMP and the main electrode 423 of the reset transistor RST of the pixel circuit 20. Wiring 425 is electrically connected to wiring 463 through through wiring 464.

[0181] Here, the wiring 425 extends in the direction of arrow Y, and the cross-sectional area of ​​the through-wiring 464 expands along the direction of extension of the wiring 425. The through-wiring 464 is arranged overlapping the element isolation region 41. In other words, the opening dimensions of the through-hole 42 of the through-wiring 464 are enlarged in the direction of arrow Y, and in plan view, the opening of the through-hole 42 is formed in a stripe shape.

[0182] Figure 43 shows an example of the main planar configuration of the pixel circuit 20 as viewed from the second surface 40B side of the semiconductor layer 40. The wiring 463 arranged on the second surface 40B side of the semiconductor layer 40 is formed in a ring shape along the contour of the pixel 10, similar to the photodetector 1 according to the second-first embodiment. Furthermore, the wiring 463 is formed in a grid shape as a whole for the pixel region 100 (see Figures 1 and 2).

[0183] Figure 44 shows an example of the cross-sectional configuration of the photodetector 1. Wiring 463 arranged on the second substrate 1B is electrically connected to wiring 551 arranged on the wiring layer 55 of the third substrate 1C through through wiring 56. Power voltage VDD is supplied to wiring 463 from wiring 551 through through wiring 56.

[0184] The components of the second- and third embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the second- and first embodiments.

[0185] [Effects and Effects] According to the second- to third embodiment of the photodetector 1, the same effects and effects as those obtained with the photodetector 1 according to the second- to first embodiment can be obtained.

[0186] Furthermore, in the photodetector 1, as shown in Figures 40 to 42, the cross-sectional area of ​​the through-wiring 464 is expanded, which reduces the resistance of the through-wiring 464 and reduces the voltage drop of the power supply voltage VDD.

[0187] <14. Second-Fourth Embodiment> The photodetector 1 according to the second-fourth embodiment of the present disclosure will be described with reference to Figures 45 and 46. The second-fourth embodiment describes a 14th example in which the wiring structure is changed in the photodetector 1 according to the second-first embodiment.

[0188] [Configuration of the Photodetector 1] Figure 45 shows an example of a schematic planar configuration of the photodetector 1 including the pixel area (pixel array) 100. Figure 46 shows an example of a schematic longitudinal cross-sectional configuration of the photodetector 1. As shown in Figures 45 and 46, in the photodetector 1, wiring 451 surrounding the pixel area 100 is provided in a wiring layer 45 disposed on the first surface 40A of the second substrate 1B. In plan view, the wiring 451 is formed in a ring shape. Power supply voltage VDD is supplied to this wiring 451. In other words, the wiring 451 is a power supply wiring. This power supply wiring corresponds to the "first power wiring" according to this disclosure.

[0189] The wiring 451 is electrically connected to the wiring 463 of the wiring layer 46 disposed on the second surface 40B of the second substrate 1B via a through-wiring 467. A power supply voltage VDD is supplied from the wiring 451 to the wiring 463. The wiring 463 is formed in a grid shape over the entire pixel area 100, for example, similar to the photodetector 1 according to the second-first embodiment.

[0190] Furthermore, in the pixel region 100, wiring 425 is arranged similarly to the light detection device 1 according to the second and third embodiments. The wiring 425 extends in the direction of arrow Y and is arranged at predetermined intervals in the direction of arrow X. The wiring 425 is electrically connected to wiring 463 through through wiring 464, and the cross-sectional area of ​​through wiring 464 is expanded along the direction in which the wiring 425 extends.

[0191] The components of the second-fourth embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the second-first embodiment.

[0192] [Effects and Effects] According to the second-to-fourth embodiment of the photodetector 1, the same effects and effects as those obtained with the second-to-first embodiment of the photodetector 1 can be obtained.

[0193] <15. Second-Fifth Embodiment> The photodetector 1 according to the second-fifth embodiment of the present disclosure will be described using Figures 47 to 49. The second-fifth embodiment describes a 15th example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 according to the second-first embodiment.

[0194] [Device Configuration of Photodetector 1] Figure 47 shows an example of the planar configuration of the main part of the pixel circuit 20 of the photodetector 1 according to the second to fifth embodiment. Figure 48 shows an example of the cross-sectional configuration of the main part of the pixel circuit 20, which is further enlarged. Figure 49 shows an example of the planar configuration of the main part of the pixel circuit 20 as seen from the second surface 40B side of the semiconductor layer 40.

[0195] As shown in Figures 47 to 49, in the light detection device 1, extension portions 422E are provided, which are extensions in the gate width direction of the gate electrodes 422 of the reset transistor RST, the selection transistor SEL, and the FD conversion gain switching transistor FDG of the pixel circuit 20. The extension portions 422E are integrally formed with the gate electrodes 422. Furthermore, the extension portions 422E are arranged overlapping the element isolation region 41.

[0196] Each extension 422E is electrically connected to the wiring 463 through the through wiring 464. As shown in Figure 49, the wiring 463 extends in the direction of arrow X and is arranged at predetermined intervals in the direction of arrow Y. In other words, each wiring 463 is formed in a stripe shape.

[0197] The components of the second-fifth embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the second-first embodiment.

[0198] [Effects and Effects] According to the photodetector 1 of the second-fifth embodiment, the same effects and effects as those obtained with the photodetector 1 of the second-first embodiment can be obtained.

[0199] <16. Second-Sixth Embodiment> The photodetector 1 according to the second-sixth embodiment of the present disclosure will be described with reference to Figures 50 and 51. The second-sixth embodiment describes the sixteenth example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 according to the second-first embodiment.

[0200] [Device Configuration of Light Detection Device 1] Figure 50 shows an example of the planar configuration of the main part of the pixel circuit 20 of the light detection device 1 according to the second to sixth embodiment. Figure 51 shows an example of a cross-sectional configuration of the main part of the pixel circuit 20, which is further enlarged.

[0201] As shown in Figures 50 and 51, the light detection device 1 has an extension portion 422E that extends in the gate width direction from the gate electrode 422 of the amplification transistor AMP of the pixel circuit 20. The extension portion 422E is integrally formed with the gate electrode 422. Furthermore, the extension portion 422E is arranged overlapping the element isolation region 41.

[0202] The extension portion 422E is electrically connected to the wiring 463 through the through wiring 464. The wiring 463, although not shown in the figures, is formed in a stripe shape, similar to the light detection device 1 according to the second to fifth embodiment.

[0203] The components of the second-sixth embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the second-first embodiment.

[0204] [Effects] According to the photodetector 1 of the second-sixth embodiment, the same effects as those obtained with the photodetector 1 of the second-first embodiment can be obtained.

[0205] <17. Second-Seventh Embodiment> The photodetector 1 according to the second-seventh embodiment of the present disclosure will be described with reference to Figures 52 and 53. The second-seventh embodiment describes the seventeenth example in which the connection structure between the photoelectric conversion element PD and the pixel transistor that constructs the pixel circuit 20 is changed in the photodetector 1 according to the second-first embodiment.

[0206] [Device Configuration of Photodetector 1] Figure 52 shows an example of an enlarged cross-sectional configuration of the main part of the photodetector 1 according to the second-seventh embodiment. Figure 53 shows an example of a planar configuration of the connection portion between the electrode 353 connected to the pixel 10 of the photodetector 1 and the electrode 453 connected to the pixel circuit 20.

[0207] As shown in Figures 52 and 53, in the photodetector 1, the amplification transistor AMP of the pixel circuit 20 is located on the second surface 40B side of the semiconductor layer 40. The gate electrode 422 of the amplification transistor AMP is electrically connected to the wiring 451 of the wiring layer 45 located on the first surface 40A side through a through wiring 464. The wiring 451 is electrically connected to the electrode of the wiring layer 45. On the other hand, the n-type semiconductor region 323 of the transfer transistor TR of the pixel 10 is electrically connected to the electrode 353 through the plug wiring 352 and wiring 351 of the wiring layer 35, respectively.

[0208] Then, electrode 453 is electrically connected to electrode 353 by a Cu-Cu junction structure, and the second substrate 1B is bonded to the first substrate 1A to form a laminate.

[0209] The components of Embodiment 2-7 other than those described above are the same as or substantially the same as the components of the photodetector 1 according to Embodiment 2-1.

[0210] [Effects] According to the photodetector 1 of the second-seventh embodiment, the same effects as those obtained with the photodetector 1 of the second-first embodiment can be obtained.

[0211] <18. Second-eighth Embodiment> The photodetector 1 according to the second-eighth embodiment of the present disclosure will be described using Figures 54 to 58. The second-eighth embodiment describes the eighteenth example in which the connection structure between the pixel transistors and wiring 463 that constitute the pixel circuit 20 is changed in the photodetector 1 according to the second-first embodiment. Here, an example of constructing a capacitive element using the connection structure will be described.

[0212] [Device Configuration of Light Detection Device 1] Figure 54 shows an example of the planar configuration of the main part of the pixel circuit 20 of the light detection device 1 according to the second-eighth embodiment. Figures 55 to 58 each show an example of an enlarged cross-sectional configuration of the main part of the pixel circuit 20.

[0213] As shown in Figures 54 to 58, in the light detection device 1, wiring 425 is drawn out from the main electrode 423 of the reset transistor RST and the FD conversion gain switching transistor FDG of the pixel circuit 20 to the element isolation region 41. Wiring 425 is electrically connected to wiring 463 through through wiring 464. Similar to the light detection device 1 according to the second to third embodiments, the cross-sectional area of ​​through wiring 464 is expanded along the direction in which wiring 425 is extended.

[0214] On the other hand, a contact area 424 electrically connected to the semiconductor layer 40 is provided on the first surface 40A of the semiconductor layer 40 of the second substrate 1B. The contact area 424 has the same conductivity type as the semiconductor layer 40 and has a higher impurity density than the semiconductor layer 40. Here, the contact area 424 is formed by a p-type semiconductor region.

[0215] A wiring 425 is drawn from this contact region 424 to the element isolation region 41. At least a portion of the wiring 425 is spaced apart from and opposite to the wiring 425 drawn from the main electrode 423. The wiring 425 is electrically connected to wiring 463 through a through-wiring 468 that penetrates the semiconductor layer 40 in the thickness direction. The cross-sectional area of ​​the through-wiring 468 is extended along the direction in which the wiring 425 extends. A reference voltage GND is supplied to wiring 463.

[0216] In the photodetector 1, the aforementioned through-wiring 464 is used as the first electrode, and the through-wiring 468 is used as the second electrode, with a dielectric material interposed between the first and second electrodes to construct a capacitive element C. Here, the capacitive element C is formed by a Metal Insulator Metal (MIM) structure. The embedded member 412 of the element isolation region 41 is used as the dielectric material. Note that the dielectric material is not limited to the embedded member 412 and may be formed from another dielectric material. Here, the through-wiring 468 corresponds to the "second through-wiring" according to this disclosure.

[0217] The components of the second-eighth embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the second-first embodiment.

[0218] [Effects] The photodetector 1 according to the second-eighth embodiment can obtain the same effects as those obtained with the photodetector 1 according to the second-first embodiment.

[0219] Furthermore, in the photodetector 1, as shown in Figures 54 to 58, the capacitive element C can be constructed using through-wiring 464 and through-wiring 468. This makes it possible to easily construct the additional capacitance used for switching the conversion efficiency. Moreover, since the photodetector 1 can construct the capacitive element C using through-wiring 464 and through-wiring 468, the occupied area of ​​the capacitive element C can be reduced, further relieving the constraints of design rules.

[0220] <19. Third-First Embodiment> The photodetector 1 according to the third-first embodiment of the present disclosure will be described using Figures 59 to 61. The third-first embodiment is the 19th example that describes the connection structure between the semiconductor layer 40 and the wiring 463 that constitute the pixel circuit 20 in any of the photodetector 1 according to the first-first to second-eighth embodiments.

[0221] [Device Configuration of Light Detection Device 1] Figure 59 shows an example of a schematic cross-sectional configuration of the light detection device 1 according to the third-first embodiment. Figure 60 shows an example of a planar configuration of the main part of the pixel circuit 20 of the light detection device 1.

[0222] As shown in Figures 59 and 60, in the photodetector 1, a contact region 424 is provided on the second surface 40B side of the semiconductor layer 40 of the second substrate 1B. In the third-first embodiment, the contact region 424 is provided over the entire pixel region 100. Since a p-type semiconductor substrate is used as the semiconductor layer 40 here, the contact region 424 is formed as a p-type semiconductor region (substrate contact region) with a high impurity density.

[0223] The contact area 424 is electrically connected to the wiring 463 through the plug wiring 462. A reference voltage GND is supplied to the wiring 463. Furthermore, the contact area 424 is electrically connected to the wiring 463 through one plug wiring 462 for, for example, one pixel circuit 20. Here, the wiring 463 is arranged as a common wiring in the pixel area 100. The wiring 463 corresponds to the "first power wiring" according to this disclosure.

[0224] [Manufacturing Method for Photodetector 1] Here, the manufacturing method for the contact region 424 will be briefly explained. Figure 61 shows an example of a cross-sectional view illustrating one step of the manufacturing method for the photodetector 1. After the semiconductor layer 40 of the second substrate 1B is thinned, the support substrate 400 is bonded to the second surface 40B of the semiconductor layer 40 (see Figure 61). The semiconductor layer 40 is thinned to a thickness of, for example, 1 μm or less.

[0225] Then, as shown in Figure 61, p-type impurities are implanted from the first surface 40A side of the semiconductor layer 40 toward the second surface 40B side, and a contact region 424 is formed on the second surface 40B side of the semiconductor layer 40. Ion implantation is used for implanting the p-type impurities.

[0226] The components of the third-first embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the first-first embodiment or the second-first embodiment.

[0227] [Effects] The photodetector 1 according to the third-first embodiment can obtain the same effects as those obtained with the photodetector 1 according to the first-first embodiment or the second-first embodiment.

[0228] As shown in Figures 59 and 60, the photodetector 1 comprises a photoelectric conversion element PD and a pixel circuit 20. The photoelectric conversion element PD is disposed on a first substrate 1A and converts light L into electric charge. The pixel circuit 20 is disposed on a second substrate 1B on which the first substrate 1A is stacked, and is electrically connected to the photoelectric conversion element PD to convert the electric charge into a pixel signal. The second substrate 1B is composed of a semiconductor layer 40. The pixel circuit 20 is composed of a pixel transistor disposed on the semiconductor layer 40 on the first surface 40A side of the second substrate 1B facing the first substrate 1A. On the second surface 40B side of the second substrate 1B facing the first surface 40A, a contact region 424 is disposed on the semiconductor layer 40, which has the same conductivity type as the semiconductor layer 40 and a higher impurity density than the semiconductor layer 40. On the second surface 40B side of the second substrate 1B, wiring 463 is provided that is electrically connected to the semiconductor layer 40 through a contact region 424. With the photodetector 1 configured in this way, the contact region 424 is provided on the second surface 40B, which is the back side of the first surface 40A of the second substrate 1B on which the pixel transistors of the pixel circuit 20 are arranged, and a reference voltage GND is supplied to the semiconductor layer 40 through the wiring 463. As a result, the constraints on the wiring layout of the wiring layer 45 are relaxed, and the constraints of the design rules can be eliminated.

[0229] Furthermore, since a reference voltage GND can be supplied to the semiconductor layer 40 without being restricted by the wiring layout of the wiring layer 45, the potential of the semiconductor layer 40 can be stably maintained.

[0230] Furthermore, in the photodetector 1, the wiring 463 is separated from the floating diffusion FD. This effectively reduces the parasitic capacitance added to the floating diffusion FD, thereby improving the photoelectric conversion efficiency.

[0231] <20. Third-Second Embodiment> The photodetector 1 according to the third-second embodiment of the present disclosure will be described with reference to Figure 62. The third-second embodiment describes a 20th example in which the method for manufacturing the contact region 424 disposed on the semiconductor layer 40 is changed in the photodetector 1 according to the third-first embodiment.

[0232] [Manufacturing Method for Photodetector 1] Figure 62 shows an example of a cross-sectional view illustrating one step of the manufacturing method for the photodetector 1 according to the third-second embodiment. The second substrate 1B is bonded to the first substrate 1A (see Figure 62). After this, as shown in Figure 62, p-type impurities are implanted into the second surface 40B of the semiconductor layer 40 of the second substrate 1B, and a contact region 424 is formed on the second surface 40B side of the semiconductor layer 40. Ion implantation is used for implanting the p-type impurities.

[0233] The components of the third-second embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the third-first embodiment.

[0234] [Effects] According to the photodetector 1 of the third-second embodiment, the same effects as those obtained with the photodetector 1 of the third-first embodiment can be obtained.

[0235] <21. Third-third embodiment> The photodetector 1 according to the third-third embodiment of the present disclosure will be described with reference to Figure 63. The third-third embodiment describes a 21st example in which the connection structure between the semiconductor layer 40 and the wiring 463 that supplies potential to the semiconductor layer 40 is changed in the photodetector 1 according to the third-first embodiment.

[0236] [Device Configuration of Photodetector 1] Figure 63 shows an example of a schematic cross-sectional configuration of the photodetector 1 according to the third-third embodiment. As shown in Figure 63, the number of plug wires 462 connecting the contact area 424 and the wiring 463 has been increased in the photodetector 1. For example, one plug wire 462 is provided for each pixel 10.

[0237] The components of the third-third embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the third-first embodiment.

[0238] [Effects and Effects] According to the photodetector 1 of the third-third embodiment, the same effects and effects as those obtained with the photodetector 1 of the third-first embodiment can be obtained.

[0239] Furthermore, in the photodetector 1, as shown in Figure 63, the number of plug wires 462 connecting the contact area 424 and the wiring 463 has been increased. As a result, a reference voltage GND can be supplied to the semiconductor layer 40 without being constrained by the wiring layout of the wiring layer 45, thereby enabling the potential of the semiconductor layer 40 to be maintained more stably.

[0240] <22. Third-Fourth Embodiment> The photodetector 1 according to the third-fourth embodiment of the present disclosure will be described with reference to Figure 64. The third-fourth embodiment describes a 22nd example in which the connection structure between the semiconductor layer 40 and the wiring that supplies potential to the semiconductor layer 40 is changed in the photodetector 1 according to the third-first embodiment.

[0241] [Device Configuration of Photodetector 1] Figure 64 shows an example of a schematic cross-sectional configuration of the photodetector 1 according to the third-third embodiment. As shown in Figure 64, in the photodetector 1, a contact region 424 is provided on the second surface 40B side of the semiconductor layer 40 of the second substrate 1B. The contact region 424 is provided for each pixel circuit 20 in the pixel region 100.

[0242] The contact area 424 is electrically connected to the electrode wiring 463 through plug wiring 462 and wiring 461. This wiring 463 is provided for each pixel circuit 20.

[0243] Meanwhile, electrodes 553 are arranged in the wiring layer 55 of the third substrate 1C, and the electrodes 553 are electrically connected to the wiring 551 through plug wiring 552. The electrodes 553, plug wiring 552, and wiring 551 are arranged for each pixel circuit 20. The electrodes 553 are electrically connected to the wiring 463 by a Cu-Cu connection structure, and the second substrate 1B is laminated to the third substrate 1C. The reference voltage GND is supplied from the third substrate 1C side to the second substrate 1B.

[0244] The components of the third to fourth embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the third to fourth embodiment.

[0245] [Effects] The photodetector 1 according to the third-fourth embodiment can obtain the same effects as those obtained with the photodetector 1 according to the third-first embodiment.

[0246] Furthermore, in the photodetector 1, as shown in Figure 64, the arrangement density of electrodes 553 of the third substrate 1C can be increased, particularly in the pixel region 100. For example, when the arrangement density of electrodes 553 is increased, step shapes are less likely to occur during the planarization process used in the manufacturing process of electrodes 553, specifically the planarization process using the CMP method. If step shapes occur, problems such as short circuits between electrodes 553 can be expected. Therefore, since such problems can be eliminated, the manufacturing yield can be improved.

[0247] <23. Third-Fifth Embodiment> The photodetector 1 according to the third-fifth embodiment of the present disclosure will be described with reference to Figure 65. The third-fifth embodiment describes a 23rd example in which the connection structure between the semiconductor layer 40 and the wiring that supplies potential to the semiconductor layer 40 is changed in the photodetector 1 according to the third-fourth embodiment.

[0248] [Device Configuration of Photodetector 1] Figure 65 shows an example of a schematic cross-sectional configuration of the photodetector 1 according to the third to fifth embodiment. As shown in Figure 65, in the photodetector 1, a plurality of contact regions 424 arranged on the second surface 40B side of the semiconductor layer 40 of the second substrate 1B are electrically connected to wiring 461 and wiring 463, which are common wirings. Wiring 461 and wiring 463 are electrically connected across two or more contact regions 424.

[0249] On the other hand, the electrodes 553 arranged in the wiring layer 55 of the third substrate 1C are similarly formed as common wiring for multiple contact regions 424.

[0250] The components of the third to fifth embodiments, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the third to fourth embodiment.

[0251] [Effects] The photodetector 1 according to the third to fifth embodiment can obtain the same effects as those obtained with the photodetector 1 according to the third to fourth embodiment.

[0252] <24. Third-Sixth Embodiment> The photodetector 1 according to the third-sixth embodiment of the present disclosure will be described with reference to Figure 66. The third-sixth embodiment describes the 24th example, which combines the photodetector 1 according to the third-first embodiment and the photodetector 1 according to the third-fourth embodiment.

[0253] [Device Configuration of Photodetector 1] Figure 66 shows an example of a schematic cross-sectional configuration of the photodetector 1 according to the third to sixth embodiment. As shown in Figure 66, in the photodetector 1, a contact region 424 is provided on the second surface 40B side of the semiconductor layer 40 of the second substrate 1B. The contact region 424 is provided over the entire area of ​​the pixel region 100.

[0254] The contact area 424 is electrically connected to the electrode wiring 463 through plug wiring 462 and wiring 461. This wiring 463 is provided for each pixel circuit 20.

[0255] Meanwhile, electrodes 553 are arranged in the wiring layer 55 of the third substrate 1C, and the electrodes 553 are electrically connected to the wiring 551 through plug wiring 552. The electrodes 553, plug wiring 552, and wiring 551 are arranged for each pixel circuit 20. The electrodes 553 are electrically connected to the wiring 463 by a Cu-Cu connection structure, and the second substrate 1B is laminated to the third substrate 1C. The reference voltage GND is supplied from the third substrate 1C side to the second substrate 1B.

[0256] The components of the third-sixth embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the third-first embodiment or the third-fourth embodiment.

[0257] [Effects] According to the photodetector 1 of the third to sixth embodiment, the same effects as those obtained with the photodetector 1 of the third to fourth embodiment can be obtained.

[0258] <25. Third-Seventh Embodiment> The photodetector 1 according to the third-seventh embodiment of the present disclosure will be described with reference to Figure 67. The third-seventh embodiment describes a 25th example in which the connection structure between the semiconductor layer 40 and the wiring 463 that supplies potential to the semiconductor layer 40 is changed in the photodetector 1 according to the third-first embodiment.

[0259] [Device Configuration of Photodetector 1] Figure 67 shows an example of a schematic cross-sectional configuration of the photodetector 1 according to the third to seventh embodiment. As shown in Figure 67, in the photodetector 1, a contact region 424 is provided on the second surface 40B side of the semiconductor layer 40 of the second substrate 1B. The contact region 424 is provided for each pixel circuit 20 in the pixel region 100.

[0260] The contact area 424 is electrically connected to the wiring 463 through the plug wiring 462. This wiring 463 is formed as a common wiring in the pixel area 100.

[0261] On the other hand, the semiconductor layer 40 has an n-type well region 401 as a semiconductor layer. A contact region 426 is provided in the n-type well region 401 on either the first surface 40A side or the second surface 40B side of the semiconductor layer 40. The contact region 426 is a so-called well contact region, formed with the same conductivity type as the n-type well region 401, and having a higher impurity density than the n-type well region 401. In other words, the contact region 426 is an n-type semiconductor region. Although not shown in the figure, the power supply voltage VDD is supplied to the contact region 426.

[0262] The components of Embodiment 3-7 other than those described above are the same as or substantially the same as the components of the photodetector 1 according to Embodiment 3-1.

[0263] [Effects and Effects] According to the photodetector 1 of the third-seventh embodiment, the same effects and effects as those obtained with the photodetector 1 of the third-first embodiment can be obtained.

[0264] <26. Third-Eighth Embodiment> The photodetector 1 according to the third-eighth embodiment of the present disclosure will be described with reference to Figure 68. The third-eighth embodiment describes the 26th example in which the connection structure between the semiconductor layer 40 and the wiring that supplies potential to the semiconductor layer 40 is changed in the photodetector according to the third-first embodiment.

[0265] [Device Configuration of Photodetector 1] Figure 68 shows an example of a schematic cross-sectional configuration of the photodetector 1 according to the third-eighth embodiment. As shown in Figure 68, in the photodetector 1, a contact region 424 is provided on the first surface 40A side of the semiconductor layer 40 of the second substrate 1B. The contact region 424 is provided for each pixel circuit 20 in the pixel region 100.

[0266] The contact area 424 is electrically connected to the plug wiring 452 and wiring 451 in the wiring layer 45. Furthermore, wiring 451 is electrically connected to wiring 463 of the wiring layer 46, which is located on the second surface 40B side of the semiconductor layer 40, through through wiring 464 that penetrates the semiconductor layer 40 in the thickness direction.

[0267] The components of the third-eighth embodiment, other than those described above, are the same as or substantially the same as the components of the photodetector 1 according to the third-first embodiment.

[0268] [Effects and Effects] According to the photodetector 1 of the third-eighth embodiment, the same effects and effects as those obtained with the photodetector 1 of the third-first embodiment can be obtained.

[0269] <27. Fourth Embodiment> A photodetector 1 according to the fourth embodiment of the present disclosure will be described with reference to the drawings. Figure 69 is a diagram showing an example of a schematic cross-sectional configuration of the photodetector 1 according to the fourth embodiment. Figure 70 shows an example of an enlarged cross-sectional configuration of the base body 1B of the photodetector 1, and Figure 71 shows an example of a planar configuration of a part of the pixel circuit 20 of the photodetector 1. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0270] The photodetector 1 has a substrate 1A, a substrate 1B, and a substrate 1C, as shown in the example in Figure 69. The photodetector 1 has a configuration in which substrates 1A, 1B, and 1C are stacked. Substrates 1A, 1B, and 1C can also be called the first layer (first hierarchy), the second layer (second hierarchy), and the third layer (third hierarchy).

[0271] Substrate 1A has a semiconductor layer 30 and a wiring layer 35. Substrate 1B has a semiconductor layer 40, a wiring layer 45 and a wiring layer 46. Substrate 1C also has a semiconductor layer 50 and a wiring layer 55. From the side where light L is incident, the semiconductor layer 30, wiring layer 35, wiring layer 46, semiconductor layer 40, wiring layer 45, wiring layer 55 and semiconductor layer 50 are provided.

[0272] The semiconductor layer 30 of the substrate 1A has opposing surfaces 30A and 30B. Surface 30B is the surface opposite to surface 30A. Surface 30A of the semiconductor layer 30 is, for example, the light-receiving surface (i.e., the light incident surface). Surface 30B of the semiconductor layer 30 is provided with a gate electrode, a gate insulating film (e.g., a gate oxide film), etc.

[0273] Each pixel 10 is provided in the semiconductor layer 30. The photoelectric conversion elements PD are provided between surfaces 30A and 30B of the semiconductor layer 30. For example, multiple photoelectric conversion elements PD are embedded in the semiconductor layer 30. The photoelectric conversion elements PD can also be called photoelectric conversion regions or light-receiving elements.

[0274] The semiconductor layer 40 of substrate 1B has opposing surfaces 40A and 40B. Surface 40B is the surface opposite to surface 40A. The semiconductor layer 50 of substrate 1C has opposing surfaces 50A and 50B. Surface 50B is the surface opposite to surface 50A. Surface 40A of semiconductor layer 40 and surface 50A of semiconductor layer 50 are provided with a gate electrode, a gate insulating film, etc., respectively.

[0275] In the photodetector 1, for example, the semiconductor layer 30 has a surface 30B as its front and a surface 30A as its back. The semiconductor layer 40 has a surface 40A as its front (i.e., the first surface of the semiconductor layer 40) and a surface 40B as its back. The semiconductor layer 50 has a surface 50A as its front and a surface 50B as its back.

[0276] A wiring layer 35 is provided on the 30B side of the semiconductor layer 30. A wiring layer 45 is provided on the 40A side of the semiconductor layer 40, and a wiring layer 46 is provided on the 40B side of the semiconductor layer 40. A wiring layer 55 is also provided on the 50A side of the semiconductor layer 50. The wiring layer 35 has a plurality of electrodes 353, and the wiring layer 46 has a plurality of wirings 463. The wiring layer 45 has a plurality of electrodes 453, and the wiring layer 55 has a plurality of electrodes 553.

[0277] Electrode 353, wiring 463, electrode 453, and electrode 553 are each formed using, for example, copper (Cu). Electrode 353, wiring 463, electrode 453, and electrode 553 are used for bonding between substrates and can also be called bonding electrodes. Bonding electrodes 353, 453, 553, and wiring 463 may be made using nickel (Ni), cobalt (Co), or other materials.

[0278] For example, a substrate 1A having a semiconductor layer 30 and a substrate 1B having a semiconductor layer 40 are bonded together by a junction between an electrode 353 and a wiring 463 made of Cu, i.e., a Cu-Cu junction. In the photodetector 1, the circuit provided on substrate 1A and the circuit provided on substrate 1B are electrically connected via the electrode 353 and the wiring 463.

[0279] Substrate 1A and substrate 1B are stacked together by bonding between electrodes, such that surfaces 30B and 40B face each other. That is, substrate 1A and substrate 1B are bonded together such that the surface of semiconductor layer 30 and the back surface of semiconductor layer 40 face each other. Substrate 1A and substrate 1B are bonded together face-to-back (FtoB). As an example, substrate 1A and substrate 1B are stacked together such that the wiring layer 35 faces the wiring layer 46.

[0280] Furthermore, the substrate 1B and substrate 1C are bonded together by a junction between electrodes 453 and 553, which are made of Cu, i.e., a Cu-Cu junction. In the photodetector 1, the circuit provided on substrate 1B and the circuit provided on substrate 1C are electrically connected via electrodes 453 and 553.

[0281] Substrate 1B and substrate 1C are stacked by bonding between electrodes so that surfaces 40A and 50A face each other. That is, substrate 1B and substrate 1C are bonded so that the surface of semiconductor layer 40 and the surface of semiconductor layer 50 face each other. Substrate 1B and substrate 1C are bonded face-to-face (FtoF). As an example, substrate 1B and substrate 1C are stacked so that the wiring layer 45 faces the wiring layer 55.

[0282] The aforementioned transfer transistor TR is provided on the surface 30B side of the semiconductor layer 30. Furthermore, a semiconductor region 323, which is part of the floating diffusion FD, is provided in the semiconductor layer 30. The semiconductor region 323 is, for example, an n-type semiconductor region and is provided as a floating diffusion region. The semiconductor region 323 is also, for example, one of the source region and drain region of the transfer transistor TR.

[0283] The substrate 1B is provided with at least a portion of the pixel circuit 20 described above. The substrate 1B is provided with some or all of the multiple circuit elements of the pixel circuit 20 (amplifier transistor AMP, reset transistor RST, selection transistor SEL, switching transistor FDG, etc.). The pixel circuit 20 has, for example, the circuit configuration shown in Figure 3 or Figure 33.

[0284] The substrate 1C is provided with at least some of the above-mentioned vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, output circuit Out, and control circuit CC (see Figure 1). As an example, the AD conversion circuit and horizontal selection switch of the column signal processing circuit CS are provided in the semiconductor layer 50 and the wiring layer 55.

[0285] The pixel circuit 20 has a plurality of pixel transistors, including, for example, an amplification transistor AMP and a selection transistor SEL, and is provided on the substrate 1B. The pixel circuit 20 is arranged for each pixel 10, or for every group of pixels 10. The light detection device 1 may have a configuration in which a group of pixels 10 (for example, four adjacent pixels 10) share one pixel circuit 20.

[0286] The amplification transistor AMP has a gate electrode 422 (referred to as gate electrode 422a) and a gate insulating film 421a, which are provided on the side opposite to the surface 40A of the semiconductor layer 40. The gate electrode 422a is formed on the gate insulating film 421a. The amplification transistor AMP also has two main electrodes 423 (electrode 423a, electrode 423b), namely a source region and a drain region.

[0287] The gate electrode 422a and the gate insulating film 421a are provided, for example, by carving into the surface 40B side of the semiconductor layer 40. The gate insulating film 421a is, for example, a gate oxide film and is provided between the gate electrode 422a and the region in the semiconductor layer 40 where a channel is formed (this is a channel formation region, or can also be called a channel region). A sidewall may be provided on the side (side wall) of the gate electrode 422a.

[0288] The semiconductor layer 40 has a recessed portion Rd, for example, as shown in Figures 69 and 70. The recessed portion Rd is provided on the side of the semiconductor layer 40 opposite to the surface 40A. The recessed portion Rd is provided so as to recess a part of the semiconductor layer 40 from the side of the surface 40B. The recessed portion Rd can also be called a recessed region.

[0289] The recessed portion Rd is formed in the substrate 1B by recessing a part of the semiconductor layer 40. The recessed portion Rd can also be called an opening. The recessed portion Rd is an opening and is defined by the end face (side surface) of the semiconductor layer 40. In plan view (i.e., when viewed in the XY plane), the recessed portion Rd may have a rectangular shape or other shapes.

[0290] The gate electrode 422a and the gate insulating film 421a are provided in the recessed portion Rd. The gate electrode 422a and the gate insulating film 421a are arranged in the recessed portion Rd, for example, between surface 40A and surface 40B. The gate electrode 422a and the gate insulating film 421a are provided so as to be embedded in the recessed portion Rd. In addition, an insulating film (SiO₂) is applied around the gate electrode 422a in the recessed portion Rd. ２ (etc.) are provided to be embedded.

[0291] The electrodes 423a and 423b of the amplification transistor AMP are each provided in the semiconductor layer 40. Each of electrodes 423a and 423b is provided, for example, from the bottom (lower end) of the recessed portion Rd to the surface 40A of the semiconductor layer 40. As an example, electrodes 423a and 423b are formed to be located to the left and right of the gate electrode 422a.

[0292] Electrode 423a is one of the source and drain regions of the amplification transistor AMP, for example, the drain region. Electrode 423b is the other of the source and drain regions of the amplification transistor AMP, for example, the source region. Electrode 423a is electrically connected, for example, to the wiring (power line) to which the power supply voltage VDD is supplied. In the example shown in Figure 70, electrode 423b is also one of the source and drain regions of the selection transistor SEL.

[0293] The selection transistor SEL is provided, for example, on the surface 40A side of the semiconductor layer 40. The selection transistor SEL has a gate electrode 422 (referred to as gate electrode 422s) and a gate insulating film 421s. The selection transistor SEL also has two main electrodes 423 (electrode 423b, electrode 423c) as the source region and drain region.

[0294] The gate electrode 422s and the gate insulating film 421s are provided on the surface 40A side of the semiconductor layer 40, as shown in the example in Figure 69 or Figure 70. The gate insulating film 421s is, for example, a gate oxide film and is provided between the gate electrode 422s and the channel formation region (i.e., channel region) in the semiconductor layer 40.

[0295] Electrode 423b is one of the source and drain regions of the selection transistor SEL, for example, the drain region. Electrode 423c is the other of the source and drain regions of the selection transistor SEL, for example, the source region. Electrode 423c is electrically connected to a signal line Lv, which is configured as a vertical signal line by means of contacts (vias) and wiring, for example.

[0296] The photodetector 1 has wiring La, as shown in the examples in Figures 69 and 70. The wiring La is provided on the substrate 1B on the surface 40B (i.e., the back surface) of the semiconductor layer 40. The wiring La is provided so as to extend in the thickness direction (i.e., the Z-axis direction) of the substrate 1B. The wiring La is arranged for each pixel circuit 20 in the pixel region 100 (i.e., the pixel array).

[0297] The wiring La is connected between the semiconductor region 323, which is a floating diffusion region (FD region), and the gate electrode 422a of the amplification transistor AMP. The semiconductor region 323 and the gate electrode 422a are electrically connected to each other via the wiring La. The wiring La is part of the floating diffusion FD and is provided as floating diffusion wiring (FD wiring).

[0298] The wiring La is provided, for example, in the wiring layer 46 and the recessed portion Rd of the substrate 1B. The wiring La extends in the thickness direction (Z-axis direction) of the wiring layer 46 (or semiconductor layer 40) between the wiring 463 in the wiring layer 46 and the gate electrode 422a in the recessed portion Rd, connecting the wiring 463 and the gate electrode 422a.

[0299] The semiconductor region 32, which is an FD region, is electrically connected to the gate electrode 422a of the amplification transistor AMP via electrodes 353, wiring 463, and wiring La, which is an FD wiring. The amplification transistor AMP converts the signal charge generated by the photoelectric conversion element PD into a voltage signal and outputs it as a pixel signal to the signal line Lv via the selection transistor SEL.

[0300] Wiring La is formed using metallic materials such as tungsten (W), copper (Cu), titanium (Ti), nickel (Ni), and cobalt (Co). Wiring La may be formed from metallic materials or metallic compounds. Wiring La may be made of polysilicon (Poly-Si) or other conductive materials.

[0301] Figures 72A to 72L illustrate an example of a method for manufacturing the photodetector 1 according to the fourth embodiment. As shown in Figure 72A, a substrate 1B having a semiconductor layer 40 is prepared. Then, as shown in Figure 72B, a recessed portion Rd (i.e., an opening) is formed, for example, by etching. Furthermore, as shown in Figure 72C, an insulating film 431 (for example, an oxide film) is formed as the material for the gate insulating film 421a.

[0302] As shown in Figure 72D, the gate electrode 422a of the amplification transistor AMP is formed. Next, as shown in Figure 72E, an insulating film 432 (for example, an oxide film) is embedded and formed around the gate electrode 422a and the gate insulating film 421a. Then, as shown in Figure 72F, wiring La as FD wiring is formed in the recessed portion Rd.

[0303] As shown in Figure 72G, a substrate 1S is prepared to serve as a support substrate. Next, as shown in Figure 72H, a substrate 1B with recessed portions Rd and the like formed thereon is joined to the substrate 1S. Then, as shown in Figure 72I, the gate insulating film 421s and gate electrode 422s of the selected transistor SEL are formed on the surface 40A side of the semiconductor layer 40.

[0304] As shown in Figure 72J, contacts and an insulating layer 455 are formed on the surface 40A side of the semiconductor layer 40, and a wiring layer 45 is formed. Next, as shown in Figure 72K, the substrate 1B laminated on the substrate 1S and the substrate 1C on which the logic circuit etc. are provided are joined together. Then, after removing the substrate 1S, as shown in Figure 72L, a wiring layer 46 having wiring La and an insulating layer 465 etc. is formed.

[0305] Then, a substrate 1A having a semiconductor layer 30 on which a photoelectric conversion element PD, etc., is provided, and a wiring layer 35 is bonded to the substrate 1B which is laminated on the substrate 1C. After that, the optical filter 7, optical lens 8, etc. described above are formed. By the above manufacturing method, the light detection device 1 shown in Figure 69, etc., can be manufactured. Note that the above manufacturing method is just one example, and other manufacturing methods may be used.

[0306] [Effects] The photodetector 1 according to the fourth embodiment includes a first substrate (substrate 1A) including a first semiconductor layer (semiconductor layer 30) having a photoelectric conversion element (photoelectric conversion element PD) and a floating diffusion region (semiconductor region 323), a second substrate (substrate 1B) including a second semiconductor layer (semiconductor layer 40), which is stacked with the first substrate such that the surface (face 30B) of the first semiconductor layer faces the back surface (face 40B) of the second semiconductor layer opposite to the first surface, a first transistor (amplifier transistor AMP) having a first gate electrode (e.g., gate electrode 422a) provided on the side of the second semiconductor layer opposite to the first surface, a second transistor (selection transistor SEL) having a second gate electrode (e.g., gate electrode 422s) provided on the first surface side of the second semiconductor layer, and wiring (wiring La) connected between the floating diffusion region and the first gate electrode.

[0307] With the photodetector 1 configured in this way, the distance (spacing) between the FD region of substrate 1A and the amplification transistor AMP of substrate 1B can be shortened. The FD wiring can be shortened, and unwanted parasitic capacitance added to the floating diffusion can be reduced. This makes it possible to improve the conversion efficiency (i.e., the conversion gain).

[0308] Furthermore, compared to the case where FD wiring penetrates the semiconductor layer 40, the area of ​​the region in the semiconductor layer 40 where the pixel transistor is formed can be increased. Constraints on the size of the pixel transistor (e.g., gate width, gate length, etc.) can be relaxed. It becomes possible to realize an optical detection device that can relax design rule constraints.

[0309] [Modifications] (Modification 1) A photodetector 1 according to Modification 1 of the fourth embodiment of the present disclosure will be described. Figure 73 shows an example of an enlarged cross-sectional configuration of the base 1B of the photodetector 1 according to Modification 1. Figure 74 shows an example of a planar configuration of a part of the pixel circuit 20 of the photodetector 1 according to Modification 1.

[0310] The source region of the amplification transistor AMP, for example, electrode 423b, may be provided in the semiconductor layer 40 around at least a portion of the wiring La, which is an FD wiring. Electrode 423b is provided around the wiring La and gate electrode 422a formed in the recessed portion Rd, as shown in the example in Figure 73 or Figure 74.

[0311] The electrode 423b, which is the source region of the amplification transistor AMP, is provided so as to sandwich the wiring La and the gate electrode 422a in a plan view (i.e., when viewed in the XY plane), as shown in the example in Figure 74. The electrode 423b may also be provided so as to surround the wiring La and the gate electrode 422a in a plan view.

[0312] The electrode 423b is provided along the wiring La and the gate electrode 422a via the insulating film 432 of the recessed portion Rd. For example, the electrode 423b is formed from the surface 40A to the surface 40B of the semiconductor layer 40. The electrode 423b may also be in one of the source region and drain region (for example, the drain region) of the selection transistor SEL.

[0313] [Effects] In the photodetector 1 according to this modified example, the first transistor (amplifier transistor AMP) has a source region (e.g., electrode 423b) provided in the second semiconductor layer (semiconductor layer 40) in at least a part of the area around the wiring (wiring La).

[0314] With the photodetector 1 configured in this way, parasitic capacitance formed in the FD wiring can be added between the floating diffusion FD and the source region of the amplification transistor AMP of the source follower circuit. Unnecessary coupling (capacitive coupling) can be reduced, and the decrease in conversion efficiency caused by parasitic capacitance can be suppressed.

[0315] (Modification 2) A photodetector 1 according to Modification 2 of the fourth embodiment of the present disclosure will now be described. Figure 75 shows an example of an enlarged cross-sectional configuration of the base 1B of the photodetector 1 according to Modification 2. Figure 76 shows an example of a planar configuration of a part of the pixel circuit 20 of the photodetector 1 according to Modification 2.

[0316] The gate electrode 422a of the amplification transistor AMP may be provided on the surface 40B (i.e., the back side) of the semiconductor layer 40. The amplification transistor AMP has, for example, a gate insulating film 421a and a gate electrode 422a provided on the surface 40B of the semiconductor layer 40. The thickness of the semiconductor layer 40 (i.e., the thickness (width) in the Z-axis direction) can be changed as appropriate and may be relatively thin.

[0317] [Effects] In the photodetector 1 according to this modified example, the first gate electrode (gate electrode 422a) of the first transistor (amplifying transistor AMP) is provided on the back surface (surface 40B) of the second semiconductor layer (semiconductor layer 40). As a result, the length of the FD wiring La can be shortened, and unwanted parasitic capacitance added to the floating diffusion can be effectively reduced.

[0318] (Modification 3) A photodetector 1 according to Modification 3 of the fourth embodiment of the present disclosure will now be described. Figure 77 shows an example of an enlarged cross-sectional configuration of the base 1B of the photodetector 1 according to Modification 3. Figure 78 shows an example of a planar configuration of a part of the pixel circuit 20 of the photodetector 1 according to Modification 3.

[0319] The gate electrode 422a and gate insulating film 421a of the amplification transistor AMP are provided, for example, so as to sandwich a part of the semiconductor layer 40 (part P1 in the example shown in Figure 77). Part P1, which is a part of the semiconductor layer 40, has a fin shape and can also be called a fin portion. The amplification transistor AMP has part P1 as a channel region.

[0320] The amplification transistor AMP is configured as a Fin-type transistor. The gate insulating film 421a is provided between portion P1 and gate electrode 422a. Each of the gate electrode 422a and the gate insulating film 421a is provided, for example, from the side of the semiconductor layer 40B to the space between the side 40B and the side 40A.

[0321] The amplification transistor AMP is configured to have one or more fin portions, as shown in the example in Figure 77 or Figure 78. The amplification transistor AMP may also have, for example, a gate electrode 422a and a gate insulating film 421a provided so as to sandwich each of the multiple fin portions (part P1).

[0322] Furthermore, other pixel transistors (selection transistor SEL, reset transistor RST, or switching transistor FDG) may be configured as Fin-type transistors. Among the multiple pixel transistors, some may be configured as Fin-type transistors, while others are configured as planar-type transistors.

[0323] [Effects and Effects] In the photodetector 1 according to this modified example, the first gate electrode (gate electrode 422a) of the first transistor (amplifying transistor AMP) is provided so as to sandwich a part (for example, part P1) of the second semiconductor layer (semiconductor layer 40). In this modified example as well, the same effects and effects as those obtained with the photodetector 1 according to the fourth embodiment described above can be obtained.

[0324] (Modification 4) A photodetector 1 according to Modification 4 of the fourth embodiment of the present disclosure will now be described. Figure 79 shows an example of an enlarged cross-sectional configuration of the base 1B of the photodetector 1 according to Modification 4. Figure 80 shows an example of a planar configuration of a part of the pixel circuit 20 of the photodetector 1 according to Modification 4.

[0325] In the substrate 1B of the photodetector 1, at least a portion of the selection transistor SEL may be positioned on the opposite side of the gate electrode 422a of the amplification transistor AMP in the thickness direction (i.e., Z-axis direction) of the semiconductor layer 40. For example, the selection transistor SEL may be provided in the region below the recessed portion Rd where the gate electrode 422a is located.

[0326] In the examples shown in Figures 79 and 80, the gate electrode 422s, gate insulating film 421s, and electrode 423c of the selection transistor SEL are provided on the surface 40A of the semiconductor layer 40 so as to be on the opposite side from the gate electrode 422a of the amplification transistor AMP. When viewed from above or below the substrate 1B, the gate electrode 422s is provided so as to overlap at least a portion of the gate electrode 422a.

[0327] [Effects] In the photodetector 1 according to this modified example, at least a portion of the second transistor (selection transistor SEL) is positioned on the opposite side of the first gate electrode (gate electrode 422a) in the thickness direction of the second semiconductor layer (semiconductor layer 40). With the photodetector 1 configured in this way, the area of ​​the region where the pixel transistor is formed on the surface 40A (i.e., surface) side of the semiconductor layer 40 can be increased.

[0328] Figure 81 shows another example of an enlarged cross-sectional configuration of the base 1B of the photodetector 1 according to Modification 4 of the fourth embodiment of the present disclosure. Figure 82 also shows another example of a planar configuration of a part of the pixel circuit 20 of the photodetector 1 according to Modification 4.

[0329] The gate electrode 422a of the amplification transistor AMP may be provided on the side 40B of the semiconductor layer 40, as shown in the example in Figure 81. The photodetector 1 may have a configuration without a recessed portion Rd. With the photodetector 1 configured as shown in the examples in Figures 81 and 82, the length of the wiring La, which is FD wiring, can be shortened, and unwanted parasitic capacitance added to the floating diffusion can be effectively reduced.

[0330] (Modification 5) A photodetector 1 according to Modification 5 of the fourth embodiment of the present disclosure will now be described. Figure 83 shows an example of an enlarged cross-sectional configuration of the base 1B of the photodetector 1 according to Modification 5. Figure 84 shows an example of a planar configuration of a part of the pixel circuit 20 of the photodetector 1 according to Modification 5.

[0331] The gate electrode 422s of a pixel transistor other than the amplification transistor AMP, such as a selection transistor SEL, may be provided on the side opposite to the surface 40A of the semiconductor layer 40. For example, the gate electrode 422s and gate insulating film 421s of the selection transistor SEL may be provided by carving into the surface 40B of the semiconductor layer 40.

[0332] In the examples shown in Figures 83 and 84, in addition to the amplification transistor AMP, the gate electrode 422s and gate insulating film 421s of the selection transistor SEL are provided in the recessed portion Rd. The gate electrode 422s and gate insulating film 421s are arranged in the recessed portion Rd, for example, between surface 40A and surface 40B. The gate electrode 422s and gate insulating film 421s are provided so as to be embedded in the recessed portion Rd.

[0333] Electrodes 423a, 423b, and 423c are provided in the semiconductor layer 40. Each of electrodes 423a, 423b, and 423c is provided, for example, from the bottom (lower end) of the recessed portion Rd to the surface 40A of the semiconductor layer 40. As an example, electrodes 423b and 423c are formed to be located to the left and right of the gate electrode 422s.

[0334] As shown in the examples in Figures 83 and 84, the light detection device 1 has wiring La and wiring 463 (referred to as wiring 463a) electrically connected to the gate electrode 422a of the amplification transistor AMP, and wiring Lb and wiring 463 (referred to as wiring 463s) electrically connected to the gate electrode 422s of the selection transistor SEL.

[0335] The wiring Lb, like the wiring La, is provided on the substrate 1B on the side 40B of the semiconductor layer 40. The wiring Lb is provided so as to extend in the thickness direction (Z-axis direction) of the substrate 1B. As an example, the wiring Lb is arranged for each pixel circuit 20 in the pixel region 100 (pixel array).

[0336] The wiring Lb is provided, for example, in the wiring layer 46 and recessed portion Rd of the substrate 1B. The wiring Lb extends in the thickness direction of the wiring layer 46 (or semiconductor layer 40) between the wiring 463s in the wiring layer 46 and the gate electrode 422s in the recessed portion Rd, connecting the wiring 463s and the gate electrode 422s. The wiring Lb may be made of the same material (metal material, etc.) as the wiring La.

[0337] The gate electrode 422s of the selection transistor SEL is electrically connected to the wiring of the wiring layer 35 in the substrate 1A, for example, via wiring Lb, wiring 463s, and electrode 353. A control signal (e.g., a selection signal) is input to the gate electrode 422s via the wiring of the wiring layer 35, which serves as a control line.

[0338] The gate insulating film 421s and gate electrode 422s of the selection transistor SEL may be provided on the surface 40B of the semiconductor layer 40, rather than within the recessed portion Rd. The photodetector 1 may have a configuration without a recessed portion Rd. The reset transistor RST or the switching transistor FDG may be provided on the side of the semiconductor layer 40 opposite to the surface 40A.

[0339] [Effects] The photodetector 1 according to this modified example further comprises a third transistor (for example, a selection transistor SEL, a reset transistor RST, or a switching transistor FDG) having a third gate electrode provided on the side of the second semiconductor layer (semiconductor layer 40) opposite to the first surface. With the photodetector 1 configured in this way, it is possible to relax the constraints on the area of ​​the pixel transistors arranged in the semiconductor layer 40.

[0340] (Modification 6) A photodetector 1 according to Modification 6 of the fourth embodiment of the present disclosure will now be described. Figure 85 shows an example of an enlarged cross-sectional configuration of the base 1B of the photodetector 1 according to Modification 6. Figure 86 shows an example of a planar configuration of a part of the pixel circuit 20 of the photodetector 1 according to Modification 6.

[0341] The amplification transistor AMP is provided on the 40B side of the semiconductor layer 40, and the selection transistor SEL is provided on the 40A side of the semiconductor layer 40 so as to be on the opposite side from the amplification transistor AMP. The switching transistor FDG is provided on the 40B side of the semiconductor layer 40, and the reset transistor RST is provided on the 40A side of the semiconductor layer 40 so as to be on the opposite side from the switching transistor FDG.

[0342] The switching transistor FDG has a gate electrode 422 (referred to as gate electrode 422f) and a gate insulating film 421 (referred to as gate insulating film 421f). The switching transistor FDG also has two main electrodes 423 (electrode 423d and electrode 423e) as the source region and drain region.

[0343] Electrode 423d is one of the source and drain regions of the switching transistor FDG, for example, the source region. Electrode 423e is the other of the source and drain regions of the switching transistor FDG, for example, the drain region. The gate electrode 422a of the amplification transistor AMP and electrode 423d of the switching transistor FDG are electrically connected to the semiconductor region 323 (FD region) of the substrate 1A via wiring 463a.

[0344] The gate electrode 422f of the switching transistor FDG is electrically connected to the wiring of the wiring layer 35 of the substrate 1A via, for example, wiring Lc, wiring 463f, and electrode 353. A control signal is input to the gate electrode 422f via the wiring of the wiring layer 35, which serves as a control line. The wiring Lc is formed using, for example, the same material (metal material, etc.) as the wiring La.

[0345] The reset transistor RST has a gate electrode 422 (referred to as gate electrode 422r) and a gate insulating film 421 (referred to as gate insulating film 421r). The reset transistor RST also has two main electrodes 423 (electrode 423e and electrode 423f) as the source region and drain region.

[0346] Electrode 423e is one of the source and drain regions of the reset transistor RST, for example, the source region. Electrode 423f is the other of the source and drain regions of the reset transistor RST, for example, the drain region. Electrode 423f is electrically connected, for example, to a wiring (power line) to which the power supply voltage VDD is supplied. Note that electrode 423e is also one of the source and drain regions of the switching transistor FDG.

[0347] [Effects] According to the modified photodetector 1, unwanted parasitic capacitance added to floating diffusion can be effectively reduced, thereby improving conversion efficiency. Area efficiency can also be further improved. For example, the size constraints on each pixel transistor in the pixel circuit 20 can be relaxed. It becomes possible to realize a photodetector that can relax design rule constraints.

[0348] <28. Examples of Application to Mobile Devices> The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be realized as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0349] Figure 87 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0350] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 87, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0351] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0352] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0353] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0354] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0355] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0356] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0357] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0358] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0359] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 87, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0360] Figure 88 shows an example of the installation position of the imaging unit 12031.

[0361] In Figure 88, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0362] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0363] Figure 88 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0364] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0365] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0366] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0367] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0368] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein may be applied to the imaging unit 12031 of the configuration described above. By applying the technology described herein to the imaging unit 12031, the constraints of design rules can be eliminated.

[0369] <29. Examples of Application to Internal Body Information Acquisition Systems> The technology disclosed herein can be applied to various products. For example, the technology disclosed herein may be applied to endoscopic surgical systems.

[0370] Figure 89 is a block diagram showing an example of a schematic configuration of a patient's internal body information acquisition system using a capsule endoscope to which the technology described herein may be applied.

[0371] The internal body information acquisition system 10001 consists of a capsule endoscope 10100 and an external control device 10200.

[0372] The capsule endoscope 10100 is swallowed by the patient during the examination. The capsule endoscope 10100 has imaging and wireless communication functions, and while moving through the inside of organs such as the stomach and intestines by peristaltic movement until it is naturally expelled from the patient, it sequentially captures images of the inside of the organs (hereinafter also referred to as intracellular images) at predetermined intervals, and sequentially transmits information about these intracellular images wirelessly to an external control device 10200 outside the body.

[0373] The external control device 10200 comprehensively controls the operation of the internal body information acquisition system 10001. The external control device 10200 also receives information about internal body images transmitted from the capsule endoscope 10100 and generates image data for displaying the internal body images on a display device (not shown) based on the received information about the internal body images.

[0374] In this way, the internal information acquisition system 10001 can continuously obtain images of the patient's internal condition from the time the capsule endoscope 10100 is swallowed until it is expelled.

[0375] The configuration and functions of the capsule endoscope 10100 and the external control device 10200 will be explained in more detail.

[0376] The capsule endoscope 10100 has a capsule-shaped housing 10101, which houses a light source unit 10111, an imaging unit 10112, an image processing unit 10113, a wireless communication unit 10114, a power supply unit 10115, a power supply unit 10116, and a control unit 10117.

[0377] The light source unit 10111 is composed of a light source such as an LED (light-emitting diode) and illuminates the imaging field of view of the imaging unit 10112 with light.

[0378] The imaging unit 10112 consists of an image sensor and an optical system comprising a plurality of lenses provided in front of the image sensor. Reflected light (hereinafter referred to as observation light) irradiated onto the body tissue to be observed is focused by the optical system and incident on the image sensor. In the imaging unit 10112, the observation light incident on the image sensor is photoelectrically converted, and an image signal corresponding to the observation light is generated. The image signal generated by the imaging unit 10112 is provided to the image processing unit 10113.

[0379] The image processing unit 10113 is composed of processors such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), and performs various signal processing on the image signal generated by the imaging unit 10112. The image processing unit 10113 provides the processed image signal to the wireless communication unit 10114 as RAW data.

[0380] The wireless communication unit 10114 performs predetermined processing, such as modulation processing, on the image signal that has been processed by the image processing unit 10113, and transmits the image signal to the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 also receives control signals related to the drive control of the capsule endoscope 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 provides the control signals received from the external control device 10200 to the control unit 10117.

[0381] The power supply unit 10115 consists of an antenna coil for receiving power, a power regeneration circuit that regenerates power from the current generated in the antenna coil, and a boost circuit, etc. Power is generated in the power supply unit 10115 using the principle of so-called contactless charging.

[0382] The power supply unit 10116 is composed of a secondary battery and stores the power generated by the power supply unit 10115. In Figure 89, to avoid making the drawing complicated, arrows and other symbols indicating the destinations of the power supply from the power supply unit 10116 are omitted, but the power stored in the power supply unit 10116 can be supplied to the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117, and used to drive them.

[0383] The control unit 10117 is composed of a processor such as a CPU and appropriately controls the operation of the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the power supply unit 10115 according to control signals transmitted from the external control device 10200.

[0384] The external control device 10200 is composed of a processor such as a CPU or GPU, or a microcomputer or control board that combines a processor and memory elements such as memory. The external control device 10200 controls the operation of the capsule endoscope 10100 by transmitting control signals to the control unit 10117 of the capsule endoscope 10100 via the antenna 10200A. In the capsule endoscope 10100, for example, the light irradiation conditions for the object of observation in the light source unit 10111 may be changed by control signals from the external control device 10200. Also, the imaging conditions (for example, frame rate, exposure value, etc. in the imaging unit 10112) may be changed by control signals from the external control device 10200. Furthermore, the content of processing in the image processing unit 10113 and the conditions for the wireless communication unit 10114 to transmit image signals (for example, transmission interval, number of transmitted images, etc.) may be changed by control signals from the external control device 10200.

[0385] Furthermore, the external control device 10200 performs various image processing on the image signals transmitted from the capsule endoscope 10100 to generate image data for displaying the captured internal images on a display device. This image processing can include, for example, development processing (demosaic processing), image enhancement processing (bandwidth enhancement, super-resolution processing, NR (Noise reduction) processing, and / or image stabilization processing), and / or magnification processing (electronic zoom processing). The external control device 10200 controls the drive of the display device to display the captured internal images based on the generated image data. Alternatively, the external control device 10200 may record the generated image data on a recording device (not shown) or print it out on a printing device (not shown).

[0386] The above describes an example of an internal body information acquisition system to which the technology relating to this disclosure may be applied. The technology relating to this disclosure can be applied to the imaging unit 10112 of the configuration described above. By applying the technology relating to this disclosure to the imaging unit 10112, the constraints of design rules can be eliminated.

[0387] <30. Other Embodiments> This technology is not limited to the embodiments described above, and can be modified in various ways without departing from its essence. For example, this technology may be a combination of two or more photodetectors from among the photodetectors described in Embodiments 1-1 to 1-10, Embodiments 2-1 to 2-8, Embodiments 3-1 to 3-8, and Embodiment 4.

[0388] A photodetector according to a first embodiment of this disclosure comprises a photoelectric conversion element disposed on a first substrate that converts light into electric charge, and a pixel circuit that converts electric charge into a pixel signal. The pixel circuit is disposed on a second substrate on which the first substrate is stacked, and the pixel circuit is electrically connected to the photoelectric conversion element. The pixel circuit includes a transistor having three terminals disposed on the first surface side of the second substrate, and a first wiring is disposed on the second surface side of the second substrate facing the first surface. At least one of the three terminals of the transistor is electrically connected to the first wiring through a first through-wiring that penetrates at least a portion of the second substrate in the thickness direction. With a photodetector configured in this way, the first wiring connected to the transistor of the pixel circuit is disposed on a wiring layer on the second surface side that is separate from the wiring layer on the first surface side of the second substrate. Therefore, constraints on the wiring layout of the wiring layer are relaxed, and constraints on design rules can be eliminated.

[0389] In the photodetector according to the second embodiment of the present disclosure, the second substrate is configured to include at least a semiconductor layer, and an insulator thicker than the thickness of the gate insulating film of the transistor is disposed between the first through-wiring and the semiconductor layer. With a photodetector configured in this way, the parasitic capacitance added to the floating diffusion can be effectively reduced, and the photoelectric conversion efficiency can be improved.

[0390] In the photodetector according to the third embodiment of this disclosure, the photodetector according to the first embodiment further comprises a second wiring arranged on the first surface side of the second substrate and electrically connected to one of the three terminals of the transistor. The first wiring is electrically connected to the transistor through the first through wiring and the second wiring. With the photodetector configured in this way, the first wiring connected to the transistor of the pixel circuit is arranged on a wiring layer on the second surface side of the second substrate, separate from the wiring layer on the first surface side. The first wiring is electrically connected to the transistor through the first through wiring and the second wiring. As a result, constraints on the wiring layout of the wiring layer are relaxed, and constraints on design rules can be eliminated.

[0391] In the photodetector according to the fourth embodiment of this disclosure, the pixel circuit is constructed to include an amplification transistor, a reset transistor, and a selection transistor, or further to include a floating diffusion conversion gain switching transistor, in the photodetector according to the third embodiment. The second wiring is a shared wiring that electrically connects the amplification transistor and the reset transistor. With a photodetector configured in this way, since the second wiring is a shared wiring, the number of wirings can be reduced, constraints on the wiring layout of the wiring layer can be relaxed, and constraints on design rules can be eliminated.

[0392] In the photodetector according to the fifth embodiment of this disclosure, in the photodetector according to the third embodiment, the pixel circuit is constructed to include an amplification transistor, a reset transistor and a selection transistor, or further to include a floating diffusion conversion gain switching transistor. The second wiring is a lead-out wiring that is drawn out from the selection transistor and electrically connects the selection transistor and the vertical signal line. With a photodetector configured in this way, since the second wiring is a lead-out wiring, the number of wirings can be reduced, constraints on the wiring layout of the wiring layer can be relaxed, and constraints on design rules can be eliminated.

[0393] In the photodetector according to the sixth embodiment of this disclosure, in the photodetector according to the third embodiment, the pixel circuit is constructed to include an amplification transistor, a reset transistor, and a selection transistor, or further to include a floating diffusion conversion gain switching transistor. A capacitive element is constructed in which a first through-wiring electrically connected to the reset transistor or the floating diffusion conversion gain switching transistor through a second wiring is used as the first electrode, a dielectric is interposed in the first through-wiring, and a second through-wiring penetrating the second substrate in the thickness direction is used as the second electrode. With a photodetector configured in this way, an additional capacitance used for switching the conversion efficiency can be easily constructed.

[0394] A photodetector according to a seventh embodiment of this disclosure comprises a photoelectric conversion element disposed on a first substrate and converting light into electric charge, and a pixel circuit disposed on a second substrate on which the first substrate is stacked, electrically connected to the photoelectric conversion element and converting the electric charge into a pixel signal. The second substrate is composed of a semiconductor layer. The pixel circuit is composed of a transistor disposed on the semiconductor layer on the first surface side of the second substrate facing the first substrate. On the second surface side of the second substrate facing the first surface, a contact region is disposed on the semiconductor layer having the same conductivity type as the semiconductor layer and a higher impurity density than the semiconductor layer. A first power supply wiring is disposed on the second surface side of the second substrate, electrically connected to the semiconductor layer through the contact region. With a photodetector configured in this way, the contact region is disposed on the second surface, which is the back side of the first surface of the second substrate on which the transistor of the pixel circuit is disposed. A power supply voltage is supplied to the semiconductor layer through the first power supply wiring. Therefore, constraints on wiring layout are relaxed and constraints on design rules can be eliminated.

[0395] A photodetector according to the eighth embodiment of the present disclosure comprises a first substrate including a first semiconductor layer having a photoelectric conversion element and a floating diffusion region; a second substrate including a second semiconductor layer, which is stacked with the first substrate such that the surface of the first semiconductor layer faces the back surface of the second semiconductor layer opposite to the first surface; a first transistor having a first gate electrode provided on the side of the second semiconductor layer opposite to the first surface; a second transistor having a second gate electrode provided on the first surface side of the second semiconductor layer; and wiring connected between the floating diffusion region and the first gate electrode. With a photodetector configured in this way, it is possible to reduce the parasitic capacitance added to the floating diffusion and improve the conversion efficiency.

[0396] <Configuration of this technology> This technology has the following configuration. With this technology configured as described below, the constraints of design rules can be eliminated in an optical detection device.

[0397] (1-1) A photodetection device comprising: a photoelectric conversion element disposed on a first base body and converting light into electric charge; and a pixel circuit that converts electric charge into a pixel signal, wherein the pixel circuit is disposed on a second base body on which the first base body is stacked; the pixel circuit is electrically connected to the photoelectric conversion element; the pixel circuit includes a transistor having three terminals disposed on the first surface side of the second base body; a first wiring is disposed on the second surface side of the second base body facing the first surface; and at least one of the three terminals of the transistor is electrically connected to the first wiring through a first through wiring that penetrates at least a portion of the second base body in the thickness direction. (1-2) The photodetector according to (1-1), wherein the pixel circuit comprises an amplification transistor, a reset transistor, and a selection transistor, or further comprises a floating diffusion conversion gain switching transistor. (1-3) The photodetector according to (1-2), wherein in the pixel circuit, the gate electrode of one or more of the three terminals of a transistor selected from the reset transistor, the selection transistor, and the floating diffusion conversion gain switching transistor is electrically connected to the first through-wiring. (1-4) The photodetector according to (1-3), wherein the gate electrode of the transistor extends in a gate width direction intersecting the gate length direction from one main electrode to the other main electrode, and the first through-wiring is electrically connected at the extension of the gate electrode. (1-5) The photodetector according to (1-4), further comprising an element isolation region between the one main electrode and the other main electrode and the first through-wiring that electrically separates them.(1-6) The photodetector according to (1-5), wherein the element isolation region comprises a trench having a depth in the thickness direction of the second substrate and an insulating embedded member embedded in the trench. (1-7) The photodetector according to any one of (1-1) to (1-6), wherein the second substrate is composed of at least a semiconductor layer, and an insulator thicker than the thickness of the gate insulating film of the transistor is disposed between the first through-wiring and the semiconductor layer. (1-8) The photodetector according to (1-2), wherein the first through-wiring is electrically connected to one or more of the three terminals of the transistor, selected from one main electrode and the other main electrode. (1-9) The photodetector according to (1-2), wherein in the pixel circuit, at least a portion of the gate electrode of one or more of the three terminals of the transistor selected from the amplification transistor, the reset transistor, the selection transistor and the floating diffusion conversion gain switching transistor extends in the thickness direction of the second substrate, and the gate width dimension is expanded. (1-10) The photodetector according to any one of (1-1) to (1-9), wherein the first wiring and the first through-wiring are supplied with a control signal or power. (1-11) The photodetector according to any one of (1-1) to (1-10), wherein the first surface of the second substrate is facing the first substrate. (1-12) The photodetector according to any one of (1-1) to (1-10), wherein the second surface of the second substrate is facing the first substrate. (1-13) The photodetector according to any one of (1-1) to (1-10), wherein the first surface of the second substrate is facing the first substrate. (1-14) The photodetector according to any one of (1-1) to (1-13), wherein the first through-wiring is formed of different conductive materials for each of the three terminals of the transistor and the wiring.(1-15) The photodetector according to any one of (1-1) to (1-14), further comprising a third base body formed by stacking the first base body with the second base body interposed therebetween, wherein a logic circuit for controlling the pixel circuit is disposed on the third base body. (2-1) The photodetector according to any one of (1-1) to (1-15), further comprising a second wiring disposed on the first surface side of the second base body and electrically connected to one of the three terminals of the transistor, wherein the first wiring is electrically connected to the transistor through the first through wiring and the second wiring. (2-2) The photodetector according to (2-1), wherein the pixel circuit is constructed including an amplification transistor, a reset transistor and a selection transistor, or further including a floating diffusion conversion gain switching transistor, and the second wiring is a shared wiring that electrically connects the amplification transistor and the reset transistor. (2-3) The photodetector according to (2-1) or (2-2), wherein, viewed from the thickness direction of the second substrate, the first wiring is formed in a ring shape along the contour of the pixel circuit. (2-4) The photodetector according to (2-1), wherein the pixel circuit is constructed including an amplification transistor, a reset transistor and a selection transistor, or further including a floating diffusion conversion gain switching transistor, and the second wiring is a drawer wiring that is drawn out from the selection transistor and electrically connects the selection transistor and a vertical signal line. (2-5) The photodetector according to (2-1) or (2-4), wherein, viewed from the thickness direction of the second substrate, the first wiring is formed in a stripe shape.(2-6) The photodetector according to any one of (2-1) to (2-5), wherein the pixel circuit is constructed including an amplification transistor, a reset transistor and a selection transistor, or further including a floating diffusion conversion gain switching transistor, and the first through wiring electrically connected to the reset transistor or the floating diffusion conversion gain switching transistor through the second wiring is a first electrode, and a dielectric is interposed in the first through wiring, and a second through wiring penetrating the second substrate in the thickness direction is a second electrode. (2-7) The photodetector according to (2-6), wherein the first wiring is formed of Cu, each of the first through wiring and the second through wiring is formed of WSi, and the second wiring is formed of a compound of Si with one or more metals selected from Ti, Mo, Ni, Co and Pt, or of Si. (2-8) The photodetector according to any one of (2-1) to (2-7), wherein the cross-sectional area of ​​the first through-wiring is expanded along the direction of extension of the second wiring. (2-9) The photodetector according to any one of (2-1) to (2-8), wherein a first power wiring is arranged along the periphery of the first base body, and the first power wiring is electrically connected to the first wiring. (2-10) The photodetector according to any one of (2-1) to (2-8), further comprising a third base body having a second power wiring, wherein the first base body is stacked with the second base body interposed between them, and the first wiring is electrically connected to the second power wiring. (2-11) The photodetector according to (2-10), wherein a logic circuit for controlling the pixel circuit is arranged on the third base body.(3-1) A photodetection device comprising: a photoelectric conversion element disposed on a first substrate and converting light into electric charge; a pixel circuit disposed on a second substrate on which the first substrate is stacked and electrically connected to the photoelectric conversion element and converting electric charge into a pixel signal, wherein the second substrate is composed of a semiconductor layer; the pixel circuit is composed of a transistor disposed on the semiconductor layer on the first surface side of the second substrate facing the first substrate; a contact area is disposed on the semiconductor layer on the second surface side of the second substrate facing the first surface, having the same conductivity type as the semiconductor layer and a higher impurity density than the semiconductor layer; and a first power wiring is disposed on the second surface side of the second substrate, electrically connected to the semiconductor layer through the contact area. (3-2) The photodetector according to (3-1), comprising a pixel region in which a plurality of photoelectric conversion elements are arranged, wherein the contact region is disposed for each photoelectric conversion element, or for each of the plurality of photoelectric conversion elements, or over the entire surface of the pixel region. (3-3) The photodetector according to (3-1) or (3-2), wherein the first power wiring is disposed for each photoelectric conversion element, or for each of the plurality of photoelectric conversion elements. (3-4) The photodetector according to any one of (3-1) to (3-3), wherein the first substrate is laminated with the second substrate interposed between them, and further comprises a third substrate having a second power wiring, wherein the first power wiring is electrically connected to the second power wiring. (3-5) The photodetector according to (3-1), wherein a plurality of contact regions are disposed on the photoelectric conversion elements. (3-6) The photodetector according to (3-2), wherein the first power supply wiring extends from the pixel area to the surrounding peripheral areas. (3-7) The photodetector according to (3-4), wherein the second power supply wiring is provided for each photoelectric conversion element, or for each of the multiple photoelectric conversion elements. (3-8) The photodetector according to (3-6), wherein the second power supply wiring extends to the peripheral areas.(4-1) A photodetector comprising: a first substrate including a first semiconductor layer having a photoelectric conversion element and a floating diffusion region; a second substrate including a second semiconductor layer, which is stacked with the first substrate such that the surface of the first semiconductor layer faces the back surface of the second semiconductor layer opposite to the first surface; a first transistor having a first gate electrode provided on the side of the second semiconductor layer opposite to the first surface; a second transistor having a second gate electrode provided on the side of the second semiconductor layer opposite to the first surface; and wiring connected between the floating diffusion region and the first gate electrode. (4-2) The photodetector according to (4-1), wherein the first transistor is an amplifying transistor. (4-3) The photodetector according to (4-1) or (4-2), wherein the second substrate has a recess provided on the side of the second semiconductor layer opposite to the first surface, and the first gate electrode is provided in the recess. (4-4) The photodetector according to (4-3), wherein the first transistor has a source region provided in the second semiconductor layer in at least a portion of the periphery of the wiring. (4-5) The photodetector according to (4-3) or (4-4), wherein the first gate electrode is provided so as to sandwich a portion of the second semiconductor layer. (4-6) The photodetector according to any one of (4-3) to (4-5), wherein at least a portion of the second transistor is provided so as to be located on the opposite side of the first gate electrode in the thickness direction of the second semiconductor layer. (4-7) The photodetector according to any one of (4-3) to (4-6), further comprising a third transistor having a third gate electrode provided on the opposite side of the first surface of the second semiconductor layer. (4-8) The photodetector according to (4-1) or (4-2), wherein the first gate electrode is provided on the back side of the second semiconductor layer. (4-9) The photodetector according to (4-8), wherein at least a portion of the second transistor is provided to be located on the opposite side of the first gate electrode in the thickness direction of the second semiconductor layer.(4-10) The photodetector according to (4-8) or (4-9), further comprising a third transistor having a third gate electrode provided on the side of the second semiconductor layer opposite to the first surface.

[0398] This application claims priority based on Japanese Patent Application No. 2024-196259, filed with the Japan Patent Office on 8 November 2024, and all contents of that application are incorporated herein by reference.

[0399] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A photodetector comprising a photoelectric conversion element disposed on a first substrate and converting light into electric charge, and a pixel circuit that converts electric charge into a pixel signal, wherein the pixel circuit is disposed on a second substrate on which the first substrate is stacked, the pixel circuit is electrically connected to the photoelectric conversion element, the pixel circuit includes a transistor having three terminals disposed on the first surface side of the second substrate, a first wiring is disposed on the second surface side of the second substrate facing the first surface, and at least one of the three terminals of the transistor is electrically connected to the first wiring through a first through-wiring that penetrates at least a portion of the second substrate in the thickness direction.

2. The photodetector according to claim 1, wherein the pixel circuit comprises an amplification transistor, a reset transistor, and a selection transistor, or further comprises a floating diffusion conversion gain switching transistor.

3. The photodetector according to claim 2, wherein in the pixel circuit, the gate electrode of one or more transistors selected from the reset transistor, the selection transistor, and the floating diffusion conversion gain switching transistor is electrically connected to the first through-wiring.

4. The photodetector according to claim 3, wherein the gate electrode extends in a gate width direction intersecting the gate length direction from one main electrode to the other main electrode among the three terminals of the transistor, and the first through-wiring is electrically connected at the extended portion of the gate electrode.

5. The photodetector according to claim 4, further comprising an element isolation region between the one main electrode and the other main electrode and the first through-wiring, which electrically separates both.

6. The photodetector according to claim 5, wherein the element isolation region comprises a groove whose depth is in the thickness direction of the second substrate and an insulating embedded member embedded in the groove.

7. The photodetector according to claim 1, wherein the second substrate comprises at least a semiconductor layer, and an insulator thicker than the thickness of the gate insulating film of the transistor is disposed between the first through-wiring and the semiconductor layer.

8. The photodetector according to claim 2, wherein the first through-wiring is electrically connected to one or more of the three terminals of the transistor, selected from one main electrode and the other main electrode.

9. The photodetector according to claim 2, wherein in the pixel circuit, at least a portion of the gate electrode of one or more transistors selected from the amplification transistor, the reset transistor, the selection transistor, and the floating diffusion conversion gain switching transistor extends in the thickness direction of the second substrate, thereby expanding the gate width dimension.

10. The light detection device according to claim 1, wherein control signals or power are supplied to the first wiring and the first through-wiring.

11. The photodetector according to claim 1, further comprising a second wiring disposed on the first surface side of the second substrate and electrically connected to one of the three terminals of the transistor, wherein the first wiring is electrically connected to the transistor through the first through wiring and the second wiring.

12. The photodetector according to claim 11, wherein the pixel circuit comprises an amplification transistor, a reset transistor, and a selection transistor, or further comprises a floating diffusion conversion gain switching transistor, and the second wiring is a shared wiring that electrically connects the amplification transistor and the reset transistor.

13. The light detection device according to claim 11, wherein, when viewed from the thickness direction of the second substrate, the first wiring is formed in a ring shape along the contour of the pixel circuit.

14. The photodetector according to claim 11, wherein the pixel circuit comprises an amplification transistor, a reset transistor and a selection transistor, or further comprises a floating diffusion conversion gain switching transistor, and the second wiring is a lead wire drawn from the selection transistor and electrically connecting the selection transistor and a vertical signal line.

15. The photodetector according to claim 11, wherein the first wiring is formed in a stripe shape when viewed from the thickness direction of the second substrate.

16. The photodetector according to claim 11, wherein the pixel circuit is constructed including an amplification transistor, a reset transistor and a selection transistor, or further including a floating diffusion conversion gain switching transistor, and further comprises a capacitive element in which the first through-wiring, electrically connected to the reset transistor or the floating diffusion conversion gain switching transistor through the second wiring, is a first electrode, and a dielectric is interposed in the first through-wiring, and the second through-wiring, which penetrates the second substrate in the thickness direction, is a second electrode.

17. A photodetector comprising: a photoelectric conversion element disposed on a first substrate and converting light into electric charge; a pixel circuit disposed on a second substrate on which the first substrate is stacked and electrically connected to the photoelectric conversion element and converting electric charge into a pixel signal, wherein the second substrate is composed of a semiconductor layer; the pixel circuit is composed of a transistor disposed on the semiconductor layer on the first surface side of the second substrate facing the first substrate; on the second surface side of the second substrate facing the first surface, a contact region having the same conductivity type as the semiconductor layer and a higher impurity density than the semiconductor layer is disposed on the semiconductor layer; and a first power supply wiring electrically connected to the semiconductor layer through the contact region is disposed on the second surface side of the second substrate.

18. The photodetector according to claim 17, comprising a pixel region in which a plurality of photoelectric conversion elements are arranged, wherein the contact region is disposed for each photoelectric conversion element, or for each of the plurality of photoelectric conversion elements, or across the entire surface of the pixel region.

19. The photodetector according to claim 17, wherein the first power supply wiring is provided for each photoelectric conversion element, or for each of the multiple photoelectric conversion elements.

20. The photodetector according to claim 17, wherein the first substrate is laminated with the second substrate interposed between them, and further comprises a third substrate having a second power supply wiring, the first power supply wiring being electrically connected to the second power supply wiring.

21. A photodetector comprising: a first substrate including a first semiconductor layer having a photoelectric conversion element and a floating diffusion region; a second substrate including a second semiconductor layer, which is stacked with the first substrate such that the surface of the first semiconductor layer faces the back surface of the second semiconductor layer opposite to the first surface; a first transistor having a first gate electrode provided on the side of the second semiconductor layer opposite to the first surface; a second transistor having a second gate electrode provided on the side of the second semiconductor layer facing the first surface; and wiring connected between the floating diffusion region and the first gate electrode.

22. The photodetector according to claim 21, wherein the first transistor is an amplifying transistor.

23. The photodetector according to claim 21, wherein the second substrate has a recess provided on the side opposite to the first surface of the second semiconductor layer, and the first gate electrode is provided in the recess.

24. The photodetector according to claim 23, wherein the first transistor has a source region provided in the second semiconductor layer in at least a portion of the periphery of the wiring.

25. The photodetector according to claim 23, wherein the first gate electrode is provided so as to sandwich a part of the second semiconductor layer.

26. The photodetector according to claim 23, wherein at least a portion of the second transistor is provided so as to be located on the opposite side of the first gate electrode in the thickness direction of the second semiconductor layer.

27. The photodetector according to claim 23, further comprising a third transistor having a third gate electrode provided on the side of the second semiconductor layer opposite to the first surface.

28. The photodetector according to claim 21, wherein the first gate electrode is provided on the back side of the second semiconductor layer.

29. The photodetector according to claim 28, wherein at least a portion of the second transistor is provided so as to be located on the opposite side of the first gate electrode in the thickness direction of the second semiconductor layer.

30. The photodetector according to claim 28, further comprising a third transistor having a third gate electrode provided on the side of the second semiconductor layer opposite to the first surface.

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