Circuit board and semiconductor package

Abstract

This circuit board comprises: a first insulating layer; a second insulating layer which is arranged on the first insulating layer and which includes a first through-hole; and a third insulating layer which is arranged on the second insulating layer and which includes a second through-hole at least partially overlapping the first through-hole in the vertical direction, wherein: the third insulating layer includes a first region having a first thickness in the vertical direction, and a second region having a second thickness that is smaller than the first thickness in the vertical direction; and, in the horizontal direction perpendicular to the vertical direction, the second region is disposed closer to the second through-hole than the first region.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products such as AI and servers have been progressing toward multi-functionality and high speed. To respond to this trend, high-layer and large-area circuit board technologies are also developing rapidly to keep pace with the fast-advancing semiconductor chip manufacturing technology.

[0004] Furthermore, regarding mobile products such as smartphones and tablets, the thickness of circuit boards applied to miniaturize finished electronic products is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to one another, which was previously considered only from the perspective of conventional semiconductor packaging.

[0005] A circuit board is formed by printing circuit line patterns using a conductive material, such as copper, onto an electrically insulating substrate; it is a general term for a board immediately before electronic components are mounted. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed on the surface of the flat plate to secure them.

[0006] Conventional embedded printed circuit boards have formed cavities for embedding components using a drill bit, used auxiliary materials such as release films for mounting components, or formed cavities for embedding components using sandblasting.

[0007] The formation of a cavity penetrating multiple insulating layers can be achieved by a process of forming a through hole in a lower insulating layer and then forming a through hole in an upper insulating layer placed on the lower insulating layer. However, there is a problem in that sagging of the upper insulating layer occurs in the inner wall region of the cavity due to various factors, such as differences in hardening degrees between multiple insulating layers. As a result of the sagging of the upper insulating layer, a portion of the upper insulating layer may encroach upon the cavity formation area, or difficulties may arise in securing space within the cavity for the placement of electronic devices.

[0008] In addition, when machining a cavity using a drill bit and / or a laser method, a metal layer may be placed on the lower insulating layer to function as an etch stopper in order to prevent damage to the lower insulating layer forming the bottom surface of the cavity. In this case, there is a problem that flip chip bonding of electronic devices is difficult on the lower insulating layer, which is the bottom surface of the cavity, and if the lower insulating layer is damaged, mechanical reliability problems such as cracks or reliability problems due to electrical short circuits may occur.

[0009]

[0010] The present invention provides a circuit board and a semiconductor package that can minimize sagging of the upper insulating layer in a structure including a cavity penetrating a plurality of insulating layers.

[0011] In addition, the invention provides a thin circuit board and semiconductor package with high reliability, which allows for easy flip-bonding of electronic devices on the cavity.

[0012]

[0013] A circuit board according to the present embodiment comprises: a first insulating layer; a second insulating layer disposed on the first insulating layer and including a first through hole; and a third insulating layer disposed on the second insulating layer and including a second through hole that overlaps at least a portion of the first through hole in a vertical direction, wherein the third insulating layer comprises a first region having a first thickness in a vertical direction and a second region having a second thickness smaller than the first thickness in the vertical direction, and with respect to a horizontal direction perpendicular to the vertical direction, the second region is disposed closer to the second through hole than the first region.

[0014] The second region may have a shape in which the thickness in the vertical direction gradually decreases as it approaches the second through hole.

[0015] The upper surface of the second region above may be a curved surface.

[0016] The upper surface of the second region above may be an inclined surface.

[0017] It may include a curved portion that roundly connects the upper surface of the third insulating layer and the inner wall of the second through hole.

[0018] The above second region can be connected to the above curved surface.

[0019] The third insulating layer may include a base portion disposed on the second insulating layer and a protrusion portion protruding from the base portion and surrounding the inner wall of the first through hole.

[0020] The lower surface of the above protrusion may come into contact with the upper surface of the first insulating layer.

[0021] The above protrusion may overlap the second insulating layer in a horizontal direction.

[0022] A semiconductor package according to the present embodiment comprises: a first insulating layer; a second insulating layer disposed on the first insulating layer and including a first through hole; a third insulating layer disposed on the second insulating layer and including a second through hole that overlaps at least a portion of the first through hole in a vertical direction; and a first electronic element disposed within the first through hole and the second through hole, wherein the third insulating layer comprises a first region having a first thickness in a vertical direction and a second region having a second thickness smaller than the first thickness in the vertical direction, and with respect to a horizontal direction perpendicular to the vertical direction, the second region is disposed closer to the second through hole than the first region.

[0023]

[0024] Through this embodiment, a plurality of regions with different thicknesses are formed within the third insulating layer, and among the plurality of regions, the region with a thinner thickness is positioned close to the cavity, thereby minimizing the reduction of the cavity space due to the sagging of the third insulating layer.

[0025] In addition, by implementing a support structure for the wiring layer and electronic components through protrusions, the bonding process of electronic components can be facilitated, and there is an advantage in that the reliability of the circuit board can be improved.

[0026] In addition, by forming a bonding structure with a protective layer or molding member through the concave surface of the protrusion, there is an advantage of being able to implement a bonding structure with the cavity more robustly.

[0027]

[0028] FIG. 1 is a plan view showing the upper surface of a circuit board according to a first embodiment of the present invention.

[0029] FIG. 2 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0030] FIG. 3 is an enlarged cross-sectional view illustrating the cavity formation structure through the first insulating layer, the second insulating layer, and the third insulating layer according to the first embodiment of the present invention.

[0031] FIG. 4 is a drawing illustrating a modified example of a circuit board according to the first embodiment of the present invention.

[0032] FIG. 5 is a cross-sectional view of a semiconductor package according to a first embodiment of the invention.

[0033] FIG. 6 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0034] FIG. 7 is a drawing showing an enlarged view of the cavity formation area according to a second embodiment of the present invention.

[0035] FIG. 8 is an enlarged view of a portion of FIG. 7.

[0036] FIG. 9 is a drawing illustrating a modified example of a cavity formation structure within a circuit board according to a second embodiment of the present invention.

[0037] FIGS. 10 and 11 are drawings for explaining the process of forming a wiring portion on the bottom surface of a cavity according to a second embodiment of the present invention.

[0038] FIGS. 12 to 14 are drawings illustrating modified examples of a structure forming a concave surface within a circuit board according to a second embodiment of the present invention.

[0039] FIGS. 15 to 17 are drawings illustrating various embedded structures of a cavity within a circuit board according to a second embodiment of the present invention.

[0040] FIG. 18 is a drawing illustrating a modified example of a circuit board according to a second embodiment of the present invention.

[0041] FIG. 19 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

[0042]

[0043] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0044] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0045] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0046] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) should be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, should be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it should be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it should not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0047] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0048] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0049] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0050] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0051] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0052] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0053] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0054] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0055] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0056] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0057] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0058] FIG. 1 is a plan view showing the upper surface of a circuit board according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, and FIG. 3 is an enlarged cross-sectional view showing the structure of forming a cavity through a first insulating layer, a second insulating layer, and a third insulating layer according to a first embodiment of the present invention.

[0059] Referring to FIGS. 1 to 3, a circuit board (10) according to the first embodiment of the present invention may include a plurality of insulating layers, a plurality of wiring portions, a plurality of via portions, and a protective layer (191, 196).

[0060] A circuit board (10) may include a plurality of insulating layers. The plurality of insulating layers may be arranged along a vertical direction. The plurality of insulating layers may include a first insulating layer (101), a second insulating layer (102) disposed on the first insulating layer (101), a third insulating layer (103) disposed on the second insulating layer (102), a fourth insulating layer (104) disposed on the lower surface of the first insulating layer (101), a fifth insulating layer (105) disposed on the lower surface of the fourth insulating layer (104), a sixth insulating layer (106) disposed on the lower surface of the fifth insulating layer (105), and a seventh insulating layer (107) disposed on the lower surface of the sixth insulating layer (106).

[0061] The first insulating layer (101), the fourth insulating layer (104), the fifth insulating layer (105), the sixth insulating layer (106), and the seventh insulating layer (107) may each be any insulating material, such as a photocurable and / or thermosetting material. As a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers.

[0062] The second insulating layer (102) and the third insulating layer (103) may be provided with a photocurable insulating material. Compared to manufacturing the cavity (150) using a drill bit and / or laser process, using a photocurable insulating material can provide a significant advantage in manufacturing process costs for manufacturing a cavity (150) with a large surface area. Additionally, the electrodes placed on the bottom surface of the cavity (150) can be freely designed, which can be advantageous for flip-bonding electronic devices such as semiconductor devices. Accordingly, the overall thickness of the semiconductor package is reduced, and the electrical operation of the semiconductor device can be further improved by increasing the number of bonded terminals compared to wire-bonding the semiconductor device placed within the cavity.

[0063] According to the embodiment, some of the insulating layers among the plurality of insulating layers may have a material different from that of other insulating layers. For example, at least one of the first insulating layer (101), the fourth insulating layer (104), and the fifth insulating layer (105) may be a prepreg (PPG) containing glass fibers in a resin, or at least one of the core layers may be a selected material, and accordingly, at least one of the first insulating layer (101), the fourth insulating layer (104), and the fifth insulating layer (105) may be a component forming the basis of the circuit board (10). For example, if the fourth insulating layer (104) is a core layer, the material of the fourth insulating layer (104) may include at least one selected from the group consisting of glass, resin, plastic, and metal. Additionally, the vertical thickness of the fourth insulating layer (104) may be thicker than the vertical thickness of the other insulating layers. Accordingly, by reinforcing the strength of the circuit board (10) through the fourth insulating layer (104), bending can be minimized.

[0064] The sixth insulating layer (106) and the seventh insulating layer (107) may also each be a photocurable insulator, and in this case, the sixth insulating layer (106) and the seventh insulating layer (107) may each be a PID (Photo Imageable Dielectric).

[0065] The vertical thickness of each of the first insulating layer (101), the fourth insulating layer (104), and the fifth insulating layer (105) may be thicker than the vertical thickness of each of the second insulating layer (102), the third insulating layer (103), the sixth insulating layer (106), and the seventh insulating layer (107). Accordingly, the bending of the circuit board (10) can be minimized through the first insulating layer (101), the fourth insulating layer (104), and the fifth insulating layer (105) which are positioned in the vertical center of the circuit board (10). To ensure the integrity of signal and / or power transmission or to alleviate the bending of the circuit board (10), the number of insulating layers positioned on the upper surface of the first insulating layer (101) and the number of insulating layers positioned on the lower surface of the fifth insulating layer (105) may be the same, but are not limited thereto and may be different from each other.

[0066] The number of stacked insulating layers described above is exemplary, and the circuit board (10) may have more or fewer insulating layers arranged in the vertical direction.

[0067] The circuit board (10) may include a protective layer (191, 196). The protective layer (191, 196) may include a first protective layer (191) disposed on the upper surface of the third insulating layer (103) and a second protective layer (196) disposed on the lower surface of the seventh insulating layer (107). The first protective layer (191) and the second protective layer (196) can perform the function of preventing short circuits between solders due to low wettability with the solder when a semiconductor device is disposed on the surface of the circuit board (10) with a material such as solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (191) and the second protective layer (196) may each be a solder resist.

[0068] The first protective layer (191) may include a hole (192) for exposing upward a wiring portion (113) disposed on the upper surface of the third insulating layer (103). The hole (192) may have a shape in which the horizontal width narrows as it approaches the third insulating layer (103). The first protective layer (191) may include a through hole that overlaps vertically with the cavity (150) to be described later. The second protective layer (196) may include a hole (197) for exposing downward a wiring portion (118) disposed on the lower surface of the seventh insulating layer (107). The hole (197) of the second protective layer (196) may have a shape in which the horizontal width narrows as it approaches the lower surface of the seventh insulating layer (107).

[0069] The circuit board (10) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0070] A plurality of wiring sections may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring sections is embedded within a plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring section may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring section being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which wiring sections are disposed on the first surface and the second surface of some of the insulating layers, respectively, and wiring sections are disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0071] A plurality of wiring sections may include a first wiring section (111) disposed on the upper surface of a first insulating layer (101), a second wiring section (112) disposed on the upper surface of a second insulating layer (102), a third wiring section (113) disposed on the upper surface of a third insulating layer (103), a fourth wiring section (114) disposed on the upper surface of a fourth insulating layer (104), a fifth wiring section (115) disposed on the upper surface of a fifth insulating layer (105), a sixth wiring section (116) disposed on the lower surface of the fifth insulating layer (105), a seventh wiring section (117) disposed on the lower surface of the sixth insulating layer (106), and an eighth wiring section (118) disposed on the lower surface of the seventh insulating layer (107). Additionally, the wiring section may include a pad section for connecting to a via section.

[0072] The via may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via may be disposed within the via hole.

[0073] The via section may include a first via section (123) penetrating at least a portion of the first insulating layer (101), a second via section (121) penetrating at least a portion of the second insulating layer (102), a third via section (122) penetrating at least a portion of the third insulating layer (103), a fourth via section (124) penetrating at least a portion of the fourth insulating layer (104), a fifth via section (125) penetrating at least a portion of the fifth insulating layer (105), a sixth via section (126) penetrating at least a portion of the sixth insulating layer (106), and a seventh via section (127) penetrating at least a portion of the seventh insulating layer (107).

[0074] The first via section (123) can electrically connect the first wiring section (111) and the fourth wiring section (114). The second via section (121) can electrically connect the first wiring section (111) and the second wiring section (112). The third via section (122) can electrically connect the second wiring section (112) and the third wiring section (113). The fourth via section (124) can electrically connect the fourth wiring section (114) and the fifth wiring section (115). The fifth via section (125) can electrically connect the fifth wiring section (115) and the sixth wiring section (116). The sixth via section (126) can electrically connect the sixth wiring section (116) and the seventh wiring section (117). The 7th via (127) can electrically connect the 7th wiring section (117) and the 8th wiring section (118).

[0075] The first via section (123), the second via section (121), the third via section (122), and the fourth via section (124) may each have a shape in which the horizontal width decreases as it goes downward. The fifth via section (125), the sixth via section (126), and the seventh via section (127) may each have a shape in which the horizontal width increases as it goes downward. Among the multiple via sections, the fifth via section (125) may be formed to have a longer vertical length than other via sections. In the case of the fifth via section (125), it is positioned to penetrate the fifth insulating layer (105) which is positioned at the vertical center of the circuit board (10), and as the fifth wiring section (115) and the sixth wiring section (116) are positioned on the upper and lower surfaces of the fifth insulating layer (105), respectively, the vertical length of the fifth via section (125) may be longer than that of other via sections. In addition, the expansion direction of a plurality of vias arranged vertically within the circuit board (10) based on the fifth insulating layer (105) can be reversed.

[0076] The circuit board (10) may include a cavity (150). The cavity (150) may be disposed on the circuit board (10). The cavity (150) may be disposed inside the first protective layer (190). At least a portion of the cavity (150) may be disposed inside the second insulating layer (102) and the third insulating layer (103). The cavity (150) may be disposed to overlap horizontally with the second insulating layer (102), the third insulating layer (103), and the first protective layer (191), respectively.

[0077] As illustrated in FIG. 1, a plurality of cavities (150) may be provided and arranged along the horizontal direction within the circuit board (10). The plurality of cavities (150) may be arranged to overlap each other in the horizontal direction. The cavities (150) may have a rectangular cross-sectional shape, but may also have a circular, triangular, or polygonal cross-sectional shape of pentagon or more.

[0078] A wiring section (160) is provided on the upper surface of the first insulating layer (101) forming the bottom surface of the cavity (150), so that a first electronic element (500) to be described later can be coupled thereto. The wiring section (160) may be provided in multiple numbers and arranged along the horizontal direction, and may overlap in the horizontal direction with the first wiring section (111) described above.

[0079] As illustrated in FIG. 3, the second insulating layer (102) may include a first through hole (152). The first through hole (152) may have a shape that penetrates from the upper surface to the lower surface of the second insulating layer (102). For example, through the first through hole (152), a portion of the upper surface of the first insulating layer (101) may be exposed from the second insulating layer (102) in a vertical direction. The first through hole (152) may form a placement area for the first electronic element (500, see FIG. 5) together with the second through hole (154) to be described later. In this case, a portion of the upper surface of the first insulating layer (101) may be provided as the bottom surface of the cavity (150) to form a placement surface for the electronic element (500).

[0080] The first through hole (152) may have a shape in which the horizontal width gradually narrows as it faces the first insulating layer (101). Accordingly, as shown in FIG. 3, the inner wall (142) of the first through hole (152) may have an inclined surface shape. The inner wall (142) of the first through hole (152) may be named the first inner wall. The first inner wall (142) may form a first angle with the upper surface of the first insulating layer (101) that forms the bottom surface of the cavity (150). The first angle may be an obtuse angle. According to an embodiment, the upper surface of the first insulating layer (101) includes one surface that constitutes the bottom surface of the cavity (150). The first angle described above refers to the angle formed between one side of the first insulating layer (101) constituting the bottom surface of the cavity (150) and the inner wall (142) of the first through hole (152).

[0081] The third insulating layer (103) may include a base (137) and a protrusion (138) protruding downward from the base (137). The base (137) may be placed on the second insulating layer (102). The base (137) may be placed so as to overlap vertically with the upper surface of the second insulating layer (102). The protrusion (138) protrudes downward from the lower surface of the base (137) and refers to a portion that is closer to the first insulating layer (101) than to the upper surface of the second insulating layer (102). The protrusion (138) may be placed to surround the first inner wall (142) of the second insulating layer (102). The protrusion (138) may be placed so as to overlap horizontally with the second insulating layer (102). The inner surface of the protrusion (138) surrounding the first inner wall (142) may have an inclined surface shape corresponding to the inclined surface of the first inner wall (142). The lower surface of the protrusion (138) may come into contact with the upper surface of the first insulating layer (101), which is the bottom surface of the cavity (150).

[0082] The third insulating layer (103) may include a second through hole (154). The second through hole (154) may be shaped to penetrate from the upper surface to the lower surface of the third insulating layer (103). Through the second through hole (154), a portion of the upper surface of the first insulating layer (101) may be exposed vertically from the second insulating layer (102) and the third insulating layer (103). The second through hole (154) may be arranged so that at least a portion overlaps the first through hole (152) in a vertical direction and / or a horizontal direction. The second through hole (154) may be formed on the inner side of the base (137) and on the inner side of the protrusion (138). The third insulating layer (103) may include a second inner wall (144) formed by the side of the base (137) facing the cavity (150) and the side of the protrusion (138). The second inner wall (144) may be arranged so that at least a portion overlaps the first inner wall (142) in a horizontal direction.

[0083] According to one embodiment, the second through hole (154) may have a shape in which the horizontal width gradually decreases as it faces the first insulating layer (101). The inner wall (144) of the second through hole (154) may have a curved shape. Accordingly, the third insulating layer (103) may have a curved area extending from the curved portion (146), which will be described later, to the inner wall (144).

[0084] As a variation, the inner wall (144) of the second through hole (154) may have an inclined surface shape. The second inner wall (144) may form a second angle on the through hole side with the upper surface of the first insulating layer (101) or the upper surface of the second insulating layer (102). The second angle may be an obtuse angle.

[0085] The second angle may be the same as the first angle formed by the upper surface of the first inner wall (142) and the first insulating layer (101). In this case, the horizontal width of the first protrusion (142) may be formed uniformly along the vertical direction.

[0086] As a variation, the second angle may be larger than the first angle. In this case, as the horizontal width of the first protrusion (138) covering the first inner wall (142) of the second insulating layer (102) increases downward, the bonding force between the second insulating layer (102) and the third insulating layer (103) in the electronic device placement area may be increased.

[0087] In another variation, the second angle may be smaller than the first angle. In this case, as the horizontal width of the lower region of the cavity (150) increases, there is an advantage in that a wider space for arranging electronic components within the cavity (150) can be secured.

[0088] The third insulating layer (103) may have regions with different vertical thicknesses. For example, the third insulating layer (103) may include a first region (132) having a first thickness (H1) in the vertical direction and a second region (134) having a second thickness (H2) in the vertical direction. The second thickness (H2) may be smaller than the first thickness (H1). The first region (132) and the second region (134) may be placed at the base (137) of the third insulating layer (103). Accordingly, the vertical thickness may be defined as the length from the upper surface of the second insulating layer (102) to the upper surface of the third insulating layer (103) which is vertically superimposed with the upper surface of the second insulating layer (102).

[0089] In the embodiment, the second thickness (H2) may not be a specific numerical value, but may represent a thickness within a range smaller than the first thickness (H1). Accordingly, the vertical thickness of the second region (134) may not be constant, but may vary along the horizontal direction within a range smaller than the first thickness (H1). For example, as illustrated in FIG. 3, the vertical thickness of the second region (134) may gradually decrease as it approaches the cavity (150) in the horizontal direction. Therefore, in the embodiment, the second region (134) should be understood as having a thickness smaller than the first thickness (H1) and being positioned closer to the cavity (150) in the horizontal direction than the first region (132).

[0090] The first region (132) may be a region that overlaps vertically with the wiring portion (111, 113) and the via portion (122). The second region (134) may be a region that is offset vertically from the wiring portion (111, 113) and the via portion (122).

[0091] Based on the horizontal direction, the second area (134) may be positioned closer to the cavity (150) than the first area (132). Based on the horizontal direction, the second area (134) may be positioned closer to the second through hole (154) than the first area (132).

[0092] According to the embodiment, the cavity (150) may have a shape that penetrates a plurality of insulating layers (102, 103). Accordingly, the formation of the cavity (150) may be achieved by a process of forming a first through hole (152) in the second insulating layer (102), and then stacking a third insulating layer (103) on the second insulating layer (102) to form a second through hole (154). In this case, due to the difference in hardness between the second insulating layer (102) and the third insulating layer (103), a portion of the third insulating layer (103) may penetrate into the space within the cavity (150) by causing sagging of the third insulating layer (103) on the inner wall of the cavity (150).

[0093] Accordingly, in the embodiment, the thickness of the second region (134) near the cavity (150) is formed to be thinner than the thickness of the first region (132), thereby minimizing the penetration of space within the cavity (150) caused by the sagging of the third insulating layer (103).

[0094] In addition, the thickness of the third insulating layer (103) near the cavity (150) is formed to be thinner than other areas, thereby allowing the horizontal length of the space of the cavity (150) to be secured more widely.

[0095] In addition, by forming the thickness relatively thick in the placement area of ​​the wiring portion (111, 113) and the via portion (122), there is an advantage in that the bonding force between the third insulating layer (103) and the wiring portion (111, 113) and the via portion (122) can be maintained more firmly than in other areas.

[0096] The second region (134) may have a shape in which the thickness in the vertical direction gradually decreases as it approaches the second through hole (154) in the horizontal direction. As shown in FIG. 3, the upper surface of the second region (134) may have a curved shape in which the thickness in the vertical direction gradually decreases as it approaches the second through hole (154). As a variation, the upper surface of the second region (134) may have an inclined surface shape in which the thickness in the vertical direction gradually decreases as it approaches the second through hole (154). Accordingly, as the thickness of the second region (134) decreases as it approaches the cavity (150), sagging toward the cavity (150) can be minimized.

[0097] The horizontal width of the second region (134) may be 15 μm or more. If the horizontal width of the second region (134) is less than 15 μm, the horizontal distance between the first region (132) and the cavity (150) is insufficient, making it difficult to resolve issues such as minimizing sagging of the inner wall of the cavity through the aforementioned second region (134). Meanwhile, considering the wiring density, the horizontal width of the second region (134) may have an upper limit within a range that limits the area of ​​the circuit board (10) from becoming unnecessarily large.

[0098] A curved portion (146) may be disposed in the area connecting the upper surface of the third insulating layer (103) and the inner wall (144) of the second through hole (154). The curved portion (146) may have a rounded curved shape to connect the upper surface of the third insulating layer (103), that is, the upper surface of the second area (134), and the inner wall (144). Accordingly, the collapse of the third insulating layer (103) due to a steep slope between the upper surface of the third insulating layer (103) and the inner wall (144) can be minimized. At least a portion of the curved portion (146) may overlap vertically with the second area (134) or be connected to the second area (134).

[0099] Meanwhile, the protective layer (191) disposed on the third insulating layer (103) may be disposed on the first region (132) and the second region (134), respectively. Accordingly, the protective layer (191) may have multiple regions with different thicknesses in the vertical direction, and the thickness of the protective layer (191) disposed on the second region (134) may be thicker than the thickness of the protective layer (191) disposed on the first region (132).

[0100] FIG. 4 is a drawing illustrating a modified example of a circuit board according to the first embodiment of the present invention.

[0101] Referring to FIG. 4, the protrusion (138) of the third insulating layer (103) may be omitted. In this case, with respect to the cavity (150), the inner wall (144) of the second through hole (154) may be positioned further outward than the inner wall (142) of the first through hole (152). The inner wall (144) of the second through hole (154) may be positioned to overlap the second insulating layer (102) in a vertical direction.

[0102] Likewise, the third insulating layer (103) may include a first region (132) having a first thickness (H1) in the vertical direction and a second region (134) having a second thickness (H2) in the vertical direction. The second region (134) may be arranged to overlap vertically with the second insulating layer (102).

[0103] In this embodiment, the inner wall (144) of the second through hole (154) is positioned further outward from the cavity (150) than the inner wall (142) of the first through hole (152), thereby structurally preventing sagging of the third insulating layer (103).

[0104] The protective layer (191) may include a protrusion (193). The protrusion (193) may be an area that protrudes downward from the base of the protective layer (191). The protrusion (193) may be positioned to protrude downward from the lower surface of the base of the protective layer (191) and to surround the inner wall (144) of the second through hole (154) and the inner wall (142) of the first through hole (152). The lower surface of the protrusion (193) of the protective layer (191) may be in contact with the upper surface of the first insulating layer (101), which is the bottom surface of the cavity (150).

[0105] Accordingly, due to the support structure of the inner walls (142, 144) of the plurality of insulating layers (102, 103) through the protrusion (193) of the protective layer (191), the sagging phenomenon of the inner walls (142, 144) in the formation area of ​​the cavity (150) can be minimized. In addition, the space of the cavity (150) can be secured through the placement area of ​​the protrusion (193) of the protective layer (191), so the formation of the space of the cavity (150) can be made easier.

[0106] FIG. 5 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

[0107] Referring to FIG. 5, a semiconductor package according to a first embodiment of the present invention may include a first electronic element (500) disposed in a cavity (150), a second electronic element (600) disposed on a first protective layer (191) and electrically connected to the first electronic element (500), and a third electronic element (700) disposed on the first protective layer (191) and electrically connected to the first electronic element (500).

[0108] The first protective layer (191) may include a base (194) and a protrusion (195) that protrudes from the base (194) and is coupled to a cavity (150). The protrusion (195) is coupled to a first through hole (152) and a second through hole (154) and can embed a first electronic element (500) within the cavity (150).

[0109] Accordingly, since the surface of the circuit board (10) can be controlled through the base portion (194) of the first protective layer (191), even if there are regions where the thickness difference between the second insulating layer (102) and the third insulating layer (103) is different, the surface of the circuit board (10) to which the second electronic element (600) and the third electronic element (700) are combined can be precisely controlled through the first protective layer (191).

[0110] Hereinafter, a circuit board and a semiconductor package according to a second embodiment of the present invention will be described.

[0111] FIG. 6 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, FIG. 7 is an enlarged view of a cavity formation area according to a second embodiment of the present invention, FIG. 8 is an enlarged view of a part of FIG. 7, and FIG. 9 is a modified example of a cavity formation structure within a circuit board according to a second embodiment of the present invention.

[0112] Referring to FIGS. 6 to 9, a circuit board (20) according to a second embodiment of the present invention may include a build-up structure (1100) and a protective layer (1210, 1220).

[0113] The build-up structure (1100) includes a build-up insulator and a build-up wiring section, and the build-up insulator may include a plurality of insulating layers stacked along a vertical direction. Additionally, the build-up wiring section may include wiring layers disposed on one side and / or the other side of each of the plurality of insulating layers, and via electrodes for connecting along the vertical direction of each wiring layer.

[0114] The build-up structure (1100) includes a build-up insulator, and the build-up insulator may include a plurality of insulating layers stacked along a vertical direction. The plurality of insulating layers may include a first insulating layer (1101), a second insulating layer (1110) disposed on the first insulating layer (1101), a third insulating layer (1120) disposed on the second insulating layer (1110), a fourth insulating layer (1130) disposed on the third insulating layer (1120), a fifth insulating layer (1102) disposed on the lower surface of the first insulating layer (1101), a sixth insulating layer (1103) disposed on the lower surface of the fifth insulating layer (1102), and a seventh insulating layer (1104) disposed on the lower surface of the sixth insulating layer (1106). The first to seventh insulating layers (1101, 1110, 1120, 1130, 1102, 1103, 1104) can be laminated along the vertical direction.

[0115] The first insulating layer (1101), the second insulating layer (1110), the fifth insulating layer (1102), the sixth insulating layer (1103), and the seventh insulating layer (1104) may each be any insulating material, such as a photocurable and / or thermosetting material. As a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers.

[0116] The third insulating layer (1120) and the fourth insulating layer (1130) may be provided with a photocurable insulating material. Compared to manufacturing the cavity (1150) using a drill bit and / or laser process, using a photocurable insulating material can provide a significant advantage in manufacturing process costs for manufacturing a cavity (1150) with a large surface area. Additionally, the electrodes placed on the bottom surface of the cavity (1150) can be freely designed, which can be advantageous for flip-bonding electronic devices such as semiconductor devices. Therefore, the overall thickness of the semiconductor package is reduced, and the electrical operation of the semiconductor device can be further improved by increasing the number of bonded terminals compared to wire-bonding the semiconductor device placed within the cavity.

[0117] According to the embodiment, some insulating layers constituting the build-up insulator may have different materials from other insulating layers. For example, the first insulating layer (1101) may be a material selected from a prepreg (PPG) containing glass fibers in a resin or a core layer, and accordingly, the first insulating layer (1101) may be a component forming the basis of the circuit board (20). When the first insulating layer (1101) is a core layer, the material of the first insulating layer (1101) may include at least one selected from the group consisting of glass, resin, plastic, and metal. Additionally, the vertical thickness of the first insulating layer (1101) may be thicker than the vertical thickness of each of the second to seventh insulating layers (1110, 1120, 1130, 1102, 1103, 1104). Accordingly, by reinforcing the strength of the circuit board (20) through the first insulating layer (1101), bending can be minimized.

[0118] The third insulating layer (1120) and the fourth insulating layer (1130) disposed on the surface of the build-up insulator may each be a photocurable insulator. The third insulating layer (1120) and the fourth insulating layer (1130) may each be a PID (Photo Imageable Dielectric). Accordingly, by configuring the third insulating layer (1120) and the fourth insulating layer (1130) disposed on the surface of the build-up insulator as photocurable insulating layers, the process of forming the cavity (1150) to be described later can be performed more easily. Specifically, since the process of forming a cavity (1150) or via hole penetrating the third insulating layer (1120) and the fourth insulating layer (1130) can be carried out through processes such as exposure and development rather than a drilling method using a laser, the shape of the inner wall of the cavity (1150) can be controlled more precisely, and a fine pattern of vias for connecting multiple wiring parts can be realized.

[0119] The sixth insulating layer (1103) and the seventh insulating layer (1104) may also each be a photocurable insulator, and in this case, the sixth insulating layer (1103) and the seventh insulating layer (1104) may each be a PID (Photo Imageable Dielectric).

[0120] The third insulating layer (1120), the fourth insulating layer (1130), the sixth insulating layer (1103), and the seventh insulating layer (1104) may each contain a filler within the resin.

[0121] The second insulating layer (1110) and the fifth insulating layer (1102), which are disposed between the third insulating layer (1120) and the first insulating layer (1101), and between the sixth insulating layer (1103) and the first insulating layer (1101), may each be thermosetting insulators. The second insulating layer (1110) and the fifth insulating layer (1102) may be insulators in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation. For example, at least a portion of the upper surface of the second insulating layer (1110) may form the bottom surface of the cavity (1150) to be described later, and since the second insulating layer (1110) does not contain glass fibers, it is possible to prevent glass fibers from being exposed from the bottom surface of the cavity (1150) according to the desmearing process after the formation of the cavity (1150). This will be described later.

[0122] Each of the second insulating layers (1110) contains a filler within the resin, and, for example, the amount of filler contained in the second insulating layer (1110) may be greater than the amount of filler contained in each of the third insulating layer (1120) and the fourth insulating layer (1130). Accordingly, the coefficient of thermal expansion (CTE) of the second insulating layer (1110) may be smaller than the coefficient of thermal expansion of each of the third insulating layer (1120) and the fourth insulating layer (1130). Accordingly, the coefficient of thermal expansion of the second insulating layer (1110) is implemented to be greater than the coefficient of thermal expansion of the first insulating layer (1101), which is prepreg (PPG), and smaller than the coefficient of thermal expansion of the third insulating layer (1120), thereby minimizing the overall stress within the circuit board (20) through the second insulating layer (1110) between the first insulating layer (1101) and the third insulating layer (1120). Additionally, considering the bending of the circuit board (20), the fifth insulating layer (1102) may be provided with the same material as the second insulating layer (1110), but is not limited thereto.

[0123] The circuit board (20) may include a protective layer (1210, 1220). The protective layer (1210, 1220) may include a first protective layer (1210) disposed on the upper surface of a build-up insulator and a second protective layer (1220) disposed on the lower surface of a build-up insulator. The first protective layer (1210) and the second protective layer (1220) can perform the function of preventing short circuits between solders due to low wettability with the solder when a semiconductor device is disposed on the surface of the circuit board (20) with a material such as solder, and can prevent the problem of external contaminants penetrating into the build-up insulator and reducing reliability. The first protective layer (1210) and the second protective layer (1220) may each be a solder resist. The first protective layer (1210) and the second protective layer (1220) may each include a hole (1212, 1222) for exposing a wiring portion (1184) disposed on the upper surface of the build-up insulator and a wiring portion (1188) disposed on the lower surface of the build-up insulator.

[0124] The build-up wiring section may include a plurality of wiring layers and a plurality of via electrodes.

[0125] A plurality of wiring layers may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring layers is embedded within each of the plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring layer may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring layer being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which a wiring layer is disposed on both the first surface and the second surface of some of the insulating layers, and a wiring layer is disposed on only one of the first surface or the second surface of other parts of the plurality of insulating layers.

[0126] A plurality of wiring layers may include a first wiring layer (1181) disposed on a first insulating layer (1101), a second wiring layer (1182) disposed on a second insulating layer (1110), a third wiring layer (1183) disposed on a third insulating layer (1120), a fourth wiring layer (1184) disposed on a fourth insulating layer (1130), a fifth wiring layer (1185) disposed on the lower surface of the first insulating layer (1101), a sixth wiring layer (1186) disposed on the lower surface of the fifth insulating layer (1102), a seventh wiring layer (1187) disposed on the lower surface of the sixth insulating layer (1103), and an eighth wiring layer (1188) disposed on the lower surface of the seventh insulating layer (1104).

[0127] A via electrode may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring layers facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via electrode may be disposed within the via hole.

[0128] A plurality of via electrodes may include a first via electrode (1191) penetrating at least a portion of the second insulating layer (1110), a second via electrode (1192) penetrating at least a portion of the third insulating layer (1120), a third via electrode (1193) penetrating at least a portion of the fourth insulating layer (1130), a fourth via electrode (1194) penetrating at least a portion of the first insulating layer (1101), a fifth via electrode (1195) penetrating at least a portion of the fifth insulating layer (1102), a sixth via electrode (1196) penetrating at least a portion of the sixth insulating layer (1103), and a seventh via electrode (1187) penetrating at least a portion of the seventh insulating layer (1104).

[0129] The first via electrode (1191) can electrically connect the first wiring layer (1181) and the second wiring layer (1182). The second via electrode (1192) can electrically connect the second wiring layer (1182) and the third wiring layer (1183). The third via electrode (1193) can electrically connect the third wiring layer (1183) and the fourth wiring layer (1184). The fourth via electrode (1194) can electrically connect the first wiring layer (1181) and the fifth wiring layer (1185). The fifth via electrode (1195) can electrically connect the fifth wiring layer (1185) and the sixth wiring layer (1186). The sixth via electrode (1196) can electrically connect the sixth wiring layer (1186) and the seventh wiring layer (1187). The seventh via electrode (1197) can electrically connect the seventh wiring layer (1187) and the eighth wiring layer (1188).

[0130] The first to fourth via electrodes (1191, 1192, 1193, 1194) may each have a shape in which the horizontal width gradually decreases as it moves downward. The fifth to seventh via electrodes (1195, 1196, 1197) may each have a shape in which the horizontal width gradually decreases as it moves upward. The expansion direction of the plurality of via electrodes within the circuit board (20) may be reversed with respect to the first insulating layer (1101). Accordingly, stress can be distributed in the vertical direction of the circuit board (20) by the structure of the reversed expansion direction of the via electrodes at the center of the vertical direction of the circuit board (20).

[0131] The circuit board (20) may include a cavity (1150). The cavity (1150) may be placed on the circuit board (20). The cavity (1150) may be placed on a build-up insulator. The cavity (1150) may have a concave shape extending from the upper surface of the build-up insulator toward the lower surface of the build-up insulator.

[0132] A portion of the insulating layer of the build-up insulator may include through holes (1122, 1132) that form a cavity (1150). As illustrated in FIG. 7, the through holes (1122, 1132) may include a first through hole (1122) penetrating from the upper surface to the lower surface of the third insulating layer (1120), and a second through hole (1132) penetrating from the upper surface to the lower surface of the fourth insulating layer (1130). The first through hole (1122) and the third through hole (1132) may be arranged so that at least a portion overlaps in the vertical direction. The first through hole (1122) and the second through hole (1132) may each have a shape in which the horizontal width gradually decreases as it goes downward. The third insulating layer (1120) may include a first inner wall (1123) forming the inner wall of the first through hole (1122). The fourth insulating layer (1130) may include a second inner wall (1133) forming the inner wall of the second through hole (1132).

[0133] A portion of the upper surface of the second insulating layer (1110) may be exposed vertically from the third insulating layer (1120) and the fourth insulating layer (1130) through the cavity (1150). The cavity (1150) may form a placement area for electronic devices to be described later. In this case, a portion of the upper surface of the second insulating layer (1110) may be provided as the bottom surface of the cavity (1150) to form a placement surface for electronic devices.

[0134] Due to the shape of the through holes (1122, 1132) described above, the first inner wall (1123) and the second inner wall (1133) may each form an obtuse angle with the bottom surface of the cavity (1150). However, this is not limited thereto, and the first inner wall (1123) may form an obtuse angle with the bottom surface of the cavity (1150), and the second inner wall (1133) may form an acute angle with the bottom surface of the cavity (1150). In this case, the plurality of inner walls (1123, 1133) may form a coupling structure through various angles with the protrusion (1216, see FIG. 16) of the molding member (1500, see FIG. 15) or protective layer (1210) to be described later.

[0135] The protective layer (1210) may include a third through hole (1214). The third through hole (1214) may be shaped to penetrate from the upper surface to the lower surface of the protective layer (1210). The third through hole (1214) may be arranged so that at least a portion overlaps the first through hole (1122) and the second through hole (1132) in a vertical direction. The third through hole (1214) may form a cavity (1150) together with the first and second through holes (1122, 1132).

[0136] A wiring layer (1160) may also be disposed on the bottom surface of the cavity (1150). The wiring layer (1160) may be electrically connected to an electronic element (2000, see FIG. 19) to be described later. The wiring layer (1160) may be disposed so as to overlap vertically with the cavity (1150). The wiring layer (1160) may be exposed above the cavity (1150) through a plurality of through holes (1122, 1132). The wiring layer (1160) may be disposed on the second insulating layer (1110). The wiring layer (1160) disposed on the bottom surface of the cavity (1150) may be disposed so as to overlap horizontally with the second wiring layer (1182), which is disposed on the second insulating layer (1110) and overlaps vertically with the third insulating layer (1120). Accordingly, the wiring layer (1160) disposed on the bottom surface of the cavity (1150) can also be named the second wiring layer (1182). The wiring layer (1160) can be electrically connected to the first wiring layer (1181) through a via electrode (1191) penetrating the second insulating layer (1110). The wiring layer (1160) can be spaced horizontally apart from the first inner wall (1123). Accordingly, damage to the electronic device (2000) caused by the inner wall can be minimized during the bonding process of the electronic device (2000) on the wiring layer (1160).

[0137] A plurality of wiring layers (1160) disposed on the bottom surface of the cavity (1150) may be provided and arranged to overlap and / or be spaced apart in the horizontal direction.

[0138] As illustrated in FIGS. 7 and 8, the cavity (1150) may include a protrusion (1112) protruding from the bottom surface of the cavity (1150). When the bottom surface of the cavity (1150) is referred to as the first-2nd surface (1116) to be described later, the first-1st surface (1113) to be described later may be referred to as the upper surface of the protruding protrusion (1112), and when the bottom surface (1150) of the cavity is referred to as the first-1st surface (1113), the first-2nd surface (1116) may be referred to as a recess. However, according to the present invention, considering the function of the cavity for placing electronic elements and improving the bonding force with the protrusion (1216) to be described later, the bottom surface of the cavity (1150) is referred to as the first-2nd surface (1116) for convenience of explanation.

[0139] Specifically, the upper surface of the second insulating layer (1110) may include a first surface (1113, 1116) that overlaps along a vertical direction with respect to the cavity (1150), and a second surface (1117) that is offset in a vertical direction with respect to the cavity (1150). The first surface (1113, 1116) may be exposed upward to the circuit board (20) through the cavity (1150). A third insulating layer (1120) may be disposed on the second surface (1117). A third insulating layer (1120) may be laminated on the second surface (1117).

[0140] The first surface (1113, 1116) may include a first-1 surface (1113) and a first-2 surface (1116) that are stepped in the vertical direction. The first-1 surface (1113) may be the upper surface of the protrusion (1112). The first-2 surface (1116) may be the bottom surface of the cavity (1150). The protrusion (1112) may be disposed on the first-2 surface (1116). The protrusion (1112) may have a shape that protrudes vertically upward from the first-2 surface (1116).

[0141] The vertical length from the lower surface of the second insulating layer (1110) to the first-1 surface (1113) may be the same as the vertical length from the lower surface of the second insulating layer (1110) to the second surface (1117). The vertical length from the lower surface of the second insulating layer (1110) to the first-2 surface (1116) may be shorter than the vertical length from the lower surface of the second insulating layer (1110) to the first-1 surface (1113) and / or the vertical length from the lower surface of the second insulating layer (1110) to the second surface (1117).

[0142] The first-1 surface (1113) and the first-2 surface (1116) may have shapes that are distinct from each other through a desmearing process or an etching process of the seed layer for forming the wiring layer (1160) after the formation of the cavity (1150). The groove (1115) including the first-2 surface (1116) is an area where the resin constituting the second insulating layer (1110) is lost due to chemicals according to the desmearing process or the etching process of the seed layer, and is referred to as the bottom surface of the cavity (1150) as it functions to improve the bonding strength by widening the bonding area with the protrusion (1216) to be described later.

[0143] According to the present embodiment, the material of the second insulating layer (1110), in which at least a portion of the upper surface forms the bottom surface of the cavity (1150), is composed of an insulator that does not contain glass fibers, thereby preventing the glass fibers from being exposed. When glass fibers are exposed from the bottom surface of the cavity (1150), contact between the glass fibers and a bonding member (2100, see FIG. 19), such as Cu and / or solder, can cause problems such as migration, which may lead to electrical reliability issues during the operation of the electronic device. Accordingly, by laminating the second insulating layer (1110) that does not contain glass fibers on the first insulating layer (1101), which is prepreg (PPG), the problem of glass fibers being exposed can be prevented in advance.

[0144] In addition, according to the embodiment, the circuit board (20) implements a support structure for the wiring layer (1160) and the electronic element (2000) through the upper surface of the protrusion (1112), and as the positional alignment can be improved, the bonding process of the electronic element (2000) can be easily performed, and the reliability of the circuit board (20) can be improved by improving the bonding area with the protrusion (1216).

[0145] Meanwhile, the side of the protrusion (1112) may include a concave surface (1114). The concave surface (1114) may have a shape that is concave in the horizontal direction from the side of the protrusion (1112). The concave surface (1114) may be formed together during the process of forming the groove (1115) according to the aforementioned desmear process. The concave surface (1114) may be a curved surface having a predetermined curvature. The concave surface (1114) may be positioned between the first-1 surface (1113) and the first-2 surface (1116).

[0146] Through the concave surface (1114), a coupling structure is formed with the protrusion (1216, see FIG. 16) of the molding member (1500, see FIG. 15) or protective layer (1210) to be described later, so that the coupling between the molding member (1500) and the cavity (1150), and between the protective layer (1210) and the cavity (1150) can be made more robust. In this case, the molding member (1500) or the protrusion (1216) may include a protruding area that is coupled to the concave surface (1114).

[0147] In addition, by partitioning the area for forming the wiring layer (1160) through the concave surface (1114), an electrical short circuit between the wiring layer (1160) and other components can be prevented.

[0148] In addition, by securing a horizontal separation distance from the inner wall of the cavity (1150) through the concave surface (1114), when an adhesive member for bonding an electronic element (2000) is placed on the wiring layer (1160), sufficient space can be secured for bubbles to form between the adhesive member and the electronic element.

[0149] The vertical thickness of the second insulating layer (1110) may be smaller than the vertical thickness of the third insulating layer (1120) and / or the vertical thickness of the first insulating layer (1101). Accordingly, the vertical length of the cavity (1150) through the through hole (1122) of the third insulating layer (1120) can be formed relatively long, while the bending phenomenon of the circuit board (20) through the first insulating layer (1101) can be minimized. In addition, in the case of the second insulating layer (1110), by forming the vertical length relatively short, a structure can be simultaneously implemented that protects the upper surface of the first insulating layer (1101) containing glass fibers and relatively lowers the vertical height of the circuit board (20).

[0150] FIG. 18 is a drawing illustrating a modified example of a circuit board according to a second embodiment of the present invention, wherein the first-2 surface (1116) may be arranged along the perimeter of the bottom surface of the cavity (1150). In this case, the first-1 surface (1113), defined as the upper surface of the protrusion (1112), is arranged inside the first-2 surface (1116) and may be partitioned from the inner wall of the cavity (1150) through the first-2 surface (1116). Accordingly, the coupling area of ​​the electronic device can be partitioned more immediately, and the sagging phenomenon of the multiple protrusions (1112) in the area between the multiple protrusions (1112) can be minimized.

[0151] FIGS. 10 and FIGS. 11 are drawings for explaining the process of forming a wiring layer on the bottom surface of a cavity according to a second embodiment of the present invention.

[0152] Referring to FIGS. 10 and 11, after the cavity (1150) is formed through the through holes of the third insulating layer (1120) and the fourth insulating layer (1130), a seed layer (1300) for forming a wiring layer (1160) may be disposed on the bottom surface of the cavity (1150). For example, the horizontal width of the seed layer (1300) may be shorter than the horizontal width of the cavity (1150), and the side of the seed layer (1300) and the inner wall (1123) of the first through hole (1122) may be spaced apart in the horizontal direction.

[0153] Accordingly, after the wiring layer (1160) is formed on the seed layer (1300), as shown in FIG. 11, during the process of removing the seed layer (1300) by etching, the first surface (1113, 1116), which is the bottom surface of the cavity (1150), can be formed by chemical treatment, with a first-1 surface (113), which is the area for forming the wiring layer (160), and a first-2 surface (1116), which is positioned on the outside of the first-1 surface (113), respectively. As described above, the first-2 surface (1116) can be formed by the bottom surface of the groove (1115) positioned on the outside of the protrusion (1112).

[0154] Meanwhile, the region that overlaps vertically with the formation region of the wiring layer (1160) in the seed layer (1300) may form a part of the wiring layer (1160), and in this case, the wiring layer (1160) may include a plurality of regions with different grain sizes. For example, the grain size of the lower region of the wiring layer (1160), which is part of the seed layer (1300), may be larger than the grain size of the upper region of the wiring layer (1160), which is the plating region through the seed layer (1300).

[0155] In this embodiment, the groove (1115) is described as being disposed between the inner walls of the cavity (1150) based on the protrusion (1112), but this is not limited thereto, and the protrusion (1112) may be provided in multiple numbers and spaced apart along the horizontal direction. In this case, the protrusion (1112) is each disposed in the formation area of ​​the wiring layer (1160), and a first-second surface (1116) may be disposed between the multiple protrusions (1112). Accordingly, a horizontal spacing structure through the groove (1115) between the multiple wiring layers (1160) is implemented, thereby providing the advantage of minimizing the occurrence of short circuits between the multiple wiring layers (1160).

[0156] FIG. 9 is a drawing illustrating a modified example of a cavity formation structure within a circuit board according to a second embodiment of the present invention. Referring to FIG. 9, the fourth insulating layer (1130) may include a base portion (1136) and a protrusion portion (1137) that protrudes from the base portion (1136) toward the second insulating layer (1110) and surrounds the inner wall (1123) of the third insulating layer (1120). The protrusion portion (1137) may include a first region (1138) that overlaps horizontally with the third insulating layer (1120) and a second region (1139) that is positioned below the first region (1138) and at least a portion of which overlaps horizontally with the second insulating layer (1110). According to the modified example, since the inner wall shape of the cavity (1150) is implemented through a single protrusion (1137), there is an advantage in that the shape of the cavity (1150) can be controlled more precisely. In addition, due to the structure of wrapping the inner wall (1123) of the third insulating layer (1120) through the protrusion (1137), there is an advantage in that the occurrence of areas with different vertical thicknesses between multiple insulating layers due to the collapse of the inner wall of the cavity (1150) can be minimized.

[0157] At least a portion of the protrusion (1137) may be placed in the groove (1115). Accordingly, at least a portion of the protrusion (1137) may be placed so as to overlap in a vertical direction with the upper surface of the second insulating layer (1110). Accordingly, a vertical coupling structure of multiple insulating layers through the protrusion (1137) can be realized, thereby increasing the rigidity of the circuit board (20). Additionally, although not illustrated, the protrusion (1137) may be coupled to fill the groove (1115), in which case the protrusion (1137) may be coupled to the aforementioned concave surface (1114) to realize a coupling structure with the protrusion (1112) of the second insulating layer (1110).

[0158] FIGS. 12 to 14 are drawings illustrating modified examples of a structure forming a concave surface within a circuit board according to a second embodiment of the present invention.

[0159] Referring to FIG. 12, a concave surface (1127) with a shape that is concave toward the horizontal outer side may be formed on the side wall of the cavity (1150). The concave surface (1127) may be placed on the inner wall (1123) of the third insulating layer (1120). The concave surface (1127) may have a shape that is concave toward the horizontal outer side in at least a portion of the inner wall (1123) of the third insulating layer (1120). The concave surface (1127) may be placed to overlap with the wiring layer (1160) along the horizontal direction. In this case, a plurality of vertical step surfaces through the protrusion (1112) placed on the bottom surface of the aforementioned cavity (1150) may be omitted.

[0160] Referring to FIGS. 13 and 14, after the cavity (1150) is formed through the through holes of the third insulating layer (1120) and the fourth insulating layer (1130), a seed layer (1300) for forming a wiring layer (1160) may be disposed on the bottom surface of the cavity (1150). For example, the horizontal width of the seed layer (1300) may be greater than the horizontal width of the cavity (1150), and accordingly, with respect to the horizontal direction, both ends of the seed layer (1300) may be disposed to penetrate the inner wall of the third insulating layer (1120).

[0161] Accordingly, after the wiring layer (1160) is formed on the seed layer (1300), as shown in FIG. 14, a concave surface (1127), which is the removal area of ​​the seed layer (1300), can be formed on the side wall of the cavity (1150) by chemical treatment during the removal process of the seed layer (1300) by etching. The concave surface (1127) can be arranged to overlap horizontally with at least a portion of the wiring layer (1160).

[0162] According to a modified example, by implementing a concave surface (1127) on the inner wall rather than on the bottom surface of the cavity (1150), the placement space of the electronic element (2000) within the cavity (1150) can be increased in the horizontal direction, and there is an advantage of minimizing the loss of resin of the second insulating layer (1110) due to chemical treatment.

[0163] FIGS. 15 to 17 are drawings illustrating various embedded structures of a cavity within a circuit board according to a second embodiment of the present invention.

[0164] Referring to FIG. 15, the circuit board (20) may include a molding member (1500). The molding member (1500) may be placed within a cavity (1150). When an electronic element (2000) is placed within the cavity (1150), the electronic element (2000) may be embedded within the cavity (1150) through the molding member (1500). The molding member (1500) may be coupled to the inner wall and first surface (1113, 1116) of the cavity (1150). A protrusion (1510) protruding in a vertical direction is disposed on the lower surface of the molding member (1500), and the protrusion (1510) may be coupled to a groove (1115). In this case, the protrusion (1510) can be joined to the concave surface (1114), and accordingly, the connection between the molding member (1500) and the second insulating layer (1110) can be made more robust.

[0165] Referring to FIG. 16, a protective layer (1210) may be embedded in the cavity (1150). In this case, the protective layer (1210) may include a base (1215) and a protrusion (1216) that protrudes downward in a vertical direction from the lower surface of the base (1215) and is disposed in the cavity (1150). In this case, an electronic element (2000) may be embedded by the protective layer (1210).

[0166] Likewise, the protrusion (1216) of the protective layer (1210) can implement a bonding structure with the groove (1115) and the concave surface (1114), and accordingly, the bonding between the protective layer (1210) and the second insulating layer (1110) can be made more robust.

[0167] Referring to FIG. 17, as described above, the second insulating layer (1110) may be a thermosetting insulator and may include a resin and a filler. In this case, the filler (1119a) of the second insulating layer (1110) may be arranged to protrude from the surface of the second insulating layer (1110), and the filler (1119a) may be coupled with a groove (1217) formed on the surface of the protective layer (1210).

[0168] Additionally, by chemical treatment, a coupling groove (1119b) with a shape that is partially concave can be formed on the surface of the second insulating layer (1110), and a protrusion (1218) that is coupled to the coupling groove (1119b) can be formed on the surface of the protective layer (1210). Accordingly, the bond between the protective layer (1210) and the second insulating layer (1110) can be made more robust.

[0169] FIG. 19 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

[0170] Referring to FIG. 19, a semiconductor package according to a second embodiment of the present invention may include a first electronic element (2000) disposed in a cavity (1150), a second electronic element (2200) disposed on a protective layer (1210) and electrically connected to the first electronic element (2000), and a third electronic element (2300) disposed on the first protective layer (1210) and electrically connected to the first electronic element (2000).

[0171] A protrusion (1216) of the aforementioned molding member (1500) or protective layer (1210) may be disposed in the cavity (1150), and the electronic element (2000) may be electrically connected to a second electronic element (2200) or a third electronic element (2300) through a hole formed on the molding member (1500) or protective layer (1210).

[0172] The first electronic element (2000) can be bonded onto the wiring layer (1160) through an adhesive member (not shown), such as a DAF (Die Attach Film). In this case, a space can be secured through the gap between the inner wall of the cavity (1150) and the wiring layer (1160) to allow for the formation of a bubble between the adhesive member and the electronic element.

[0173] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0174] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0175] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0176] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. First insulating layer; A second insulating layer disposed on the first insulating layer and including a first through hole; and A third insulating layer disposed on the second insulating layer and including a second through hole that is vertically overlapped with at least a portion of the first through hole, and The third insulating layer comprises a first region having a first thickness in the vertical direction and a second region having a second thickness smaller than the first thickness in the vertical direction. Based on the horizontal direction perpendicular to the vertical direction, the second region is a circuit board positioned closer to the second through-hole than the first region.

2. In Paragraph 1, The above second region is a circuit board having a shape in which the thickness in the vertical direction gradually decreases as it approaches the above second through hole.

3. In Paragraph 2, The upper surface of the second region is a curved circuit board.

4. In Paragraph 2, The upper surface of the second region above is a circuit board that is an inclined surface.

5. In Paragraph 1, A circuit board comprising a curved portion that roundly connects the upper surface of the third insulating layer and the inner wall of the second through hole.

6. In Paragraph 5, The second region above is a circuit board connected to the curved surface.

7. In Paragraph 1, The third insulating layer comprises a base portion disposed on the second insulating layer and a protrusion portion protruding from the base portion and surrounding the inner wall of the first through hole.

8. In Paragraph 7, The lower surface of the above protrusion is a circuit board in contact with the upper surface of the first insulating layer.

9. In Paragraph 7, The above protrusion is a circuit board that overlaps the above second insulating layer in a horizontal direction.

10. First insulating layer; A second insulating layer disposed on the first insulating layer and including a first through hole; A third insulating layer disposed on the second insulating layer and comprising a second through-hole that is vertically superimposed with at least a portion of the first through-hole; and It includes a first electronic element disposed within the first through hole and the second through hole, and The third insulating layer comprises a first region having a first thickness in the vertical direction and a second region having a second thickness smaller than the first thickness in the vertical direction. A semiconductor package in which, based on a horizontal direction perpendicular to the vertical direction, the second region is positioned closer to the second through-hole than the first region.

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