Data generation circuit for high-speed transmitter

Abstract

The present application relates to the technical field of integrated circuits. Disclosed is a data generation circuit for a high-speed transmitter. The circuit uses a two-stage structural design, wherein a first-stage circuit unit generates a narrow pulse signal by means of the coordination of an input transistor, a pre-discharge control transistor, a reset control transistor and a pre-charge control transistor, and a second-stage circuit unit converts a non-full-swing pulse signal into a full-swing signal by means of a pull-down transistor and a plurality of pull-up transistors, and then outputs the full-swing signal. The present application realizes stable and reliable signal generation and shaping in an ultra-high-speed scenario in which a unit time interval is less than or equal to 10 picoseconds, is applicable to a 1 / 4-rate or 1 / 8-rate high-speed transmitter, and has the characteristics of a simple structure and precise timing.

Description

Data generation circuit for high-speed transmitters Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a data generation circuit for an ultra-high-speed transmitter. Background Technology

[0002] With the rapid development of communication technology and the continuous improvement of data transmission rates, modern high-speed communication systems are placing increasingly higher demands on signal quality and transmission reliability. In ultra-high-speed transmitters, 1 / 4 or 1 / 8 rate structures are widely used. Their core idea is to use multi-phase clock signals to synthesize multiple low-speed data streams into full-rate data for transmission. While this architecture reduces the transmission rate requirement for a single data stream, it still faces significant technical challenges in the data synthesis stage.

[0003] Especially with the continuous increase in data transmission rates, the unit time interval (1-UI) has been shortened to the order of 10 picoseconds. Within such a short timeframe, traditional data generation circuits struggle to achieve complete charging and discharging of the MOSFET, directly impacting signal quality and system reliability. Existing data generation circuits typically employ simple charging and discharging structures, which are prone to problems such as insufficient signal amplitude, non-sharp edges, and inaccurate timing in ultra-high-speed scenarios. Furthermore, the lack of an effective pre-charge / discharge mechanism makes it difficult for the circuit's response speed to meet the requirements of ultra-high-speed transmission.

[0004] Another prominent issue is signal swing control. In ultra-high-speed scenarios, due to the extremely limited charging and discharging time, the generated signal often cannot achieve the ideal full swing (0 to VDD). This not only reduces the signal's noise margin but also increases the difficulty of decision-making at the receiver. Existing signal shaping circuits are complex in structure and have cumbersome control logic, making it difficult to complete effective signal shaping in an ultra-short time.

[0005] Meanwhile, in high-speed transmitters driven by multi-phase clocks, precise timing control between various signals is also a critical issue. Traditional circuit structures struggle to ensure accurate synchronization between narrow pulse signals and control signals, easily leading to signal distortion and data transmission errors. Especially during the coordination of multiple stages such as pre-charging, pre-discharging, and signal shaping, ensuring precise control of each timing node has long been a challenging problem for the industry.

[0006] Therefore, there is an urgent need for a novel data generation circuit capable of reliable signal generation and shaping within ultra-short unit time intervals, while also possessing characteristics such as simple structure, precise timing, and ease of implementation. This circuit should be able to solve the charging and discharging efficiency problem in ultra-high-speed scenarios, ensure the full-swing characteristics of the output signal, and guarantee accurate signal transmission through a reasonable timing control mechanism, thereby meeting the ever-increasing performance requirements of modern high-speed communication systems. Summary of the Invention

[0007] The purpose of this application is to provide a data generation circuit for a high-speed transmitter to solve the problems mentioned in the background art.

[0008] This application discloses a data generation circuit for a high-speed transmitter, comprising a first-stage circuit unit and a second-stage circuit unit, wherein...

[0009] The first-stage circuit unit is used to generate a narrow pulse signal, including:

[0010] The input transistor (M1) has a gate used to receive input data signals;

[0011] The pre-discharge control transistor (M2) has its source connected to the drain of the input transistor (M1) to form a first intermediate node, and its gate is used to receive the A-phase clock signal.

[0012] The reset control transistor (M3) has its drain connected to the drain of the pre-discharge control transistor (M2) to form an output node, and its gate is used to receive the A-phase clock signal.

[0013] A pre-charge control transistor (M4) has its drain connected to the output node, its source used to receive the power supply voltage, and its gate used to receive the B-phase clock signal; wherein the B-phase clock signal has a predetermined time delay compared to the A-phase clock signal; the pre-discharge control transistor (M2) and the pre-charge control transistor (M4) respond to the A-phase clock signal and the B-phase clock signal, respectively, to perform pre-charge and pre-discharge on the output node, generating a pulse signal;

[0014] The second-stage circuit unit is used to shape the pulse signal into a full-swing signal, including:

[0015] The pull-down transistor (M5) is connected between the final output node and the lowest potential, and its control terminal is used to receive the reset signal.

[0016] Multiple pull-up transistors (M6, M7) have their drain and source terminals connected between the final output node and the power supply voltage, respectively. The control terminal is used to receive the pulse signal output by the first-stage circuit unit. The pull-down transistor (M5) cooperates with the pull-up transistors (M6, M7) to convert the non-full-swing pulse signal into a full-swing signal output in response to the reset signal and the pulse signal.

[0017] In a preferred embodiment, the time width of the narrow pulse signal is 1-UI, where UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

[0018] In a preferred embodiment, the A-phase clock signal and the B-phase clock signal are two phases of the same set of multi-phase clock signals, wherein the multi-phase clock signals include at least 4-phase clock signals, and the time interval between the rising edges of each pair of adjacent clock signals is 1-UI; wherein the B-phase clock signal leads the A-phase clock signal by 3-UI.

[0019] In a preferred embodiment, the gate of the input transistor (M1) is connected to the input terminal to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control transistor (M2) to form a first intermediate node (Data_int).

[0020] In a preferred embodiment, the operation of the first-stage circuit unit includes: (1) before the rising edge of the A-phase clock signal arrives, the reset control transistor (M3) is turned on to precharge the output node (Dout_int) to the power supply voltage; during the time before the rising edge of the A-phase clock signal arrives and after the falling edge of the B-phase clock signal arrives, the precharge control transistor (M4) is turned on, and the precharge of the output node (Dout_int) is maintained at the power supply voltage; (2) when the rising edge of the A-phase clock signal arrives, the pre-discharge control transistor (M2) is turned on to discharge the output node to a preset level; (3) when the rising edge of the B-phase clock signal arrives, the precharge control transistor (M4) is turned off, and the output node is further discharged to the lowest potential; (4) when the falling edge of the A-phase clock signal arrives, the reset control transistor (M3) is turned on, the pre-discharge control transistor (M2) is turned off, and the output node is reset and charged to the power supply voltage.

[0021] In a preferred embodiment, the system further includes at least one set of reset signal generation circuits for generating a reset signal synchronized with the pulse signal based on a multi-phase clock signal. The reset signal generation circuits include: a first AND gate, whose inputs are respectively connected to a second clock signal and a fourth clock signal, for performing an AND operation on the two; a second AND gate, whose inputs are respectively connected to a sixth clock signal and an eighth clock signal, for performing an AND operation on the two; and a NOR gate, whose inputs are respectively connected to the outputs of the first AND gate and the second AND gate, for performing a NOR operation on the output signals of the two, and whose output is used to output the reset signal.

[0022] In a preferred embodiment, the reset signal generation circuit receives an 8-phase clock signal as an input signal, and the time interval between the rising edges of any two adjacent clock signals is 1-UI.

[0023] In a preferred embodiment, the operation of the second-stage circuit unit includes:

[0024] When the reset signal is high and the pulse signal output by the first stage circuit unit is high, the pull-down transistor (M5) is turned on, discharging the final output node to the zero potential;

[0025] When the reset signal is low and the pulse signal output by the first stage circuit unit is low, the multiple pull-up transistors (M6, M7) are turned on alternately to charge the final output node to the power supply voltage.

[0026] In a preferred embodiment, the data generation circuit is used for a high-speed transmitter at 1 / 4 or 1 / 8 rate.

[0027] The embodiments of this application have the following technical effects:

[0028] The data generation circuit proposed in this application adopts a two-stage structure design, successfully solving the key problems of signal generation and shaping in ultra-high-speed scenarios. The first-stage circuit achieves efficient generation of narrow pulse signals through the ingenious cooperation of the input transistor (M1), pre-discharge control transistor (M2), reset control transistor (M3), and pre-charge control transistor (M4). Especially within the extremely short 1-UI of the time interval less than or equal to 10 picoseconds, reliable signal generation is ensured through multiple precisely controlled stages such as pre-charge and pre-discharge. The second-stage circuit, through the coordinated operation of the pull-down transistor (M5) and multiple pull-up transistors (M6, M7), converts the non-full-swing pulse signal into a full-swing signal, significantly improving signal quality.

[0029] In terms of timing control, this application utilizes the delay relationship between the A-phase clock signal and the B-phase clock signal, along with the synchronous RST signal output by the reset signal generation circuit, to achieve precise timing coordination. Specifically, for the 1 / 8 speed structure, the A-phase and B-phase clock signals differ by 3-UI; for the 1 / 4 speed structure, the A-phase and B-phase clock signals differ by 1-UI. Specifically, in the first-stage circuit, the pre-charge control transistor and the pre-discharge control transistor work alternately to complete the pre-charge, pre-discharge, complete discharge, and reset charge processes of the signal. This carefully designed timing arrangement ensures that all necessary signal processing steps are completed within an extremely short time.

[0030] It is worth noting that the reset signal generation circuit of this application generates a reset signal synchronized with the 1-UI pulse by using a simple combination of two AND gates and one NOR gate, utilizing a specific phase combination in the multi-phase clock signal. It should be noted that the specific number of groups and clock combinations in the reset signal generation circuit will vary depending on the rate used by the transmitter.

[0031] Taking a 1 / 8 rate transmitter as an example, since it uses an 8-phase clock (CK1 / CK2 / ... / CK7 / CK8), four sets of reset signals are required. Besides the CK2 / CK4 / CK6 / CK8 set mentioned above, the generation logic for the other three sets of reset signals is as follows:

[0032] Group 2: Perform an AND operation between CK2 and CK8, and an AND operation between CK4 and CK6. Then perform a NOR operation on the results of the two AND operations.

[0033] Group 3: Perform an AND operation between CK3 and CK5, and an AND operation between CK1 and CK7. Then perform a NOR operation on the results of the two AND operations.

[0034] Group 4: Perform an AND operation between CK5 and CK7, and an AND operation between CK1 and CK3. Then perform a NOR operation on the results of the two AND operations.

[0035] Each set of reset signals consists of two AND gates and one NOR gate, but with different input clock combinations. The four sets of reset signals are staggered by 1-UI in time and synchronized with the corresponding 1-UI data pulses, thus achieving precise timing control.

[0036] For a 1 / 4 rate transmitter, since a 4-phase clock is used, only two sets of reset signals are needed. Their generation logic can be referenced from the 1 / 8 rate case, selecting an appropriate clock combination.

[0037] The introduction of multiple reset signals is a significant innovation in timing control in this application. By utilizing different clock combinations, the phases of each reset signal are cleverly staggered, avoiding signal conflicts and ensuring that each 1-UI data pulse receives synchronous reset control. This design not only simplifies the circuit structure but also greatly improves the system's reliability. In ultra-high-speed scenarios, this multi-set reset signal scheme undoubtedly provides greater flexibility and adaptability for the implementation of the data generation circuit.

[0038] In summary, the above-described reset signal generation scheme fully demonstrates the innovative approach to timing optimization in this application. By designing multiple sets of reset signals tailored to local conditions, key timing issues in ultra-high-speed data transmission are effectively resolved. This design, together with the 1-UI pulse generation circuit and the full-swing conversion circuit, constitutes the complete technical solution of this application, possessing strong feasibility and practical value.

[0039] This design not only simplifies the circuit structure but also ensures the accuracy of signal shaping. In particular, in the second-stage circuit, the RST signal, in conjunction with the pulse signal, controls the conduction state of the pull-down and pull-up transistors, achieving a stable full-swing signal output.

[0040] Overall, this application is applicable to high-speed transmitters at 1 / 4 or 1 / 8 speeds, achieving complex signal processing functions through a simple circuit structure. The operation of all MOSFETs in the circuit is closely coordinated and mutually supportive, ensuring both signal quality and reliable circuit operation. This design not only solves the signal processing challenges in ultra-high-speed scenarios but also possesses strong engineering practicality, providing crucial technical support for the development of high-speed communication systems.

[0041] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0042] Figure 1 is a timing diagram of the generation of 1-UI data and RST signal according to an embodiment of this application.

[0043] [Correction 02.02.2026 based on Rule 91] Figure 2 is a schematic diagram of a 1-UI data generation circuit according to an embodiment of this application, wherein: the left side of Figure 2(a) is a structural schematic diagram of the 1-UI data circuit, as an example of multiple sets of 1-UI data generation circuits (a 1 / 8 rate transmitter requires 8 such 1-UI data generation circuits, and a 1 / 4 rate transmitter requires 4 such 1-UI data generation circuits); the right side of Figure 2(a) is a schematic diagram of the voltage waveform of a key node; Figure 2(b) is a schematic diagram of the node voltage timing, showing the detailed change process of the Dout_int node voltage under the control of clock signals CK1 and CK6 and the correspondence between the two.

[0044] Figure 3 is a schematic diagram of a 1-UI data full swing circuit according to an embodiment of this application, wherein: Figure 3(a) is a schematic diagram of the full swing conversion circuit; Figure 3(b) is a schematic diagram of the RST signal generation circuit, as an example of a set of reset signal generation circuits; Figure 3(c) is a schematic diagram of the voltage waveform of a key node. Detailed Implementation

[0045] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0046] Explanation of some concepts:

[0047] In digital communication systems, a unit interval (UI) represents the duration of one data bit. In this application, 1-UI refers to the smallest unit of time required to transmit a single data bit, which can be as small as 10 picoseconds in ultra-high-speed scenarios. This basic unit of time plays a crucial role in signal generation and processing.

[0048] A full-swing signal is a signal whose voltage swings completely between the power supply voltage (VDD) and ground (0V). Compared to non-full-swing signals, full-swing signals have greater noise margin and better signal integrity, which is crucial for ensuring reliable data transmission.

[0049] Pre-charge is the process of charging the output node to the power supply voltage VDD before the actual data transmission. In this application, this process is achieved by turning on the M4 transistor, preparing it for subsequent signal generation. The introduction of pre-charge significantly improves the circuit's response speed.

[0050] Pre-discharge is the process of pre-discharging the node voltage to a specific level (Vout_precharge) before full discharge. This process is controlled by transistor M2 and is one of the key steps in achieving high-speed signal generation in this application, laying the foundation for obtaining the ideal signal waveform.

[0051] 1 / 4 rate and 1 / 8 rate are operating modes where the transmitter's highest clock frequency is 1 / 4 or 1 / 8 of the full rate, respectively. This architecture is widely used in high-speed transmitters, which combine multiple low-speed data streams into full-rate data through multi-phase clocks, effectively reducing the transmission rate requirement of a single data stream.

[0052] A multi-phase clock refers to a set of clock signals with a fixed phase difference. This application uses eight phase clocks (CK1-CK8), where the phase difference between adjacent clock signals is 1-UI. The precise coordination of this set of clock signals is the foundation for achieving high-speed data transmission.

[0053] A multi-phase clock refers to a set of clock signals with a fixed phase difference. This application employs different numbers of phase clocks depending on the transmitter's rate requirements: eight phase clocks (CK1-CK8) are used for a 1 / 8 rate transmitter; and four phase clocks (CK1-CK4) are used for a 1 / 4 rate transmitter. In both cases, the phase difference between adjacent clock signals is 1-UI. The precise coordination of these clock signals is fundamental to achieving high-speed data transmission.

[0054] The RST (Reset Signal) is a reset control signal used to control signal shaping. It is synchronized with the 1-UI pulse and controls the critical timing in the full-swing conversion circuit to ensure the accuracy of signal shaping.

[0055] Reset charging is the process of restoring the output node voltage to its initial level. This process is achieved by turning on transistor M3, ensuring sufficient preparation for signal generation in the next cycle and guaranteeing continuous and stable operation of the circuit.

[0056] Pull-up and pull-down transistors are MOSFETs used to pull the node voltage high to VDD or low to ground, respectively. In the full-swing conversion circuit of this application, M5 acts as a pull-down transistor, and M6 / M7 acts as a pull-up transistor. Their coordinated operation enables full-swing signal conversion.

[0057] A non-full-swing pulse refers to a pulse signal whose voltage swing does not reach 0 to VDD. This type of signal is a raw signal that needs to be shaped. After processing by this application, it can be converted into an ideal full-swing signal, thereby improving the reliability of the system.

[0058] The following is a brief summary of some of the innovative aspects of this application:

[0059] In summary, this application relates to a 1-UI data generation circuit for an ultra-high-speed transmitter. In the field of ultra-high-speed data transmission, since the unit time interval (1-UI) has been shortened to approximately 10 ps, ​​achieving complete charging and discharging of a MOSFET within such a short time has become a significant technical challenge. Therefore, the 1-UI data generation circuit, as one of the most critical modules in an ultra-high-speed transmitter, directly affects the reliability of the entire system.

[0060] To address this technical challenge, this application proposes an innovative circuit scheme that reliably generates 1-UI data through the ingenious coordination of four MOSFETs. The basic circuit operation is as follows: First, input transistor M1 controls the input data. When the input data is high, M1 is turned on, ensuring data readiness. Before the rising edge of the B-phase clock signal (e.g., CK1), transistor M4 pre-charges the output node to VDD level. When the rising edge of the A-phase clock signal (e.g., CK6) arrives, transistor M2 turns on, initiating pre-discharge of the output node until the preset Vout_precharge level is reached. Subsequently, when the rising edge of the B-phase clock signal (CK1) arrives, transistor M4 turns off, and the circuit enters the full discharge stage. Finally, after the falling edge of the A-phase clock signal (CK6), transistor M2 turns off while transistor M3 turns on, resetting and charging the output node to VDD, preparing for the next cycle. By continuously cycling through these steps, the 1-UI pulse signal can be reliably generated. To further improve signal quality, this application also introduces an RST control signal and a shaping amplifier circuit composed of three MOSFETs in the output stage to convert the non-full-swing pulse signal into a full-swing signal from 0 to VDD. The innovation of this design is mainly reflected in three aspects: First, through the precise coordination of four MOSFETs and a multi-phase clock, the complete pre-charge, pre-discharge, full discharge, and reset charge processes are realized in an extremely short time of 1-UI; second, the full-swing characteristics of the output signal are ensured by utilizing the RST signal and the shaping amplifier circuit of three MOSFETs; finally, the overall circuit structure is simple, requiring no complex control logic, making it very suitable for ultra-high-speed applications.

[0061] This application successfully generates and shapes ultra-short 1-UI pulses by cleverly utilizing the turn-on / off timing of MOSFETs and the coordination of multi-phase clocks, significantly improving the circuit's response speed. This design not only solves the signal generation problem in ultra-high-speed scenarios but also has advantages such as simple structure and high reliability, representing a practical ultra-high-speed signal processing solution.

[0062] Figure 1 is a timing diagram of the 1-UI data generation circuit of this application, which focuses on how to use a multi-phase clock to accurately control the generation of the 1-UI pulse signal and the synchronization of the reset signal in the ultra-high-speed data transmission scenario.

[0063] As shown in the figure, this application uses an 8-phase clock signal (CK1 to CK8), where the time interval between the rising edges of two adjacent clocks is one unit interval (UI). These 8-phase clocks serve as both the timing control signal and the reference clock for data splicing in this application's circuit.

[0064] It should be noted that in the description of this application, the aforementioned 8-phase clock signal is represented by symbols such as CK1 and CK2, where the numbers represent the sequence numbers of the clock phases. It should also be noted that the multi-phase clock signal used in this application is not limited to 8 phases; it can be flexibly set according to the transmitter's rate requirements in actual applications (such as 1 / 4 rate or 1 / 8 rate). For example, in a 1 / 4 rate application scenario, 4 phase clock signals from CK1 to CK4 can be used; while in a 1 / 8 rate application scenario, 8 phase clock signals from CK1 to CK8 can be used. For ease of description, this application uses a 1 / 8 rate, 8-phase clock signal as an example, but the embodiments described are not limited thereto.

[0065] When using an 8-phase clock signal, the definitions of each clock signal are as follows:

[0066] CK1 represents the first clock signal.

[0067] CK2 represents the second clock signal.

[0068] CK3 represents the third clock signal.

[0069] CK4 represents the fourth clock signal.

[0070] CK5 represents the fifth clock signal.

[0071] CK6 represents the sixth clock signal.

[0072] CK7 indicates the seventh clock signal.

[0073] CK8 represents the eighth clock signal.

[0074] In the following description, the above symbols will be used consistently to refer to the corresponding clock signals to maintain consistency and conciseness. This consistent descriptive approach helps to understand the key technical aspects of this application, such as using multi-phase clocks to precisely control signal timing and achieve data splicing.

[0075] Taking D1_LOW as an example, after the low-speed data signal is processed by the 1-UI data generation circuit of this application, a narrow pulse signal D1_UI with a width of only 1-UI is generated under the coordination of the rising edges of CK6 and CK1. Using a similar method, other low-speed data signals can also generate corresponding 1-UI pulse signals.

[0076] To further improve the quality of the 1-UI pulse signal, this application also introduces an RST reset signal. Taking RST1 as an example, this reset signal is generated by the combinational logic from CK2 to CK8, and remains low during the D1_UI pulse, and high at other times. RST1 is strictly synchronized with D1_UI in time and is used to control the subsequent shaping circuit to shape the 1-UI pulse into a full-swing signal.

[0077] Finally, all 1-UI pulse signals (i.e., D1_UI, D2_UI, ..., D8_UI) are sequentially and alternately spliced ​​together in a time-division multiplexing manner to form the complete high-speed data output signal DOUT_HIGH. It can be seen that each data bit in DOUT_HIGH corresponds to one 1-UI pulse.

[0078] In summary, this application ingeniously utilizes the time interval characteristics of multi-phase clocks and the precise coordination between different clocks to reliably generate and shape 1-UI pulse signals, thereby achieving ultra-high-speed serial data transmission. Figure 1 vividly illustrates the timing control relationship of this application, intuitively revealing its core innovative idea.

[0079] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0080] The first embodiment of this application relates to a data generation circuit for a high-speed transmitter, as shown in Figures 2 and 3, which includes a first-stage circuit unit and a second-stage circuit unit.

[0081] The first-stage circuit unit is used to generate narrow pulse signals, including:

[0082] The input transistor (M1) has a gate used to receive input data signals;

[0083] The pre-discharge control transistor (M2) has its source connected to the drain of the input transistor (M1) to form a first intermediate node, and its gate is used to receive the A-phase clock signal.

[0084] The reset control transistor (M3) has its drain connected to the drain of the pre-discharge control transistor (M2) to form an output node, and its gate is used to receive the A-phase clock signal.

[0085] A pre-charge control transistor (M4) has its drain connected to the output node, its source used to receive the power supply voltage, and its gate used to receive the B-phase clock signal; wherein the B-phase clock signal has a predetermined time interval compared to the A-phase clock signal; the pre-discharge control transistor (M2) and the pre-charge control transistor (M4) respond to the A-phase clock signal and the B-phase clock signal, respectively, to perform pre-charge and pre-discharge on the output node, generating a pulse signal;

[0086] The second-level circuit unit is used to shape the pulse signal into a full-swing signal, including:

[0087] The pull-down transistor (M5) is connected between the final output node and the lowest potential, and its control terminal is used to receive the reset signal.

[0088] Multiple pull-up transistors (M6, M7) have their source and drain terminals connected between the final output node and the power supply voltage, respectively. The control terminal is used to receive the pulse signal output by the first-stage circuit unit. The pull-down transistor (M5) cooperates with the pull-up transistors (M6, M7) to convert the non-full-swing pulse signal into a full-swing signal output in response to the reset signal and the pulse signal.

[0089] Optionally, the time width of the narrow pulse signal is 1-UI, where UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

[0090] Optionally, the A-phase clock signal and the B-phase clock signal are two phases of the same set of multi-phase clock signals, wherein the multi-phase clock signals include at least 4-phase clock signals, and the time interval between the rising edges of each two adjacent phase clock signals is 1-UI; wherein the B-phase clock signal leads the A-phase clock signal by 3-UI.

[0091] Optionally, the gate of the input transistor (M1) is connected to the input terminal to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control transistor (M2) to form a first intermediate node (Data_int).

[0092] Optionally, the operation of the first-stage circuit unit includes: (1) before the rising edge of the A-phase clock signal arrives, the reset control transistor (M3) is turned on to precharge the output node (Dout_int) to the power supply voltage; during the time period before the rising edge of the A-phase clock signal arrives and after the falling edge of the B-phase clock signal arrives, the precharge control transistor (M4) is turned on, and the precharge of the output node (Dout_int) is maintained at the power supply voltage; (2) when the rising edge of the A-phase clock signal arrives, the pre-discharge control transistor (M2) is turned on to discharge the output node to a preset level; (3) when the rising edge of the B-phase clock signal arrives, the precharge control transistor (M4) is turned off, and the output node is further discharged to the lowest potential; (4) when the falling edge of the A-phase clock signal arrives, the reset control transistor (M3) is turned on, the pre-discharge transistor (M2) is turned off, and the output node is reset and charged to the power supply voltage.

[0093] Optionally, the circuit further includes at least one set of reset signal generation circuits for generating a reset signal synchronized with the pulse signal based on a multi-phase clock signal. For ease of understanding, the structure of one set of reset signal generation circuits is described below as an example. This set of reset signal generation circuits includes: a first AND gate, whose inputs are connected to the second and fourth clock signals respectively, for performing an AND operation on the two; a second AND gate, whose inputs are connected to the sixth and eighth clock signals respectively, for performing an AND operation on the two; and a NOR gate, whose inputs are connected to the outputs of the first and second AND gates respectively, for performing a NOR operation on the output signals of the two, and whose output is used to output the reset signal. The structures of other sets of reset signal generation circuits are the same, differing only in the selected combination of clock signals.

[0094] Optionally, the reset signal generation circuit receives an 8-phase clock signal as an input signal, and the time interval between the rising edges of two adjacent clock signals is 1-UI.

[0095] Optionally, the operation of the second-level circuit unit includes:

[0096] When the reset signal is high and the pulse signal output by the first stage circuit unit is high, the pull-down transistor (M5) is turned on, discharging the final output node to the zero potential;

[0097] When the reset signal is low and the pulse signal output by the first stage circuit unit is low, the multiple pull-up transistors (M6, M7) are turned on alternately to charge the final output node to the power supply voltage.

[0098] Optionally, the data generation circuit is used for a high-speed transmitter at 1 / 4 or 1 / 8 rate.

[0099] The following is a further explanation of Figures 2 and 3.

[0100] [Corrected according to Rule 91, 02.02.2026] Figure 2 is a schematic diagram of the specific implementation of the 1-UI data generation circuit. When the input data is high, M1 is turned on, and the voltage of node Data_int is pulled down to 0, preparing for the subsequent discharge process; when the input data is low, M1 is turned off. At this time, even if the CK6 and CK1 clock signals work normally, the Dout_int node will always remain at the pre-charge high level VDD and will not generate a 1-UI pulse. Referring to Figure 2(a), its working principle is as follows:

[0101] (1) During the pre-charge phase, the input data signal needs to be considered. When the input data is high, M1 is turned on, and the Data_int node is pulled down to low. If CK1 is high and CK6 is low, then M3 is turned on, M2 is turned off, and the output node Dout_int is charged to VDD level. After CK1 goes low and before the rising edge of CK6 arrives, M4 is turned on, and the output node Dout_int remains at VDD level. It should be noted that the above pre-charge process is based on the premise that the input data signal is high. When the input data is low, M1 is turned off, and the Data_int node remains high. At this time, regardless of the levels of CK1 and CK6, since there is no low-level drive at the source of M2, the Dout_int node cannot discharge and will remain at VDD level.

[0102] (2) When the rising edge of CK6 arrives (CK1 is high at this time), M2 and M4 are turned on (M3 is turned off). Under the combined action of M2 and M4, Dout_int begins pre-discharge, and the voltage drops to a certain value Vout_precharge. This process is the pre-discharge implemented using M2 and M4.

[0103] (3) When the rising edge of CK1 arrives (CK6 is still at a high level at this time), both M3 and M4 are turned off. With M2 continuously conducting, Dout_int enters the complete discharge stage, and the voltage drops further to close to VSS. At this time, the 1-UI pulse is generated.

[0104] (4) When the falling edge of CK6 arrives, M2 is turned off, M3 is turned on, and Dout_int is reset and charged back to VDD to prepare for the next cycle.

[0105] (5) Input data Data is prepared in the Data_int node after being controlled by M1. M1 acts as an input switch, and its operation can be divided into two types:

[0106] When the input data Data is high, M1 is turned on, and the node Data_int is pulled down to low. This low-level signal is transmitted to the source of M2, and with the coordination of the CK6 and CK1 clocks, the Dout_int node will generate a narrow pulse signal with a width of 1-UI.

[0107] When the input data Data is low, M1 is turned off, and node Data_int is in a high-impedance state. Its voltage is determined by the parasitic capacitance and is usually near VDD. Even if the clocks CK6 and CK1 are working normally, the Dout_int node cannot discharge because there is no low-level drive at the source of M2, and it remains in a pre-charged high-level state. In other words, the output node will not generate a 1-UI pulse, and the circuit is in a silent state.

[0108] In summary, the conduction of transistor M1 directly affects the operation of subsequent circuits. The Dout_int node only generates 1-UI pulses in sync with the clock signal during the period when the input data Data is high; when the input data is low, the output node remains stationary. This design ensures accurate control of the output pulses by the input data.

[0109] (6) Throughout the process, the pulse signal is reliably generated within 1-UI time by coordinating the timing of M1, M2, M3, M4 with CK1 and CK6.

[0110] (7) Figure b shows the voltage waveform diagram of each key node, which intuitively shows the working process of the circuit in 1-UI.

[0111] In summary, this circuit efficiently generates 1-UI pulses by utilizing the switching on and off of four MOSFETs and coordinating the timing of two-phase clocks. Its key innovation lies in cleverly embedding multiple stages—pre-charging, pre-discharging, complete discharging, and reset charging—within an 8UI timeframe, making full use of limited time resources.

[0112] [Corrected according to Rule 91, 02.02.2026] Further, Figure 2(b) is a voltage waveform timing diagram of the key node Dout_int in the data generation circuit of the present invention, further demonstrating the details of the voltage change of this node under the control of clock signals CK1 and CK6. As shown in the figure, the voltage of Dout_int goes through three main stages: reset, pre-discharge, and generation of a 1-UI pulse. Specifically, as can be seen in the figure, when the falling edge of CK6 arrives (at this time, the rising edge of CK1 has already become high by 1UI), the Dout_int node will be reset (also known as pre-charge) to the VDD level, and the reset time lasts for 4UI, which is sufficient time to ensure complete reset. Subsequently, when the rising edge of CK6 arrives (at this time, CK1 is low), Dout_int begins pre-discharge, using the 3UI time between the rising edge of CK6 and the falling edge of CK1 to realize the drop of the node voltage. When the rising edge of CK1 arrives, Dout_int is further pulled down for 1UI time to form a narrow pulse signal with a width of 1-UI. Finally, the arrival of the next falling edge of CK6 (at which point CK1 has returned to a high level) triggers the reset of Dout_int again, and the circuit repeats the above waveform change cycle. The precise correspondence between the Dout_int node voltage and the clock signals CK1 and CK6 in Figure 2(b) intuitively demonstrates the innovative idea of ​​the circuit of this invention to reliably generate 1-UI pulse signals within limited time resources through carefully designed timing control.

[0113] Figure 3(a) is a schematic diagram of the 1-UI data full swing circuit, which is used to shape the 1-UI pulse signal generated in Figure 2 into a full swing (i.e., from 0 to VDD) signal.

[0114] Its main circuit structure and working principle are as follows:

[0115] 1. An RST control signal and three MOSFETs (M5, M6, M7) are introduced to shape and amplify the 1-UI pulse signal.

[0116] 2. When the falling edge of the 1-UI pulse signal (Dout_int1 or Dout_int2) arrives, the RST signal is low. At this time, M5 is turned off and M6 or M7 is turned on, charging the final output node Dout to the VDD level.

[0117] 3. When the rising edge of the 1-UI pulse signal (Dout_int1 or Dout_int2) arrives, the RST signal is high. At this time, M6 and M7 are turned off, and M5 is turned on, discharging the final output node Dout to 0 (VSS).

[0118] 4. By coordinating the timing of M5, M6, and M7 with the RST signal and the 1-UI pulse signal, the non-full-amplitude 1-UI pulse can be reliably converted into a rail-to-rail full-amplitude signal output.

[0119] Therefore, the circuit in Figure 3(a), as the successor to the circuit in Figure 2, further improves the swing and quality of the output signal and is an important component of the 1-UI data generation circuit. The RST signal is generated by a multi-phase clock combination, ensuring synchronization with the 1-UI pulse.

[0120] Figure 3(b) is a schematic diagram of the RST signal generation circuit. Its function is to generate an RST control signal synchronized with the 1-UI pulse based on the multi-phase clock signal, so as to provide appropriate control timing for the shaping circuit in Figure 3(a).

[0121] The specific circuit structure is as follows:

[0122] 1. Two AND gates are used to perform AND operations on CK2 and CK4, and CK6 and CK8 respectively.

[0123] 2. A NOR gate performs a NOR operation on the outputs of two AND gates to obtain the final RST signal.

[0124] Its working principle is:

[0125] 1. Assume the input is an 8-phase clock signal (CK1 to CK8), with a rising edge interval of 1-UI between any two adjacent clock cycles.

[0126] 2. The first AND operation is performed on CK2 and CK4. The output is high if and only if both CK2 and CK4 are high, and the corresponding RST signal should be low.

[0127] 3. Similarly, the second AND gate performs an AND operation on CK6 and CK8. Its output is high if and only if both CK6 and CK8 are high, and the corresponding RST signal should be low.

[0128] 4. The last NOR gate performs a NOR operation on the outputs of the two AND gates. The RST signal is high only if both AND gate outputs are low; otherwise, it is low.

[0129] 5. This generates an RST control signal that is synchronized with the 1-UI pulse. It is low when CK2 / CK4 are both high or CK6 / CK8 are both high, and high at other times.

[0130] Therefore, the circuit in Figure 3(b) cleverly generates the required RST control signal by using the combinational logic of multi-phase clocks, providing precise control timing for the shaping circuit in Figure 3(a), thereby reliably realizing the shaping and amplification of the 1-UI pulse signal.

[0131] Figure 3(c) shows the key node voltage waveforms of the 1-UI data full swing circuit, clearly reflecting the complete working process of the circuit within the 1-UI time. These waveforms demonstrate the shaping effect of transistors M5-M7 on the input pulse signal in Figure 3(a), as well as the control timing of the RST signal.

[0132] First, looking at the waveform (red) at the Dout_int node, this is the initial 1-UI pulse signal generated by the circuit in Figure 2. This waveform shows the complete charging and discharging process: starting from the VDD level, it drops to the Vout_precharge voltage after a pre-discharge stage, and then enters the full discharge stage until it approaches ground level, forming a characteristic narrow pulse shape. This process demonstrates the precise timing control of the preceding circuitry.

[0133] Secondly, the waveform of the RST signal (green) demonstrates the timing characteristics of the reset control. This control signal, generated by the circuit in Figure 3(b), remains low during the 1-UI pulse, with its falling edge arriving 1UI time before the falling edge of the 1-UI pulse, and its rising edge arriving strictly synchronously with the rising edge of the 1-UI pulse. The RST signal achieves precise timing control of the output node by controlling the conduction state of transistor M5: when RST is high, M5 is turned on and pulls down the output; when RST is low, M5 is turned off and pulls up the output.

[0134] Finally, the shaped Dout output waveform (red) clearly shows the full swing characteristic. Its operation can be divided into three stages:

[0135] 1. When RST is at a low-high level (before the 1-UI pulse arrives), M6 and M7 are turned off, M5 is turned on, and Dout is discharged to ground level.

[0136] 2. When 1UI time before the falling edge of the 1-UI pulse arrives, RST goes low, M5 is turned off, and Dout remains at ground level; after the falling edge of the 1-UI pulse arrives, M6 or M7 is turned on, and Dout is charged to VDD.

[0137] 3. When the 1-UI pulse ends (rising edge arrives), the RST rising edge also arrives synchronously. M6 / M7 is turned off, M5 is turned on, and Dout discharges to a low level under the action of M5.

[0138] It is worth noting that, due to the strong pull-down capability of M5, the falling edge of Dout exhibits a steep characteristic. The rising edge, however, shows a relatively flat characteristic due to the alternating conduction of M6 and M7 and the parasitic RC effect. Nevertheless, the final output Dout signal still achieves a stable 0-VDD full-amplitude swing, significantly improving signal quality.

[0139] This set of waveforms fully records the shaping process of the 1-UI pulse signal, demonstrating the circuit's precise timing control and reliable operation. The coordinated changes in the voltages of the three key nodes intuitively showcase the innovative design concept of this application in ultra-high-speed signal processing.

[0140] Working principle:

[0141] The operation of the above embodiment can be divided into two core parts: the first-stage circuit generates the 1-UI pulse, and the second-stage circuit completes the full-swing conversion of the signal. Specifically, the first-stage circuit operates under the control of a multi-phase clock through the precise coordination of four MOSFETs; the second-stage circuit utilizes three MOSFETs and the RST signal to achieve signal shaping.

[0142] First, the operation of the first-stage circuit is shown in Figure 2. Due to the use of a 1 / 8 speed structure, the input data signal is relatively slow, ensuring that the input transistor M1 is fully turned on, thus stabilizing the level of node Data_int. The circuit operation can be divided into two cases:

[0143] When the input data is high, M1 is turned on, and Data_int is pulled low. During the precharge phase, clock CK1 is low, and precharge control transistor M4 is turned on, charging the output node Dout_int to VDD level. When the rising edge of CK6 arrives, pre-discharge control transistor M2 is turned on while reset control transistor M3 is turned off, and Dout_int begins the pre-discharge process, with the voltage dropping to the preset Vout_precharge level. Subsequently, when the rising edge of CK1 arrives, precharge control transistor M4 is turned off, and the circuit enters the full discharge phase, with the Dout_int voltage dropping further. Finally, when the falling edge of CK6 arrives, M2 is turned off while M3 is turned on, and Dout_int is reset and charged to VDD, preparing for the next cycle. Through this precise timing control, narrow pulse signals can be reliably generated within 1-UI time.

[0144] When the input data is low, M1 is turned off, and the Data_int node remains high. At this time, regardless of the clock changes of CK6 and CK1, the Dout_int node cannot discharge because there is no low-level drive at the source of M2, and it remains at VDD level. In other words, during the period when the input is low, the output node will not generate a 1-UI pulse, and the circuit is in a silent state.

[0145] In summary, the first-stage circuit initiates a series of actions, including pre-charging and pre-discharging, to generate a narrow pulse within a 1-UI time period only when the input data is high. During periods when the input data is low, the circuit remains stationary. The high or low level of the input data directly controls the generation of the output pulse.

[0146] Secondly, the operation of the second-stage circuit is shown in Figure 3. The RST signal is generated by the combinational logic circuit shown in Figure 3(b), obtained by performing logical operations on the four even-phase clock signals CK2 / CK4 / CK6 / CK8. When RST is low and Dout_int1 or Dout_int2 is low, pull-up transistors M6 or M7 are turned on, while pull-down transistor M5 is turned off, and the output node Dout is charged to VDD. When RST is high (Dout_int1 or Dout_int2 also goes high simultaneously), M5 is turned on and M6 / M7 are turned off, and Dout is pulled low to ground. In this way, the non-full-swing Dout_int signal is converted into a full-swing signal from 0 to VDD.

[0147] The RST signal generation circuit employs a simple combinational logic structure, as shown in Figure 3(b). Two AND gates perform AND operations on CK2 / CK4 and CK6 / CK8 respectively, and then pass them through a NOR gate to obtain the final RST signal. This design ensures precise synchronization between the RST signal and the 1-UI pulse, thereby guaranteeing the accuracy of signal shaping.

[0148] The overall circuit waveform is shown in Figure 3(c). It can be clearly seen that the non-full-swing pulse of Dout_int, after processing by the second-stage circuit, becomes a well-defined full-swing square wave signal at the output node Dout. This signal has greater noise margin and better signal integrity, making it ideal for transmission in ultra-high-speed systems.

[0149] The above embodiments, through ingenious circuit design and precise timing control, successfully achieve signal generation and shaping in an ultra-short time, providing a reliable technical solution for ultra-high-speed data transmission.

[0150] Furthermore, the above embodiment proposes an innovative two-stage ultra-high-speed data generation circuit. The first-stage circuit, through precise coordination of the input transistor, pre-discharge control transistor, reset control transistor, and pre-charge control transistor, utilizes the phase difference between the two-phase clock signals CK1 and CK6 to achieve reliable narrow pulse signal generation in an extremely short time of less than 10 picoseconds. The second-stage circuit innovatively introduces a multi-set RST reset signal mechanism, using precise driving of pull-down and pull-up transistors to further shape the non-full-swing signal into an ideal full-swing signal. This synergistic innovation of the two-stage circuit not only breaks through the key bottleneck of ultra-high-speed data transmission but also flexibly adapts to different application scenarios such as 1 / 4 and 1 / 8 data rates, showing broad application prospects in fields such as fiber optic communication and chip interconnection.

[0151] Technical effects:

[0152] The data generation circuit proposed in the above embodiment adopts a two-stage structure design, successfully solving the key problems of signal generation and shaping in ultra-high-speed scenarios. The first-stage circuit achieves efficient generation of narrow pulse signals through the ingenious cooperation of the input transistor (M1), pre-discharge control transistor (M2), reset control transistor (M3), and pre-charge control transistor (M4). Especially within the extremely short 1-UI of a time interval less than or equal to 10 picoseconds, reliable signal generation is ensured through multiple precisely controlled stages such as pre-charge and pre-discharge. The second-stage circuit, through the coordinated work of the pull-down transistor (M5) and multiple pull-up transistors (M6, M7), converts the non-full-swing pulse signal into a full-swing signal, significantly improving signal quality.

[0153] In terms of timing control, this application utilizes the delay relationship between the A-phase clock signal and the B-phase clock signal, along with the synchronous RST signal output by the reset signal generation circuit, to achieve precise timing coordination. Specifically, for the 1 / 8 speed structure, the A-phase and B-phase clock signals differ by 3-UI; for the 1 / 4 speed structure, the A-phase and B-phase clock signals differ by 1-UI. Specifically, in the first-stage circuit, the pre-charge control transistor and the pre-discharge control transistor work alternately to complete the pre-charge, pre-discharge, complete discharge, and reset charge processes of the signal. This carefully designed timing arrangement ensures that all necessary signal processing steps are completed within an extremely short time.

[0154] Those skilled in the art will understand that the technical solution of this application is applicable to both 1 / 4-speed and 1 / 8-speed high-speed transmitters. For ease of description and understanding, the detailed descriptions of circuit structure, operation process, and timing relationships in the specification all use a 1 / 8-speed transmitter as an example. In the 1 / 8-speed structure, an 8-phase clock signal (CK1 to CK8) is used, with the A-phase and B-phase clock signals differing by 3-UI, requiring 4 sets of reset signal generation circuits. In the 1 / 4-speed structure, only a 4-phase clock signal is needed, with the A-phase and B-phase clock signals differing by 1-UI, correspondingly requiring only 2 sets of reset signal generation circuits. Although the specific number of clock phases and timing relationships differ, the core circuit structure, pre-charge / discharge mechanism, and signal shaping principle remain unchanged. In other words, the two-stage circuit structure proposed in this application (including the first-stage 1-UI pulse generation circuit and the second-stage full-swing conversion circuit) can flexibly adapt to the application requirements of different speeds by adjusting the clock phase configuration and the number of reset signal sets. This design ensures both the versatility of the technical solution and provides sufficient flexibility for practical applications.

[0155] It is worth noting that the above embodiment demonstrates an implementation of a set of reset signal generation circuits. Taking this set as an example, a reset signal synchronized with the corresponding 1-UI pulse is generated by a simple combination of two AND gates and one NOR gate, utilizing CK2, CK4, CK6, and CK8 from the 8-phase clock signal. Several other similar reset signal generation circuits are needed in the 1 / 8 rate transmitter; they use different clock phase combinations but all employ the same circuit structure. This design not only simplifies the circuit structure but also ensures the accuracy of signal shaping. Especially in the second-stage circuit, the RST signal, in conjunction with the pulse signal, controls the conduction state of the pull-down and pull-up transistors, achieving a stable full-swing signal output.

[0156] Overall, the above embodiments are applicable to high-speed transmitters at 1 / 4 or 1 / 8 speeds, achieving complex signal processing functions through a simple circuit structure. The operation of all MOSFETs in the circuit is closely coordinated and mutually supportive, ensuring both signal quality and reliable circuit operation. This design not only solves the signal processing challenges in ultra-high-speed scenarios but also possesses strong engineering practicality, providing crucial technical support for the development of high-speed communication systems.

[0157] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0158] This example presents a 1-UI full-swing data generation circuit that integrates pre-charge and discharge functions, greatly improving the circuit response speed and making it suitable for use in ultra-high-speed transmitters.

[0159] Specifically, this example proposes a design as shown in Figure 2, using four MOSFETs to implement the 1-UI data generation function (Figure 2a). Taking a 1 / 8 speed as an example (Figure 2b), the rising edge of clock CK6 leads the rising edge of CK1 by 3-UI time. Since the input data is a relatively low-speed signal, it can be assumed that the input Data is fully ready, MOSFET M1 is fully turned on, and the node Data_int voltage is 0. During the pre-charge phase, CK6 is low, MOSFET M3 is turned on, and node Dout_int is charged to VDD. After the falling edge of CK1, MOSFET M4 is turned on, and Dout_int remains at VDD. After the rising edge of CK6, MOSFET M2 is turned on (MOSFET M3 is turned off), and Dout_int begins pre-discharge. When discharging to vout_prechage, the rising edge of CK1 arrives, MOSFET M4 is turned off, and the full discharge phase begins. After the falling edge of CK6, MOSFET M2 is turned off, MOSFET M3 is turned on, and Dout_int is reset and charged to VDD, and then the above process is continuously repeated. It's important to note that the above analysis is based on the case where the input data signal is high. When the input data is low, transistor M1 is off, and node Data_int remains at VDD level. In this case, regardless of the changes in CK1 and CK6, node Dout_int will not discharge but will remain at VDD level. In other words, when the input data is low, the output node will not generate a narrow pulse, and the circuit is in a silent state. In this case, since there is no large current charging or discharging, there is no issue with charging / discharging speed. The circuit timing is entirely determined by the high-level period of the input data.

[0160] In the circuit described above, the Dout_int signal cannot reach the full swing (0→VDD); combined with the circuit shown in Figure 3, the output signal Dout can reach the full swing, where the RST signal comes from the combinational logic implementation of the previous clock signal (CK2 / CK4 / CK6 / CK8), and the circuit diagram is shown in Figure 3b; the signal timing is shown in Figure 1.

[0161] As shown in Figure 3c, when the falling edge of the Dout_int1 or Dout_int2 pulse signal arrives, the RST signal is low, transistor M5 is turned off, and transistors M6 or M7 charge the output node Dout to VDD; when the rising edge of the Dout_int1 or Dout_int2 pulse signal arrives, the RST signal is high, transistors M6 / M7 are both turned off, and transistor M5 discharges the output node Dout to zero; after this processing, the Dout_int1 or Dout_int2 pulse signal is shaped into a full-swing signal.

[0162] In summary, this application achieves ultra-high-speed, low-power, and high-precision pulse signal generation through system optimization in pre-charge and pre-discharge control, MOSFET size matching, and second-stage shaping circuitry, greatly expanding the application scope of ultra-high-speed serial communication. This technical solution is simple to operate, easy to integrate, and can be widely applied in high-speed fiber optic communication, chip interconnection, radar, and other fields, possessing significant technical advantages and commercial value.

[0163] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0164] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A data generation circuit for a high-speed transmitter, characterized in that, It includes first-level circuit units and second-level circuit units, wherein, The first-stage circuit unit is used to generate a narrow pulse signal, including: The gate of the input transistor M1 is used to receive input data signals; The source of the pre-discharge control transistor M2 is connected to the drain of the input transistor M1 to form a first intermediate node, and the gate is used to receive the A-phase clock signal. The drain of the reset control transistor M3 is connected to the drain of the pre-discharge control transistor M2 to form an output node, and the gate is used to receive the A-phase clock signal. The pre-charge control transistor M4 has its drain connected to the output node, its source used to receive the power supply voltage, and its gate used to receive the B-phase clock signal; wherein the B-phase clock signal has a predetermined time delay compared to the A-phase clock signal; the pre-discharge control transistor M2 and the pre-charge control transistor M4 respond to the A-phase clock signal and the B-phase clock signal, respectively, to perform pre-charge and pre-discharge on the output node, generating a pulse signal; The second-stage circuit unit is used to shape the pulse signal into a full-swing signal, including: The pull-down transistor M5 is connected between the final output node and the lowest potential, and its control terminal is used to receive the reset signal. Multiple pull-up transistors M6 and M7 have their drain and source terminals connected between the final output node and the power supply voltage, respectively. The control terminal is used to receive the pulse signal output by the first-stage circuit unit. The pull-down transistor M5 cooperates with the pull-up transistors M6 and M7 to convert the non-full-swing pulse signal into a full-swing signal output in response to the reset signal and the pulse signal.

2. The data generation circuit as described in claim 1, characterized in that, The time width of the narrow pulse signal is 1-UI, where UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

3. The data generation circuit as described in claim 2, characterized in that, The A-phase clock signal and the B-phase clock signal are two phases of the same set of multi-phase clock signals, wherein the multi-phase clock signals include at least 4 phase clock signals, and the time interval between the rising edges of each two adjacent phase clock signals is 1-UI; wherein the B-phase clock signal leads the A-phase clock signal by 3-UI.

4. The data generation circuit as described in claim 3, characterized in that, The gate of the input transistor M1 is connected to the input terminal to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control transistor M2 to form a first intermediate node.

5. The data generation circuit as described in claim 4, characterized in that, The operation of the first-stage circuit unit includes: before the rising edge of the A-phase clock signal arrives, the pre-charge control transistor M4 is turned on to pre-charge the output node to the power supply voltage; when the rising edge of the A-phase clock signal arrives, the pre-discharge control transistor M2 is turned on to discharge the output node to a preset level; when the rising edge of the B-phase clock signal arrives, the pre-charge control transistor M4 is turned off, and the output node is further discharged to the lowest potential; when the falling edge of the A-phase clock signal arrives, the reset control transistor M3 is turned on, the pre-discharge control transistor M2 is turned off, and the output node is reset and charged to the power supply voltage.

6. The data generation circuit as described in claim 3, characterized in that, It also includes at least one set of reset signal generation circuits for generating a reset signal synchronized with the pulse signal according to the multi-phase clock signal. The reset signal generation circuit includes: a first AND gate, whose input terminals are respectively connected to the second clock signal and the fourth clock signal, for performing an AND operation on the two; a second AND gate, whose input terminals are respectively connected to the sixth clock signal and the eighth clock signal, for performing an AND operation on the two; and a NOR gate, whose input terminals are respectively connected to the output terminals of the first AND gate and the second AND gate, for performing a NOR operation on the output signals of the two, and whose output terminal is used to output the reset signal.

7. The data generation circuit as described in claim 6, characterized in that, The reset signal generation circuit receives an 8-phase clock signal as an input signal, and the time interval between the rising edges of two adjacent clock signals is 1-UI.

8. [Correction 02.02.2026 according to Rule 91] The data generation circuit as described in claim 7, characterized in that, The operation of the second-level circuit unit includes: When the reset signal is high and the pulse signal output by the first stage circuit unit is high, the pull-down transistor M5 is turned on, discharging the final output node to zero potential; When the reset signal is low and the pulse signal output by the first stage circuit unit is low, the multiple pull-up transistors M6 and M7 are alternately turned on to charge the final output node to the power supply voltage.

9. The data generation circuit as described in claim 8, characterized in that, The data generation circuit is used in high-speed transmitters with a 1 / 4 or 1 / 8 rate.

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