Transistor, driving backplane, display screen, and electronic device

Abstract

The present application relates to the technical field of electronic products, and provides a transistor, a driving backplane, a display screen, and an electronic device, configured to solve the difficulty in ensuring a large on-state current for transistors, and to avoid brightness jumps and uneven brightness in display screens at low grayscale and low brightness levels. Specifically, the transistor comprises a gate, an insulating layer, a source, a drain, and a plurality of channels. The insulating layer is connected onto the gate. The source and the drain are spaced apart. The plurality of channels are spaced apart, and each channel is connected to the side of the insulating layer facing away from the gate and is connected between the source and the drain. The plurality of channels comprise a first channel and a second channel. A subthreshold slope of the first channel is greater than a subthreshold slope of the second channel, and a threshold voltage of the first channel is less than a threshold voltage of the second channel.

Description

Transistors, driver backplanes, displays, and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510066986.0, filed on January 15, 2025, entitled "Transistor, Driver Backplane, Display Screen and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic product technology, and more particularly to transistors, driver backplanes, displays, and electronic devices. Background Technology

[0003] Transistors are typically placed in the driver backplane of a display screen to control the brightness of light-emitting diodes (LEDs) using their switching characteristics. Specifically, the number of charge carriers in the transistor's channel can be controlled by adjusting the voltage at the transistor's gate, thereby controlling the current when the transistor's source and drain are conducting. The magnitude of this current controls the brightness of the LED.

[0004] In related technologies, it is difficult for transistors to avoid brightness jumps and uneven brightness in low grayscale and low brightness displays while ensuring a large on-state current. Summary of the Invention

[0005] This application provides transistors, driving backplanes, displays, and electronic devices to solve the problem that transistors are difficult to maintain a large on-state current, thus avoiding brightness jumps and uneven brightness in displays at low grayscale and low brightness levels.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, a transistor is provided, the transistor including a gate, an insulating layer, a source, a drain, and a plurality of channels, the insulating layer being connected to the gate; the source and drain being spaced apart; the plurality of channels being spaced apart, each channel being connected to the side of the insulating layer opposite to the gate, and each channel being connected between the source and the drain; the plurality of channels including a first channel and a second channel, the subthreshold slope of the first channel being greater than the subthreshold slope of the second channel, and the threshold voltage of the first channel being less than the threshold voltage of the second channel.

[0008] According to the transistor of the present application embodiment, since the threshold voltage of the first channel is lower than the threshold voltage of the second channel, after a voltage is applied to the gate, the first channel will reach the subthreshold voltage before the second channel, thereby generating current in the first channel first. Furthermore, in the subthreshold voltage region, even if some carriers flow in the second channel, the number of carriers in the first channel will be greater than the number of carriers in the second channel. Therefore, in the subthreshold voltage region, the source and drain of the transistor are mainly turned on through the first channel.

[0009] Furthermore, since the subthreshold slope of the first channel is greater than that of the second channel, the adjustment window of the gate voltage will be correspondingly increased in the subthreshold voltage region. This can reduce the adjustment precision of the gate voltage, thereby reducing the probability of brightness jumps and uneven brightness in the display screen under low grayscale and low brightness conditions, thus improving the display effect of the display screen.

[0010] Once the voltage applied to the gate reaches the threshold voltage, both the first and second channels are fully turned on, and the source and drain are connected through the first and second channels. That is, the source and drain of the transistor can be turned on through multiple channels. The number of carriers in multiple channels is greater than that in a single channel, which increases the current when the transistor is fully turned on, i.e., increases the on-state current.

[0011] In summary, by ensuring that the subthreshold slope of the first channel is greater than that of the second channel, and that the threshold voltage of the first channel is less than that of the second channel, it is possible to guarantee that the transistor has a large on-state current and reduce the probability of brightness jumps and uneven brightness in the display screen at low grayscale and low brightness, thereby improving the display screen's display effect.

[0012] In one possible implementation of the first aspect, the subthreshold slope of the first channel is greater than or equal to 0.1V / dec and less than or equal to 1V / dec. When the subthreshold slope of the first channel is within the range of greater than or equal to 0.1V / dec and less than or equal to 1V / dec, the gate voltage adjustment window is kept within a suitable range when the transistor is in the subthreshold voltage region. This avoids excessively high gate voltage adjustment precision, which could lead to brightness jumps and uneven brightness in the display screen at low grayscale and low brightness levels.

[0013] And / or, the subthreshold slope of the second channel is greater than or equal to 0.006V / dec and less than or equal to 0.3V / dec. A subthreshold slope of the second channel within the range of greater than or equal to 0.006V / dec and less than or equal to 0.3V / dec ensures good conductivity of the second channel when the source and drain of the transistor are fully turned on, thereby guaranteeing a large on-state current and low power consumption.

[0014] In one possible implementation of the first aspect, the material of the first channel is the same as that of the second channel; the thickness of the first channel is greater than the thickness of the second channel along the arrangement direction of the insulating layer and the gate, and the width of the first channel is less than or equal to the width of the second channel along the first direction; the first direction is perpendicular to the arrangement direction of the source and drain, and perpendicular to the arrangement direction of the gate and the insulating layer.

[0015] In this way, since the first and second channels use the same material, when the thickness of the first channel is greater than that of the second channel, the defect density of the first channel will be greater than that of the second channel, and the subthreshold slope of the first channel will be greater than that of the second channel. The adjustment window of the gate voltage in the subthreshold voltage region of the transistor will be correspondingly increased, thereby reducing the gate voltage adjustment precision. This, in turn, reduces the probability of brightness jumps and uneven brightness at low grayscale and low brightness levels, thus improving the display effect.

[0016] When the gate voltage reaches the threshold voltage, both the first and second channels are fully open, and the source and drain are connected through the first and second channels. At this time, if the widths of the first and second channels are equal, the number of channels used by the transistor to conduct the source and drain increases, which can increase the current of the transistor when it is fully turned on, that is, increase the on-state current.

[0017] Furthermore, the first and second channels can be manufactured using the same process, allowing them to be fabricated in the same step, which simplifies the transistor manufacturing process and reduces costs.

[0018] In one possible implementation of the first aspect, the ratio of the thickness of the first channel to the thickness of the second channel is greater than or equal to 2 and less than or equal to 20.

[0019] By setting the ratio of the thickness of the first channel to the thickness of the second channel within the range of greater than or equal to 2 and less than or equal to 20, a suitable difference can be made between the thickness of the first channel and the thickness of the second channel. This ensures that the current of the transistor in the subthreshold voltage region is dominated by the first channel, and that the second channel has a smaller impact on the first channel, thereby ensuring the performance of the transistor.

[0020] In one possible implementation of the first aspect, the ratio of the width of the second channel to the width of the first channel is greater than or equal to 5 and less than or equal to 50.

[0021] By setting the ratio of the width of the second channel to the width of the first channel within the range of greater than or equal to 5 and less than or equal to 50, the widths of the second channel and the first channel can have a suitable difference. This ensures that when the gate voltage is greater than the threshold voltage, the transistor current is dominated by the second channel, and the first channel has a smaller impact on the second channel, thereby ensuring the performance of the transistor.

[0022] In one possible implementation of the first aspect, multiple channels are arranged along a first direction, which is perpendicular to the arrangement direction of the source and drain electrodes and also perpendicular to the arrangement direction of the gate and insulating layer. This facilitates the arrangement of multiple channels.

[0023] In one possible implementation of the first aspect, the gate includes a plurality of sub-gates, the insulating layer includes a plurality of sub-insulating layers, and the plurality of sub-gates, the plurality of sub-insulating layers and the plurality of channels are arranged alternately in sequence; a sub-insulating layer is connected between a sub-gate and a channel; the arrangement direction of the plurality of sub-gates, the arrangement direction of the plurality of insulating layers and the arrangement direction of the plurality of channels are the same.

[0024] In this way, multiple channels, multiple sub-gates, and multiple sub-insulating layers can make full use of the space in the arrangement direction of multiple channels to reduce the space occupied in the direction perpendicular to the arrangement direction of multiple channels, making the transistor applicable to more scenarios.

[0025] In one possible implementation of the first aspect, the gate further includes a gate voltage control terminal, to which multiple sub-gates are connected. This ensures that when a voltage is input to the multiple sub-gates through the gate voltage control terminal, the voltages of the multiple sub-gates are identical, guaranteeing normal transistor operation.

[0026] In one possible implementation of the first aspect, the source includes multiple sub-sources, the drain includes multiple sub-drains, and a channel connects one sub-source and one sub-drain. Setting the source as multiple sub-sources and the drain as multiple sub-drains facilitates the configuration of the drain, source, and multiple channels, thereby simplifying transistor fabrication.

[0027] In one possible implementation of the first aspect, the source also includes a source voltage control terminal, to which multiple sub-sources are connected. By connecting multiple sub-sources to the source voltage control terminal, it is convenient to connect multiple sub-sources to the driving circuit. The drain also includes a drain voltage control terminal, to which multiple sub-drains are connected. By connecting multiple sub-drains to the drain voltage control terminal, it is convenient to connect multiple sub-drains to the light-emitting diode.

[0028] In one possible implementation of the first aspect, an insulating medium is filled between any two adjacent channels. By filling the space between any two adjacent channels with an insulating medium, multiple channels can be isolated by the insulating medium to prevent conduction between channels from affecting the transistor's performance in the subthreshold voltage region and above the threshold voltage.

[0029] In one possible implementation of the first aspect, the channel material includes oxide. Using oxide as the channel material can reduce the subthreshold slope of the transistor, improve the display effect, and reduce the power consumption of the display.

[0030] In one possible implementation of the first aspect, the oxide is one of indium oxide, gallium oxide, zinc oxide, indium gallium zinc oxide, indium gallium oxide, and indium zinc oxide.

[0031] In one possible implementation of the first aspect, the plurality of channels further includes at least one third channel, wherein the subthreshold slope of the third channel is greater than the subthreshold slope of the second channel and less than the subthreshold slope of the first channel; and the threshold voltage of the third channel is greater than the threshold voltage of the first channel and less than the threshold voltage of the second channel.

[0032] In this way, the gate voltage of the transistor can transition from subthreshold voltage to threshold voltage through at least one third channel until the first channel, at least one third channel, and the second channel are all fully turned on, thus improving the stability of the transistor's gate voltage transition from subthreshold voltage to threshold voltage.

[0033] In one possible implementation of the first aspect, the material of the third channel is the same as that of the first channel and the same as that of the second channel; the thickness of the third channel is greater than the thickness of the second channel and less than the thickness of the first channel along the arrangement direction of the insulating layer and the gate; the width of the third channel is greater than or equal to the width of the first channel and less than or equal to the width of the second channel along a first direction; the first direction is perpendicular to the arrangement direction of the source and drain and perpendicular to the arrangement direction of the gate and the insulating layer.

[0034] In this way, the subthreshold slope of the third channel can be between the subthreshold slope of the first channel and the subthreshold slope of the second channel, and the threshold voltage of the third channel can be between the threshold voltage of the first channel and the threshold voltage of the second channel, so that the gate voltage of the transistor can transition from the subthreshold voltage to the threshold voltage.

[0035] In one possible implementation of the first aspect, the thickness of the channel along the alignment direction of the insulating layer and the gate is greater than or equal to 5 nm and less than or equal to 500 nm.

[0036] Setting the channel thickness within the range of 5 nm or greater and 500 nm or less ensures the mobility of charge carriers within the channel, thereby guaranteeing its conductivity. It also ensures channel uniformity, guaranteeing the stability of current transport between the source and drain, and improving transistor reliability.

[0037] In one possible implementation of the first aspect, the width of the channel along the first direction is greater than or equal to 0.1 μm and less than or equal to 200 μm; the first direction is perpendicular to the arrangement direction of the source and drain, and perpendicular to the arrangement direction of the gate and the insulating layer.

[0038] The channel width is set within the range of greater than or equal to 0.1 μm and less than or equal to 200 μm, which can ensure normal conduction of the source and drain, and ensure the stability of current transmission between the source and drain, thereby improving the reliability of the transistor.

[0039] In one possible implementation of the first aspect, the transistor further includes a substrate connected to the side of the gate opposite to the insulating layer; or, the substrate is connected to the side of the insulating layer opposite to the gate.

[0040] In one possible implementation of the first aspect, at least a portion of the source is connected to the side of the plurality of channels opposite to the gate, and at least a portion of the drain is connected to the side of the plurality of channels opposite to the gate; or, at least a portion of the source is connected between the plurality of channels and the insulating layer, and at least a portion of the drain is connected between the plurality of channels and the insulating layer.

[0041] Secondly, this application provides a drive backplane, which includes a circuit board and the aforementioned transistors, with the transistors connected to the circuit board.

[0042] Since the driving backplane provided in this application embodiment includes the transistors described above, both can solve the same problem and achieve the same effect.

[0043] Thirdly, this application provides a display screen, which includes the aforementioned driving backplane and light-emitting diodes, wherein the transistors of the driving backplane are electrically connected to the light-emitting diodes.

[0044] Since the display screen provided in this application embodiment includes the driving backplane as described above, both can solve the same problem and achieve the same effect.

[0045] Fourthly, this application provides an electronic device including a housing and the aforementioned display screen, the display screen being connected to the housing.

[0046] Since the electronic device provided in this application includes the display screen described above, both can solve the same problem and achieve the same effect. Attached Figure Description

[0047] Figure 1 shows the curves of the drain and source currents of transistors with different subthreshold slopes as a function of gate voltage.

[0048] Figure 2 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0049] Figure 3 is a schematic diagram of the structure of the display screen of the electronic device provided in the embodiment of this application;

[0050] Figure 4 is a schematic diagram of the basic structure of a transistor provided in an embodiment of this application;

[0051] Figure 5 is a schematic diagram of the grayscale change when the transistor corresponding to curve M1 in Figure 1 is applied to the display screen.

[0052] Figure 6 is a schematic diagram of the grayscale changes when the transistor corresponding to curve M2 in Figure 1 is applied to a display screen.

[0053] Figure 7 is a top view of another transistor structure provided in an embodiment of this application;

[0054] Figure 8 is a schematic diagram of the cross-sectional structure along A1-A1 in Figure 7;

[0055] Figure 9 is a simulation curve of the change of current between the source and drain in transistors with different channel thicknesses in the embodiments of this application as a function of gate voltage;

[0056] Figure 10 is a simulation curve of the change of current between the source and drain in transistors with different channel widths in the embodiments of this application as a function of gate voltage;

[0057] Figure 11 is a schematic diagram of the cross-sectional structure along A2-A2 in Figure 7;

[0058] Figure 12 is a simulation curve of the change of the current in the first channel, the current in the second channel, and the total current of the transistor as a function of the gate voltage when the thickness of the first channel in the transistor shown in Figure 11 is greater than the thickness of the second channel and the width of the first channel is less than the width of the second channel.

[0059] Figure 13 is a schematic diagram of another structure of the transistor provided in an embodiment of this application;

[0060] Figure 14 is a schematic diagram of the cross-sectional structure along B1-B1 in Figure 13;

[0061] Figure 15 is a schematic diagram of the cross-sectional structure along B2-B2 in Figure 13;

[0062] Figure 16 is a schematic diagram of another structure of the transistor provided in an embodiment of this application;

[0063] Figure 17 is a schematic diagram of the cross-sectional structure along C1-C1 in Figure 16;

[0064] Figure 18 is a schematic diagram of the cross-sectional structure along C2-C2 in Figure 16;

[0065] Figure 19 is another schematic diagram of the C1-C1 cross-sectional structure in Figure 16;

[0066] Figure 20 is another schematic diagram of the C2-C2 cross-sectional structure in Figure 16;

[0067] Figure 21 is a schematic diagram of the structure of a transistor including a third channel according to an embodiment of this application;

[0068] Figure 22 is a schematic diagram of the DD cross-sectional structure in Figure 21;

[0069] Figure 23 is a top view of the transistor provided in the embodiment of this application when multiple channels are arranged along the second direction;

[0070] Figure 24 is a schematic diagram of the EE cross-sectional structure in Figure 23.

[0071] Reference numerals: 1000, Electronic device; 100, Display screen; 10, Driver backplane; 20, Display panel; 30, Light-emitting diode; 200, Housing; 1, Transistor; 1A, Sub-cell; 1B, First sub-cell; 1C, Second sub-cell; 11, Gate; 111, Sub-gate; 112, Gate voltage control terminal; 12, Insulating layer; 121, First receiving groove; 122, Second receiving groove; 123, Sub-insulating layer; 13, Channel; 131, First channel; 132, Second channel; 133, Third channel; 14, Source; 141, Sub-source; 142, Source voltage control terminal; 15, Drain; 151, Sub-drain; 152, Drain voltage control terminal; 16, Substrate; 17, Insulating medium; 2, Circuit board. Detailed Implementation

[0072] In the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0073] In the embodiments of this application, it should be understood that the directional terms mentioned, such as "up", "down", "left", "right", "inner", "outer", etc., are only for reference to the direction of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0074] In the embodiments of this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," "third," and "fourth" may explicitly or implicitly include one or more of that feature.

[0075] In embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0076] In the embodiments of this application, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0077] In the embodiments of this application, it should be noted that the descriptions of "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range. This error range can be a range with a deviation angle of less than or equal to 5°, 8° or 10° relative to absolute verticality and absolute parallelism, respectively, and is not specifically limited here.

[0078] Before introducing the embodiments involved in this application, some technical terms related to the embodiments of this application will be introduced as follows:

[0079] The threshold voltage of a transistor is the critical voltage value required for the transistor to transition from the off state to the on state. For example, for a thin-film transistor (TFT), the threshold voltage is the voltage at which, under standard conditions, the drain current of the TFT begins to increase significantly when the voltage between the control gate and the source reaches a certain value. This is because at this voltage, the electric field strength formed on the control gate is sufficient to completely attract or flatten the underlying thin-film channel region, forming a conduction channel.

[0080] For example, in a metal-oxide-semiconductor field-effect transistor (MOSFET), the threshold voltage is the voltage required for the charge generated in the channel to just offset the electric field applied to the gate when the gate voltage is zero. When the gate voltage reaches or exceeds the threshold voltage, the number of charge carriers in the channel will increase significantly, causing the transistor to enter the conduction state.

[0081] The subthreshold voltage of a transistor refers to the operating state in which the transistor is not fully turned on when the voltage between its top electrodes is lower than its threshold voltage. In this state, the transistor's leakage current is small, and its power consumption is also low. Although the subthreshold current is small, it is well controlled by the gate voltage, making it very advantageous in low-voltage, low-power applications, especially in large-scale integrated circuit applications such as logic switches and memories.

[0082] The subthreshold slope of a transistor refers to the gate voltage required to increase by an order of magnitude in the drain current during the subthreshold region, reflecting the steepness of the current transition from the off-state to the on-state. A larger subthreshold slope indicates a gentler transition from the off-state to the on-state.

[0083] Specifically, please refer to Figure 1, which shows the on-state current of the drain and source transistors with different subthreshold slopes as a function of the gate voltage. The horizontal axis in Figure 1 represents the gate voltage (i.e., Log ID in Figure 1), in volts (V), and the vertical axis represents the current between the source and drain (i.e., VG in Figure 1), in amperes (A).

[0084] In Figure 1, curve M1 is the curve of the on-current of the drain and source of the first transistor changing with the gate voltage, and curve M2 is the curve of the on-current of the drain and source of the second transistor changing with the gate voltage.

[0085] Taking curve M1 as an example, segment L1 of curve M1 shows the change of drain and source currents with gate voltage when the gate voltage of the first transistor is at the subthreshold voltage. Segment L2 of curve M1 shows the change of drain and source currents with gate voltage when the gate voltage of the first transistor is greater than the threshold voltage. The voltage corresponding to the junction of segments L1 and L2 is the threshold voltage of the first transistor.

[0086] The steepness of segment L1 in curve M1 reflects the magnitude of the subthreshold slope of the first transistor. A comparison of curves M1 and M2 in Figure 1 shows that the subthreshold slope of curve M1 is greater than that of curve M2.

[0087] On-state current: The on-state current of a transistor refers to the current between the drain and source when the transistor is in the on state (i.e., the gate voltage is greater than or equal to the threshold voltage), and is usually called drain current.

[0088] Channel defect density refers to the number of defect points per unit area within the channel. These defect points are typically charge traps whose energy levels differ from the bottom energy level of the channel, and they can significantly affect transistor performance parameters such as leakage current and subthreshold slope.

[0089] The solutions involved in the embodiments of this application will be described below with reference to the accompanying drawings.

[0090] Please refer to Figure 2, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. This application provides an electronic device 1000. The electronic device 1000 includes mobile phones, tablets, personal digital assistants (PDAs), televisions, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, and vehicle-mounted equipment, etc. This application does not limit the specific form of the electronic device 1000. The electronic device 1000 shown in Figure 2 is a mobile phone.

[0091] In some embodiments, the electronic device 1000 includes a display screen 100 and a housing 200. The display screen 100 is connected to the housing 200. The housing 200 supports the display screen 100. The display screen 100 displays images and screens to facilitate user operation and use of the electronic device 1000.

[0092] Please refer to Figure 3, which is a schematic diagram of the structure of the display screen 100 of the electronic device 1000 provided in this application embodiment. The display screen 100 includes a driving backplate 10, a display panel 20, and light-emitting diodes 30. The light-emitting diodes 30 are disposed on the display panel 20, and the driving backplate 10 is electrically connected to the light-emitting diodes 30.

[0093] The drive backplate 10 is used to control the light emission of the LED 30 and the brightness of the LED 30, so that the LED 30 displays images and pictures on the display panel 20.

[0094] In some embodiments, there are multiple light-emitting diodes 30, which are arranged in an array on the display panel 20. The multiple light-emitting diodes 30 emit light of different colors and brightness, thereby forming images and screens of various colors on the display panel 20.

[0095] In some other embodiments, the display screen 100 may also include only the light-emitting diodes 30 and the driving backplane 10.

[0096] In some examples, the light-emitting diode 30 can be an organic light-emitting diode (OLED) or an inorganic light-emitting diode (LED), etc.

[0097] In some embodiments, referring to FIG3, the driving backplane 10 includes a transistor 1 and a circuit board 2. The transistor 1 is connected to the circuit board 2. Specifically, a driving circuit is provided on the circuit board 2, and the transistor 1 is connected to the driving circuit and to the anode of the light-emitting diode 30.

[0098] Transistor 1 has switching characteristics, which can be used to control the switching of LED 30 and adjust its brightness. By energizing the driving circuit, a voltage can be input to transistor 1. When the voltage of transistor 1 reaches the subthreshold voltage, transistor 1 will conduct, thereby energizing LED 30 and causing it to emit light. The brightness of LED 30 can be adjusted by controlling the voltage of transistor 1.

[0099] In some embodiments, please refer to FIG4, which is a schematic diagram of the basic structure of a transistor 1 provided in this application embodiment. The transistor 1 includes a gate 11, an insulating layer 12, a channel 13, a source 14, and a drain 15. The insulating layer 12 is connected between the gate 11 and the channel 13, the source 14 and the drain 15 are spaced apart, and the channel 13 is connected between the source 14 and the drain 15.

[0100] Gate 11 is connected to the driving circuit. Source 14 is connected to the driving circuit, drain 15 is connected to the anode of LED 30, and cathode of LED 30 is connected to the driving circuit. A voltage is input to gate 11 through the driving circuit. When the gate voltage reaches the subthreshold voltage, carriers flow in channel 13, generating current. This causes source 14 and drain 15 to conduct, thus energizing LED 30 and causing it to emit light.

[0101] At this point, the gate voltage has not yet reached the threshold voltage, and the source 14 and drain 15 are not fully turned on. With a low gate voltage, the current between the source 14 and drain 15 is small. Therefore, by controlling the magnitude of the gate voltage, the brightness of the light-emitting diode 30 can be controlled, i.e., low-current control of transistor 1.

[0102] When the gate voltage reaches or exceeds the threshold voltage, the source 14 and drain 15 are fully turned on. A higher gate voltage results in a larger current (i.e., the on-state current) between the source 14 and drain 15. Therefore, by controlling the gate voltage, the brightness of the LED 30 can also be controlled.

[0103] In some embodiments, transistor 1 may be a thin-film transistor, a metal-oxide-semiconductor field-effect transistor, etc.

[0104] The transistor 1 used to drive the backplane 10 is typically a thin-film transistor (TFT), while the thin-film transistor used to control the brightness of the light-emitting diode 30 is a driving thin-film transistor (Drive TFT). One driving TFT can control the brightness of one light-emitting diode 30.

[0105] Traditional driving thin-film transistors (Drive TFTs) use low-temperature polysilicon thin-film transistors (LTPS TFTs) as the channel material. The subthreshold slope of LTPS TFTs is typically greater than 0.3V / dec, meaning they have a high subthreshold slope, which allows for better control of the low-brightness, low-grayscale display characteristics of the display screen 100.

[0106] However, as the requirements for display effect and power consumption of display screen 100 continue to increase, oxide thin-film transistors (Oxide TFTs), which use oxide as the channel material, are gradually being used to drive the backplane 10 to control the brightness of the light-emitting diode 30. However, due to the characteristics of its material, oxide thin-film transistors (Oxide TFTs) have a very small subthreshold slope, typically around 0.1V / dec.

[0107] Therefore, a small subthreshold slope in the oxide thin-film transistor (OTFT) results in a small adjustment window for the gate voltage. When using the OTFT for low-current control, precise control of the gate voltage is necessary; otherwise, the display 100 may exhibit abrupt brightness variations and uneven brightness at low grayscale and low brightness levels.

[0108] In other words, when transistor 1 is used to control the brightness of the light-emitting diode 30, its subthreshold slope cannot be too small; otherwise, it may easily cause the display screen 100 to exhibit brightness jumps and uneven brightness at low grayscale and low brightness levels. Specifically, please refer to Figure 1, and in conjunction with Figures 5 and 6. Figure 5 is a schematic diagram of the grayscale changes when transistor 1 (the first transistor) corresponding to curve M1 in Figure 1 is applied to the display screen 100. Figure 6 is a schematic diagram of the grayscale changes when transistor 1 (the second transistor) corresponding to curve M2 in Figure 1 is applied to the display screen 100.

[0109] As can be seen from Figures 1, 5, and 6, the subthreshold slope of the first transistor is greater than that of the second transistor. Therefore, the display screen 100 corresponding to the first transistor exhibits a clearer grayscale gradient at low grayscale and low brightness, meaning the brightness of the display screen 100 is relatively uniform. Conversely, the display screen 100 corresponding to the second transistor shows a more blurred grayscale gradient at low grayscale and low brightness (as shown in the dashed box in Figure 6), indicating that the brightness of the display screen 100 exhibits abrupt changes.

[0110] However, if the subthreshold slope of transistor 1 is simply increased in order to ensure the uniformity of display at low grayscale and low brightness and to avoid the phenomenon of brightness jumps, it is easy to cause the on-state current of transistor 1 to decrease, thereby affecting the stability of the circuit.

[0111] Based on this, please refer to Figures 7 and 8. Figure 7 is a top view of another transistor 1 provided in this embodiment, and Figure 8 is a cross-sectional view along line A1-A1 in Figure 7. The transistor 1 includes a gate 11, an insulating layer 12, a source 14, a drain 15, and multiple channels 13. The insulating layer 12 is connected to the gate 11, and the multiple channels 13 are spaced apart, with each channel 13 connected to the side of the insulating layer 12 opposite to the gate 11. The insulating layer 12 is used to isolate the channels 13 from the gate 11 to prevent the voltage applied to the gate 11 from directly acting on the channels 13.

[0112] Each channel 13 is connected to the side of the insulating layer 12 opposite to the gate 11, which can be the surface of the insulating layer 12 opposite to the gate 11.

[0113] In some examples, the material of insulating layer 12 can be silicon oxide, silicon nitride, etc.

[0114] In some examples, the material of gate 11 can be a conductive material, such as aluminum, titanium, etc.

[0115] In some examples, the material of channel 13 can be an oxide. Exemplarily, the oxide can be one of indium oxide, gallium oxide, zinc oxide, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), or indium zinc oxide (IZO). Using an oxide material for channel 13 can reduce the subthreshold slope of transistor 1, improve the display effect of display 100, and reduce the power consumption of display 100.

[0116] In other examples, the material of the channel 13 can also be low-temperature polycrystalline silicon, germanium, etc.

[0117] This application is illustrated by way of example using an oxide as the material of the channel 13.

[0118] The source 14 and drain 15 are spaced apart. That is to say, the source 14 and drain 15 cannot touch or connect to each other, so as to avoid direct conduction between the source 14 and drain 15.

[0119] In some examples, both source 14 and drain 15 are located on the side of insulating layer 12 opposite to gate 11. Insulating layer 12 is used to isolate gate 11 and drain 15 to prevent direct conduction between them. Insulating layer 12 is also used to isolate gate 11 and source 14 to prevent direct conduction between them. It can be understood that source 14, drain 15, and gate 11 constitute three mutually isolated electrodes of transistor 1.

[0120] Multiple channels 13 are connected between the source 14 and the drain 15. That is, for any one of the multiple channels 13, one end is connected to the source 14 and the other end is connected to the drain 15. In other words, multiple channels 13 are connected in parallel between the source 14 and the drain 15.

[0121] Thus, after applying a voltage to the gate 11, the source 14 and drain 15 can be turned on as long as the subthreshold voltage of any channel 13 is reached.

[0122] In some examples, the source 14 can be made of conductive materials, such as gold, molybdenum, aluminum, titanium, etc.

[0123] In some examples, the drain 15 can be made of conductive materials, such as gold, molybdenum, aluminum, titanium, etc.

[0124] In some examples, source 14 and drain 15 may be in contact with or connected to insulating layer 12. Source 14 and drain 15 may also not be in contact with or connected to insulating layer 12.

[0125] The plurality of channels 13 include a first channel 131 and a second channel 132. The subthreshold slope of the first channel 131 is greater than that of the second channel 132, and the threshold voltage of the first channel 131 is less than that of the second channel 132.

[0126] In this way, since the threshold voltage of the first channel 131 is lower than that of the second channel 132, after a voltage is applied to the gate 11, the first channel 131 will reach the subthreshold voltage before the second channel 132, thus causing the first channel 131 to generate current first. Furthermore, in the subthreshold voltage region, even if some carriers flow in the second channel 132, the number of carriers in the first channel 131 will be greater than that in the second channel 132. Therefore, in the subthreshold voltage region, the source 14 and drain 15 of transistor 1 are mainly turned on through the first channel 131.

[0127] Furthermore, since the subthreshold slope of the first channel 131 is greater than that of the second channel 132, the adjustment window of the gate voltage will be increased accordingly in the subthreshold voltage region, thereby reducing the adjustment precision of the gate voltage. This can further reduce the probability of brightness jumps and uneven brightness in the display screen 100 under low grayscale and low brightness conditions, thereby improving the display effect of the display screen 100.

[0128] After the voltage applied to the gate 11 reaches the threshold voltage, both the first channel 131 and the second channel 132 are fully turned on, and the source 14 and the drain 15 are turned on through the first channel 131 and the second channel 132. That is, the source 14 and the drain 15 of transistor 1 can be turned on through multiple channels 13. The amount of carriers in multiple channels 13 is increased compared to the amount of carriers in a single channel 13, thereby increasing the current of transistor 1 when it is fully turned on, that is, increasing the on-state current.

[0129] In summary, by ensuring that the subthreshold slope of the first channel 131 is greater than that of the second channel 132, and that the threshold voltage of the first channel 131 is less than that of the second channel 132, it is possible to ensure that the transistor 1 has a large on-state current and reduce the probability of brightness jumps and uneven brightness in the display screen 100 under low grayscale and low brightness conditions, thereby improving the display effect of the display screen 100.

[0130] In some embodiments, the subthreshold slope of the first channel 131 is greater than or equal to 0.1V / dec and less than or equal to 1V / dec. For example, the subthreshold slope of the first channel 131 can be 0.1V / dec, 0.2V / dec, 0.25V / dec, 0.3V / dec, 0.35V / dec, 0.4V / dec, 0.45V / dec, 0.5V / dec, 0.55V / dec, 0.6V / dec, 0.65V / dec, 0.7V / dec, 0.75V / dec, 0.8V / dec, 0.85V / dec, 0.9V / dec, 0.95V / dec, 1V / dec, etc.

[0131] The subthreshold slope of the first channel 131 is within the range of greater than or equal to 0.1V / dec and less than or equal to 1V / dec. This allows the gate voltage adjustment window to be within a suitable range when the transistor 1 is in the subthreshold voltage region, thereby avoiding excessively high gate voltage adjustment precision that could cause brightness jumps and uneven brightness in the display screen 100 at low grayscale and low brightness.

[0132] If the subthreshold slope of the first channel 131 is too low, for example, less than 0.1V / dec, it will result in a small adjustment window range for the gate voltage, which may easily cause the display screen 100 to exhibit brightness jumps and uneven brightness under low grayscale and low brightness conditions.

[0133] If the subthreshold slope of the first channel 131 is too high, for example, greater than 1V / dec, it will cause a large change in the leakage current of transistor 1, thereby increasing the energy consumption of sluggish transistor 1 and affecting the switching speed of transistor 1.

[0134] In some embodiments, the subthreshold slope of the second channel 132 is greater than or equal to 0.006V / dec and less than or equal to 0.3V / dec. For example, the subthreshold slope of the second channel 132 can be 0.006V / dec, 0.01V / dec, 0.02V / dec, 0.03V / dec, 0.05V / dec, 0.08V / dec, 0.1V / dec, 0.15V / dec, 0.18V / dec, 0.2V / dec, 0.25V / dec, 0.28V / dec, 0.3V / dec, etc.

[0135] The subthreshold slope of the second channel 132 is within the range of greater than or equal to 0.006V / dec and less than or equal to 0.3V / dec, which allows the second channel 132 to have good conductivity when the source 14 and drain 15 of transistor 1 are fully turned on, thereby ensuring that transistor 1 has a large on-state current and low power consumption.

[0136] If the subthreshold slope of the second channel 132 is too large, for example, greater than 0.3V / dec, it will affect the conductivity of the second channel 132, thereby affecting the magnitude of the on-state current of transistor 1, and thus affecting the performance and energy consumption of transistor 1.

[0137] If the subthreshold slope of the second channel 132 is too small, for example, less than 0.006V / dec, it will make the fabrication of the second channel 132 more difficult, which is not conducive to the fabrication of the second channel 132, and thus not conducive to the fabrication of transistor 1.

[0138] In some embodiments, among different transistors 1 corresponding to channels 13 made of the same material, when the length and width of channel 13 are the same, the greater the thickness of channel 13, the greater the defect density of channel 13, the smaller the threshold voltage of the corresponding transistor 1, and the greater the subthreshold slope. Specifically, please refer to Figure 9, which is a simulation curve of the change of current between the source 14 and drain 15 with gate voltage in transistors 1 corresponding to channels 13 of different thicknesses in this application embodiment. The horizontal axis in Figure 9 represents the gate voltage (i.e., Log ID in Figure 9), in volts (V), and the vertical axis represents the current between the source and drain (i.e., VG in Figure 9), in amperes (A).

[0139] In Figure 9, curves M3, M4, M5, M6, and M7 correspond to the third, fourth, fifth, sixth, and seventh transistors, respectively. The thickness of the channel 13 of the third, fourth, fifth, sixth, and seventh transistors increases sequentially. Specifically, the channel 13 width of the third transistor is 20 nm, that of the fourth transistor is 35 nm, that of the fifth transistor is 50 nm, that of the sixth transistor is 70 nm, and that of the seventh transistor is 100 nm.

[0140] As can be seen from Figure 9, the subthreshold slopes of the third, fourth, fifth, sixth, and seventh transistors increase sequentially (i.e., the steepness of the subthreshold region gradually decreases), and the threshold voltage decreases sequentially.

[0141] In Figure 9, the L3 segment of curve M3 corresponds to the subthreshold voltage region of the third transistor, and the horizontal axis corresponding to the upper end of the L3 segment is the threshold voltage of the third transistor.

[0142] In curve M4, segment L4 corresponds to the subthreshold voltage region of the fourth transistor, and the horizontal axis corresponding to the upper endpoint of segment L4 is the threshold voltage of the fourth transistor.

[0143] In curve M5, segment L5 corresponds to the subthreshold voltage region of the fifth transistor, and the horizontal axis corresponding to the upper endpoint of segment L5 is the threshold voltage of the fifth transistor.

[0144] In curve M6, segment L6 corresponds to the subthreshold voltage region of the sixth transistor, and the horizontal axis corresponding to the upper endpoint of segment L6 is the threshold voltage of the sixth transistor.

[0145] In curve M7, segment L7 corresponds to the subthreshold voltage region of the seventh transistor, and the horizontal axis corresponding to the upper end of segment L7 is the threshold voltage of the seventh transistor.

[0146] Among the different transistors 1 corresponding to the channel 13 made of the same material, when the length and thickness of the channel 13 are the same, the larger the width of the channel 13, the larger the on-state current of the corresponding transistor 1, but the subthreshold slope of the corresponding transistor 1 remains basically unchanged.

[0147] Specifically, please refer to Figure 10, which is a simulation curve of the change of current between the source 14 and drain 15 in transistor 1 corresponding to different channel widths 13 in the embodiments of this application as a function of gate voltage. The horizontal axis in Figure 10 represents the gate voltage (i.e., Log ID in Figure 10), in volts (V), and the vertical axis represents the current between the source and drain (i.e., VG in Figure 10), in amperes (A).

[0148] In Figure 10, curves M8, M9, M10, and M11 correspond to the eighth, ninth, tenth, and eleventh transistors, respectively. The widths of the eighth, ninth, tenth, and eleventh transistors increase sequentially. Specifically, the width of the eighth transistor is 20 μm, the ninth transistor is 40 μm, the tenth transistor is 80 μm, and the eleventh transistor is 160 μm.

[0149] As can be seen from Figure 10, the subthreshold slopes of the eighth, ninth, tenth, and eleventh transistors are basically the same, but the on-state currents of the eighth, ninth, tenth, and eleventh transistors increase sequentially.

[0150] In Figure 10, the L8 segment of curve M8 is the curve segment when the gate voltage of the eighth transistor is greater than or equal to the threshold voltage. The horizontal axis corresponding to the lower end of the L8 segment is the threshold voltage of the eighth transistor, and the vertical axis is the minimum value of the on-state current of the eighth transistor.

[0151] The L9 segment in curve M9 represents the curve segment when the gate voltage of the ninth transistor is greater than or equal to the threshold voltage. The horizontal axis corresponding to the lower endpoint of the L9 segment is the threshold voltage of the ninth transistor, and the vertical axis is the minimum value of the on-state current of the ninth transistor.

[0152] The L10 segment in curve M10 is the curve segment when the gate voltage of the tenth transistor is greater than or equal to the threshold voltage. The horizontal axis corresponding to the lower end of the L10 segment is the threshold voltage of the tenth transistor, and the vertical axis is the minimum value of the on-state current of the tenth transistor.

[0153] The L11 segment in curve M11 is the curve segment when the gate voltage of the eleventh transistor is greater than or equal to the threshold voltage. The horizontal axis corresponding to the lower end of the L11 segment is the threshold voltage of the eleventh transistor, and the vertical axis is the minimum value of the on-state current of the eleventh transistor.

[0154] Based on this, when the materials of the first channel 131 and the second channel 132 of the transistor 1 shown in Figure 7 are the same, the subthreshold slope of the first channel 131 and the second channel 132 can be adjusted by adjusting the thickness and width of the first channel 131 and the second channel 132, and the on-state current of the transistor 1 can also be adjusted.

[0155] In some embodiments, please continue to refer to Figures 7 and 8, and in conjunction with Figure 11, which is a schematic cross-sectional view along line A2-A2 in Figure 7. The material of the first channel 131 is the same as that of the second channel 132. Along the arrangement direction of the insulating layer 12 and the gate 11, the thickness of the first channel 131 (thickness H1 shown in Figure 11) is greater than the thickness of the second channel 132 (thickness H2 shown in Figure 11), and along the first direction (direction X shown in Figure 11), the width of the first channel 131 (width W1 shown in Figure 11) is less than or equal to the width of the second channel 132 (width W2 shown in Figure 11).

[0156] The first direction is perpendicular to the arrangement direction of the source 14 and drain 15, and perpendicular to the arrangement direction of the gate 11 and insulating layer 12. In some examples, the arrangement direction of the source 14 and drain 15 is perpendicular to the arrangement direction of the gate 11 and insulating layer 12, or the arrangement direction of the source 14 and drain 15 forms an acute angle with the arrangement direction of the gate 11 and insulating layer 12.

[0157] In this way, since the first channel 131 and the second channel 132 are made of the same material, when the thickness of the first channel 131 is greater than the thickness of the second channel 132, the defect density of the first channel 131 will be greater than the defect density of the second channel 132. Therefore, the first channel 131 is easier to conduct than the second channel 132, meaning the threshold voltage of the first channel 131 will be lower than the threshold voltage of the second channel 132. Furthermore, the first channel 131 and the second channel 132 can be manufactured using the same process, allowing them to be fabricated in the same step, which simplifies the manufacturing process of transistor 1 and reduces costs.

[0158] After a voltage is applied to the gate 11 of transistor 1, as the gate voltage increases, carriers will flow first in the first channel 131, while there will be no carrier flow or very little carrier flow in the second channel 132. That is, the source 14 and drain 15 are turned on first through the first channel 131. In the subthreshold voltage region of transistor 1, the amount of carriers in the first channel 131 is greater than that in the second channel 132.

[0159] In other words, in the subthreshold voltage region, the current of transistor 1 is dominated by the first channel 131. Furthermore, since the thickness of the first channel 131 is greater than the thickness of the second channel 132, the subthreshold slope of the first channel 131 is greater than that of the second channel 132. The gate voltage adjustment window in the subthreshold voltage region of transistor 1 is correspondingly increased, thereby reducing the gate voltage adjustment precision. This, in turn, reduces the probability of brightness jumps and uneven brightness in the display screen 100 at low grayscale and low brightness levels, thus improving the display effect of the display screen 100.

[0160] When the gate voltage reaches the threshold voltage, both the first channel 131 and the second channel 132 are fully turned on, and the source 14 and the drain 15 are turned on through the first channel 131 and the second channel 132. At this time, if the widths of the first channel 131 and the second channel 132 are equal, the number of channels 13 used by transistor 1 to turn on the source 14 and the drain 15 increases, which can increase the current of transistor 1 when it is fully turned on, that is, increase the on-state current.

[0161] If the width of the first channel 131 is smaller than the width of the second channel 132, since reducing the width of the channel 13 of transistor 1 can increase the on-state current of transistor 1, the on-state current of transistor 1 can also be improved, thereby improving the performance of transistor 1.

[0162] Furthermore, when the width of the first channel 131 is smaller than the width of the second channel 132, when the gate voltage reaches the threshold voltage, a large number of charge carriers will flow instantaneously in the second channel 132. The conductivity of the second channel 132 will be better than that of the first channel 131. Therefore, the number of charge carriers in the second channel 132 will be greater than that in the first channel 131. At this time, the current of transistor 1 (i.e., the on-state current) is dominated by the second channel 132.

[0163] Since the thickness of the second channel 132 is less than the thickness of the first channel 131, the defect density of the second channel 132 is less than that of the first channel 131. In this case, the on-state current of transistor 1 is dominated by the second channel 132, which can reduce the leakage current and power consumption of transistor 1, thereby improving the performance of transistor 1.

[0164] It should be noted that when multiple channels 13 are made of the same material, they are usually manufactured using the same process. For example, multiple channels 13 may be manufactured using a deposition process.

[0165] In some embodiments, the width of the first channel 131 is smaller than the width of the second channel 132.

[0166] Please refer to Figure 12. Figure 12 is a simulation curve of the current in the first channel 131, the current in the second channel 132, and the total current of transistor 1 as a function of the gate voltage when the thickness of the first channel 131 in transistor 1 shown in Figure 11 is greater than the thickness of the second channel 132, and the width of the first channel 131 is less than the width of the second channel 132. In Figure 12, the horizontal axis represents the gate voltage (i.e., Log ID in Figure 12), in volts (V), and the vertical axis represents the current between the source and drain (i.e., VG in Figure 12), in amperes (A).

[0167] In Figure 12, curve M12 is a simulated curve of the current of the first channel 131 changing with the gate voltage. The L12 segment in curve M12 is the subthreshold voltage region of the first channel 131, and the horizontal axis corresponding to the upper end of the L12 segment is the threshold voltage of the first channel 131.

[0168] Curve M13 is a simulation curve showing the change of current in the second channel 132 with the gate voltage. Segment L13 in curve M13 represents the subthreshold voltage region of the second channel 132, and the x-axis corresponding to the upper endpoint of segment L13 is the threshold voltage of the second channel 132.

[0169] Curve M14 is a simulation curve showing the total current of transistor 1 as a function of the gate voltage. Segment L14 in curve M14 represents the subthreshold voltage region of transistor 1, and the horizontal axis corresponding to the upper endpoint of segment L14 represents the overall threshold voltage of transistor 1.

[0170] As shown in Figure 12, in the subthreshold voltage region, the total current curve of transistor 1 is close to the current curve of the first channel 131. That is, in the subthreshold region, the current of transistor 1 is dominated by the first channel 131. After the gate voltage exceeds the threshold voltage, the total current curve of transistor 1 is close to the current curve of the second channel 132. That is, after exceeding the threshold voltage, the current of transistor 1 is dominated by the second channel 132.

[0171] It can be seen that the thickness of the first channel 131 is greater than the thickness of the second channel 132, and the width of the first channel 131 is less than the thickness of the second channel 132. This can reduce the adjustment precision of the gate voltage, thereby reducing the probability of brightness jumps and uneven brightness in the display screen 100 under low grayscale and low brightness, so as to improve the display effect of the display screen 100 and increase the on-state current of the transistor 1.

[0172] In some other embodiments, the subthreshold slope of the first channel 131 can be made greater than that of the second channel 132, and the threshold voltage of the first channel 131 can be less than that of the second channel 132, by making the materials of the first channel 131 and the second channel 132 different.

[0173] In some embodiments, the ratio of the thickness of the first channel 131 to the thickness of the second channel 132 is greater than or equal to 2 and less than or equal to 20. For example, the ratio of the thickness of the first channel 131 to the thickness of the second channel 132 can be 2, 5, 8, 10, 12, 15, 18, 20, etc.

[0174] By setting the ratio of the thickness of the first channel 131 to the thickness of the second channel 132 within the range of greater than or equal to 2 and less than or equal to 20, the thickness of the first channel 131 and the thickness of the second channel 132 can have a suitable difference, so as to ensure that the current of the transistor 1 in the subthreshold voltage region is dominated by the first channel 131 and the second channel 132 has a small influence on the first channel 131, thereby ensuring the performance of the transistor 1.

[0175] If the ratio of the thickness of the first channel 131 to the thickness of the second channel 132 is too small, for example less than 2, it will result in a small difference between the thickness of the first channel 131 and the thickness of the second channel 132, thereby affecting the performance of transistor 1 in the subthreshold voltage region.

[0176] Due to space and process requirements of transistor 1, the thickness of channel 13 needs to meet certain ranges. If the ratio of the thickness of the first channel 131 to the thickness of the second channel 132 is too small, for example, greater than 20, it may lead to the second channel 132 being too thin, resulting in increased processing difficulty, or the first channel 131 being too thick, resulting in an excessively high defect density in the first channel 131, affecting the performance of transistor 1 in the subthreshold voltage region.

[0177] In some embodiments, the ratio of the width of the second channel 132 to the width of the first channel 131 is greater than or equal to 5 and less than or equal to 50. For example, the ratio of the width of the second channel 132 to the width of the first channel 131 can be 5, 8, 10, 15, 20, 25, 30, 35, 40, 45, 50, etc.

[0178] By setting the ratio of the width of the second channel 132 to the width of the first channel 131 to a range greater than or equal to 5 and less than or equal to 50, the widths of the second channel 132 and the first channel 131 can have a suitable difference, so as to ensure that after the gate voltage reaches the threshold voltage, the current of the transistor 1 is dominated by the second channel 132, and the first channel 131 has a small influence on the second channel 132, thereby ensuring the performance of the transistor 1.

[0179] If the ratio of the width of the second channel 132 to the width of the first channel 131 is too small, for example less than 5, it will result in a small difference between the width of the second channel 132 and the width of the first channel 131, thereby affecting the performance of transistor 1 after the gate voltage reaches the threshold voltage.

[0180] Due to space and process requirements of transistor 1, the width of channel 13 needs to meet certain ranges. If the ratio of the width of the second channel 132 to the width of the first channel 131 is too large, for example, greater than 50, it may cause the width of the second channel 132 to be too large, resulting in increased resistance and power consumption, and may cause the width of the first channel 131 to be too small, resulting in increased processing difficulty.

[0181] In some embodiments, along the arrangement direction of the insulating layer 12 and the gate 11, the thickness of the channel 13 is greater than or equal to 5 nm and less than or equal to 500 nm. For example, the thickness of the channel 13 can be 5 nm, 10 nm, 20 nm, 30 nm, 50 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 280 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, etc.

[0182] The thickness of channel 13 is set within the range of greater than or equal to 5 nm and less than or equal to 500 nm. This ensures the carrier mobility (i.e., the carrier movement speed) within channel 13, thereby guaranteeing the conductivity of channel 13. Furthermore, it ensures the uniformity of channel 13, guaranteeing the stability of current transmission between source 14 and drain 15, and improving the reliability of transistor 1.

[0183] If the thickness of channel 13 is too small, for example, less than 5 nm, it will result in low mobility and poor uniformity of channel 13, thereby affecting the conductivity and stability of the transmission current of channel 13.

[0184] If the thickness of channel 13 is too large, for example, greater than 500nm, it will cause the threshold voltage of transistor 1 to drift negatively (i.e., the threshold voltage is less than the design value), which will lead to an increase in leakage current and power consumption of transistor 1, and will also increase the fabrication time of channel 13, affecting the processing efficiency.

[0185] In some embodiments, the width of the channel 13 along a first direction is greater than or equal to 0.1 μm and less than or equal to 200 μm. The first direction is perpendicular to the arrangement direction of the source 14 and drain 15, and perpendicular to the arrangement direction of the gate 11 and insulating layer 12. Exemplarily, the width of the channel 13 can be 0.1 μm, 0.5 μm, 1 μm, 5 μm, 8 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, etc.

[0186] The width of the channel 13 is set within the range of greater than or equal to 0.1 μm and less than or equal to 200 μm, which can ensure the normal conduction of the source 14 and the drain 15, and ensure the stability of current transmission between the source 14 and the drain 15, thereby improving the reliability of transistor 1.

[0187] If the width of channel 13 is too small, for example, less than 0.1 μm, it will be difficult to achieve the desired process, increasing the fabrication difficulty of channel 13. If the width of channel 13 is too large, for example, greater than 200 μm, it will lead to a decrease in the uniformity of channel 13, affecting the stability of current transmission between source 14 and drain 15, and may also increase the resistance of channel 13, affecting the conductivity of channel 13.

[0188] In some embodiments, along the arrangement direction of the source 14 and the drain 15, the length of the channel 13 is greater than or equal to 0.1 μm and less than or equal to 200 μm. For example, the length of the channel 13 can be 0.1 μm, 0.5 μm, 1 μm, 5 μm, 8 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, etc.

[0189] The length of the channel 13 is set within the range of greater than or equal to 0.1 μm and less than or equal to 200 μm, which can ensure the normal conduction of the source 14 and the drain 15, and ensure the stability of current transmission between the source 14 and the drain 15, thereby improving the reliability of transistor 1.

[0190] If the length of channel 13 is too small, for example, less than 0.1 μm, a short-channel effect may occur due to the close proximity of the source 14 and drain 15, thus affecting the switching performance of transistor 1. If the length of channel 13 is too large, for example, greater than 200 μm, the uniformity of channel 13 will deteriorate, affecting the stability of current transmission between the source 14 and drain 15, and may also increase the resistance of channel 13, affecting the conductivity of channel 13.

[0191] In some embodiments, please continue to refer to FIG11, a plurality of channels 13 are arranged along a first direction, which is perpendicular to the arrangement direction of the source 14 and the drain 15, and perpendicular to the arrangement direction of the gate 11 and the insulating layer 12.

[0192] In this way, multiple channels 13 can be arranged at intervals on the insulating layer 12, thereby facilitating the setting of multiple channels 13 and the connection between multiple channels 13 and the insulating layer 12.

[0193] Multiple channels 13 are connected to the gate 11 through an insulating layer 12. That is, multiple channels 13 share the gate 11.

[0194] In some embodiments, referring further to Figures 8 and 11, transistor 1 also includes a substrate 16. The substrate 16 is connected to the side of the gate 11 opposite to the insulating layer 12. The substrate 16 serves to support the gate 11. Exemplarily, the substrate 16 can be a glass plate, a plastic plate, etc.

[0195] In some examples, at least a portion of the source 14 is connected to the side of the plurality of channels 13 opposite to the gate 11. That is, at least a portion of the source 14 covers the side of the plurality of channels 13 opposite to the gate 11. In this way, the connection between the source 14 and the plurality of channels 13 can be made more stable, thereby making the current transfer between the source 14 and the channels 13 more stable.

[0196] At least a portion of the drain 15 is connected to the side of the plurality of channels 13 opposite to the gate 11. That is, at least a portion of the drain 15 covers the side of the plurality of channels 13 opposite to the gate 11. In this way, the connection between the drain 15 and the plurality of channels 13 can be made more stable, thereby making the current transmission between the drain 15 and the channels 13 more stable.

[0197] The source 14 and drain 15 are located on the side of the insulating layer 12 opposite to the gate 11. The source 14 and drain 15 may or may not be in contact with the insulating layer 12.

[0198] In some embodiments, the first channel 131 and the second channel 132 are both made of the same oxide material and are both fabricated using a deposition process. For example, the gate 11 is first deposited on the substrate 16, then an insulating layer 12 is deposited on the gate 11, then a plurality of channels 13 are deposited on the insulating layer 12, and finally the source 14 and drain 15 are deposited on the plurality of channels 13.

[0199] In some embodiments, referring to FIG11, an insulating medium 17 is filled between any two adjacent channels 13. For example, the insulating medium 17 may be silicon oxide, silicon nitride, etc.

[0200] By filling the space between any two adjacent channels 13 with an insulating medium 17, multiple channels 13 can be isolated by the insulating medium 17 to prevent conduction between channels 13 from affecting the performance of transistor 1 in the subthreshold pressure region and above the threshold voltage.

[0201] In some other embodiments, please refer to Figures 13, 14 and 15. Figure 13 is another structural schematic diagram of transistor 1 provided in the embodiment of this application. Figure 14 is a cross-sectional view of B1-B1 in Figure 13. Figure 15 is a cross-sectional view of B2-B2 in Figure 13.

[0202] The gate 11 of transistor 1 is disposed on substrate 16, and the insulating layer 12 is disposed on the side of gate 11 facing away from substrate 16. A plurality of channels 13 are disposed at intervals and are all connected to the side of insulating layer 12 facing away from gate 11.

[0203] Both the source 14 and the gate 11 are located on the side of the insulating layer 12 opposite to the gate 11. The source 14 is connected to one side of the plurality of channels 13, and the drain 15 is connected to the opposite side of the plurality of channels 13.

[0204] At least a portion of the source 14 is connected between the plurality of channels 13 and the insulating layer 12, and at least a portion of the drain 15 is connected between the plurality of channels 13 and the insulating layer 12.

[0205] In this way, since at least a portion of the source 14 is connected between the plurality of channels 13 and the insulating layer 12, and at least a portion of the drain 15 is connected between the plurality of channels 13 and the insulating layer 12, charge carriers can be directly injected into the first channel and the second channel from the edge of the source or the edge of the drain, thereby reducing the contact resistance between the source and the first channel and the second channel, as well as reducing the contact resistance between the drain and the first channel and the second channel, and improving the carrier injection efficiency.

[0206] In some other embodiments, please refer to Figures 16, 17 and 18. Figure 16 is a schematic diagram of another structure of transistor 1 provided in the embodiment of this application. Figure 17 is a schematic diagram of the cross-sectional structure of C1-C1 in Figure 16. Figure 18 is a schematic diagram of the cross-sectional structure of C2-C2 in Figure 16.

[0207] The insulating layer 12 of transistor 1 is connected to the substrate 16, and the gate 11 is connected to the side of the insulating layer 12 facing away from the substrate 16. A plurality of channels 13 are spaced apart and are all connected between the substrate 16 and the insulating layer 12. The source 14 and the drain 15 are spaced apart and are all connected between the plurality of channels 13 and the insulating layer 12.

[0208] The insulating layer 12 is provided with a first receiving groove 121, which is recessed from the side surface of the insulating layer 12 facing the substrate 16 in the direction opposite to the substrate 16. Multiple channels 13, source electrodes 14, and drain electrodes 15 are all disposed in the first receiving groove 121. It should be noted that the inner wall surface of the first receiving groove 121 is a part of the side surface of the insulating layer 12 opposite to the gate.

[0209] At least a portion of the source 14 is connected to the side of the plurality of channels 13 facing the gate 11. At least a portion of the drain 15 is connected to the side of the plurality of channels 13 facing the gate 11.

[0210] In this way, since at least a portion of the source 14 is connected to the side of the plurality of channels 13 facing the gate 11, and at least a portion of the drain 15 is connected to the side of the plurality of channels 13 facing the gate 11, the transistor 1 can withstand higher voltage and larger current, thereby facilitating the brightness control of the light-emitting diode.

[0211] In some other embodiments, please refer to Figures 19 and 20. Figure 19 is another schematic diagram of the cross-sectional structure along C1-C1 in Figure 16, and Figure 20 is another schematic diagram of the cross-sectional structure along C2-C2 in Figure 16.

[0212] The insulating layer 12 of transistor 1 is connected to the substrate 16, and the gate 11 is connected to the side of the insulating layer 12 facing away from the substrate 16. A plurality of channels 13 are spaced apart and are all connected between the substrate 16 and the insulating layer 12. The source 14 and the drain 15 are spaced apart and are all connected between the plurality of channels 13 and the insulating layer 12.

[0213] The insulating layer 12 is provided with a second receiving groove 122, which is recessed from the side surface of the insulating layer 12 facing the substrate 16 in the direction opposite to the substrate 16. Multiple channels 13, source electrodes 14, and drain electrodes 15 are all disposed in the second receiving groove 122. It should be noted that the inner wall surface of the second receiving groove 122 is a part of the side surface of the insulating layer 12 opposite to the gate.

[0214] At least a portion of the source electrode 14 is connected between the plurality of channels 13 and the substrate 16. At least a portion of the drain electrode 15 is connected between the plurality of channels 13 and the substrate 16.

[0215] This increases the contact area between the source and the first and second channels, as well as the contact area between the drain and the first and second channels, thereby improving the conductivity between the source and drain and enhancing the transistor's performance.

[0216] In some embodiments, please refer to FIG21, which is a schematic diagram of the structure of the transistor 1 provided in the embodiments of this application when it includes a third channel 133. In addition to including the first channel 131 and the second channel 132, the plurality of channels 13 may also include at least one third channel 133.

[0217] The subthreshold slope of the third channel 133 is greater than the subthreshold slope of the second channel 132 and less than the subthreshold slope of the first channel 131; the threshold voltage of the third channel 133 is greater than the threshold voltage of the first channel 131 and less than the threshold voltage of the second channel 132.

[0218] In this way, when transistor 1 is in the subthreshold voltage region, the current is still dominated by the first channel 131, thereby improving the uniformity of brightness variation of the display screen 100 under low grayscale and low brightness conditions, and thus improving the display effect of the display screen 100. During the process of the gate voltage of transistor 1 changing from subthreshold voltage to threshold voltage, it can be transitioned through at least one third channel 133 until the first channel 131, at least one third channel 133, and the second channel 132 are all fully turned on. This can improve the stability of the gate voltage of transistor 1 during the process of changing from subthreshold voltage to threshold voltage.

[0219] In some examples, the number of third channels 133 can be one or more.

[0220] In some examples, the number of channels 13 can be greater than or equal to 2 and less than or equal to 10. For example, the number of channels 13 can be 2, 3, 4, 5, 6, 7, 8, 9, 10, etc.

[0221] The number of third channels 133 can be greater than or equal to 0 and less than or equal to 8. For example, the number of third channels 133 can be 0, 1, 2, 3, 4, 5, 6, 7, 8, etc.

[0222] When there are multiple third channels 133, the subthreshold slopes of the multiple third channels 133 may be equal or unequal. The threshold voltages of the multiple third channels 133 may be equal or unequal.

[0223] For example, the subthreshold slopes of the plurality of third channels 133 increase sequentially, and along the increasing order of the subthreshold slopes of the plurality of third channels 133, the threshold voltages of the plurality of third channels 133 decrease sequentially. That is, if the subthreshold slope of any two third channels 133 is greater than that of the other third channel 133, then the threshold voltage of the one third channel 133 is less than that of the other third channel 133.

[0224] In some embodiments, please refer to FIG22, which is a schematic cross-sectional view of the DD structure in FIG21. The material of the third channel 133 is the same as the material of the first channel 131 and the same as the material of the second channel 132. Along the arrangement direction of the insulating layer 12 and the gate 11, the thickness of the third channel 133 (thickness H3 shown in FIG22) is greater than the thickness of the second channel 132 (thickness H2 shown in FIG22) and less than the thickness of the first channel 131 (thickness H1 shown in FIG22); along the first direction, the width of the third channel 133 (width W3 shown in FIG22) is greater than or equal to the width of the first channel 131 (width W1 shown in FIG22) and less than or equal to the width of the second channel 132 (width W2 shown in FIG22).

[0225] The first direction is perpendicular to the arrangement direction of the source 14 and the drain 15, and perpendicular to the arrangement direction of the gate 11 and the insulating layer 12.

[0226] It should be noted that the materials and manufacturing processes of the first channel 131, the second channel 132, and the third channel 133 are all the same.

[0227] In this way, the thickness of the third channel 133 is greater than the thickness of the second channel 132 and less than the thickness of the first channel 131; and the width of the third channel 133 is greater than or equal to the width of the first channel 131 and less than or equal to the width of the second channel 132. The subthreshold slope of the third channel 133 can be between the subthreshold slope of the first channel 131 and the subthreshold slope of the second channel 132, and the threshold voltage of the third channel 133 can be between the threshold voltage of the first channel 131 and the threshold voltage of the second channel 132, so that the gate voltage of transistor 1 transitions from the subthreshold voltage to the threshold voltage.

[0228] When there are multiple third channels 133, the thickness of the multiple third channels 133 may be equal or unequal. The width of the multiple third channels 133 may be equal or unequal.

[0229] For example, the thickness of the plurality of third channels 133 increases sequentially, and along the order of increasing thickness of the plurality of third channels 133, the width of the plurality of third channels 133 decreases sequentially. That is, if the thickness of one third channel 133 is greater than the thickness of the other third channel 133, then the width of one third channel 133 is less than the width of the other third channel 133.

[0230] In some other embodiments, please refer to Figures 23 and 24. Figure 23 is a top view of the transistor 1 provided in this application when the plurality of channels 13 are arranged along a second direction (direction Y shown in Figure 24). Figure 24 is a cross-sectional view of the EE structure in Figure 23.

[0231] The gate 11 includes a plurality of sub-gates 111, and the insulating layer 12 includes a plurality of sub-insulating layers 123. The plurality of sub-gates 111, the plurality of sub-insulating layers 123, and the plurality of channels 13 are arranged alternately in sequence. A sub-insulating layer 123 connects a sub-gate 111 and a channel 13. The arrangement directions of the plurality of sub-gates 111, the plurality of sub-insulating layers 123, and the plurality of channels 13 are the same.

[0232] For ease of description, the arrangement direction of the plurality of sub-gates 111, the arrangement direction of the plurality of sub-insulating layers 123, and the arrangement direction of the plurality of channels 13 are referred to as the second direction. The second direction may be consistent with the thickness direction of the substrate 16. Alternatively, the second direction may form an acute angle with the thickness direction of the substrate 16.

[0233] The arrangement direction of a sub-gate 111 and a sub-insulating layer 123 is consistent with the arrangement direction of the gate 11 and the insulating layer 12.

[0234] By arranging multiple channels 13 along the second direction, and setting the gate 11 as multiple sub-gates 111, and the insulating layer 12 as multiple sub-insulating layers 123, the multiple sub-gates 111 and the multiple sub-insulating layers 123 can make full use of the space in the second direction, thereby reducing the space occupied in the direction perpendicular to the second direction and making the transistor 1 applicable to more scenarios.

[0235] Furthermore, setting the gate 11 as multiple sub-gates 111 and the insulating layer 12 as multiple sub-insulating layers 123 facilitates the arrangement of the gate 11, the insulating layer 12 and the multiple channels 13, thereby facilitating the fabrication of the transistor 1.

[0236] In some examples, a sub-insulating layer 123 and a sub-gate 111 and a channel 13 connected thereto form a sub-cell 1A, and an insulating medium 17 is filled between any two adjacent sub-cells 1A to isolate the two adjacent sub-cells 1A through the insulating medium 17, so as to prevent the sub-gate 111 of one sub-cell 1A from contacting the channel 13 of the other sub-cell 1A.

[0237] In some examples, transistor 1 further includes a substrate 16, and a plurality of sub-units 1A including a first sub-unit 1B and at least one second sub-unit 1C. The first sub-unit 1B is connected to the substrate 16, and at least one second sub-unit 1C is sequentially disposed along a second direction on the side of the first sub-unit 1B opposite to the substrate 16. That is, the second direction is consistent with the thickness direction of the substrate 16.

[0238] In some examples, gate 11 also includes a gate voltage control terminal 112, to which multiple sub-gates 111 are connected. The gate voltage control terminal 112 is connected to a driving circuit to input voltage to the multiple sub-gates 111. That is, the multiple sub-gates 111 are connected in parallel to the gate voltage control terminal 112, thus ensuring that the voltages of the multiple sub-gates 111 are the same when voltage is input through the gate voltage control terminal 112, guaranteeing the normal operation of transistor 1.

[0239] The gate voltage control terminal 112 can be located on the side of the multiple sub-units 1A facing away from the substrate 16, or it can be located on the side of the multiple sub-units 1A facing the substrate 16. This application does not make any specific limitation on this.

[0240] In some other examples, the gate voltage control terminal 112 may not be set, and the same voltage may be directly input to multiple sub-gates 111 through the driving circuit.

[0241] In some examples, source 14 includes multiple sub-sources 141, drain 15 includes multiple sub-drains 151, and a channel 13 is connected between a sub-source 141 and a sub-drain 151.

[0242] In this way, by setting the source 14 as multiple sub-sources 141 and the drain 15 as multiple sub-drains 151, it is convenient to set up the drain 15, the source 14 and multiple channels 13, thereby facilitating the fabrication of the transistor 1.

[0243] It should be noted that each sub-source 141 needs to be isolated from each sub-gate 111. Each sub-drain 151 also needs to be isolated from each sub-gate 111. Each sub-source 141 also needs to be isolated from each sub-drain 151.

[0244] In some other examples, only one source 14 and one drain 15 can be set, with one source 14 connected to multiple channels 13 at the same time, and one drain 15 connected to multiple channels 13 at the same time.

[0245] In some examples, source 14 also includes a source voltage control terminal 142, to which multiple sub-sources 141 are connected. The source voltage control terminal 142 is used to connect to the drive circuit. By connecting multiple sub-sources 141 to the source voltage control terminal 142, it is convenient to connect multiple sub-sources 141 to the drive circuit.

[0246] The drain 15 also includes a drain voltage control terminal 152, to which multiple sub-drains 151 are connected. The drain voltage control terminal 152 is used to connect to the light-emitting diode 30. By connecting multiple sub-drains 151 to the drain voltage control terminal 152, multiple sub-drains 151 can be easily connected to the light-emitting diode 30.

[0247] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0248] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A transistor, characterized in that, include: Gate; An insulating layer, the insulating layer being connected to the gate; The source and drain are spaced apart. Multiple channels are provided, the multiple channels are spaced apart, each channel is connected to the side of the insulating layer opposite to the gate, and is connected between the source and the drain; The plurality of channels include a first channel and a second channel, wherein the subthreshold slope of the first channel is greater than the subthreshold slope of the second channel, and the threshold voltage of the first channel is less than the threshold voltage of the second channel.

2. The transistor according to claim 1, characterized in that, The subthreshold slope of the first channel is greater than or equal to 0.1V / dec and less than or equal to 1V / dec; And / or, the subthreshold slope of the second channel is greater than or equal to 0.006V / dec and less than or equal to 0.3V / dec.

3. The transistor according to claim 1 or 2, characterized in that, The material of the first channel is the same as the material of the second channel; Along the arrangement direction of the insulating layer and the gate, the thickness of the first channel is greater than the thickness of the second channel, and along the first direction, the width of the first channel is less than or equal to the width of the second channel. The first direction is perpendicular to the arrangement direction of the source and the drain, and also perpendicular to the arrangement direction of the gate and the insulating layer.

4. The transistor according to claim 3, characterized in that, The ratio of the thickness of the first channel to the thickness of the second channel is greater than or equal to 2 and less than or equal to 20.

5. The transistor according to claim 3 or 4, characterized in that, The ratio of the width of the second channel to the width of the first channel is greater than or equal to 5 and less than or equal to 50.

6. The transistor according to any one of claims 1-5, characterized in that, The plurality of channels are arranged along a first direction, which is perpendicular to the arrangement direction of the source and the drain, and also perpendicular to the arrangement direction of the gate and the insulating layer.

7. The transistor according to any one of claims 1-5, characterized in that, The gate includes a plurality of sub-gates, the insulating layer includes a plurality of sub-insulating layers, and the plurality of sub-gates, the plurality of sub-insulating layers and the plurality of channels are arranged alternately in sequence; One of the sub-insulating layers is connected between one of the sub-gates and one of the channels; the arrangement directions of the plurality of sub-gates, the arrangement directions of the plurality of sub-insulating layers, and the arrangement directions of the plurality of channels are the same.

8. The transistor according to claim 7, characterized in that, The gate also includes a gate voltage control terminal, and the plurality of sub-gates are all connected to the gate voltage control terminal.

9. The transistor according to claim 7 or 8, characterized in that, The source includes multiple sub-sources, the drain includes multiple sub-drains, and a channel is connected between a sub-source and a sub-drain.

10. The transistor according to claim 9, characterized in that, The source electrode further includes a source voltage control terminal, and all of the plurality of sub-source electrodes are connected to the source voltage control terminal; and / or The drain electrode also includes a drain voltage control terminal, and the plurality of sub-drain electrodes are all connected to the drain voltage control terminal.

11. The transistor according to any one of claims 1-10, characterized in that, An insulating medium is filled between any two adjacent channels.

12. The transistor according to any one of claims 1-11, characterized in that, The material of the channel includes oxides.

13. The transistor according to claim 12, characterized in that, The oxide is one of indium oxide, gallium oxide, zinc oxide, indium gallium zinc oxide, indium gallium oxide, and indium zinc oxide.

14. The transistor according to any one of claims 1-13, characterized in that, The plurality of channels further includes at least one third channel, wherein the subthreshold slope of the third channel is greater than the subthreshold slope of the second channel and less than the subthreshold slope of the first channel; and the threshold voltage of the third channel is greater than the threshold voltage of the first channel and less than the threshold voltage of the second channel.

15. The transistor according to claim 14, characterized in that, The material of the third channel is the same as that of the first channel and the same as that of the second channel; Along the arrangement direction of the insulating layer and the gate, the thickness of the third channel is greater than the thickness of the second channel and less than the thickness of the first channel; along the first direction, the width of the third channel is greater than or equal to the width of the first channel and less than or equal to the width of the second channel. The first direction is perpendicular to the arrangement direction of the source and the drain, and also perpendicular to the arrangement direction of the gate and the insulating layer.

16. The transistor according to any one of claims 1-15, characterized in that, Along the alignment direction of the insulating layer and the gate, the thickness of the channel is greater than or equal to 5 nm and less than or equal to 500 nm.

17. The transistor according to any one of claims 1-16, characterized in that, Along a first direction, the width of the channel is greater than or equal to 0.1 μm and less than or equal to 200 μm; the first direction is perpendicular to the arrangement direction of the source and the drain, and perpendicular to the arrangement direction of the gate and the insulating layer.

18. The transistor according to any one of claims 1-17, characterized in that, It also includes a substrate connected to the side of the gate opposite to the insulating layer; or, the substrate is connected to the side of the insulating layer opposite to the gate.

19. The transistor according to claim 18, characterized in that, At least a portion of the source is connected to the side of the plurality of channels opposite to the gate, and at least a portion of the drain is connected to the side of the plurality of channels opposite to the gate. Alternatively, at least a portion of the source electrode is connected between the plurality of channels and the insulating layer, and at least a portion of the drain electrode is connected between the plurality of channels and the insulating layer.

20. A drive backplane, characterized in that, It includes a circuit board and a transistor according to any one of claims 1-19, the transistor being connected to the circuit board.

21. A display screen, characterized in that, include: The drive backplate as described in claim 20; A light-emitting diode (LED), wherein the transistor on the driving backplane is electrically connected to the LED.

22. An electronic device, characterized in that, It includes a housing and a display screen as described in claim 21, the display screen being attached to the housing.

Images