Method and device for multilevel converters for limiting a DC voltage in the DC voltage circuit with activation of a schema of the pulse inhibitor
Patent Information
- Application Number
- PCT/EP2026/054180
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-20
- Filing Date
- 2026-02-17
- Publication Date
- 2026-08-27
Smart Images
Figure EP2026054180_27082026_PF_FP_ABST
Abstract
Description
[0001] Description
[0002] Method and device for multilevel converters for limiting a DC voltage in a DC circuit with activation of a pulse blocking mechanism
[0003] Multilevel converters are specially designed electrical converters which, starting from an electrical supply network, convert direct current from a DC circuit - also called a DC intermediate circuit - into alternating current for the operation of an electrical machine or another electrical network, at least in a supplying operating mode, whereby several voltage levels can be generated.
[0004] These converters offer advantages over traditional two-stage electrical converters, particularly in terms of harmonic reduction, higher voltage levels and higher efficiency.
[0005] To illustrate the increasing importance of multilevel converters in industrial environments, some of the features and advantages of this type of electrical converter are presented below.
[0006] Multilevel converters can provide different voltage levels by generating multiple voltage stages. This allows for fine-grained adjustment of the output voltage and results in a smoother sinusoidal output voltage compared to conventional two-stage electrical converters.
[0007] By generating a near-sinusoidal output voltage, multilevel converters reduce harmonics and improve the overall quality of the power supply. This is particularly important for sensitive electronic devices and applications with high power requirements.
[0008] Multilevel converters can generate higher output voltages, which is advantageous for high-voltage direct current (HVDC) applications and for industrial drives – especially higher power applications.
[0009] Thanks to improved voltage matching and harmonic reduction, multilevel converters operate more efficiently and with lower power loss than two-level electrical converters. Multilevel converters often consist of modular units that can be easily expanded or adapted to meet the requirements of different applications. This makes them scalable and adaptable.
[0010] There are several topologies of multilevel converters, including:
[0011] • a cascaded H-bridge converter (CHB), which consists of several H-bridge modules connected in series to generate the desired output voltage,
[0012] • a diode-clamped inverter (Neutral Point Clamped, NPC), which uses diodes to generate and stabilize the different voltage levels, and • a flying-capacitor inverter, which uses capacitors that are switched between the different voltage levels to achieve the desired output voltage.
[0013] There are various reasons for putting a multilevel converter into a safe state during operation, where no current can be supplied to a connected load or network on the output side. This can be achieved from normal operation to a process-related shutdown by means of pulse blocking at the power semiconductor switches, particularly in operational situations such as emergency stop or rapid stop. Essentially, it must be ensured that, for example, an electric machine can no longer perform any mechanical movements as quickly as possible.
[0014] During the transition of the multilevel converter from normal operation to pulse blocking, decreasing currents due to existing inductances (branch choke, load, feed-in), especially at the DC link, lead to voltage increases.
[0015] When the pulse blocking occurs, a voltage is generated on the DC link side of the multilevel converter, depending on the sign of the branch currents. This voltage is at most equal to the sum of the current capacitor voltages of all submodules of the multilevel converter in a bridge circuit of one AC phase. This high voltage ensures a rapid decay of the DC link current. Depending on the number of submodules connected in series and their current capacitor voltages, the resulting voltage level at the DC link can be more than twice the DC link voltage during normal operation.
[0016] Similarly, in a multilevel converter powered by a transformer and a diode rectifier, voltage increases can occur at the DC link during pulse blocking when a mains-side circuit breaker opens. The opening of the circuit breaker causes the magnetizing current remaining in the transformer to briefly induce a DC link current at the DC link, resulting in a voltage level that, in this case as well, is more than twice the DC link voltage during normal operation.
[0017] All electrical components installed in the multilevel converter and the associated air gaps within the converter must be dimensioned to withstand the voltages occurring during the transition to pulse blocking, particularly at the DC link. When operating the multilevel converter with a diode rectifier, this applies especially to the maximum reverse voltage of the diodes in the submodules of the multilevel converter.
[0018] The multilevel converter is designed for a DC link voltage that is more than twice the DC link voltage used for normal operation. Alternatively, a central DC link capacitor can be used, or overvoltage protection can be implemented for the rectifier diodes.
[0019] The invention is based on the objective of providing a method for pulse blocking operation and a device of a multilevel converter for carrying out the method, which improves the limitation of a DC voltage on the DC circuit compared to the prior art by inserting a pulse block on the multilevel converter.
[0020] The problem is solved by a method with the features specified in claim 1 and an apparatus for carrying out the method with the features specified in claim 4. To solve the problem, a method for limiting a DC voltage on the DC circuit of a multilevel converter is proposed, wherein a first, second, and third half-bridge of half-bridges of the multilevel converter on the DC circuit—each with an upper half-bridge branch and a lower half-bridge branch per half-bridge—generate an AC voltage for AC phases of the multilevel converter, wherein in each of the upper and lower half-bridge branches at least two series-connected submodules are configured as the first submodules of the first half-bridge.The second submodules of the second half-bridge and the third submodules of the third half-bridge are operated, and in each of the submodules two series-connected power semiconductor switches with a surge module capacitor connected in parallel to them are operated, characterized in that, upon application of a pulse blocking signal at the multilevel converter, the power semiconductor switches of the first submodules of the first half-bridge on a first phase of the AC voltage phases and the power semiconductor switches of the second submodules of the second half-bridge on a second phase of the AC voltage phases are blocked by means of a pulse blocking signal, and the power semiconductor switches of the third submodules of the third half-bridge are switched for a third phase of the AC voltage phases by means of a first switching signal and / or a second switching signal, wherein the DC voltage on the DC voltage circuit is limited.
[0021] The underlying idea is to avoid immediately applying the pulse blocking signal to all of the power semiconductor switches of the submodules of the half-bridges after the pulse block is engaged.
[0022] Generally, the upper and lower half-bridge branches are connected to the pulse blocking signal. Typically, the switching power semiconductor switches of the corresponding submodules belong to one phase of the AC voltage phases of a load / electric motor or connected electrical network connected to the multilevel converter. The submodule capacitors of the half-bridge branch submodules remain connected to the DC circuit (the DC link) and limit the maximum possible voltage rise of the DC voltage in the DC circuit.
[0023] The submodule capacitors in the switching power semiconductor switches of the corresponding submodules act like a central DC circuit capacitor, maintaining the DC voltage at an adjustable value. The switching power semiconductor switches of the corresponding submodules of the corresponding half-bridge set a voltage at the DC circuit that leads to a reduction of the intermediate circuit current at the beginning of the pulse blocking phase.
[0024] In a first advantageous embodiment of the method, the power semiconductor switches of the third submodules of the third half-bridge are switched on the DC voltage in the DC circuit by means of the first switching signal and / or second switching signal, so that a DC current in the DC circuit is reduced after the pulse block is applied.
[0025] In a further advantageous embodiment of the method, the power semiconductor switches of the third submodules of the third half-bridge are switched by means of the first switching signal in such a way that a submodule output voltage of all or at least some of the third submodules is equal to a submodule voltage at the submodule capacitor of the respective third submodule, or the power semiconductor switches of the third submodules of the third half-bridge are switched by means of the second switching signal in such a way that a submodule output voltage of all or at least some of the third submodules is zero.
[0026] In a further advantageous embodiment of the method, when the pulse block is engaged, the alternating voltage caused by a load or an electrical network induces an alternating current flow to the submodules of the multilevel converter on the first, second and third phases of the AC voltage phases, and the power semiconductor switches of the third submodules of the third half-bridge are switched by means of the first switching signal and / or second switching signal in such a way as to adjust the alternating voltage on the AC voltage phases so that the current flow of the alternating current originating from the load or the electrical network is suppressed.
[0027] In a further advantageous embodiment of the method, the first submodules of the first half-bridge and the second submodules of the second half-bridge to be blocked by the pulse blocking signal are selected such that the half-bridges with the smallest currents of branch currents flowing in the upper half-bridge branches and lower half-bridge branches are selected.
[0028] In a further advantageous embodiment of the method, the power semiconductor switches of the third submodules of the third half-bridge are supplied with an impulse blocking signal when an impermissibly high DC voltage on the DC circuit has subsided or been eliminated after the impulse block has been applied.
[0029] To solve the problem, a multilevel converter is further proposed, which is configured to perform a method for limiting a DC voltage on the DC circuit, wherein an AC voltage for AC phases of the multilevel converter can be generated on the DC circuit by means of a first, second and third half-bridge of half-bridges (3) of the multilevel converter - with one upper half-bridge branch and one lower half-bridge branch per half-bridge, wherein at least two series-connected submodules can be operated in each of the upper and lower half-bridge branches as first submodules of the first half-bridge, second submodules of the second half-bridge and third submodules of the third half-bridge, and wherein two series-connected power semiconductor switches with a sum-module capacitor connected in parallel to them can be operated in each of the submodules.characterized in that, by engaging a pulse blocking signal on the multilevel converter, the power semiconductor switches of the first submodules of the first half-bridge on a first phase of the AC voltage phases and the power semiconductor switches of the second submodules of the second half-bridge on a second phase of the AC voltage phases can be blocked by means of a pulse blocking signal, and the power semiconductor switches of the third submodules of the third half-bridge for a third phase of the AC voltage phases can be switched by means of a first switching signal and / or a second switching signal, wherein the DC voltage on the DC circuit can be limited.
[0030] The properties, features, and advantages of this invention described above, as well as the manner in which they are achieved, will become clearer and more readily understandable in connection with the following description of the exemplary embodiments, which are explained in more detail in conjunction with the figures. It shows:
[0031] FIG 1 shows a schematic circuit diagram illustrating the method according to the invention in connection with a multilevel converter with submodules in the bridge branches, which is designed to carry out the method and,
[0032] FIG 2 shows another schematic circuit diagram, which shows a submodule of the multilevel converter according to FIG 1.
[0033] FIG. 1 shows a schematic circuit diagram illustrating the inventive method V in connection with a multilevel converter 2 with submodules 6 in the bridge branches 3, which is configured to carry out the method V. The multilevel converter 2 is connected to a DC circuit 1 with a DC voltage UDC. The DC circuit 2, also called the DC intermediate circuit, is supplied with electrical energy via a diode rectifier 15, which is equipped with rectifier diodes 16, by means of a supply network 13 via an AC network 14.
[0034] The multilevel converter 2 has half-bridges 3, a first half-bridge 3a, a second half-bridge 3b and a third half-bridge 3c, wherein all half-bridges 3, 3a, 3b, 3c are formed with an upper half-bridge branch 4 and a lower half-bridge branch 5.
[0035] The half-bridges 3 also each have submodules 6 arranged in series as first submodules 6a for the first half-bridge 3a, second submodules 6b for the second half-bridge 3b and third submodules 6c for the third half-bridge 3c.
[0036] In the respective upper half-bridge branches 4 and lower half-bridge branches 5, inductors 12 are located, which schematically represent inductors 12 in the use of the multilevel converter 2, such as branch chokes, the load 9 - in particular an electric motor 11 - 11, the electrical network 10 as well as supply lines to the load 9 / the electric motor 11 / the electrical network 10 with the AC phases L, as first phase L1, second phase L2 and third phase L3, which have the AC voltage UAC, but also of the supply network 13 with its AC network 14.
[0037] The method V for limiting the DC voltage UDC on the DC circuit 1 of the multilevel converter 2 in the event of an impulse blocking signal I being applied to the multilevel converter 2 now provides not to immediately apply an impulse blocking signal (see FIG 2) to all of the submodules 6 of the half-bridges 3 with their power semiconductor switches (see FIG 2), but rather – in order to reduce or prevent an unwanted increase in the DC voltage UDC on the DC circuit 1 – to initially block only the power semiconductor switches of the first submodules 6a of the first half-bridge 3a and the power semiconductor switches of the first submodules 6a of the first half-bridge 3a accordingly.
[0038] The selection of the switches to be immediately connected to the pulse blocking signal of the corresponding power semiconductor switches depends on the smallest of the branch currents Izwi4, lzwis, lzw24, lzw25, lzw34, lzw35 in the upper half-bridge branches 4 and lower half-bridge branches 5 of the half-bridges 3. It is also considered whether the flow direction of the branch currents Izwi4, lzw5, lzw24, lzw25, lzw34, lzw35 is positive, as with the branch currents Izwi4, lzw24, lzw34 of the upper half-bridge branches 4, or negative, as with the branch currents Izwi4, lzw24, lzw34 of the lower half-bridge branches 5.
[0039] The negative flow direction is advantageous because a positive flow direction of the branch currents Izwi4,lzwi5,lzw24,lzw25,lz 34,lz 35 would cause a high back EMF when commutating its upper half-bridge branch 4 or lower half-bridge branch 5, which is set to pulse block I with the pulse blocking signal.
[0040] If an increase in the DC voltage UDC on the DC circuit 1 has subsided or it is ensured that it can no longer occur during the pulse blocking I, the power semiconductor switches the third submodules 6c of the third half-bridge 3 are also supplied with a pulse blocking signal, so that the multilevel converter 2 has entered an operating state of complete pulse blocking.
[0041] FIG 2 shows another schematic circuit diagram with a submodule 6, 6a, 6b, 6c of the multi-level converter 2 according to FIG 1.
[0042] The submodule 6, 6a, 6b, 6c is designed with two power semiconductor switches 7 connected in series, a so-called freewheeling diode 17 is arranged in parallel to each of the power semiconductor switches 7 and a submodule capacitor 8 is connected in parallel to both power semiconductor switches 7 connected in series.
[0043] The submodule 6, 6a, 6b, 6c can be connected via the center tap of the series-connected power semiconductor switches 7 and via at least one of the remaining power terminals of the power semiconductor switch 7 in the half-bridges of the multilevel converter 2, whereby the submodule output voltage U ou t falls.
[0044] The capacitor submodule voltage USMK drops across submodule capacitor 8.
[0045] If submodule 6, 6a, 6b, 6c is blocked during pulse blocking, the pulse blocking signal IS is present at the power semiconductor switches 7. If submodule 6, 6a, 6b, 6c remains switched on at least for a limited period of time during pulse blocking with the power semiconductor switches 7, the first or the second switching signal S1, S2 is present at the power semiconductor switches 7.
Claims
Patent claims 1. Method (V) for limiting a DC voltage (UDC) on the DC circuit (1) of a multilevel converter (2), wherein - a first, second and third half-bridge (3a, 3b, 3c) of half-bridges (3) of the multilevel converter (2) on the DC circuit (1) - with one upper half-bridge branch (4) and one lower half-bridge branch (5) per half-bridge (3a, 3b, 3c) - generate an AC voltage (UAC) for AC phases (L) of the multilevel converter (2), - in each of the upper and lower half-bridge branches (4,5) at least two series-connected submodules (6) are operated as first submodules (6a) of the first half-bridge (3a), second submodules (6b) of the second half-bridge (3b) and third submodules (6c) of the third half-bridge (3c) and - in each of the submodules (6) two series-connected power semiconductor switches (7) are operated with a surge module capacitor (8) connected in parallel to them, characterized in that when an impulse block (I) is applied to the multilevel converter (2) - the power semiconductor switches (7) of the first submodules (6a) of the first half-bridge (3a) on a first phase (L1) of the AC phases (L) and the power semiconductor switches (7) of the second submodules (6b) of the second half-bridge (3b) on a second phase (L2) of the AC phases (L) are blocked by means of an impulse block signal (IS) and - the power semiconductor switches (7) of the third submodules (6, 6c) of the third half-bridge (3c) for a third phase (L3) of the AC phases (L) are switched by means of a first switching signal (S1) and / or second switching signal (S2) such that the DC voltage (UDC) at DC circuit (1) is limited.
2. Method (V) according to claim 1, wherein the selection of the first submodules (6a) of the first half-bridge (3a) and the second submodules (6b) of the second half-bridge (3b) to be blocked by the pulse blocking signal (IS) is carried out such that the half-bridges with the smallest currents of branch currents (Izwi4,lzwi5,l z24,lz 25,lzw34,lzw35,) flowing in the upper half-bridge branches (4) and lower half-bridge branches (5) are selected.
3. Method (V) according to any one of the preceding claims, wherein the power semiconductor switches (7) of the third submodules (6, 6c) of the third half-bridge (3c) are supplied with a pulse blocking signal (IS) when an impermissibly high DC voltage (UDC) on the DC circuit (1) has decayed or been eliminated after the pulse block (I) has been applied.
4. Multi-level inverter (2) configured to perform a method (V) for limiting a DC voltage (UDC) on the DC circuit (1) according to any one of claims 1 to 3, wherein - by means of a first, second and third half-bridge (3a, 3b, 3c) of half-bridges (3) of the multilevel converter (2) on the DC circuit (1) - with one upper half-bridge branch (4) and one lower half-bridge branch (4) per half-bridge (3a, 3b, 3c) - an AC voltage (UAC) for AC phases (L) of the multilevel converter (2) can be generated, - in each of the upper and lower half-bridge branches (4, 5) at least two series-connected submodules (6) can be operated as first submodules (6a) of the first half-bridge (3a), second submodules (6b) of the second half-bridge (3b) and third submodules (6c) of the third half-bridge (3c), - in each of the submodules (6) two series-connected power semiconductor switches (7) can be operated with a submodule capacitor (8) connected in parallel to them, characterized in that, by applying an impulse block (I) to the multilevel converter (2), the power semiconductor switches (7) of the first submodules (6a) of the first half-bridge (3a) on a first phase (L1) of the AC phases (L) and the power semiconductor switches (7) of the second submodules (6b) of the second half-bridge (3b) on a second phase (L2) of the AC phases (L) can be blocked by means of an impulse block signal (IS) and - the power semiconductor switches (7) of the third submodules (6,6c) of the third half-bridge (3c) for a third phase (L3) of the AC phases (L) can be switched by means of a first switching signal (S1) and / or second switching signal (S2) in such a way that the DC voltage (UDC) on the DC circuit (1) can be limited.