Power conversion apparatus

Abstract

This power conversion apparatus makes it possible to achieve zero-voltage soft switching without directly controlling a plurality of switches for zero-voltage soft switching by a control device, and reduces current distortion. The control device sets a second dead time period (Td2). A signal generation circuit generates a control signal for each of the plurality of switches. When the difference (Δd) between duty command values of any two phases among duty command values (du, dv, dw) of a plurality of phases is less than a prescribed threshold (Δdth), the control device determines a common shift amount (dcom) so that a duty command value of one phase among the duty command values of the two phases becomes a value corresponding to 100% or a value corresponding to 0%, and shifts each of the duty command values (du, dv, dw) of the plurality of phases by the common shift amount (dcom) to generate a plurality of first PWM signals (SU1, SV1, SW1) and a plurality of second PWM signals (SU2, SV2, SW2).

Description

Power converter

[0001] This disclosure relates to a power conversion device, and more particularly to a power conversion device capable of converting DC power to AC power.

[0002] Patent document 1 discloses a power conversion system.

[0003] The power conversion device disclosed in Patent Document 1 includes a first DC terminal, a second DC terminal, a power conversion circuit, a plurality of AC terminals, a plurality of switches, a plurality of resonance capacitors, a resonance inductor, a capacitor, and a control device. The power conversion circuit has a plurality of first switching elements and a plurality of second switching elements. In the power conversion circuit, a plurality of switching circuits in which a plurality of first switching elements and a plurality of second switching elements are connected in series one-to-one are connected in parallel with each other. In the power conversion circuit, a plurality of first switching elements are connected to the first DC terminal, and a plurality of second switching elements are connected to the second DC terminal. The plurality of AC terminals correspond one-to-one to the plurality of switching circuits. Each of the plurality of AC terminals is connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit. The plurality of switches correspond one-to-one to the plurality of switching circuits. Each of the plurality of switches has its first end connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit and its second end commonly connected to the common connection point. The plurality of resonance capacitors correspond one-to-one to the plurality of switches. Each of the plurality of resonance capacitors is connected between the first end of the corresponding switch and the second DC terminal. The resonance inductor has a first end and a second end. In the resonance inductor, the first end of the resonance inductor is connected to the common connection point. The capacitor is connected between the second end of the resonance inductor and the second DC terminal. The control device controls the plurality of first switching elements, the plurality of second switching elements, and the plurality of switches. When the control device determines that two-phase resonance currents corresponding to two of the plurality of switching circuits flow simultaneously in the resonance inductor, the control device performs control to shift the on-periods of each of the first switching element and the second switching element in one of the two switching circuits.

[0004] In the power conversion device disclosed in Patent Document 1, soft switching can be performed more reliably.

[0005] In the power conversion device disclosed in Patent Document 1, the control device needs to generate and output multiple first PWM signals, multiple second PWM signals, and multiple control signals, which results in a large control device.

[0006] Furthermore, in the power conversion device disclosed in Patent Document 1, the current distortion of the load current may increase due to the difference in line voltage generated by shifting the ON periods of the first switching element and the second switching element in a single switching circuit.

[0007] International Publication No. 2023 / 074636

[0008] The object of this disclosure is to provide a power conversion device that can perform zero-voltage soft switching without directly controlling multiple switches for zero-voltage soft switching in the control device, and that can reduce current distortion.

[0009] A power conversion device according to one embodiment of the present disclosure comprises a first DC terminal, a second DC terminal, a power conversion circuit, a plurality of AC terminals, a plurality of switches, a plurality of resonant capacitors, a resonant inductor, a regenerative capacitor, a control device, and a signal generation circuit. The power conversion circuit has a plurality of first switching elements and a plurality of second switching elements. In the power conversion circuit, a plurality of switching circuits, each in which the plurality of first switching elements and the plurality of second switching elements are connected in series in a one-to-one relationship, are connected in parallel to each other. In the power conversion circuit, the plurality of first switching elements are connected to the first DC terminal. In the power conversion circuit, the plurality of second switching elements are connected to the second DC terminal. The plurality of AC terminals correspond one-to-one to the plurality of switching circuits. Each of the plurality of AC terminals is connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit among the plurality of switching circuits, and load current flows through it. The plurality of switches correspond one-to-one to the plurality of switching circuits. Each of the plurality of switches has its first end connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit among the plurality of switching circuits. The plurality of resonant capacitors correspond one-to-one with the plurality of switches. Each of the plurality of resonant capacitors is connected between the first end and the second DC terminal of the corresponding switch among the plurality of switches. The resonant inductor has a third end and a fourth end. In the resonant inductor, the third end is connected to the second end of the plurality of switches. The regenerative capacitor has a fifth end and a sixth end. In the regenerative capacitor, the fifth end is connected to the first DC terminal or the second DC terminal, and the sixth end is connected to the fourth end of the resonant inductor. The control device generates a plurality of first PWM signals to control the plurality of first switching elements and a plurality of second PWM signals to control the plurality of second switching elements, based on a plurality of phase duty cycle command values ​​that correspond one-to-one with the plurality of switching circuits.The signal generation circuit provides each of the plurality of switches with a control signal whose potential changes between a high level and a low level. The control device sets a second dead time period for each of the plurality of switching circuits, which is a predetermined time added to a first dead time period that is set so that the on periods of the first switching element and the second switching element do not overlap between the high-level period of the first PWM signal to the first switching element and the high-level period of the second PWM signal to the second switching element. The predetermined time is determined according to the current value of the load current, the inductance of the resonant inductor and the voltage value of the regenerative capacitor. The signal generation circuit generates the control signal for each of the plurality of switches, which has a high-level period corresponding to the second dead time period for the corresponding switching circuit among the plurality of switching circuits. The control device determines a common shift amount when the difference between the duty cycle command values ​​of any two of the multiple phases is less than a predetermined threshold, such that the duty cycle command value of one of the two phases becomes a value equivalent to 100% or 0%, and shifts each of the multiple phases' duty cycle command values ​​by the common shift amount to generate the multiple first PWM signals and the multiple second PWM signals.

[0010] Figure 1 is a circuit diagram of a system equipped with a power converter according to Embodiment 1. Figure 2 is an explanatory diagram of the duty cycle command values ​​used in the control device of the power converter. Figure 3 is a timing chart of the power converter before shifting the duty cycle command values ​​of multiple phases. Figure 4 is a timing chart of the power converter after shifting the duty cycle command values ​​of multiple phases. Figure 5 is a timing chart of the power converter before shifting the duty cycle command values ​​of multiple phases. Figure 6 is a timing chart of the power converter after shifting the duty cycle command values ​​of multiple phases. Figure 7 is a timing chart of the power converter before shifting the duty cycle command values ​​of multiple phases. Figure 8 is a timing chart of the power converter after shifting the duty cycle command values ​​of multiple phases. Figure 9 is a circuit block diagram of the signal generation circuit in the power converter. Figure 10 is a timing chart to explain the operation of the power converter. Figure 11 is a timing chart to explain the operation of the power converter. Figure 12 is a timing chart illustrating the operation of the power converter described above. Figure 13 is an explanatory diagram of the operation of the power converter described above when the U-phase load current is positive. Figure 14 is an explanatory diagram of the operation of the power converter described above when the polarity of the U-phase load current is negative. Figure 15 is a circuit diagram of a system equipped with the power converter according to Embodiment 2. Figure 16 is a circuit diagram of a system equipped with the power converter according to Embodiment 3. Figure 17 is an explanatory diagram of the operation of the power converter described above when the U-phase load current is positive. Figure 18 is an explanatory diagram of the operation of the power converter described above when the polarity of the U-phase load current is negative. Figure 19 is a timing chart of the power converter described above before shifting the duty cycle command values ​​of multiple phases. Figure 20 is a timing chart of the power converter described above after shifting the duty cycle command values ​​of multiple phases. Figure 21 is a circuit diagram of a system equipped with the power converter according to Embodiment 4. Figure 22 is an explanatory diagram of the operation of the power converter described above when the U-phase load current is positive. Figure 23 is an explanatory diagram of the operation of the power converter described above when the polarity of the U-phase load current is negative.Figure 24 is a timing chart of the power converter described above before shifting the duty cycle command values ​​of multiple phases. Figure 25 is a timing chart of the power converter described above after shifting the duty cycle command values ​​of multiple phases. Figure 26 is a circuit diagram of a system equipped with the power converter according to Embodiment 5. Figure 27 is a circuit diagram of the signal generation circuit in the power converter described above. Figure 28 is a circuit diagram of a system equipped with the power converter according to Embodiment 6. Figure 29 is a timing chart of the power converter described above before shifting the duty cycle command values ​​of multiple phases. Figure 30 is a timing chart of the power converter described above after shifting the duty cycle command values ​​of multiple phases.

[0011] (Embodiment 1) Below, the power conversion device 100 according to Embodiment 1 will be described with reference to Figures 1 to 14.

[0012] (1) Overall Configuration of the Power Converter The power converter 100 includes, for example, a first DC terminal 31, a second DC terminal 32, and a plurality (for example, three) AC terminals 41, as shown in Figure 1. A DC power supply E1 is connected between the first DC terminal 31 and the second DC terminal 32 of the power converter 100, and an AC load RA1 is connected to the plurality of AC terminals 41. The AC load RA1 is, for example, a three-phase servo motor. The power converter 100 converts the DC output from the DC power supply E1 into AC power and outputs it to the AC load RA1. The DC power supply E1 includes, for example, an AC-DC converter, a DC-DC converter, a solar cell, or a fuel cell. In the power converter 100, if the plurality of AC terminals 41 are three AC terminals 41, the AC power is, for example, three-phase AC power having U-phase, V-phase, and W-phase.

[0013] The power converter 100 comprises a power conversion circuit 11, a plurality (for example, three) of switches 8, a plurality (for example, three) of resonant capacitors 9, a resonant inductor L1, a regenerative capacitor 15, a control device 51, and a signal generation circuit 52. Each of the plurality of switches 8 is, for example, a bidirectional switch. The power converter 100 further comprises a protection circuit 17 including a first clamp diode 13 and a second clamp diode 14. The power converter 100 further comprises a capacitor C10.

[0014] The power conversion circuit 11 has a plurality (for example, three) of first switching elements 1 and a plurality (for example, three) of second switching elements 2. In the power conversion circuit 11, a plurality (for example, three) of switching circuits 10, each consisting of a plurality of first switching elements 1 and a plurality of second switching elements 2 connected in a one-to-one series relationship, are connected in parallel to each other. In the power conversion circuit 11, the plurality of first switching elements 1 are connected to a first DC terminal 31, and the plurality of second switching elements 2 are connected to a second DC terminal 32.

[0015] The multiple AC terminals 41 correspond one-to-one with the multiple switching circuits 10. Each of the multiple AC terminals 41 is connected to the connection point 3 of the first switching element 1 and the second switching element 2 in the corresponding switching circuit 10 among the multiple switching circuits 10.

[0016] The multiple switches 8 correspond one-to-one with the multiple switching circuits 10. Each of the multiple switches 8 has a first end 81 and a second end 82. The first end 81 of each of the multiple switches 8 is connected to the connection point 3 of the first switching element 1 and the second switching element 2 in the corresponding switching circuit 10 among the multiple switching circuits 10.

[0017] Multiple resonant capacitors 9 correspond one-to-one with multiple switches 8. Each of the multiple resonant capacitors 9 is connected between the first terminal 81 and the second DC terminal 32 of the corresponding switch 8 among the multiple switches 8.

[0018] The resonant inductor L1 has a third terminal and a fourth terminal. In the resonant inductor L1, the third terminal is connected to the second terminal 82 of a plurality (for example, three) switches 8.

[0019] The regenerative capacitor 15 has a fifth terminal 153 and a sixth terminal 154. In the regenerative capacitor 15, the fifth terminal 153 is connected to the second DC terminal 32, and the sixth terminal 154 is connected to the fourth terminal of the resonant inductor L1.

[0020] The control device 51 generates a plurality of first PWM (Pulse Width Modulation) signals SU1, SV1, SW1 for controlling a plurality of first switching elements 1, and a plurality of second PWM signals SU2, SV2, SW2 for controlling a plurality of second switching elements 2.

[0021] The signal generation circuit 52 generates multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 to control multiple switches 8.

[0022] (2) Details of the power converter In the following description, for the sake of convenience, the switching circuits 10 corresponding to the U-phase, V-phase, and W-phase may be referred to as switching circuit 10U, switching circuit 10V, and switching circuit 10W, respectively. Also, in the following description, the first switching element 1 and the second switching element 2 of switching circuit 10U may be referred to as the first switching element 1U and the second switching element 2U. Also, in the following description, the first switching element 1 and the second switching element 2 of switching circuit 10V may be referred to as the first switching element 1V and the second switching element 2V. Also, in the following description, the first switching element 1 and the second switching element 2 of switching circuit 10W may be referred to as the first switching element 1W and the second switching element 2W. Furthermore, in the following, the connection point 3 between the first switching element 1U and the second switching element 2U may be referred to as connection point 3U, the connection point 3 between the first switching element 1V and the second switching element 2V may be referred to as connection point 3V, and the connection point 3 between the first switching element 1W and the second switching element 2W may be referred to as connection point 3W. Furthermore, in the following, the AC terminal 41 connected to connection point 3U may be referred to as AC terminal 41U, the AC terminal 41 connected to connection point 3V may be referred to as AC terminal 41V, and the AC terminal 41 connected to connection point 3W may be referred to as AC terminal 41W. Furthermore, in the following, the resonant capacitor 9 connected in parallel to the second switching element 2U may be referred to as resonant capacitor 9U, the resonant capacitor 9 connected in parallel to the second switching element 2V may be referred to as resonant capacitor 9V, and the resonant capacitor 9 connected in parallel to the second switching element 2W may be referred to as resonant capacitor 9W. Furthermore, in the following, the switch 8 connected to connection point 3U may be referred to as switch 8U, the switch 8 connected to connection point 3V as switch 8V, and the switch 8 connected to connection point 3W as switch 8W.

[0023] In the power converter 100, for example, the high-potential output terminal (positive terminal) of the DC power supply E1 is connected to the first DC terminal 31, and the low-potential output terminal (negative terminal) of the DC power supply E1 is connected to the second DC terminal 32. In addition, in the power converter 100, for example, the U-phase terminal, V-phase terminal, and W-phase terminal of the AC load RA1 are connected to the three AC terminals 41U, 41V, and 41W, respectively.

[0024] In the power conversion circuit 11, each of the multiple (three in the example of Figure 1) first switching elements 1 and each of the multiple (three in the example of Figure 1) second switching elements 2 has a control terminal, a first main terminal, and a second main terminal. The control terminals of the multiple first switching elements 1 and the multiple second switching elements 2 are connected to the control device 51. In each of the multiple switching circuits 10 of the power conversion device 100, the first main terminal of the first switching element 1 is connected to the first DC terminal 31, the second main terminal of the first switching element 1 is connected to the first main terminal of the second switching element 2, and the second main terminal of the second switching element 2 is connected to the second DC terminal 32. In each of the multiple switching circuits 10, the first switching element 1 is a high-side switching element (P-side switching element), and the second switching element 2 is a low-side switching element (N-side switching element). Each of the multiple first switching elements 1 and the multiple second switching elements 2 is, for example, an IGBT (Insulated Gate Bipolar Transistor). Therefore, the control terminal, first main terminal, and second main terminal of each of the multiple first switching elements 1 and the multiple second switching elements 2 are the gate terminal, collector terminal, and emitter terminal, respectively.

[0025] The power conversion circuit 11 further includes a plurality of first diodes 4 connected in antiparallel in a one-to-one relationship to a plurality of first switching elements 1 (three), and a plurality of second diodes 5 connected in antiparallel in a one-to-one relationship to a plurality of second switching elements 2 (three). In each of the plurality of first diodes 4, the anode of the first diode 4 is connected to the second main terminal (emitter terminal) of the first switching element 1 corresponding to the first diode 4, and the cathode of the first diode 4 is connected to the first main terminal (collector terminal) of the first switching element 1 corresponding to the first diode 4. In each of the plurality of second diodes 5, the anode of the second diode 5 is connected to the second main terminal (emitter terminal) of the second switching element 2 corresponding to the second diode 5, and the cathode of the second diode 5 is connected to the first main terminal (collector terminal) of the second switching element 2 corresponding to the second diode 5.

[0026] At the connection point 3U between the first switching element 1U and the second switching element 2U, the U-phase terminal of the AC load RA1 is connected via the AC terminal 41U. At the connection point 3V between the first switching element 1V and the second switching element 2V, the V-phase terminal of the AC load RA1 is connected via the AC terminal 41V. At the connection point 3W between the first switching element 1W and the second switching element 2W, the W-phase terminal of the AC load RA1 is connected via the AC terminal 41W.

[0027] Multiple resonant capacitors 9 correspond one-to-one with multiple switches 8. Each of the multiple resonant capacitors 9 is connected between the first terminal 81 and the second DC terminal 32 of the corresponding switch 8 among the multiple switches 8. The power converter 100 has multiple (three in the example of Figure 1) resonant circuits. Each of the multiple resonant circuits includes a resonant capacitor 9 and a resonant inductor L1. In this embodiment, the resonant inductor L1 is common to the multiple resonant circuits.

[0028] Each of the multiple switches 8 has a third switching element 6 and a fourth switching element 7. Each of the multiple (three in the example of Figure 1) third switching elements 6 and each of the multiple (three in the example of Figure 1) fourth switching elements 7 has a control terminal, a first main terminal, and a second main terminal. The control terminals of the multiple third switching elements 6 and the multiple fourth switching elements 7 are connected to the signal generation circuit 52. Each of the multiple third switching elements 6 and the multiple fourth switching elements 7 is, for example, an IGBT. Therefore, the control terminal, first main terminal, and second main terminal of each of the multiple third switching elements 6 and the multiple fourth switching elements 7 are the gate terminal, collector terminal, and emitter terminal, respectively. In each of the multiple switches 8, the third switching element 6 and the fourth switching element 7 are connected in reverse series. In each of the multiple switches 8, the first main terminal (collector terminal) of the third switching element 6 is connected to the first main terminal (collector terminal) of the fourth switching element 7. In each of the multiple switches 8, the second main terminal (emitter terminal) of the third switching element 6 is connected to the connection point 3 of the corresponding switching circuit 10 among the multiple switching circuits 10, and the second main terminal (emitter terminal) of the fourth switching element 7 is connected to the resonant inductor L1. Furthermore, each of the multiple switches 8 has a diode 61 connected in antiparallel to the third switching element 6 and a diode 71 connected in antiparallel to the fourth switching element 7.

[0029] In the power converter 100, switch 8U is connected to the connection point 3U between the first switching element 1U and the second switching element 2U. Switch 8V is connected to the connection point 3V between the first switching element 1V and the second switching element 2V. Switch 8W is connected to the connection point 3W between the first switching element 1W and the second switching element 2W. For convenience of explanation, the third switching element 6 and the fourth switching element 7 of switch 8U may be referred to as the third switching element 6U and the fourth switching element 7U, respectively; the third switching element 6 and the fourth switching element 7 of switch 8V may be referred to as the third switching element 6V and the fourth switching element 7V, respectively; and the third switching element 6 and the fourth switching element 7 of switch 8W may be referred to as the third switching element 6W and the fourth switching element 7W, respectively.

[0030] Multiple switches 8 are controlled by a signal generation circuit 52. In other words, the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W are controlled by the signal generation circuit 52.

[0031] The resonant inductor L1 has a third terminal and a fourth terminal. In the resonant inductor L1, the third terminal is connected to the second terminal 82 of the plurality of switches 8. More specifically, the third terminal of the resonant inductor L1 is connected to a common connection point 25 to which the second terminals 82 of the plurality of switches 8 are connected. The fourth terminal of the resonant inductor L1 is connected to the sixth terminal 154 of the regenerative capacitor 15.

[0032] The regenerative capacitor 15 is connected between the fourth terminal of the resonant inductor L1 and the second DC terminal 32. The regenerative capacitor 15 is, for example, a film capacitor.

[0033] Capacitor C10 is connected between the first DC terminal 31 and the second DC terminal 32, and is connected in parallel to the power conversion circuit 11. Capacitor C10 is, for example, an electrolytic capacitor.

[0034] The control device 51 controls a plurality of first switching elements 1 and a plurality of second switching elements 2. The control device 51 includes a computer system. The computer system mainly consists of a processor and memory as hardware. The processor executes a program recorded in the memory of the computer system, thereby realizing the function of the control device 51 in this disclosure. The processor of the computer system is composed of one or more electronic circuits including semiconductor integrated circuits (ICs) or large-scale integrated circuits (LSIs). The integrated circuits such as ICs and LSIs referred to here are named differently depending on the degree of integration, and include integrated circuits called system LSIs, VLSIs (Very Large Scale Integrations), or ULSIs (Ultra Large Scale Integrations). Furthermore, FPGAs (Field-Programmable Gate Arrays) that are programmed after the manufacture of the LSI, or logic devices that allow for the reconstruction of junction relationships or circuit compartments within the LSI, can also be used as processors. The plurality of electronic circuits may be aggregated on a single chip or distributed across multiple chips. Multiple chips may be integrated into a single device or distributed across multiple devices. The computer system referred to here includes a microcontroller having one or more processors and one or more memories. Therefore, the microcontroller also consists of one or more electronic circuits, including semiconductor integrated circuits or large-scale integrated circuits.

[0035] The control device 51 outputs multiple first PWM signals SU1, SV1, and SW1 to control the on / off state of each of the multiple first switching elements 1U, 1V, and 1W. Each of the multiple first PWM signals SU1, SV1, and SW1 is a PWM signal whose potential level changes between, for example, a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level. The first switching elements 1U, 1V, and 1W are turned on when the first PWM signals SU1, SV1, and SW1 are at a high level and turned off when they are at a low level, respectively. The control device 51 also outputs multiple second PWM signals SU2, SV2, and SW2 to control the on / off state of each of the multiple second switching elements 2U, 2V, and 2W. Each of the multiple second PWM signals SU2, SV2, and SW2 is a PWM signal whose potential level changes between, for example, a first potential level (hereinafter also referred to as the low level) and a second potential level (hereinafter also referred to as the high level) that is higher than the first potential level. The second switching elements 2U, 2V, and 2W are turned on when the second PWM signals SU2, SV2, and SW2 are at a high level and turned off when they are at a low level, respectively.

[0036] The control device 51 generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2 based on the three-phase duty command values ​​du, dv, dw (see Figure 2) of the three-phase modulation scheme. Figure 2 shows a U-phase modulated wave with the U-phase duty command value du as the instantaneous value, a V-phase modulated wave with the V-phase duty command value dv as the instantaneous value, and a W-phase modulated wave with the W-phase duty command value dw as the instantaneous value. The U-phase modulated wave, V-phase modulated wave, and W-phase modulated wave are sinusoidal and have a phase difference of 120° from each other. The length of one period of each of the U-phase modulated wave, V-phase modulated wave, and W-phase modulated wave is the same. The control device 51 generates the three-phase modulated duty command values ​​du, dv, dw based on information regarding the state of the AC load RA1. If the AC load RA1 is a three-phase servo motor, information regarding the state of the AC load RA1 includes, for example, the detected values ​​from multiple current sensors that detect the output currents (hereinafter also referred to as load currents) iU, iV, and iW flowing through the U-phase, V-phase, and W-phase terminals of the AC load RA1, respectively.

[0037] As shown in Figures 3 to 8, the control device 51 generates multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2 using the three-phase duty command values ​​du, dv, dw and the carrier signal CA1 for each period of the triangular wave carrier signal CA1. Of Figures 3 to 8, Figures 3, 5, and 7 show the timing charts estimated before the shift operation when the control device 50 performs the shift operation described later, while Figures 4, 6, and 8 correspond to Figures 3, 5, and 7, respectively, and show the timing charts when the shift operation is performed. Note that one period of the carrier signal CA1 is shorter than one period of each of the U-phase modulated wave, V-phase modulated wave, and W-phase modulated wave.

[0038] The control device 51 generates a first PWM signal SU1 and a second PWM signal SU2 to be supplied to the first switching element 1U and the second switching element 2U, respectively, based on the carrier signal CA1 and the duty cycle command value du. The control device 51 also generates a first PWM signal SV1 and a second PWM signal SV2 to be supplied to the first switching element 1V and the second switching element 2V, respectively, based on the carrier signal CA1 and the duty cycle command value dv of the V phase. The control device 51 also generates a first PWM signal SW1 and a second PWM signal SW2 to be supplied to the first switching element 1W and the second switching element 2W, respectively, based on the carrier signal CA1 and the duty cycle command value dw of the W phase. In this embodiment, the control device 51 sets the maximum value of the carrier signal CA1 to 1 and the minimum value to 0. Furthermore, the control device 51 sets the maximum value (corresponding to 100%) of each of the three-phase duty command values ​​du, dv, and dw to 1, and the minimum value (corresponding to 0%) to 0. In this embodiment, when the duty command value du of the U phase is greater than 0.5, the polarity of the U phase load current iU is positive, and when the duty command value du of the U phase is less than 0.5, the polarity of the U phase load current iU is negative. Also in this embodiment, when the duty command value dv of the V phase is greater than 0.5, the polarity of the V phase load current iV is positive, and when the duty command value dv of the V phase is less than 0.5, the polarity of the V phase load current iV is negative. Also in this embodiment, when the duty command value dw of the W phase is greater than 0.5, the polarity of the W phase load current iW is positive, and when the duty command value dw of the W phase is less than 0.5, the polarity of the W phase load current iW is negative. Furthermore, the control device 51 may set the maximum and minimum values ​​of the carrier signal CA1 to values ​​other than 1 and 0, respectively, and the maximum and minimum values ​​of the three-phase duty command values ​​du, dv, and dw to values ​​other than 1 and 0, respectively. In this case, if the duty command value du of the U-phase is greater than {(maximum value of duty command value du) - (minimum value of duty command value du)} / 2, the polarity of the U-phase load current iU is positive, and if it is less than {(maximum value of duty command value du) - (minimum value of duty command value du)} / 2, the polarity of the U-phase load current iU is negative.Furthermore, if the duty cycle command value dv of the V phase is greater than {(maximum value of duty cycle command value dv) - (minimum value of duty cycle command value dv)} / 2, the polarity of the V phase load current iV is positive, and if it is less than {(maximum value of duty cycle command value dv) - (minimum value of duty cycle command value dv)} / 2, the polarity of the V phase load current iV is negative. Also, if the duty cycle command value dw of the W phase is greater than {(maximum value of duty cycle command value dw) - (minimum value of duty cycle command value dw)} / 2, the polarity of the W phase load current iW is positive, and if it is less than {(maximum value of duty cycle command value dw) - (minimum value of duty cycle command value dw)} / 2, the polarity of the W phase load current iW is negative.

[0039] The duty cycles of the first PWM signal SU1 and the second PWM signal SU2, generated by the control device 51, change based on the duty cycle command value du. The control device 51 generates the first PWM signal SU1 by comparing the duty cycle command value du with the carrier signal CA1. More specifically, the control device 51 compares the duty cycle command value du with the carrier signal CA1 and generates the first PWM signal SU1 which is high level when the duty cycle command value du is greater than the carrier signal CA1 and low level when the duty cycle command value du is less than or equal to the carrier signal CA1. The control device 51 also generates the second PWM signal SU2 by inverting the first PWM signal SU1. Furthermore, the control device 51 sets a first dead time period Td1 (see Figure 10) between the high-level period of the first PWM signal SU1 and the high-level period of the second PWM signal SU2 so that the ON period of the first switching element 1U and the ON period of the second switching element 2U do not overlap.

[0040] The duty cycles of the first PWM signal SV1 and the second PWM signal SV2, both generated by the control device 51, change based on the duty cycle command value dv. The control device 51 generates the first PWM signal SV1 by comparing the duty cycle command value dv with the carrier signal CA1. More specifically, the control device 51 compares the duty cycle command value dv with the carrier signal CA1 and generates the first PWM signal SV1 which is high level when the duty cycle command value dv is greater than the carrier signal CA1 and low level when the duty cycle command value dv is less than or equal to the carrier signal CA1. The control device 51 also generates the second PWM signal SV2 by inverting the first PWM signal SV1. Furthermore, the control device 51 sets a first dead time period Td1 (see Figure 11) between the high-level period of the first PWM signal SV1 and the high-level period of the second PWM signal SV2 so that the ON period of the first switching element 1V and the ON period of the second switching element 2V do not overlap.

[0041] The duty cycles of the first PWM signal SW1 and the second PWM signal SW2, both generated by the control device 51, change based on the duty cycle command value dw. The control device 51 generates the first PWM signal SW1 by comparing the duty cycle command value dw with the carrier signal CA1. More specifically, the control device 51 compares the duty cycle command value dw with the carrier signal CA1 and generates the first PWM signal SW1 which is high level when the duty cycle command value dw is greater than the carrier signal CA1 and low level when the duty cycle command value dw is less than or equal to the carrier signal CA1. The control device 51 also generates the second PWM signal SW2 by inverting the first PWM signal SW1. Furthermore, the control device 51 sets a first dead time period Td1 (see Figure 12) between the high-level period of the first PWM signal SW1 and the high-level period of the second PWM signal SW2 so that the ON period of the first switching element 1W and the ON period of the second switching element 2W do not overlap.

[0042] When the difference Δd between the duty command values of any two phases among the duty command values du, dv, and dw of multiple phases is less than a predetermined threshold value Δdth, the control device 51 determines a common shift amount dcom such that the duty command value of one of the duty command values of the two phases becomes a value corresponding to 100% or a value corresponding to 0%, and shifts each of the duty command values du, dv, and dw of the multiple phases by the common shift amount dcom. Based on the shifted duty command values du, dv, and dw, the control device 51 generates a plurality of first PWM signals SU1, SV1, SW1, a plurality of second PWM signals SU2, SV2, SW2, and a plurality of control signals SU6, SU7, SV6, SV7, SW6, SW7.

[0043] The control device 51 sets the maximum value Cmax of the carrier signal CA1 to 1, the minimum value Cmin of the carrier signal CA1 to 0, the maximum value of each of the three-phase duty command values du, dv, and dw to 1, and the minimum value to 0.

[0044] For example, every cycle of the carrier signal CA1, when the difference Δd between the duty command values of any two phases among the duty command values du, dv, and dw of multiple phases is less than the predetermined threshold value Δdth, the control device 51 obtains the common shift amount dcom by calculating dcom = Cmax - max{du, dv, dw} or dcom = |Cmin - min{du, dv, dw}|. When the difference Δd between the duty command values of any two phases among the duty command values du, dv, and dw of multiple phases is less than the predetermined threshold value Δdth, and each of the duty command values of the two phases is greater than (Cmax - Cmin) / 2 = 0.5, the control device 51 obtains the common shift amount dcom by calculating dcom = Cmax - max{du, dv, dw}. When the difference Δd between the duty command values of any two phases among the duty command values du, dv, and dw of multiple phases is less than the predetermined threshold value Δdth, and each of the duty command values of the two phases is less than (Cmax - Cmin) / 2 = 0.5, the control device 51 obtains the common shift amount dcom by calculating dcom = |Cmin - min{du, dv, dw}|.

[0045] Further, the control device 51 shifts each of the three-phase duty command values du, dv, and dw by a common shift amount dcom so that the duty command value of one phase among the two-phase duty command values becomes 1 or 0, and based on the carrier signal CA1 and the shifted three-phase duty command values du, dv, and dw, a plurality of first PWM signals SU1, SV1, and SW1, and a plurality of second PWM signals SU2, SV2, and SW2 are generated. When shifting each of the three-phase duty command values du, dv, and dw by the common shift amount dcom so that the duty command value of one phase among the two-phase duty command values becomes 1, the common shift amount dcom is added to each of the three-phase duty command values du, dv, and dw. When shifting each of the three-phase duty command values du, dv, and dw by the common shift amount dcom so that the duty command value of one phase among the two-phase duty command values becomes 0, the common shift amount dcom is subtracted from each of the three-phase duty command values du, dv, and dw.

[0046] The plurality of switches 8, the resonance inductor L1, the plurality of resonance capacitors 9, and the regeneration capacitor 15 are provided for performing zero-voltage soft switching of the plurality of first switching elements 1 and the plurality of second switching elements 2.

[0047] The switch 8U can pass the charging current flowing through the path of the regeneration capacitor 15 - resonance inductor L1 - switch 8U - resonance capacitor 9U when the third switching element 6U is in the on state and the fourth switching element 7U is in the off state. The charging current is the current for charging the resonance capacitor 9U. The switch 8U can pass the discharge current flowing through the path of the resonance capacitor 9U - switch 8U - resonance inductor L1 - regeneration capacitor 15 when the third switching element 6U is in the off state and the fourth switching element 7U is in the on state. The discharge current is the current for discharging the charge of the resonance capacitor 9U.

[0048] Switch 8V allows the charging current flowing through the path of regenerative capacitor 15 - resonant inductor L1 - switch 8V - resonant capacitor 9V to pass through when the third switching element 6V is ON and the fourth switching element 7V is OFF. The charging current is the current that charges the resonant capacitor 9V. Switch 8V allows the discharge current flowing through the path of resonant capacitor 9V - switch 8V - resonant inductor L1 - regenerative capacitor 15 to pass through when the third switching element 6V is OFF and the fourth switching element 7V is ON. The discharge current is the current that discharges the charge from the resonant capacitor 9V.

[0049] Switch 8W can pass the charging current flowing through the path of regenerative capacitor 15 - resonant inductor L1 - switch 8W - resonant capacitor 9W when the third switching element 6W is ON and the fourth switching element 7W is OFF. The charging current is the current that charges the resonant capacitor 9W. Switch 8W can pass the discharge current flowing through the path of resonant capacitor 9W - switch 8W - resonant inductor L1 - regenerative capacitor 15 when the third switching element 6W is OFF and the fourth switching element 7W is ON. The discharge current is the current that discharges the charge from the resonant capacitor 9W.

[0050] In this embodiment, the control device 51 sets the dead time period between the high-level period of the first PWM signal to the first switching element 1 and the high-level period of the second PWM signal to the second switching element 2 for each of the plurality of switching circuits 10 to a second dead time period Td2 (see Figures 10 to 14), which is determined by the first dead time period Td1 and a predetermined time (additional time). The second dead time period Td2 includes the first dead time period Td1. The second dead time period Td2 has a length equal to the length of the first dead time period Td1 plus a predetermined time (the sum of the length of the first dead time period Td1 and the length of the predetermined time). In other words, the control device 51 uses the second dead time period Td2, which is the first dead time period Td1 extended by a predetermined time, as the dead time period.

[0051] The first dead time period Td1 is a period set for each of the multiple switching circuits 10 between the high-level period of the first PWM signal to the first switching element 1 and the high-level period of the second PWM signal to the second switching element 2, during which both the first PWM signal to the first switching element 1 and the second PWM signal to the second switching element 2 are set to a low level so that the on periods of the first switching element 1 and the second switching element 2 do not overlap (there is no period in which both the first switching element 1 and the second switching element 2 are on). In this embodiment, for example, the length of the resonant half-period corresponding to each of the multiple switches 8 is designed according to the length of the first dead time period Td1 for each of the multiple switching circuits 10. The resonant half-period is half of the resonant period, which is the reciprocal of the resonant frequency of the resonant circuit including the switch 8, the resonant inductor L1, and one resonant capacitor 9. Therefore, if the inductance of the resonant inductor L1 is L and the capacitance of the resonant capacitor 9 is C, then the resonant half-period is π × (L・C) １／２ The length of the resonant half-period is set to be the same as, for example, the length of the first dead time period Td1.

[0052] The length of the resonant half-period of a resonant circuit including a resonant inductor L1 and a resonant capacitor 9U is set to the length of a first dead time period Td1 (see Figure 10) set between the high-level period of the first PWM signal SU1 and the high-level period of the second PWM signal SU2. The length of the resonant half-period of a resonant circuit including a resonant inductor L1 and a resonant capacitor 9V is set to the length of a first dead time period Td1 (see Figure 11) set between the high-level period of the first PWM signal SV1 and the high-level period of the second PWM signal SV2. The length of the resonant half-period of a resonant circuit including a resonant inductor L1 and a resonant capacitor 9W is set to the length of a first dead time period Td1 (see Figure 12) set between the high-level period of the first PWM signal SW1 and the high-level period of the second PWM signal SW2.

[0053] If the resonant period is Tres, then Tres / 2, which is the resonant half-period, is the length of the first dead time period Td1. It is desirable that the end of the resonant half-period coincides with the end of the first dead time period Td1 for the switching circuit 10 corresponding to the switch 8. Figure 10 illustrates the first PWM signal SU1, the second PWM signal SU2, the control signal SU6, the control signal SU7, the first dead time period Td1, the additional time Tadu, and the second dead time period Td2. In the example in Figure 10, the start and end times of the first dead time period Td1 are time t12 and time t13, respectively. Also, Figure 11 illustrates the first PWM signal SV1, the second PWM signal SV2, the control signal SV6, the control signal SV7, the first dead time period Td1, the additional time Tadv, and the second dead time period Td2. In the example in Figure 11, the start and end times of the first dead time period Td1 are time points t22 and t23, respectively. Figure 12 illustrates the first PWM signal SW1, the second PWM signal SW2, the control signal SW6, the control signal SW7, the first dead time period Td1, the additional time Tadw, and the second dead time period Td2. In the example in Figure 12, the start and end times of the first dead time period Td1 are time points t32 and t33, respectively.

[0054] The length of the resonant half-period described above is an ideal design example, and may be 90% to 110% of the length of the first dead time period Td1. The resonant half-period and the first dead time period Td1 may also be different lengths.

[0055] The second dead time period Td2 is the first dead time period Td1 plus a predetermined time determined by the load current value and the voltage value of the regenerative capacitor 15. The predetermined time is, for example, an additional time determined by the load current value, the voltage value of the regenerative capacitor 15, and the inductance of the resonant inductor L1. The load current value is, for example, the detection result of the load current by a current sensor or its signal processing value, or an estimated value of the load current. The detection result of the load current or its signal processing value at this time is the detection value at the carrier cycle in which the additional time is added to the first dead time period Td1, or at the timing closest to that carrier cycle. The estimated value of the load current at this time is the value obtained by estimating the load current at the carrier cycle in which the additional time is added to the first dead time period Td1. The inductance of the resonant inductor L1 is a value stored in advance in the control device 51. Hereinafter, the inductance of the resonant inductor L1 will be described as L. The voltage value of the regenerative capacitor 15 is the detected value of the voltage V15 of the regenerative capacitor 15 (the potential V15 at the sixth terminal 154 of the regenerative capacitor 15). In the example in Figure 10, the additional time Tadu is a value obtained by the calculation Tadu = iU × (L / V15). In the example in Figure 11, the additional time Tadv is a value obtained by the calculation Tadv = iV × (L / V15). In the example in Figure 12, the additional time Tadw is a value obtained by the calculation Tadw = iW × (L / V15).

[0056] The specified time is an ideal design example, and may be between 90% and 110% of the additional time.

[0057] In the power converter 100, a signal generation circuit 52, separate from the control device 51, controls a plurality of switches 8.

[0058] The signal generation circuit 52 generates control signals SU6, SU7, SV6, SV7, SW6, and SW7 to control the on / off state of the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W, respectively. The signal generation circuit 52 outputs these signals to the gate terminals of the third switching element 6U, the fourth switching element 7U, the third switching element 6V, the fourth switching element 7V, the third switching element 6W, and the fourth switching element 7W.

[0059] The signal generation circuit 52 generates a control signal for each of the multiple switches 8 that has a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10.

[0060] In the signal generation circuit 52, the start time of the high-level period of the control signal generated for each of the multiple switches 8 is synchronized with the start timing of the second dead time period Td2. In this disclosure, "synchronizing the start time of the high-level period of the control signal with the start timing of the second dead time period Td2" means that the start time of the high-level period of the control signal (start time) is between the start time (start time) and end time (end time) of the second dead time period Td2, and the time length between the start time of the high-level period of the control signal and the end time of the second dead time period Td2 is greater than or equal to the length of the first dead time period Td1. In this embodiment, the signal generation circuit 52 synchronizes the start time of the high-level period of the control signal for each of the multiple switches 8 with the start time of the second dead time period Td2. In this embodiment, the length of the high-level period of the control signal for each of the multiple switches 8 is longer than the length of the second dead time period Td2.

[0061] The signal generation circuit 52 generates a control signal for each of the multiple switches 8 using a first PWM signal to the first switching element 1 and a second PWM signal to the second switching element 2 of the corresponding switching circuit 10 among the multiple switching circuits 10. In this embodiment, as shown in Figure 9, the signal generation circuit 52 has multiple logic circuits 521 to 526 and multiple gate drive circuits 531 to 536. In the signal generation circuit 52, the multiple logic circuits 521 to 526 correspond one-to-one with the multiple gate drive circuits 531 to 536.

[0062] The logic circuit 521 is configured to generate a control signal SU6 using a first PWM signal SU1 and a second PWM signal SU2. The logic circuit 521 is, for example, a two-input, one-output logic circuit, which receives the first PWM signal SU1 and the second PWM signal SU2 output from the control device 51 and outputs the control signal SU6. The control signal SU6 is supplied to the third switching element 6U via the gate drive circuit 531.

[0063] The logic circuit 522 is configured to generate a control signal SU7 using a first PWM signal SU1 and a second PWM signal SU2. The logic circuit 522 is, for example, a two-input, one-output logic circuit, which receives the first PWM signal SU1 and the second PWM signal SU2 output from the control device 51 and outputs the control signal SU7. The control signal SU7 is supplied to the fourth switching element 7U via the gate drive circuit 532.

[0064] The logic circuit 523 is configured to generate a control signal SV6 using the first PWM signal SV1 and the second PWM signal SV2. The logic circuit 523 is, for example, a two-input, one-output logic circuit, which receives the first PWM signal SV1 and the second PWM signal SV2 output from the control device 51 and outputs the control signal SV6. The control signal SV6 is supplied to the third switching element 6V via the gate drive circuit 533.

[0065] The logic circuit 524 is configured to generate a control signal SV7 using the first PWM signal SV1 and the second PWM signal SV2. The logic circuit 524 is, for example, a two-input, one-output logic circuit, which receives the first PWM signal SV1 and the second PWM signal SV2 output from the control device 51 and outputs the control signal SV7. The control signal SV7 is supplied to the fourth switching element 7V via the gate drive circuit 534.

[0066] The logic circuit 525 is configured to generate a control signal SW6 using a first PWM signal SW1 and a second PWM signal SW2. The logic circuit 525 is, for example, a two-input, one-output logic circuit, which receives the first PWM signal SW1 and the second PWM signal SW2 output from the control device 51 and outputs the control signal SW6. The control signal SW6 is supplied to the third switching element 6W via the gate drive circuit 535.

[0067] The logic circuit 526 is configured to generate a control signal SW7 using a first PWM signal SW1 and a second PWM signal SW2. The logic circuit 526 is, for example, a two-input, one-output logic circuit, which receives the first PWM signal SW1 and the second PWM signal SW2 output from the control device 51 and outputs the control signal SW7. The control signal SW7 is supplied to the fourth switching element 7W via the gate drive circuit 536.

[0068] The first clamp diode 13 has its anode connected to the third terminal of the resonant inductor L1 and its cathode connected to the first DC terminal 31. The second clamp diode 14 has its cathode connected to the third terminal of the resonant inductor L1 and its anode connected to the second DC terminal 32.

[0069] (3) Operation of the power converter In the following, the current iL1 flowing through the resonant inductor L1 will be described as positive when flowing in the direction of the arrow in Figure 1, and negative when flowing in the opposite direction to the arrow in Figure 1. Furthermore, the load currents iU, iV, and iW flowing through the U-phase, V-phase, and W-phase terminals of the AC load RA1 will be described as positive when flowing in the direction of the arrow in Figure 1, and negative when flowing in the opposite direction to the arrow in Figure 1. Furthermore, the currents i9U, i9V, and i9W flowing through the resonant capacitors 9U, 9V, and 9W will be described as positive when flowing in the direction of the arrow in Figure 1, and negative when flowing in the opposite direction to the arrow in Figure 1. Therefore, in the discharge operation where the resonant capacitors 9U, 9V, and 9W are discharged, the polarity of the currents i9U, i9V, and i9W becomes positive, and in the charging operation where the resonant capacitors 9U, 9V, and 9W are charged, the polarity of the currents i9U, i9V, and i9W becomes negative.

[0070] Furthermore, in the following, the switching element targeted for zero-voltage soft switching (first switching element 1 or second switching element 2) will also be referred to as the target switching element.

[0071] The following describes the basic zero-voltage soft switching operation of each of the multiple first switching elements 1 and the multiple second switching elements 2 with reference to Figures 1, 10 to 14. The basic operation is the operation when the control device 51 determines that the difference Δd between the duty cycle command values ​​of any two-phase combination of the three-phase duty cycle command values ​​du, dv, and dw is greater than or equal to a predetermined threshold Δdth, and is the operation when resonant current does not flow simultaneously through two or more of the multiple switches 8 to the resonant inductor L1. After describing the basic operation, the shift operation when the control device 51 has previously determined that the difference Δd between the duty cycle command values ​​of any two-phase combination of the three-phase duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth will be described. If the control device 51 has previously determined that the difference Δd between the two-phase duty cycle command values ​​du and dv is greater than or equal to a predetermined threshold Δdth, it will not perform a shift operation and will perform the basic operation.

[0072] (3.1) Basic Operation In the power converter 100, when the target switching element is the first switching element 1 (hereinafter also referred to as the target first switching element 1), and the polarity of the load current flowing to the AC terminal 41 connected to the target first switching element 1 is positive, the signal generation circuit 52 turns on the third switching element 6 corresponding to the target first switching element 1. As a result, the power converter 100 causes the resonant inductor L1 and the resonant capacitor 9 connected to the target first switching element 1 to resonate, charging the resonant capacitor 9 from the regenerative capacitor 15, and setting the voltage across the target first switching element 1 to zero. As a result, the power converter 100 can achieve zero-voltage soft switching of the target first switching element 1.

[0073] Furthermore, in the power converter 100, if the target switching element is the second switching element 2 (hereinafter also referred to as the target second switching element 2), and the polarity of the load current flowing to the AC terminal 41 connected to the target second switching element 2 is negative, the signal generation circuit 52 turns on the fourth switching element 7 corresponding to the target second switching element 2. As a result, the power converter 100 causes the resonant capacitor 9 and the resonant inductor L1 connected to the target second switching element 2 to resonate, causing the resonant capacitor 9 to discharge and reducing the voltage across the target second switching element 2 to zero. As a result, the power converter 100 can achieve zero-voltage soft switching of the target second switching element 2.

[0074] When the control device 51 sets a second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time) to the first dead time period Td1 by shortening the high-level period of the second PWM signal to the second switching element 2.

[0075] For example, when the control device 51 sets a second dead time period Td2 for the switching circuit 10U, as shown in Figure 13, if the polarity of the load current iU is positive, it shortens a predetermined time (additional time Tadu) of the high-level period of the second PWM signal SU2 to the second switching element 2U, thereby adding a predetermined time (additional time Tadu) to the first dead time period Td1.

[0076] Figure 13 shows the case where the target switching element is the first switching element 1U of the switching circuit 10U, illustrating the first PWM signal SU1, the second PWM signal SU2, the control signal SU6, the current iL1 flowing through the resonant inductor L1, the load current iU, and the voltage V1u across the first switching element 1U. In Figure 13, the voltage value of the DC power supply E1 is shown as Vd.

[0077] When the target switching element is the first switching element 1U, in the switching circuit 10U, the voltage V2u across the second switching element 2U (not shown in Figure 13) becomes Vd at time t13, when the second dead time period Td2 immediately preceding the high-level period of the first PWM signal SU1 ends, and the voltage V1u across the first switching element 1U becomes zero at time t13, when the second dead time period Td2 immediately preceding the high-level period of the first PWM signal SU1 ends. Therefore, when the first PWM signal SU1 changes from a low level to a high level at time t13, the first switching element 1U is soft-switched to zero voltage. In the example shown in Figure 13, the current iL1 flowing through the resonant inductor L1 begins to flow from time t11, when the high-level period of the control signal SU6 starts, reaches the same value as the load current iU at time t12, after a predetermined time (additional time Tadu) has elapsed from time t11, reaches the same value as the load current iU at time t13, when the second dead time period Td2 ends, and becomes zero at time t14, after a second predetermined time Tad2, which is the same length as the first predetermined time (additional time Tadu), has elapsed from time t13. In the signal generation circuit 52, at time t11, when the second PWM signal SU2 changes from a high level to a low level, the control signal SU6 changes from a low level to a high level, and at time t14, when the total time of the second dead time period Td2 and a specified time shorter than the second predetermined time Tad2 has elapsed, the control signal SU6 changes from a high level to a low level. The current iL1 flowing between time point t12 and time point t13 is the resonant current (charging current of the resonant capacitor 9U) flowing from the regenerative capacitor 15 through the resonant inductor L1 to the resonant capacitor 9U.

[0078] In the following, the period T01 in which the absolute value of the current iL1 increases from zero to the absolute value of the load current (load current iU in the example of Figure 13) will be referred to as the first period T01, the period T02 in which the absolute value of the current iL1 is greater than the load current (load current iU in the example of Figure 13) will be referred to as the second period T02, and the period T03 in which the absolute value of the current iL1 decreases from the absolute value of the load current (load current iU in the example of Figure 13) to zero will be referred to as the third period T03. In the power converter 100, when the current iL1 increases from zero to iL1 = iU in the first period T01, the system transitions from the first period T01 to the second period T02. In the second period T02, a resonant current flows, and when the PWM signal to the target switching element changes from a low level to a high level, the system transitions from the second period T02 to the third period T03.

[0079] In Figure 13, the first period T01 is the period from time t11 to t12. The length of the first period T01 is the same as the first predetermined time (additional time Tadu). During the first period T01, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the off state, and the third switching element 6U is in the on state. During the first period T01, the current iL1 flows through the path of regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U - AC terminal 41U. Also during the first period T01, the load current iU flows through the path of second diode 5, which is antiparallel connected to the second switching element 2U - AC terminal 41U - AC load RA1.

[0080] In Figure 13, the second period T02 is the period from time t12 to t13. The length of the second period T02 is the same as the length of the resonant half-period. During the second period T02, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the off state, and the third switching element 6U is in the on state. During the second period T02, the current iL1 flows through the path of regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U, and is divided into a current flowing to the AC terminal 41U and a current flowing to the resonant capacitor 9U (resonant current). During the second period T02, the resonant capacitor 9U is charged by the current flowing through the resonant capacitor 9.

[0081] In Figure 13, the third period T03 is the period from time t13 to t14. The length of the third period T03 is the same as the second predetermined time Tad2. During the third period T03, until the predetermined time has elapsed, the first switching element 1U and the third switching element 6U are each in the ON state, and the second switching element 2U and the fourth switching element 7U are each in the OFF state. After the predetermined time has elapsed, the first switching element 1U is in the ON state, and the second switching element 2U, the third switching element 6U, and the fourth switching element 7U are each in the OFF state. Therefore, during the third period T03, until the control signal SU6 changes from a high level to a low level, the current iL1 flows through the path of regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U - connection point 3U - AC terminal 41U. Furthermore, during the third period T03, after the control signal SU6 changes to a low level, the current iL1 flows through the path of the regenerative capacitor 15 - resonant inductor L1 - first clamp diode 13. This reduces the current iL1 to zero. Also during the third period T03, the load current iU flows through the path of the first DC terminal 31 - first switching element 1U - AC terminal 41U - AC load RA1.

[0082] When the control device 51 sets a second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is negative, it adds a predetermined time (additional time Tadu) to the first dead time period Td1 by shortening the high-level period of the first PWM signal to the first switching element 1.

[0083] For example, when the control device 51 sets a second dead time period Td2 for the switching circuit 10U, as shown in Figure 14, if the polarity of the load current iU is negative, it adds a predetermined time (additional time Tadu) to the first dead time period Td1 by shortening a predetermined time (additional time Tadu) of the high-level period of the first PWM signal SU1 to the first switching element 1U.

[0084] Figure 14 shows the case where the target switching element is the second switching element 2U of the switching circuit 10U, illustrating the first PWM signal SU1, the second PWM signal SU2, the control signal SU7, the current iL1 flowing through the resonant inductor L1, the load current iU, and the voltage V2u across the second switching element 2U.

[0085] When the target switching element is the second switching element 2U, in the switching circuit 10U, the voltage V1u across the first switching element 1U (not shown in Figure 14) becomes Vd at time t43, when the second dead time period Td2 ends immediately before the high-level period of the second PWM signal SU2, and the voltage V2u across the second switching element 2U becomes zero at time t43, when the second dead time period Td2 ends. Therefore, when the second PWM signal SU2 changes from a low level to a high level at time t43, the second switching element 2U is soft-switched to zero voltage. In the example shown in Figure 14, the current iL1 flowing through the resonant inductor L1 begins to flow from time t41, when the high-level period of the control signal SU7 starts, becomes equal to the load current iU at time t42, when the additional time Tadu has elapsed, becomes equal to the load current iU at time t43, when the second dead time period Td2 ends, and becomes zero at time t44, when the second predetermined time Tad2, which is the same length as the first predetermined time, has elapsed from time t43. In the signal generation circuit 52, when the first PWM signal SU1 changes from a high level to a low level, the control signal SU7 changes from a low level to a high level. The current iL1 flowing between time t42 and time t43 is the resonant current (discharge current of the resonant capacitor 9U) flowing from the resonant capacitor 9U to the resonant inductor L1.

[0086] In Figure 14, the first period T01 is the period from time t41 to t42. During the first period T01, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in the off state, and the fourth switching element 7U is in the on state. During the first period T01, the current iL1 flows through the path from the AC terminal 41U - diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15. Also during the first period T01, the load current iU flows through the path from the AC load RA1 - AC terminal 41U - first diode 4 which is connected in antiparallel to the first switching element 1U.

[0087] In Figure 14, the second period T02 is the period from time t42 to t43. During the second period T02, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in the off state, and the fourth switching element 7U is in the on state. During the second period T02, the current iL1 flowing through the resonant inductor L1 is the combined current of the current flowing from the AC terminal 41U through the diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15 and the current flowing from the resonant capacitor 9U through the diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15 (resonant current). During the second period T02, the resonant capacitor 9 is discharged.

[0088] In Figure 14, the third period T03 is the period from time t43 to t44. During the third period T03, until the specified time has elapsed, the second switching element 2U and the fourth switching element 7U are each in the ON state, and the first switching element 1U and the third switching element 6U are each in the OFF state. After the specified time has elapsed, the second switching element 2U is turned ON, and the first switching element 1U, the third switching element 6U, and the fourth switching element 7U are each turned OFF. Therefore, during the third period T03, until the control signal SU7 changes from a high level to a low level, the current iL1 flows through the path of AC terminal 41U - connection point 3U - diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15. Also, during the third period T03, after the control signal SU7 changes to a low level, the current iL1 flows through the path of second clamp diode 14 - resonant inductor L1 - regenerative capacitor 15. As a result, the absolute value of the current iL1 is reduced to zero. Also, during the third period T03, the load current iU flows through the path from the AC load RA1 - AC terminal 41U - second switching element 2U - second DC terminal 32.

[0089] The above describes an example of setting the second dead time period Td2 for switching circuit 10U, but the same applies when setting the second dead time period Td2 for switching circuit 10V and switching circuit 10W.

[0090] (3.2) In the shift-operated power converter 100, the duty cycle command values ​​of two of the three phases, du, dv, and dw, approach each other at electrical angles of 60°, and during one cycle of the carrier signal CA1, the time difference between the start of the ON period of each of the two phase switches 8 becomes shorter, and there is a possibility that resonant currents will flow simultaneously through the resonant capacitors 9 of the two switching circuits 10 corresponding to the duty cycle command values ​​of the two phases in the resonant inductor L1.

[0091] For example, in the example shown in Figure 2, if the duty cycle command values ​​du and dv are both 0.75 or close to 0.75, the time difference between the start of the high-level period of the control signal SU6 and the start of the high-level period of the control signal SV6 becomes shorter, and it is possible that the resonant current passing through the resonant capacitor 9U (hereinafter also referred to as the "U-phase resonant current") and the resonant current passing through the resonant capacitor 9V (hereinafter also referred to as the "V-phase resonant current") will flow through the resonant inductor L1 simultaneously. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the U-phase resonant current and the V-phase resonant current is positive.

[0092] Furthermore, in the example shown in Figure 2, if the duty cycle command values ​​dv and dw are both 0.75 or close to 0.75, the time difference between the start of the high-level period of the control signal SV6 and the start of the high-level period of the control signal SW6 becomes shorter, and it is possible that the resonant current of the V phase and the resonant current passing through the resonant capacitor 9W (hereinafter also referred to as the "W phase resonant current") will flow through the resonant inductor L1 simultaneously. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the V phase resonant current and the W phase resonant current is positive.

[0093] Furthermore, in the example shown in Figure 2, if the duty cycle command values ​​dw and du are both 0.75 or close to 0.75, the time difference between the start of the high-level period of the control signal SW6 and the start of the high-level period of the control signal SU6 becomes shorter, and it is possible that the resonant current of the W phase and the resonant current of the U phase will flow simultaneously through the resonant inductor L1. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the resonant current of the W phase and the resonant current of the U phase is positive.

[0094] Furthermore, in the example shown in Figure 2, if the duty cycle command values ​​du and dv are both 0.25 or close to 0.25, the time difference between the start of the high-level period of the control signal SU7 and the start of the high-level period of the control signal SV7 becomes shorter, and it is possible that the resonant current of the U-phase and the resonant current of the V-phase will flow simultaneously through the resonant inductor L1. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the resonant current of the U-phase and the resonant current of the V-phase is negative.

[0095] Furthermore, in the example shown in Figure 2, if the duty cycle command values ​​dv and dw are both 0.25 or close to 0.25, the time difference between the start of the high-level period of the control signal SV7 and the start of the high-level period of the control signal SW7 becomes shorter, and it is possible that the resonant current of the V-phase and the resonant current of the W-phase will flow simultaneously through the resonant inductor L1. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the resonant current of the V-phase and the resonant current of the W-phase is negative.

[0096] Furthermore, in the example shown in Figure 2, if the duty cycle command values ​​dw and du are both 0.25 or close to 0.25, the time difference between the start of the high-level period of the control signal SW7 and the start of the high-level period of the control signal SU7 becomes shorter, and it is possible that the resonant current passing through the resonant capacitor 9W and the resonant current passing through the resonant capacitor 9U will flow through the resonant inductor L1 simultaneously. In this case, with respect to the current iL1 flowing through the resonant inductor L1, the polarity of the resonant current passing through the resonant capacitor 9W and the resonant current passing through the resonant capacitor 9U is negative.

[0097] In the power converter 100, if two-phase current flows simultaneously through the resonant inductor L1 (in other words, if current flows simultaneously through each of the two resonant capacitors 9), the resonant frequency of the resonant circuit including the resonant inductor L1 changes compared to the case where one-phase current flows through the resonant inductor L1, and it may become impossible to achieve zero-voltage soft switching.

[0098] The control device 51 compares predetermined duty cycle command values ​​du, dv, and dw for each cycle of the carrier signal CA1. Here, the control device 51 calculates the difference Δd between the U-phase duty cycle command value du and the V-phase duty cycle command value dv (Δduv = |du - dv|), calculates the difference Δd between the V-phase duty cycle command value dv and the W-phase duty cycle command value dw (Δdvw = |dv - dw|), and calculates the difference Δd between the W-phase duty cycle command value dw and the U-phase duty cycle command value du (Δdwu = |dw - du|).

[0099] The control device 51 determines a common shift amount dcom such that the duty cycle command value of one of the two phases becomes either 100% (1 in this embodiment) or 0% (0 in this embodiment) when the difference Δd between the duty cycle command values ​​of any two of the multiple phases of duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth. The predetermined threshold Δdth is determined to satisfy the first condition, the second condition, and the third condition.

[0100] The first condition includes the case where the resonant current of the U phase and the resonant current of the V phase overlap in the resonant inductor L1 when Δduv is less than a predetermined threshold Δdth, and the condition where the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1 when Δduv is greater than or equal to a predetermined threshold Δdth. The first condition includes the cases where the resonant current of the U phase and the resonant current of the V phase overlap and the cases where they do not overlap in the resonant inductor L1 when Δduv is less than a predetermined threshold Δdth.

[0101] The second condition includes the case where the resonant current of the V phase and the resonant current of the W phase overlap in the resonant inductor L1 when Δdvw is less than a predetermined threshold Δdth, and the condition where the resonant current of the V phase and the resonant current of the W phase do not overlap in the resonant inductor L1 when Δdvw is greater than or equal to a predetermined threshold Δdth. The second condition includes the cases where the resonant current of the V phase and the resonant current of the W phase overlap and the cases where they do not overlap in the resonant inductor L1 when Δdvw is less than a predetermined threshold Δdth.

[0102] The third condition includes the case where the W-phase resonant current and the U-phase resonant current overlap in the resonant inductor L1 when Δdwu is less than a predetermined threshold Δdth, and the condition where the W-phase resonant current and the U-phase resonant current do not overlap in the resonant inductor L1 when Δdwu is greater than or equal to a predetermined threshold Δdth. The third condition includes the cases where the W-phase resonant current and the U-phase resonant current overlap and do not overlap in the resonant inductor L1 when Δdwu is less than a predetermined threshold Δdth.

[0103] The predetermined threshold Δdth is set to a value greater than the maximum value (e.g., 0.16) that satisfies the boundary condition when the two-phase resonant currents overlap in the resonant inductor L1 (e.g., 0.20). More specifically, the predetermined threshold Δdth is set to, for example, 0.20 × |Cmax - Cmin|.

[0104] The control device 51 determines a common shift amount dcom by calculating dcom = Cmax - max{du,dv,dw} if the difference Δd of the duty command values ​​of any two phases of the multi-phase duty command values ​​du,dv,dw is less than a predetermined threshold Δdth, and the values ​​of each of the two phase duty command values ​​for which the difference Δd is less than the predetermined threshold Δdth are greater than 0.5. If the values ​​of each of the two phase duty command values ​​for which the difference Δd is less than the predetermined threshold Δdth are greater than 0.5, the polarity of the load current of the two phases is positive.

[0105] For example, as shown in Figure 3, if the difference Δd between the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase is less than a predetermined threshold Δdth, and the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase are greater than 0.5, and the duty cycle command value du of the U phase is greater than the duty cycle command value dv of the V phase, the control device 51 determines the common shift amount dcom by calculating dcom = Cmax - du. In the example in Figure 3, the duty cycle command value dw of the W phase is less than 0.5.

[0106] Figure 3 illustrates the timing chart when the control device 51 has determined in advance that the difference Δd between the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase is less than a predetermined threshold Δdth, and that the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase are greater than 0.5. Here, Figure 3 illustrates the timing chart of the three phase duty cycle command values ​​du, dv, dw before the shift, the first PWM signal SU1, the second PWM signal SU2, the first PWM signal SV1, the second PWM signal SV2, the first PWM signal SW1, the second PWM signal SW2, the control signals SU6, SU7, SV6, SV7, SW6, SW7, the current iL1, the line voltage Vuv between the U phase and the V phase, and the load current iU of the U phase. In Figure 3, the current iL1 is shown separately from the U-phase and V-phase resonant currents, which are estimated when no shift operation is performed, and which partially overlap with each other.

[0107] As shown in Figure 4, the control device 51 shifts each of the multi-phase duty command values ​​du, dv, and dw by a common shift amount dcom, and generates multiple first PWM signals SU1, SV1, SW1, multiple second PWM signals SU2, SV2, SW2, and multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 based on the carrier signal CA1 and the shifted three-phase duty command values ​​du, dv, and dw. Figure 4 shows the timing charts for the three phases after the shift: duty cycle command values ​​du, dv, dw, first PWM signal SU1, second PWM signal SU2, first PWM signal SV1, second PWM signal SV2, first PWM signal SW1, second PWM signal SW2, control signals SU6, SU7, SV6, SV7, SW6, SW7, current iL1, line voltage Vuv between the U-phase and V-phase, and load current iU of the U-phase. In Figure 4, the duty cycle command values ​​du, dv, dw of the multiple phases before the shift (see Figure 3), the current iL1 that is estimated to flow through the resonant inductor L1 before the shift (see Figure 3) but does not flow through the resonant inductor L1 after the shift, and the line voltage Vuv estimated before the shift (see Figure 3) are shown with dashed lines.

[0108] When the duty cycle command value du after the shift is 1, the control device 51 generates a first PWM signal SU1 that is high level for the entire duration of one cycle of the carrier signal CA1, and generates a second PWM signal SU2 that is low level for the entire duration of one cycle of the carrier signal CA1.

[0109] As can be seen from the waveform of current iL1 in Figure 3 and the waveform of current iL1 in Figure 4, in the power converter 100, if the control device 51 determines in advance that the difference Δd between the two-phase duty command values ​​du and dv is less than a predetermined threshold Δdth, it performs a shift operation, so that the first switching element 1U is turned on and the second switching element 2U is turned off for one period of the carrier signal CA1, and the resonant current of the U phase does not flow during the high-level period of the control signal SU6. As a result, in the power converter 100C, the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1, so the switching of the first switching element 1V becomes zero-voltage soft switching.

[0110] Furthermore, as can be seen from Figures 3 and 4, in the power converter 100 according to Embodiment 1, the fluctuation of the line voltage Vuv between the U phase and the V phase is small, and it is possible to reduce current distortion compared to the power converter of Patent Document 1.

[0111] Furthermore, as can be seen from Figures 3 and 4, in the power converter 100, the first switching element 1U and the second switching element 2U are not switched within one cycle of the carrier signal CA1, so the switching loss can be reduced to two-thirds.

[0112] Furthermore, as shown in Figure 5, for example, if the difference Δd between the duty command value du of the U phase and the duty command value dv of the V phase is less than a predetermined threshold Δdth, and the duty command value du of the U phase and the duty command value dv of the V phase are greater than 0.5, and the duty command value dv of the V phase is greater than the duty command value du of the U phase, the control device 51 determines the common shift amount dcom by calculating dcom = Cmax - dv. In the example in Figure 5, the duty command value dw of the W phase is less than 0.5.

[0113] As shown in Figure 6, the control device 51 shifts each of the multi-phase duty cycle command values ​​du, dv, and dw by a common shift amount dcom, and generates multiple first PWM signals SU1, SV1, SW1, multiple second PWM signals SU2, SV2, SW2, and multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 based on the carrier signal CA1 and the shifted three-phase duty cycle command values ​​du, dv, and dw. Note that the interpretation of Figure 6 is the same as that of Figure 4. In Figure 6, the multi-phase duty cycle command values ​​du, dv, and dw before the shift (see Figure 5), the current iL1 that is estimated to flow through the resonant inductor L1 before the shift (see Figure 5) but does not flow through the resonant inductor L1 after the shift, and the line voltage Vuv estimated before the shift (see Figure 5) are shown by dashed lines.

[0114] When the duty cycle command value dv after the shift is 1, the control device 51 generates a first PWM signal SV1 that is high level for the entire duration of one cycle of the carrier signal CA1, and generates a second PWM signal SV2 that is low level for the entire duration of one cycle of the carrier signal CA1.

[0115] As can be seen from the waveform of current iL1 in Figure 5 and the waveform of current iL1 in Figure 6, in the power converter 100, if the control device 51 determines in advance that the difference Δd between the two-phase duty command values ​​du and dv is less than a predetermined threshold Δdth, it performs a shift operation, so that the first switching element 1V is turned on and the second switching element 2V is turned off for one cycle of the carrier signal CA1, and the resonant current of the V phase does not flow during the high-level period of the control signal SV6. As a result, in the power converter 100, the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1, so the switching of the first switching element 1U becomes zero-voltage soft switching.

[0116] Furthermore, as can be seen from Figures 5 and 6, the fluctuation of the line voltage Vuv between the U-phase and V-phase is small, making it possible to reduce current distortion compared to the power conversion device of Patent Document 1.

[0117] Furthermore, as can be seen from Figures 5 and 6, in the power converter 100, the first switching element 1V and the second switching element 2V are not switched within one cycle of the carrier signal CA1, so the switching loss can be reduced to two-thirds.

[0118] The control device 51 determines a common shift amount dcom by calculating dcom = |Cmin - min{du,dv,dw}| if the difference Δd of the duty command values ​​of any two of the multiphase duty command values ​​du,dv,dw is less than a predetermined threshold Δdth, and the values ​​of each of the two phase duty command values ​​for which the difference Δd is less than the predetermined threshold Δdth are less than 0.5 (or if the polarity of the two phase load currents is negative). If the values ​​of each of the two phase duty command values ​​for which the difference Δd is less than the predetermined threshold Δdth are less than 0.5, the polarity of the two phase load currents is negative.

[0119] Furthermore, as shown in Figure 7, for example, if the difference Δd between the duty command value du of the U phase and the duty command value dv of the V phase is less than a predetermined threshold Δdth, and the duty command value du of the U phase and the duty command value dv of the V phase are both less than 0.5, and the duty command value du of the U phase is less than the duty command value dv of the V phase, the control device 51 determines the common shift amount dcom by calculating dcom = |Cmin - du|. In the example in Figure 7, the duty command value dw of the W phase is greater than 0.5.

[0120] Figure 7 illustrates the timing chart when the control device 51 has determined in advance that the difference Δd between the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase is less than a predetermined threshold Δdth, and that the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase are less than 0.5. Here, Figure 7 illustrates the timing chart of the three phase duty cycle command values ​​du, dv, dw before the shift, the first PWM signal SU1, the second PWM signal SU2, the first PWM signal SV1, the second PWM signal SV2, the first PWM signal SW1, the second PWM signal SW2, the control signals SU6, SU7, SV6, SV7, SW6, SW7, the current iL1, the line voltage Vuv between the U phase and the V phase, and the load current iU of the U phase.

[0121] As shown in Figure 8, the control device 51 shifts each of the multi-phase duty command values ​​du, dv, and dw by a common shift amount dcom, and generates multiple first PWM signals SU1, SV1, SW1, multiple second PWM signals SU2, SV2, SW2, and multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 based on the carrier signal CA1 and the shifted three-phase duty command values ​​du, dv, and dw. Figure 8 shows the timing charts for the three phases after the shift: duty cycle command values ​​du, dv, dw, first PWM signal SU1, second PWM signal SU2, first PWM signal SV1, second PWM signal SV2, first PWM signal SW1, second PWM signal SW2, control signals SU6, SU7, SV6, SV7, SW6, SW7, current iL1, line voltage Vuv between the U-phase and V-phase, and load current iU of the U-phase. In Figure 8, the duty cycle command values ​​du, dv, dw of the multiple phases before the shift (see Figure 7), the current iL1 that is estimated to flow through the resonant inductor L1 before the shift (see Figure 7) but does not flow through the resonant inductor L1 after the shift, and the line voltage Vuv estimated before the shift (see Figure 7) are shown with dashed lines.

[0122] When the duty cycle command value du after the shift is 0, the control device 51 generates a first PWM signal SU1 that is low level for the entire duration of one cycle of the carrier signal CA1, and generates a second PWM signal SU2 that is high level for the entire duration of one cycle of the carrier signal CA1.

[0123] As can be seen from the waveform of current iL1 in Figure 7 and the waveform of current iL1 in Figure 8, in the power converter 100, if the control device 51 determines in advance that the difference Δd between the two-phase duty command values ​​du and dv is less than a predetermined threshold Δdth, it performs a shift operation, so that the first switching element 1U is turned off and the second switching element 2U is turned on for one cycle of the carrier signal CA1, and the resonant current of the U phase does not flow during the high-level period of the control signal SU7. As a result, in the power converter 100, the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1, so the switching of the second switching element 2V becomes zero-voltage soft switching.

[0124] Furthermore, as can be seen from Figures 7 and 8, the fluctuation of the line voltage Vuv between the U-phase and V-phase is small, making it possible to reduce current distortion compared to the power conversion device of Patent Document 1.

[0125] Furthermore, as can be seen from Figures 7 and 8, in the power converter 100, the first switching element 1U and the second switching element 2U are not switched within one cycle of the carrier signal CA1, so the switching loss can be reduced to two-thirds.

[0126] (4) Advantages The power conversion device 100 according to Embodiment 1 includes a first DC terminal 31 and a second DC terminal 32, a power conversion circuit 11, a plurality of AC terminals 41, a plurality of switches 8, a plurality of resonant capacitors 9, a resonant inductor L1, a regenerative capacitor 15, a control device 51, and a signal generation circuit 52. The power conversion circuit 11 has a plurality of first switching elements 1 and a plurality of second switching elements 2. In the power conversion circuit 11, a plurality of switching circuits 10, each in which a plurality of first switching elements 1 and a plurality of second switching elements 2 are connected in series in a one-to-one relationship, are connected in parallel to each other. The control device 51 generates a plurality of first PWM signals SU1, SV1, SW1 for controlling the plurality of first switching elements 1 and a plurality of second PWM signals SU2, SV2, SW2 for controlling the plurality of second switching elements 2, based on a plurality of phase duty command values ​​du, dv, dw corresponding to a one-to-one relationship between the plurality of switching circuits 10. The signal generation circuit 52 provides control signals SU6, SU7, SV6, SV7, SW6, SW7 to each of the plurality of switches 8, which change potential between high level and low level. The control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10, which is a predetermined first dead time period Td1 plus a predetermined time, so that the on periods of the first switching element 1 and the second switching element 2 do not overlap between the high-level period of the first PWM signal to the first switching element 1 and the high-level period of the second PWM signal to the second switching element 2. The predetermined time is determined according to the current value of the load current, the inductance of the resonant inductor L1 and the voltage value of the regenerative capacitor 15. For each of the plurality of switches 8, the signal generation circuit 52 generates a control signal that has a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10 among the plurality of switching circuits 10.The control device 51 determines a common shift amount dcom when the difference Δd between the duty cycle command values ​​of any two of the multi-phase duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth, such that the duty cycle command value of one of the two phases corresponds to a value equivalent to 100% or 0%, and shifts each of the multi-phase duty cycle command values ​​du, dv, and dw by the common shift amount dcom to generate multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2.

[0127] With the above configuration, zero-voltage soft switching can be performed without the control device 51 directly controlling the multiple switches 8 for zero-voltage soft switching, and current distortion can be reduced. More specifically, the control device 51 does not need to generate control signals to directly control the multiple switches 8 for zero-voltage soft switching, and zero-voltage soft switching of each of the multiple first switching elements 1 and the multiple second switching elements 2 can be realized without the control device 51 directly controlling the multiple switches 8. Furthermore, with the above configuration, the control device 51 does not need to generate and output multiple control signals SU6, SU7, SV6, SV7, SW6, SW7, so the control device 51 can be simplified, for example, an increase in the number of control ports of the microcomputer included in the control device 51 can be suppressed, and the size of the control device 51 can be suppressed. Furthermore, with the above configuration, when the difference Δd between the duty cycle command values ​​of any two of the multi-phase duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth, the control device 51 determines a common shift amount dcom such that the duty cycle command value of one of the two phases corresponds to a value equivalent to 100% or 0%, and shifts each of the multi-phase duty cycle command values ​​du, dv, and dw by the common shift amount dcom to generate multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2. This makes it possible to reduce current distortion and switch losses.

[0128] Furthermore, in the power conversion device 100 according to Embodiment 1, when the control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time) to the first dead time period Td1 by shortening the high-level period of the second PWM signal to the second switching element 2. Also, when the control device 51 sets a second dead time period Td2 for each of the plurality of switching circuits 10, if the polarity of the load current is negative, it adds a predetermined time (additional time) to the first dead time period Td1 by shortening the high-level period of the first PWM signal to the first switching element 1.

[0129] With the above configuration, it becomes possible to achieve zero-voltage soft switching while further reducing dead time loss and dead time error.

[0130] (Embodiment 2) The power converter 100A according to Embodiment 2 will be described below with reference to Figure 15.

[0131] (1) The power converter 100A according to Embodiment 2 differs from the power converter 100 according to Embodiment 1 in that the fifth terminal 153 of the regenerative capacitor 15 is connected to the first DC terminal 31 instead of the second DC terminal 32. With respect to the power converter 100A according to Embodiment 2, the same reference numerals are used for components that are the same as those in the power converter 100 according to Embodiment 1, and their descriptions are omitted.

[0132] (2) In the power converter 100A according to the second operating embodiment, the operation of the control device 51 and the signal generation circuit 52 is the same as the operation of the control device 51 and the signal generation circuit 52 in the first embodiment, so the explanation is omitted.

[0133] (3) Advantages The power converter 100A according to Embodiment 2, like the power converter 100 according to Embodiment 1, is capable of performing zero-voltage soft switching without the control device 51 directly controlling the multiple switches 8 for zero-voltage soft switching, and is also capable of reducing current distortion.

[0134] (Embodiment 3) The power converter 100B according to Embodiment 3 will be described with reference to Figures 16 to 20. With respect to the power converter 100B according to Embodiment 3, components that are the same as those in the power converter 100 according to Embodiment 1 (see Figure 1) are denoted by the same reference numerals and their description is omitted.

[0135] (1) The configured power converter 100B differs from the power converter 100 in that, as shown in Figure 16, it is equipped with a control device 51B instead of the control device 51 of the power converter 100.

[0136] In the power converter 100B, the control device 51B generates multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2, similar to the control device 51, to control multiple first switching elements 1 and multiple second switching elements 2.

[0137] When the control device 51B sets a second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, it lengthens the first dead time period Td1 by a predetermined time (additional time Tadu in the example of Figure 17) by advancing the end time of the high-level period of the second PWM signal to the second switching element 2 and delaying the start time of the high-level period of the first PWM signal to the first switching element 1. If the time for advancing the end time of the high-level period of the second PWM signal to the second switching element 2 is Ta21 (see Figure 17), and the time for delaying the start time of the high-level period of the first PWM signal to the first switching element 1 is Ta11 (see Figure 17), then the predetermined time (additional time) is Ta11 + Ta21. In the example of Figure 17, Ta11 = Ta21 = Tadu / 2.

[0138] When the control device 51B sets a second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is negative, it lengthens the first dead time period Td1 by a predetermined time (additional time Tadu in the example of Figure 18) by advancing the end time of the high-level period of the first PWM signal to the first switching element 1 and delaying the start time of the high-level period of the second PWM signal to the second switching element 2. If the time for advancing the end time of the high-level period of the first PWM signal to the first switching element 1 is Ta12 (see Figure 18), and the time for delaying the start time of the high-level period of the second PWM signal to the second switching element 2 is Ta22 (see Figure 18), then the predetermined time (additional time) is Ta12 + Ta22. In the example of Figure 18, Ta12 = Ta22 = Tadu / 2.

[0139] The signal generation circuit 52 of this embodiment, like the signal generation circuit 52 of Embodiment 1, generates a control signal for each of the multiple switches 8 using a first PWM signal to the first switching element 1 and a second PWM signal to the second switching element 2 of the corresponding switching circuit 10 among the multiple switching circuits 10.

[0140] The control device 51B, like the control device 51, generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2 based on three-phase duty command values ​​du, dv, dw (see Figure 2) of a three-phase modulation scheme. The control device 51B generates three-phase duty command values ​​du, dv, dw based on information regarding the state of the AC load RA1. If the AC load RA1 is a three-phase servo motor, the information regarding the state of the AC load RA1 includes, for example, detected values ​​from a plurality of current sensors that detect the output currents (hereinafter also referred to as load currents) iU, iV, iW flowing through the U-phase terminal, V-phase terminal, and W-phase terminal, respectively, of the AC load RA1.

[0141] The control device 51B generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2, for each period of the triangular wave carrier signal CA1, using the three-phase duty command values ​​du, dv, dw and the carrier signal CA1. Figure 19 shows the timing chart estimated before the shift operation when the control device 51B performs the shift operation described later, and Figure 20 corresponds to Figure 19 and shows the timing chart when the shift operation is performed.

[0142] The control device 51B generates a first PWM signal SU1 and a second PWM signal SU2 to be supplied to the first switching element 1U and the second switching element 2U, respectively, based on the carrier signal CA1 and the duty cycle command value du. The control device 51B also generates a first PWM signal SV1 and a second PWM signal SV2 to be supplied to the first switching element 1V and the second switching element 2V, respectively, based on the carrier signal CA1 and the duty cycle command value dv of the V phase. The control device 51B also generates a first PWM signal SW1 and a second PWM signal SW2 to be supplied to the first switching element 1W and the second switching element 2W, respectively, based on the carrier signal CA1 and the duty cycle command value dw of the W phase. In this embodiment, the control device 51B sets the maximum value of the carrier signal CA1 to 1 and the minimum value to 0. Furthermore, the control device 51B sets the maximum value (equivalent to 100%) of each of the three-phase duty cycle command values ​​du, dv, and dw to 1, and the minimum value (equivalent to 0%) to 0.

[0143] The control device 51B, like the control device 51, generates a first PWM signal SU1 by comparing the duty cycle command value du with the carrier signal CA1. The control device 51B also generates a second PWM signal SU2 by inverting the first PWM signal SU1. Furthermore, the control device 51B sets a first dead time period Td1 (see Figures 17 and 19) between the high-level period of the first PWM signal SU1 and the high-level period of the second PWM signal SU2 so that the on-period of the first switching element 1U and the on-period of the second switching element 2U do not overlap.

[0144] The control device 51B, like the control device 51, generates a first PWM signal SV1 by comparing the duty cycle command value dv with the carrier signal CA1. The control device 51B also generates a second PWM signal SV2 by inverting the first PWM signal SV1. Furthermore, the control device 51B sets a first dead time period Td1 (see Figure 19) between the high-level period of the first PWM signal SV1 and the high-level period of the second PWM signal SV2 so that the on-period of the first switching element 1V and the on-period of the second switching element 2V do not overlap.

[0145] The control device 51B, like the control device 51, generates a first PWM signal SW1 by comparing the duty cycle command value dw with the carrier signal CA1. The control device 51B also generates a second PWM signal SW2 by inverting the first PWM signal SW1. Furthermore, the control device 51B sets a first dead time period Td1 (see Figure 19) between the high-level period of the first PWM signal SW1 and the high-level period of the second PWM signal SW2 so that the on-period of the first switching element 1W and the on-period of the second switching element 2W do not overlap.

[0146] Similar to the control device 51, the control device 51B determines a common shift amount dcom when the difference Δd between the duty command values ​​of any two of the multi-phase duty command values ​​du, dv, and dw is less than a predetermined threshold Δdth, such that the duty command value of one of the two phases corresponds to a value equivalent to 100% or 0%, and shifts each of the multi-phase duty command values ​​du, dv, and dw by the common shift amount dcom, and generates multiple first PWM signals SU1, SV1, SW1, multiple second PWM signals SU2, SV2, SW2, and multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 based on the shifted duty command values ​​du, dv, and dw.

[0147] Similar to the control device 51, the control device 51B sets the maximum value Cmax of the carrier signal CA1 to 1, the minimum value Cmin of the carrier signal CA1 to 0, and sets the maximum value of each of the three-phase duty command values ​​du, dv, and dw to 1 and the minimum value to 0.

[0148] The control device 51B, similar to the control device 51, for example, for each period of the carrier signal CA1, if the difference Δd between the duty cycle command values ​​of any two of the multi-phase duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth, it calculates the common shift amount dcom by performing the calculation dcom = Cmax - max{du, dv, dw} or dcom = |Cmin - min{du, dv, dw}|. The control device 51 calculates the common shift amount dcom by performing the calculation dcom = Cmax - max{du, dv, dw} if the difference Δd between the duty cycle command values ​​of any two of the multi-phase duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth, and each of the two duty cycle command values ​​is greater than (Cmax - Cmin) / 2 = 0.5. The control device 51B determines the common shift amount dcom by calculating dcom = |Cmin - min{du, dv, dw}| if the difference Δd between the duty cycle command values ​​of two phases of the multi-phase duty cycle command values ​​du, dv, dw is less than a predetermined threshold Δdth, and each of the two phase duty cycle command values ​​is less than (Cmax - Cmin) / 2 = 0.5.

[0149] Furthermore, the control device 51B shifts the three-phase duty command values ​​du, dv, and dw by a common shift amount dcom so that the duty command value of one of the two-phase duty command values ​​becomes 1 or 0, and generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2 based on the carrier signal CA1 and the shifted three-phase duty command values ​​du, dv, and dw. When shifting the three-phase duty command values ​​du, dv, and dw by a common shift amount dcom so that the duty command value of one of the two-phase duty command values ​​becomes 1, the common shift amount dcom is added to each of the three-phase duty command values ​​du, dv, and dw. To shift the duty cycle values ​​of the three phases du, dv, and dw by a common shift amount dcom so that the duty cycle value of one of the two phases becomes 0, subtract the common shift amount dcom from each of the three phase duty cycle values ​​du, dv, and dw.

[0150] (2) Operation (2.1) Basic Operation Figure 17 shows the case where the target switching element is the first switching element 1U of the switching circuit 10U, illustrating the first PWM signal SU1, the second PWM signal SU2, the control signal SU6, the current iL1 flowing through the resonant inductor L1, and the voltage V1u across the first switching element 1U. Also in Figure 17, the voltage value of the DC power supply E1 is shown as Vd.

[0151] When the target switching element is the first switching element 1U, in the switching circuit 10U, the voltage V2u across the second switching element 2U (not shown in Figure 17) becomes Vd at time t13, when the second dead time period Td2 immediately preceding the high-level period of the first PWM signal SU1 ends, and the voltage V1u across the first switching element 1U becomes zero at time t13, when the second dead time period Td2 immediately preceding the high-level period of the first PWM signal SU1 ends. Therefore, when the first PWM signal SU1 changes from a low level to a high level at time t13, the first switching element 1U is soft-switched to zero voltage. In the example shown in Figure 17, the current iL1 flowing through the resonant inductor L1 begins to flow from time t11, when the high-level period of the control signal SU6 starts, reaches the same value as the load current iU at time t12, when a time equal to the length of the additional time Tadu has elapsed, reaches the same value as the load current iU at time t13, when the second dead time period Td2 ends, and becomes zero at time t14, when the third period T03 has elapsed from time t13. In the signal generation circuit 52, at time t11, when the second PWM signal SU2 changes from a high level to a low level, the control signal SU6 changes from a low level to a high level. The current iL1 flowing between time t12 and time t13 is the resonant current (charging current of the resonant capacitor 9U) flowing from the regenerative capacitor 15 through the resonant inductor L1 to the resonant capacitor 9U.

[0152] During the first period T01, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the off state, and the third switching element 6U is in the on state. During the first period T01, the current iL1 flows through the path from the regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U - AC terminal 41U. Also during the first period T01, the load current iU flows through the path from the second diode 5, which is antiparallel connected to the second switching element 2U - AC terminal 41U - AC load RA1.

[0153] During the second period T02, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the off state, while the third switching element 6U is in the on state. During the second period T02, the current iL1 flows through the path from the regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U, and is divided into a current flowing to the AC terminal 41U and a current flowing to the resonant capacitor 9U (resonant current). During the second period T02, the resonant capacitor 9U is charged by the current flowing through the resonant capacitor 9.

[0154] During the third period T03, the first switching element 1U and the third switching element 6U are both in the ON state, while the second switching element 2U and the fourth switching element 7U are both in the OFF state. During the third period T03, the current iL1 flows through the path from the regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U - AC terminal 41U. This reduces the current iL1 to zero. Also during the third period T03, the load current iU flows through the path from the first DC terminal 31 - first switching element 1U - AC terminal 41U - AC load RA1.

[0155] Figure 18 shows the case where the target switching element is the second switching element 2U of the switching circuit 10U, illustrating the first PWM signal SU1, the second PWM signal SU2, the control signal SU7, the current iL1 flowing through the resonant inductor L1, and the voltage V2u across the second switching element 2U. In Figure 18, the voltage value of the DC power supply E1 is shown as Vd.

[0156] When the target switching element is the second switching element 2U, in the switching circuit 10U, the voltage V1u across the first switching element 1U (not shown in Figure 18) becomes Vd at time t43, when the second dead time period Td2 ends immediately before the high-level period of the second PWM signal SU2, and the voltage V2u across the second switching element 2U becomes zero at time t43, when the second dead time period Td2 ends. Therefore, when the second PWM signal SU2 changes from a low level to a high level at time t43, the second switching element 2U is soft-switched to zero voltage.

[0157] In the example shown in Figure 18, the current iL1 flowing through the resonant inductor L1 begins to flow from time t41, when the high-level period of the control signal SU7 starts, reaches the same value as the load current iU at time t42, after a predetermined time (additional time Tadu) has elapsed, reaches the same value as the load current iU at time t43, when the second dead time period Td2 ends, and becomes zero at time t44, after a predetermined time (additional time Tadu) has elapsed from time t43. In the signal generation circuit 52, the control signal SU7 changes from a low level to a high level at the same time that the first PWM signal SU1 changes from a high level to a low level. The current iL1 flowing between time t42 and time t43 is the resonant current (discharge current of the resonant capacitor 9U) flowing from the resonant capacitor 9U to the resonant inductor L1.

[0158] In Figure 18, the first period T01 is the period from time t41 to t42. During the first period T01, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in the off state, and the fourth switching element 7U is in the on state. During the first period T01, the current iL1 flows through the path from the AC terminal 41U - diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15. Also during the first period T01, the load current iU flows through the path from the AC load RA1 - AC terminal 41U - first diode 4 which is connected in antiparallel to the first switching element 1U.

[0159] In Figure 18, the second period T02 is the period from time t42 to t43. During the second period T02, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in the off state, and the fourth switching element 7U is in the on state. During the second period T02, the current iL1 flowing through the resonant inductor L1 is the combined current of the current flowing from the AC terminal 41U through the diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15 and the current flowing from the resonant capacitor 9U through the diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15 (resonant current). During the second period T02, the resonant capacitor 9 is discharged.

[0160] In Figure 18, the third period T03 is the period from time t43 to t44. During the third period T03, the second switching element 2U and the fourth switching element 7U are both in the ON state, and the first switching element 1U and the third switching element 6U are both in the OFF state. During the third period T03, the current iL1 flows through the path from the AC terminal 41U - connection point 3U - diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15. As a result, the absolute value of the current iL1 is reduced to zero. Also during the third period T03, the load current iU flows through the path from the AC load RA1 - AC terminal 41U - second switching element 2U - second DC terminal 32.

[0161] The above describes an example of when the control device 51B sets the second dead time period Td2 for the switching circuit 10U, but the same applies when setting the second dead time period Td2 for the switching circuit 10V and the switching circuit 10W.

[0162] (2.2) The shift operation of the shift operation control device 51B is the same as the shift operation of the control device 51 in Embodiment 1, so the explanation will be omitted as appropriate.

[0163] For example, as shown in Figure 19, if the difference Δd between the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase is less than a predetermined threshold, and the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase are greater than 0.5, and the duty cycle command value du of the U phase is greater than the duty cycle command value dv of the V phase, the control device 51B determines the common shift amount dcom by calculating dcom = Cmax - du. In the example in Figure 19, the duty cycle command value dw of the W phase is less than 0.5.

[0164] Figure 19 shows a timing chart when the control device 51B has determined in advance that the difference Δd between the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase is less than a predetermined threshold, and that the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase are greater than 0.5. Here, Figure 19 shows the timing chart of the duty cycle command values ​​du, dv, dw of the three phases before the shift, the first PWM signal SU1, the second PWM signal SU2, the first PWM signal SV1, the second PWM signal SV2, the first PWM signal SW1, the second PWM signal SW2, the control signals SU6, SU7, SV6, SV7, SW6, SW7, the current iL1, the line voltage Vuv between the U phase and the V phase, and the load current iU of the U phase. The way to read Figure 19 is the same as the way to read Figure 3.

[0165] As shown in Figure 20, the control device 51B shifts each of the multi-phase duty command values ​​du, dv, and dw by a common shift amount dcom, and generates multiple first PWM signals SU1, SV1, SW1, multiple second PWM signals SU2, SV2, SW2, and multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 based on the carrier signal CA1 and the shifted three-phase duty command values ​​du, dv, and dw. Figure 20 shows the timing charts for the three phases after the shift: duty cycle command values ​​du, dv, dw, first PWM signal SU1, second PWM signal SU2, first PWM signal SV1, second PWM signal SV2, first PWM signal SW1, second PWM signal SW2, control signals SU6, SU7, SV6, SV7, SW6, SW7, current iL1, line voltage Vuv between the U-phase and V-phase, and load current iU of the U-phase. In Figure 20, the duty cycle command values ​​du, dv, dw of the multiple phases before the shift (see Figure 19), the current iL1 that is estimated to flow through the resonant inductor L1 before the shift (see Figure 19) but does not flow through the resonant inductor L1 after the shift, and the line voltage Vuv estimated before the shift (see Figure 19) are shown with dashed lines.

[0166] When the duty cycle command value du after the shift is 1, the control device 51B generates a first PWM signal SU1 that is high level for the entire duration of one cycle of the carrier signal CA1, and generates a second PWM signal SU2 that is low level for the entire duration of one cycle of the carrier signal CA1.

[0167] As can be seen from the waveform of current iL1 in Figure 19 and the waveform of current iL1 in Figure 20, in the power converter 100B, if the control device 51B determines in advance that the difference Δd between the two-phase duty command values ​​du and dv is less than a predetermined threshold Δdth, it performs a shift operation, so that the first switching element 1U is turned on and the second switching element 2U is turned off for one period of the carrier signal CA1, and the resonant current of the U phase does not flow during the high-level period of the control signal SU6. As a result, in the power converter 100B, the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1, so the switching of the first switching element 1V becomes zero-voltage soft switching.

[0168] Furthermore, as can be seen from Figures 19 and 20, in the power converter 100B according to Embodiment 3, the fluctuation of the line voltage Vuv between the U phase and the V phase is small, and it is possible to reduce current distortion compared to the power converter of Patent Document 1.

[0169] Furthermore, as can be seen from Figures 19 and 20, in the power converter 100B, the first switching element 1U and the second switching element 2U are not switched within one cycle of the carrier signal CA1, so the switching loss can be reduced to two-thirds.

[0170] (3) Advantages The power converter 100B according to Embodiment 3, like the power converter 100 according to Embodiment 1, is capable of performing zero-voltage soft switching without the control device 51B directly controlling the multiple switches 8 for zero-voltage soft switching, and is also capable of reducing current distortion.

[0171] Furthermore, in the power conversion device 100B according to Embodiment 3, when the control device 51B sets a second dead time period Td2 for each of the plurality of switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time) to the first dead time period Td1 by advancing the end time of the high-level period of the second PWM signal to the second switching element 2 and delaying the start time of the high-level period of the first PWM signal to the first switching element 1. If the polarity of the load current is negative, it adds a predetermined time (additional time) to the first dead time period Td1 by advancing the end time of the high-level period of the first PWM signal to the first switching element 1 and delaying the start time of the high-level period of the second PWM signal to the second switching element 2.

[0172] With the above configuration, it is possible to achieve zero-voltage soft switching while reducing dead-time loss and dead-time error.

[0173] (Embodiment 4) The power converter 100C according to Embodiment 4 will be described with reference to Figures 21 to 25. With respect to the power converter 100C according to Embodiment 4, components that are the same as those in the power converter 100 according to Embodiment 1 (see Figure 1) are denoted by the same reference numerals and their description is omitted.

[0174] (1) The configured power converter 100C differs from the power converter 100 in that, as shown in Figure 21, it is equipped with a control device 51C instead of the control device 51 of the power converter 100.

[0175] In the power converter 100C, the control device 51C generates multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2, similar to the control device 51, to control multiple first switching elements 1 and multiple second switching elements 2.

[0176] When the control device 51C sets a second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is positive, it shortens the high-level period of the first PWM signal to the first switching element 1 to add a predetermined time (additional time) to the first dead time period Td1.

[0177] When the control device 51C sets a second dead time period Td2 for each of the multiple switching circuits 10, if the polarity of the load current is negative, it shortens the high-level period of the second PWM signal to the second switching element 2 to add a predetermined time (additional time) to the first dead time period Td1.

[0178] The signal generation circuit 52 of this embodiment, like the signal generation circuit 52 of Embodiment 1, generates a control signal for each of the multiple switches 8 using a first PWM signal to the first switching element 1 and a second PWM signal to the second switching element 2 of the corresponding switching circuit 10 among the multiple switching circuits 10.

[0179] The control device 51C, like the control device 51, generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2 based on three-phase duty command values ​​du, dv, dw (see Figure 2) of a three-phase modulation scheme. The control device 51C generates three-phase duty command values ​​du, dv, dw based on information regarding the state of the AC load RA1. If the AC load RA1 is a three-phase servo motor, the information regarding the state of the AC load RA1 includes, for example, detected values ​​from a plurality of current sensors that detect the output currents (hereinafter also referred to as load currents) iU, iV, iW flowing through the U-phase terminal, V-phase terminal, and W-phase terminal, respectively, of the AC load RA1.

[0180] The control device 51C generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2, for each period of the triangular wave carrier signal CA1, using the three-phase duty command values ​​du, dv, dw and the carrier signal CA1. Figure 24 shows the timing chart estimated before the shift operation when performing the shift operation described later, and Figure 25 corresponds to Figure 24 and shows the timing chart when the shift operation is performed.

[0181] The control device 51C generates a first PWM signal SU1 and a second PWM signal SU2 to be supplied to the first switching element 1U and the second switching element 2U, respectively, based on the carrier signal CA1 and the duty cycle command value du. The control device 51C also generates a first PWM signal SV1 and a second PWM signal SV2 to be supplied to the first switching element 1V and the second switching element 2V, respectively, based on the carrier signal CA1 and the duty cycle command value dv of the V phase. The control device 51C also generates a first PWM signal SW1 and a second PWM signal SW2 to be supplied to the first switching element 1W and the second switching element 2W, respectively, based on the carrier signal CA1 and the duty cycle command value dw of the W phase. In this embodiment, the control device 51C sets the maximum value of the carrier signal CA1 to 1 and the minimum value to 0. Furthermore, the control device 51C sets the maximum value (equivalent to 100%) of each of the three-phase duty cycle command values ​​du, dv, and dw to 1, and the minimum value (equivalent to 0%) to 0.

[0182] The control device 51C, like the control device 51, generates a first PWM signal SU1 by comparing the duty cycle command value du with the carrier signal CA1. The control device 51C also generates a second PWM signal SU2 by inverting the first PWM signal SU1. Furthermore, the control device 51C sets a first dead time period Td1 (see Figures 22 and 24) between the high-level period of the first PWM signal SU1 and the high-level period of the second PWM signal SU2 so that the on-period of the first switching element 1U and the on-period of the second switching element 2U do not overlap.

[0183] The control device 51C, like the control device 51, generates a first PWM signal SV1 by comparing the duty cycle command value dv with the carrier signal CA1. The control device 51C also generates a second PWM signal SV2 by inverting the first PWM signal SV1. Furthermore, the control device 51C sets a first dead time period Td1 (see Figure 24) between the high-level period of the first PWM signal SV1 and the high-level period of the second PWM signal SV2 so that the on-period of the first switching element 1V and the on-period of the second switching element 2V do not overlap.

[0184] The control device 51C, like the control device 51, generates a first PWM signal SW1 by comparing the duty cycle command value dw with the carrier signal CA1. The control device 51C also generates a second PWM signal SW2 by inverting the first PWM signal SW1. Furthermore, the control device 51C sets a first dead time period Td1 (see Figure 24) between the high-level period of the first PWM signal SW1 and the high-level period of the second PWM signal SW2 so that the ON period of the first switching element 1W and the ON period of the second switching element 2W do not overlap.

[0185] Similar to the control device 51, the control device 51C determines a common shift amount dcom when the difference Δd between the duty cycle command values ​​of any two of the multi-phase duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth, such that the duty cycle command value of one of the two phases corresponds to a value equivalent to 100% or 0%, and shifts each of the multi-phase duty cycle command values ​​du, dv, and dw by the common shift amount dcom, and generates multiple first PWM signals SU1, SV1, SW1, multiple second PWM signals SU2, SV2, SW2, and multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 based on the shifted duty cycle command values ​​du, dv, and dw.

[0186] Similar to the control device 51, the control device 51C sets the maximum value Cmax of the carrier signal CA1 to 1, the minimum value Cmin of the carrier signal CA1 to 0, and sets the maximum value of each of the three-phase duty command values ​​du, dv, and dw to 1 and the minimum value to 0.

[0187] The control device 51C, similar to the control device 51, for example, for each period of the carrier signal CA1, if the difference Δd between the duty cycle command values ​​of any two of the multi-phase duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth, then calculates the common shift amount dcom by performing the calculation dcom = Cmax - max{du, dv, dw} or dcom = |Cmin - min{du, dv, dw}|. The control device 51 calculates the common shift amount dcom by performing the calculation dcom = Cmax - max{du, dv, dw} if the difference Δd between the duty cycle command values ​​of any two of the multi-phase duty cycle command values ​​du, dv, and dw is less than a predetermined threshold Δdth, and each of the two duty cycle command values ​​is greater than (Cmax - Cmin) / 2 = 0.5. The control device 51C determines the common shift amount dcom by calculating dcom = |Cmin - min{du, dv, dw}| if the difference Δd between the duty cycle command values ​​of two phases of the multi-phase duty cycle command values ​​du, dv, dw is less than a predetermined threshold Δdth, and each of the two phase duty cycle command values ​​is less than (Cmax - Cmin) / 2 = 0.5.

[0188] Furthermore, the control device 51C shifts the duty cycle command values ​​du, dv, and dw of the three phases by a common shift amount dcom so that the duty cycle command value of one of the two phases becomes 1 or 0, and generates a plurality of first PWM signals SU1, SV1, SW1 and a plurality of second PWM signals SU2, SV2, SW2 based on the carrier signal CA1 and the shifted three phase duty cycle command values ​​du, dv, and dw. When shifting the duty cycle command values ​​du, dv, and dw of the three phases by a common shift amount dcom so that the duty cycle command value of one of the two phases becomes 1, the common shift amount dcom is added to the three phase duty cycle command values ​​du, dv, and dw. To shift the duty cycle values ​​of the three phases du, dv, and dw by a common shift amount dcom so that the duty cycle value of one of the two phases becomes 0, subtract the common shift amount dcom from each of the three phase duty cycle values ​​du, dv, and dw.

[0189] (2) Operation (2.1) Basic Operation Diagram 22 shows the case where the target switching element is the first switching element 1U of the switching circuit 10U, illustrating the first PWM signal SU1, the second PWM signal SU2, the control signal SU6, the current iL1 flowing through the resonant inductor L1, and the voltage V1u across the first switching element 1U. Also in Figure 22, the voltage value of the DC power supply E1 is shown as Vd.

[0190] When the target switching element is the first switching element 1U, in the switching circuit 10U, the voltage V2u across the second switching element 2U (not shown in Figure 22) becomes Vd at time t13, when the second dead time period Td2 immediately preceding the high-level period of the first PWM signal SU1 ends, and the voltage V1u across the first switching element 1U becomes zero at time t13, when the second dead time period Td2 immediately preceding the high-level period of the first PWM signal SU1 ends. Therefore, when the first PWM signal SU1 changes from a low level to a high level at time t13, the first switching element 1U is soft-switched at zero voltage. In the example shown in Figure 22, the current iL1 flowing through the resonant inductor L1 begins to flow from time t11, when the high-level period of the control signal SU6 starts, reaches the same value as the load current iU at time t12, when the first period T01 has elapsed from time t11, reaches the same value as the load current iU at time t13, when the second dead time period Td2 ends, and becomes zero at time t14, when the third period T03 has elapsed from time t13. In the signal generation circuit 52, at time t11, when the second PWM signal SU2 changes from a high level to a low level, the control signal SU6 changes from a low level to a high level. The current iL1 flowing between time t12 and time t13 is the resonant current (charging current of the resonant capacitor 9U) flowing from the regenerative capacitor 15 through the resonant inductor L1 to the resonant capacitor 9U.

[0191] During the first period T01, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the off state, and the third switching element 6U is in the on state. During the first period T01, the current iL1 flows through the path from the regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U - AC terminal 41U. Also during the first period T01, the load current iU flows through the path from the second diode 5, which is antiparallel connected to the second switching element 2U - AC terminal 41U - AC load RA1.

[0192] During the second period T02, the first switching element 1U, the second switching element 2U, and the fourth switching element 7U are all in the off state, while the third switching element 6U is in the on state. During the second period T02, the current iL1 flows through the path from the regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U, and is divided into a current flowing to the AC terminal 41U and a current flowing to the resonant capacitor 9U (resonant current). During the second period T02, the resonant capacitor 9U is charged by the current flowing through the resonant capacitor 9.

[0193] During the third period T03, the first switching element 1U and the third switching element 6U are both in the ON state, while the second switching element 2U and the fourth switching element 7U are both in the OFF state. During the third period T03, the current iL1 flows through the path from the regenerative capacitor 15 - resonant inductor L1 - diode 71 - third switching element 6U - AC terminal 41U. This reduces the current iL1 to zero. Also during the third period T03, the load current iU flows through the path from the first DC terminal 31 - first switching element 1U - AC terminal 41U - AC load RA1.

[0194] Figure 23 illustrates the case where the target switching element is the second switching element 2U of the switching circuit 10U, showing the first PWM signal SU1, the second PWM signal SU2, the control signal SU7, the current iL1 flowing through the resonant inductor L1, and the voltage V2u across the second switching element 2U. In Figure 23, the voltage value of the DC power supply E1 is shown as Vd.

[0195] When the target switching element is the second switching element 2U, in the switching circuit 10U, the voltage V1u across the first switching element 1U (not shown in Figure 23) becomes Vd at time t43, when the second dead time period Td2 ends immediately before the high-level period of the second PWM signal SU2, and the voltage V2u across the second switching element 2U becomes zero at time t43, when the second dead time period Td2 ends. Therefore, when the second PWM signal SU2 changes from a low level to a high level at time t43, the second switching element 2U is soft-switched to zero voltage. In the example shown in Figure 23, the current iL1 flowing through the resonant inductor L1 begins to flow from time t41, when the high-level period of the control signal SU7 starts, reaches the same value as the load current iU at time t42, after a predetermined time (additional time Tadu) has elapsed, reaches the same value as the load current iU at time t43, when the second dead time period Td2 ends, and becomes zero at time t44, after a second predetermined time Tad2, which is the same length as the predetermined time (additional time Tadu), has elapsed from time t43. In the signal generation circuit 52, the control signal SU7 changes from a low level to a high level when the first PWM signal SU1 changes from a high level to a low level. The current iL1 flowing between time t42 and time t43 is the resonant current (discharge current of the resonant capacitor 9U) flowing from the resonant capacitor 9U to the resonant inductor L1.

[0196] In Figure 23, the first period T01 is the period from time t41 to t42. During the first period T01, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in the off state, and the fourth switching element 7U is in the on state. During the first period T01, the current iL1 flows through the path from the AC terminal 41U - diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15. Also during the first period T01, the load current iU flows through the path from the AC load RA1 - AC terminal 41U - first diode 4 which is connected in antiparallel to the first switching element 1U.

[0197] In Figure 23, the second period T02 is the period from time t42 to t43. During the second period T02, the first switching element 1U, the second switching element 2U, and the third switching element 6U are all in the off state, and the fourth switching element 7U is in the on state. During the second period T02, the current iL1 flowing through the resonant inductor L1 is the combined current of the current flowing from the AC terminal 41U through the diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15 and the current flowing from the resonant capacitor 9U through the diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15 (resonant current). During the second period T02, the resonant capacitor 9 is discharged.

[0198] In Figure 23, the third period T03 is the period from time t43 to t44. During the third period T03, the second switching element 2U and the fourth switching element 7U are both in the ON state, and the first switching element 1U and the third switching element 6U are both in the OFF state. During the third period T03, the current iL1 flows through the path from the AC terminal 41U - diode 61 - fourth switching element 7U - resonant inductor L1 - regenerative capacitor 15. As a result, the absolute value of the current iL1 is reduced to zero. Also during the third period T03, the load current iU flows through the path from the AC load RA1 - AC terminal 41U - second switching element 2U - second DC terminal 32.

[0199] The above describes an example of setting the first dead time period Td1 to the second dead time period Td2 for the switching circuit 10U, but the same applies when setting the first dead time period Td1 to the second dead time period Td2 for the switching circuit 10V and the switching circuit 10W.

[0200] (2.2) The shift operation of the shift operation control device 51C is the same as the shift operation of the control device 51 in Embodiment 1, so the explanation will be omitted as appropriate.

[0201] For example, as shown in Figure 24, if the difference Δd between the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase is less than a predetermined threshold Δdth, and the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase are greater than 0.5, and the duty cycle command value du of the U phase is greater than the duty cycle command value dv of the V phase, the control device 51C determines the common shift amount dcom by calculating dcom = Cmax - du. In the example in Figure 24, the duty cycle command value dw of the W phase is less than 0.5.

[0202] Figure 24 illustrates the timing chart when the control device 51C has determined in advance that the difference Δd between the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase is less than a predetermined threshold Δdth, and that the duty cycle command value du of the U phase and the duty cycle command value dv of the V phase are greater than 0.5. Here, Figure 24 illustrates the timing chart of the duty cycle command values ​​du, dv, dw of the three phases before the shift, the first PWM signal SU1, the second PWM signal SU2, the first PWM signal SV1, the second PWM signal SV2, the first PWM signal SW1, the second PWM signal SW2, the control signals SU6, SU7, SV6, SV7, SW6, SW7, the current iL1, the line voltage Vuv between the U phase and the V phase, and the load current iU of the U phase. The way to read Figure 24 is the same as the way to read Figure 3.

[0203] As shown in Figure 25, the control device 51C shifts each of the multi-phase duty command values ​​du, dv, and dw by a common shift amount dcom, and generates multiple first PWM signals SU1, SV1, SW1, multiple second PWM signals SU2, SV2, SW2, and multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 based on the carrier signal CA1 and the shifted three-phase duty command values ​​du, dv, and dw. Figure 25 shows the timing charts for the three phases after the shift: duty cycle command values ​​du, dv, dw, first PWM signal SU1, second PWM signal SU2, first PWM signal SV1, second PWM signal SV2, first PWM signal SW1, second PWM signal SW2, control signals SU6, SU7, SV6, SV7, SW6, SW7, current iL1, line voltage Vuv between the U-phase and V-phase, and load current iU of the U-phase. In Figure 25, the duty cycle command values ​​du, dv, dw of the multiple phases before the shift (see Figure 24), the current iL1 that is estimated to flow through the resonant inductor L1 before the shift (see Figure 24) but does not flow through the resonant inductor L1 after the shift, and the line voltage Vuv estimated before the shift (see Figure 24) are shown with dashed lines.

[0204] When the duty cycle command value du after the shift is 1, the control device 51C generates a first PWM signal SU1 that is high level for the entire duration of one cycle of the carrier signal CA1, and generates a second PWM signal SU2 that is low level for the entire duration of one cycle of the carrier signal CA1.

[0205] As can be seen from the waveform of current iL1 in Figure 24 and the waveform of current iL1 in Figure 25, in the power converter 100C, if the control device 51C determines in advance that the difference Δd between the two-phase duty command values ​​du and dv is less than a predetermined threshold Δdth, it performs a shift operation, so that the first switching element 1U is turned on and the second switching element 2U is turned off for one cycle of the carrier signal CA1, and the resonant current of the U phase does not flow during the high-level period of the control signal SU6. As a result, in the power converter 100C, the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1, so the switching of the first switching element 1V becomes zero-voltage soft switching.

[0206] Furthermore, as can be seen from Figures 24 and 25, in the power converter 100C according to Embodiment 4, the fluctuation of the line voltage Vuv between the U phase and the V phase is small, and it is possible to reduce current distortion compared to the power converter of Patent Document 1.

[0207] Furthermore, as can be seen from Figures 24 and 25, in the power converter 100C, the first switching element 1U and the second switching element 2U are not switched within one cycle of the carrier signal CA1, so the switching loss can be reduced to two-thirds.

[0208] (3) Advantages The power converter 100C according to Embodiment 4 is capable of performing zero-voltage soft switching without the control device 51C directly controlling the multiple switches 8 for zero-voltage soft switching, and is also capable of reducing current distortion.

[0209] Furthermore, in the power conversion device 100C according to Embodiment 4, when the control device 51C sets a second dead time period Td2 for each of the plurality of switching circuits 10, if the polarity of the load current is positive, it adds a predetermined time (additional time) to the first dead time period Td1 by advancing the end time of the high-level period of the second PWM signal to the second switching element 2 and delaying the start time of the high-level period of the first PWM signal to the first switching element 1. If the polarity of the load current is negative, it adds a predetermined time (additional time) to the first dead time period Td1 by advancing the end time of the high-level period of the first PWM signal to the first switching element 1 and delaying the start time of the high-level period of the second PWM signal to the second switching element 2.

[0210] With the above configuration, it is possible to achieve zero-voltage soft switching while reducing dead-time loss and dead-time error.

[0211] (Embodiment 5) The power conversion device 100D according to Embodiment 5 will be described below with reference to Figures 26 to 27.

[0212] (1) Configuration of the power converter The power converter 100D according to Embodiment 5 differs from the power converter 100 according to Embodiment 1 (see Figure 1) in that, as shown in Figure 26, it is equipped with a signal generation circuit 52D instead of the signal generation circuit 52 of the power converter 100 according to Embodiment 1. With respect to the power converter 100D according to Embodiment 5, the same reference numerals are used for components that are the same as those in the power converter 100 according to Embodiment 1, and their descriptions are omitted.

[0213] In this embodiment, the configuration and operation of the signal generation circuit 52D differ from those of the signal generation circuit 52.

[0214] The signal generation circuit 52D generates a control signal for each of the multiple switches 8 that has a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10. The signal generation circuit 52D delays the start of the high-level period of the control signal for each of the multiple switches 8 by a predetermined time from the start of the second dead time period Td2, and delays the end of the high-level period of the control signal for each of the multiple switches 8 from the end of the second dead time period Td2. The length of the high-level period of the control signal for each of the multiple switches 8 (hereinafter also referred to as the "fixed length") is longer than the length of the first dead time period Td1.

[0215] The signal generation circuit 52D generates a control signal for each of the multiple switches 8 using either a first PWM signal to the first switching element 1 of the corresponding switching circuit 10 and a second PWM signal to the second switching element 2 of the multiple switching circuits 10. The signal generation circuit 52D sets the length of the high-level period of the control signal generated for each of the multiple switches 8 to a fixed length, and sets the start timing of the fixed-length high-level period to follow the start timing of the second dead time period Td2 for the corresponding switching circuit 10 of the multiple switching circuits 10 for each of the multiple switches 8. In this embodiment, the signal generation circuit 52D has, for example, a plurality (e.g., six) of logic circuits 521D to 526D and a plurality (e.g., six) of gate drive circuits 531 to 536, as shown in Figure 27. In the signal generation circuit 52D, the plurality of logic circuits 521D to 526D correspond one-to-one with the plurality of gate drive circuits 531 to 536.

[0216] The logic circuit 521D is configured to generate a control signal SU6 using the second PWM signal SU2. The logic circuit 521D detects the falling edge of the second PWM signal SU2 to the second switching element 2U and generates a control signal SU6 having a fixed-length high-level period.

[0217] The logic circuit 522D is configured to generate a control signal SU7 using a first PWM signal SU1. The logic circuit 522D detects the falling edge of the first PWM signal SU1 to the first switching element 1U and generates a control signal SU7 having a fixed-length high-level period.

[0218] The logic circuit 523D is configured to generate a control signal SV6 using the second PWM signal SV2. The logic circuit 523D detects the falling edge of the second PWM signal SV2 to the second switching element 2V and generates a control signal SV6 having a fixed-length high-level period.

[0219] The logic circuit 524D is configured to generate a control signal SV7 using a first PWM signal SV1. The logic circuit 524D detects the falling edge of the first PWM signal SV1 to the first switching element 1V and generates a control signal SV7 having a fixed-length high-level period.

[0220] The logic circuit 525D is configured to generate a control signal SW6 using the second PWM signal SW2. The logic circuit 525D detects the falling edge of the second PWM signal SW2 to the second switching element 2W and generates a control signal SW6 having a fixed-length high-level period.

[0221] The logic circuit 526D is configured to generate a control signal SW7 using a first PWM signal SW1. The logic circuit 526D detects the falling edge of the first PWM signal SW1 to the first switching element 1W and generates a control signal SW7 having a fixed-length high-level period.

[0222] Each of the logic circuits 521D to 526D includes, for example, two multivibrators M11 and M12 connected in series. Each of the two multivibrators M11 and M12 is an edge-triggered monostable multivibrator. In each of the logic circuits 521D to 526D, the inverting output terminal of the preceding multivibrator M11 (represented by Q with an overline in Figure 27) is connected to the inverting trigger terminal of the following multivibrator M12. In each of the logic circuits 521D to 526D, the specified time is the length of the CR time constant, which is determined by the capacitance of the capacitor C11 connected to the preceding multivibrator M11 and the resistance of the resistor R11. Furthermore, in each of the multiple logic circuits 521D to 526D, the fixed length is the length of the CR time constant, which is determined by the capacitance of the capacitor C12 connected to the subsequent multivibrator M12 and the resistance of the resistor R12.

[0223] The logic circuit 521D receives the second PWM signal SU2 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SU6 from the output terminal Q of the subsequent multivibrator M12. The control signal SU6 is supplied to the third switching element 6U via the gate drive circuit 531.

[0224] The logic circuit 522D receives the first PWM signal SU1 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SU7 from the output terminal Q of the subsequent multivibrator M12. The control signal SU7 is supplied to the fourth switching element 7U via the gate drive circuit 532.

[0225] The logic circuit 523D receives the second PWM signal SV2 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SV6 from the output terminal Q of the subsequent multivibrator M12. The control signal SV6 is supplied to the third switching element 6V via the gate drive circuit 533.

[0226] The logic circuit 524D receives the first PWM signal SV1 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SV7 from the output terminal Q of the subsequent multivibrator M12. The control signal SV7 is supplied to the fourth switching element 7V via the gate drive circuit 534.

[0227] The logic circuit 525D receives the second PWM signal SW2 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SW6 from the output terminal of the subsequent multivibrator M12. The control signal SW6 is supplied to the third switching element 6W via the gate drive circuit 535.

[0228] The logic circuit 526D receives the first PWM signal SW1 output from the control device 51 as input to the inverting trigger terminal of the preceding multivibrator M11, and outputs a control signal SW7 from the output terminal of the subsequent multivibrator M12. The control signal SW7 is supplied to the fourth switching element 7W via the gate drive circuit 536.

[0229] (2) Operation of the power converter The operation of the power converter 100D is the same as the operation of the power converter 100 according to Embodiment 1, so the explanation will be omitted.

[0230] (3) Advantages The power converter 100D according to Embodiment 5, like the power converter 100 according to Embodiment 1, is capable of performing zero-voltage soft switching without the control device 51 directly controlling the multiple switches 8 for zero-voltage soft switching, and is also capable of reducing current distortion.

[0231] Furthermore, in the power conversion device 100D according to Embodiment 5, the signal generation circuit 52D generates a control signal for each of the multiple switches 8 using either the first PWM signal to the first switching element 1 of the corresponding switching circuit 10 or the second PWM signal to the second switching element 2.

[0232] The above configuration makes it possible to simplify the signal generation circuit 52D.

[0233] (Embodiment 6) The power converter 100E according to Embodiment 6 will be described below with reference to Figures 28 to 30.

[0234] (1) The power converter 100E according to Embodiment 6 differs from the power converter 100 according to Embodiment 1 (see Figure 1) in that, as shown in Figure 28, it is equipped with a signal generation circuit 52E instead of the signal generation circuit 52 of the power converter 100 according to Embodiment 1. With respect to the power converter 100E according to Embodiment 6, the same reference numerals are used for components that are the same as those in the power converter 100 according to Embodiment 1, and their descriptions are omitted.

[0235] In this embodiment, the signal generation circuit 52E includes a PLD (Programmable Logic Device) 520 and a plurality of gate drive circuits 531 to 536 (see Figure 9). The signal generation circuit 52E is equipped with the PLD 520 instead of the plurality of logic circuits 521 to 526 (see Figure 9) of the signal generation circuit 52.

[0236] The signal generation circuit 52E, like the signal generation circuit 52, provides a control signal to each of the multiple switches 8, which changes potential between high and low levels. For each of the multiple switches 8, the signal generation circuit 52E generates a control signal that has a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10. The operation of the signal generation circuit 52E is the same as the relationship between the input and output of the signal generation circuit 52 when considering the relationship between the input and output of the signal generation circuit 52E.

[0237] The signal generation circuit 52E, like the signal generation circuit 52, makes the start time of the high-level period of the control signal generated for each of the multiple switches 8 follow the start timing of the second dead time period Td2. In this embodiment, the signal generation circuit 52E synchronizes the start time of the high-level period of the control signal for each of the multiple switches 8 with the start time of the second dead time period Td2. In this embodiment, the length of the high-level period of the control signal for each of the multiple switches 8 is longer than the length of the second dead time period Td2.

[0238] In the signal generation circuit 52E, the PLD 520 generates a control signal for each of the multiple switches 8 using a first PWM signal to the first switching element 1 and a second PWM signal to the second switching element 2 of the corresponding switching circuit 10 among the multiple switching circuits 10. For each of the multiple switches 8, the PLD 520 generates a control signal having a high-level period corresponding to the second dead time period Td2 for the corresponding switching circuit 10 among the multiple switching circuits 10.

[0239] In the signal generation circuit 52E, the PLD 520 synchronizes the start time of the high-level period of the control signal generated for each of the multiple switches 8 with the start timing of the second dead time period Td2.

[0240] In the power converter 100E of this embodiment, when the control device 51 shifts the duty cycle command values ​​du, dv, and dw of multiple phases by a common shift amount dcom, the PLD 520 of the signal generation circuit 52E shortens the on period of one of the multiple switches 8. The one switch 8 corresponds to a switching circuit 10 among the multiple switching circuits 10 that is controlled based on a duty cycle command value of one phase, where the duty cycle command value is 1 or 0. In this embodiment, the PLD 520 of the signal generation circuit 52E shortens the high-level period of the control signal for one switch 8 among the multiple switches 8 that corresponds to the switching circuit 10 of the phase where the duty cycle command value becomes 1 or 0 in the shifted three-phase duty cycle command values ​​du, dv, and dw. In this embodiment, the PLD 520 shortens the high-level period of the control signal for the one switch 8 to zero. Furthermore, when shortening the high-level period of the control signal for one of the switches 8, the PLD 520 may shorten it to zero, or it may shorten it to a high-level period that is shorter than the high-level period before the shift but longer than zero.

[0241] Figure 29 shows the timing chart for the three phases before the shift, including duty cycle command values ​​du, dv, dw, first PWM signal SU1, second PWM signal SU2, first PWM signal SV1, second PWM signal SV2, first PWM signal SW1, second PWM signal SW2, control signals SU6, SU7, SV6, SV7, SW6, SW7, current iL1, line voltage Vuv between the U phase and V phase, and load current iU of the U phase.

[0242] In the example shown in Figure 30, the control device 51 shifts the duty cycle command values ​​du, dv, and dw of each of the multiple phases by a common shift amount dcom, and generates multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2 based on the carrier signal CA1 and the shifted three-phase duty cycle command values ​​du, dv, and dw, and the PLD 520 of the signal generation circuit 52E generates multiple control signals SU6, SU7, SV6, SV7, SW6, SW7. Figure 30 shows the timing chart for the three phases after the shift: duty cycle command values ​​du, dv, dw, first PWM signal SU1, second PWM signal SU2, first PWM signal SV1, second PWM signal SV2, first PWM signal SW1, second PWM signal SW2, control signals SU6, SU7, SV6, SV7, SW6, SW7, current iL1, line voltage Vuv between the U-phase and V-phase, and U-phase load current iU. In Figure 30, the duty cycle command values ​​du, dv, dw for multiple phases before the shift (see Figure 29), the current iL1 that is estimated to flow through the resonant inductor L1 before the shift (see Figure 29) but does not flow through the resonant inductor L1 after the shift, and the line voltage Vuv estimated before the shift (see Figure 29) are shown with dashed lines.

[0243] When the duty cycle command value du after the shift is 1, the control device 51 generates a first PWM signal SU1 that is high level for the entire duration of one cycle of the carrier signal CA1, and generates a second PWM signal SU2 that is low level for the entire duration of one cycle of the carrier signal CA1.

[0244] As can be seen from the waveform of current iL1 in Figure 29 and the waveform of current iL1 in Figure 30, in the power converter 100E, if the control device 51 determines in advance that the difference Δd between the two-phase duty command values ​​du and dv is less than a predetermined threshold Δdth, it performs a shift operation, so that the first switching element 1U turns on and the second switching element 2U turns off for one period of the carrier signal CA1, and the resonant current of the U phase stops flowing. As a result, in the power converter 100E, the resonant current of the U phase and the resonant current of the V phase do not overlap in the resonant inductor L1, so the switching of the first switching element 1V becomes zero-voltage soft switching.

[0245] Furthermore, as can be seen from Figures 29 and 30, the power converter 100E exhibits small fluctuations in the line voltage Vuv between the U-phase and V-phase, making it possible to reduce current distortion compared to the power converter described in Patent Document 1.

[0246] Furthermore, as can be seen from Figures 29 and 30, in the power converter 100E, the first switching element 1U and the second switching element 2U are not switched within one cycle of the carrier signal CA1, so the switching loss can be reduced to two-thirds.

[0247] In the example shown in Figure 30, the on-period of switch 8U is reduced to zero by shortening the high-level periods of control signals SU6 and SU7 to zero during one cycle of the carrier signal CA1.

[0248] (2) Advantages The power converter 100E according to Embodiment 6, like the power converter 100 according to Embodiment 1, is capable of performing zero-voltage soft switching without the control device 51 directly controlling the multiple switches 8 for zero-voltage soft switching, and is also capable of reducing current distortion.

[0249] Furthermore, in the power converter 100E according to Embodiment 6, when the control device 51 shifts the duty cycle command values ​​du, dv, and dw of multiple phases by a common shift amount dcom, the signal generation circuit 52E shortens the on-time of one of the multiple switches 8. The one switch 8 corresponds to a switching circuit 10 among the multiple switching circuits 10 that is controlled based on the duty cycle command value of the one phase.

[0250] With the above configuration, by shortening the on-period of the switch 8 corresponding to the switching circuit 10 of the phase where the duty cycle command value is shifted to a value equivalent to 100% or a value equivalent to 0%, it is possible to reduce the loss of current flowing through the switch 8.

[0251] (Modifications) Embodiments 1 to 6 described above are merely one of many embodiments of the present disclosure. Embodiments 1 to 6 described above can be modified in various ways depending on the design, etc., as long as the objectives of the present disclosure are achieved.

[0252] In embodiments 1 to 5, which differ from embodiment 6, instead of the multiple logic circuits 521 to 526 and 521D to 526D of the signal generation circuits 52 and 52D, a PLD 520 that generates multiple control signals SU6, SU7, SV6, SV7, SW6, SW7 may be provided.

[0253] Furthermore, the carrier signal CA1 is a carrier signal used to generate multiple first PWM signals SU1, SV1, SW1 and multiple second PWM signals SU2, SV2, SW2, but it is not limited to a triangular waveform; a sawtooth waveform carrier signal is also acceptable.

[0254] Furthermore, each of the multiple first switching elements 1 and the multiple second switching elements 2 is not limited to IGBTs, but may also be a MOSFET. In this case, each of the multiple first diodes 4 may be replaced with a parasitic diode of the MOSFET constituting the corresponding first switching element 1. Similarly, each of the multiple second diodes 5 may be replaced with a parasitic diode of the MOSFET constituting the corresponding second switching element 2. The MOSFETs are, for example, Si-based MOSFETs or SiC-based MOSFETs. Each of the multiple first switching elements 1 and the multiple second switching elements 2 may also be, for example, a bipolar transistor or a GaN-based GIT.

[0255] Furthermore, in power converters 100, 100A to 100E, if the capacitance of each of the multiple resonant capacitors 9 is relatively small, instead of externally attaching the multiple resonant capacitors 9 between the ends of the multiple second switching elements 2, the parasitic capacitance between the ends of the multiple second switching elements 2 may also serve as the multiple resonant capacitors 9.

[0256] Furthermore, in power converters 100, 100A to 100E, the length of the first dead time period Td1 is set to be the same as the resonant half-period, but it may be set to a length different from the resonant half-period.

[0257] Furthermore, in the power conversion device 100 according to Embodiment 1, the diodes 61 and 71 are not limited to being externally attached to the third switching element 6 and the fourth switching element 7, respectively, but may also be elements built into a single chip.

[0258] Furthermore, the power converters 100, 100B to 100E may also include a second regenerative capacitor connected between the sixth terminal 154 of the regenerative capacitor 15 (hereinafter also referred to as the first regenerative capacitor 15) and the first DC terminal 31. The capacitance of the second regenerative capacitor is the same as the capacitance of the first regenerative capacitor 15. "The capacitance of the second regenerative capacitor is the same as the capacitance of the first regenerative capacitor 15" is not limited to the case where the capacitance of the second regenerative capacitor perfectly matches the capacitance of the first regenerative capacitor 15, but is sufficient if the capacitance of the second regenerative capacitor is within the range of 90% to 110% of the capacitance of the first regenerative capacitor 15.

[0259] In each of the multiple switches 8, the second main terminal (emitter terminal) of the third switching element 6 is connected to the second main terminal (emitter terminal) of the fourth switching element 7, the first main terminal (collector terminal) of the third switching element 6 is connected to the connection point 3 of the corresponding switching circuit 10 among the multiple switching circuits 10, and the first main terminal (collector terminal) of the fourth switching element 7 is connected to the common connection point 25. In this case, each of the multiple switches 8 further has a diode antiparallel connected to the third switching element 6 and a diode antiparallel connected to the fourth switching element 7.

[0260] Furthermore, each of the third switching element 6 and the fourth switching element 7 may be replaced with a MOSFET or a bipolar transistor.

[0261] In each of the multiple switches 8, the third switching element 6 and the fourth switching element 7 may be connected in antiparallel. Furthermore, each of the multiple switches 8 may further include a diode connected in antiparallel to the third switching element 6 and a diode connected in antiparallel to the fourth switching element 7.

[0262] Each of the multiple switches 8 may be a dual-gate type GaN-based GIT having a first source terminal, a first gate terminal, a second gate terminal, and a second source terminal. In this case, a control signal SU6 is applied between the first gate terminal and the first source terminal of the dual-gate type GaN-based GIT constituting switch 8U, and a control signal SU7 is applied between the second gate terminal and the second source terminal. Similarly, a control signal SV6 is applied between the first gate terminal and the first source terminal of the dual-gate type GaN-based GIT constituting switch 8V, and a control signal SV7 is applied between the second gate terminal and the second source terminal. Furthermore, a control signal SW6 is applied between the first gate terminal and the first source terminal of the dual-gate type GaN-based GIT constituting switch 8W, and a control signal SW7 is applied between the second gate terminal and the second source terminal.

[0263] Furthermore, the power converters 100, 100A to 100E are not limited to a configuration that outputs three-phase AC, but may be configured to output three or more phases of multi-phase AC.

[0264] (Aspects) The following aspects are disclosed herein.

[0265] The power conversion device (100; 100A; 100B; 100C; 100D; 100E) according to the first embodiment comprises a first DC terminal (31), a second DC terminal (32), a power conversion circuit (11), a plurality of AC terminals (41), a plurality of switches (8), a plurality of resonant capacitors (9), a resonant inductor (L1), a regenerative capacitor (15), a control device (51; 51B; 51C), and a signal generation circuit (52; 52D; 52E). The power conversion circuit (11) has a plurality of first switching elements (1) and a plurality of second switching elements (2). In the power conversion circuit (11), a plurality of switching circuits (10), each of which a plurality of first switching elements (1) and a plurality of second switching elements (2) are connected in series in a one-to-one relationship, are connected in parallel to each other. In the power conversion circuit (11), multiple first switching elements (1) are connected to the first DC terminal (31). In the power conversion circuit (11), multiple second switching elements (2) are connected to the second DC terminal (32). Multiple AC terminals (41) correspond one-to-one to multiple switching circuits (10). Each of the multiple AC terminals (41) is connected to the connection point (3) of the first switching element (1) and the second switching element (2) in the corresponding switching circuit (10) among the multiple switching circuits (10), and load current flows through it. Multiple switches (8) correspond one-to-one to multiple switching circuits (10). Each of the multiple switches (8) has its first end (81) connected to the connection point (3) of the first switching element (1) and the second switching element (2) in the corresponding switching circuit (10) among the multiple switching circuits (10), with the first end (81) being connected to the second end (82). Multiple resonant capacitors (9) correspond one-to-one with multiple switches (8). Each of the multiple resonant capacitors (9) is connected between the first terminal (81) and the second DC terminal (32) of the corresponding switch (8) among the multiple switches (8). The resonant inductor (L1) has a third terminal and a fourth terminal. In the resonant inductor (L1), the third terminal is connected to the second terminal (82) of the multiple switches (8). The regenerative capacitor (15) has a fifth terminal (153) and a sixth terminal (154).In the regenerative capacitor (15), the fifth terminal (153) is connected to the first DC terminal (31) or the second DC terminal (32), and the sixth terminal (154) is connected to the fourth terminal of the resonant inductor (L1). The control device (51) generates a plurality of first PWM signals (SU1, SV1, SW1) to control a plurality of first switching elements (1) and a plurality of second PWM signals (SU2, SV2, SW2) to control a plurality of second switching elements (2), based on a plurality of phase duty cycle command values ​​(du, dv, dw) that correspond one-to-one to the plurality of switching circuits (10). The signal generation circuits (52; 52D; 52E) provide each of the plurality of switches (8) with a control signal (SU6, SU7, SV6, SV7, SW6, SW7) whose potential changes between high level and low level. The control devices (51; 51B; 51C) set a second dead time period (Td2) for each of the plurality of switching circuits (10) by adding a predetermined time to a first dead time period (Td1) which is set so that the ON periods of the first switching element (1) and the second switching element (2) do not overlap between the high-level period of the first PWM signal to the first switching element (1) and the high-level period of the second PWM signal to the second switching element (2). The predetermined time is determined according to the current value of the load current, the inductance of the resonant inductor (L1), and the voltage value of the regenerative capacitor (15). The signal generation circuits (52; 52D; 52E) generate a control signal for each of the plurality of switches (8) that has a high-level period corresponding to the second dead time period (Td2) for the corresponding switching circuit (10) among the plurality of switching circuits (10). The control devices (51; 51B; 51C) determine a common shift amount (dcom) such that the duty cycle command value of one of the two phases corresponds to either 100% or 0% when the difference (Δd) between the duty cycle command values ​​of any two of the multiple phases (du, dv, dw) is less than a predetermined threshold (Δdth). They then shift each of the multiple phases (du, dv, dw) by the common shift amount (dcom) to generate multiple first PWM signals (SU1, SV1, SW1) and multiple second PWM signals (SU2, SV2, SW2).

[0266] According to this embodiment, zero-voltage soft switching can be performed without the control device (51; 51B; 51C) directly controlling the plurality of switches (8) for zero-voltage soft switching, and current distortion can be reduced.

[0267] In the power converter according to the second embodiment (100; 100A; 100B; 100C; 100D; 100E), in the first embodiment, the control device (51; 51B; 51C) determines a common shift amount (dcom) based on the maximum value (Cmax) or minimum value (Cmin) of the carrier signal (CA1) used to generate a plurality of first PWM signals (SU1, SV1, SW1) and a plurality of second PWM signals (SU2, SV2, SW2), and the duty command values ​​of the two phases.

[0268] In the power converter (100E) according to the third embodiment, in the first or second embodiment, the control device (51) shortens the on-time of one of the multiple switches (8) when the duty cycle command values ​​(du, dv, dw) of multiple phases are shifted by a common shift amount (dcom). The one switch (8) corresponds to a switching circuit (10) among the multiple switching circuits (10) that is controlled based on the duty cycle command value of the one phase.

[0269] According to this embodiment, by shortening the on-period of the switch (8) corresponding to the switching circuit (10) of the phase in which the duty cycle command value has been shifted to a value equivalent to 100% or a value equivalent to 0%, it is possible to reduce the loss of current flowing through the switch (8).

[0270] In the power converter (100; 100A; 100E) according to the fourth embodiment, in any one embodiment of the first to third embodiments, the control device (51; 51B; 51C) sets a second dead time period (Td2) for each of the plurality of switching circuits (10). When the polarity of the load current is positive, a predetermined time (additional time Tad) is added to the first dead time period (Td1) by shortening the high-level period of the second PWM signal to the second switching element (2). When the polarity of the load current is negative, a predetermined time is added to the first dead time period (Td1) by shortening the high-level period of the first PWM signal to the first switching element (1).

[0271] According to this embodiment, it is possible to achieve zero-voltage soft switching while further reducing dead time loss and dead time error.

[0272] In the power converter (100B) according to the fifth embodiment, in any one of the first to third embodiments, when the control device (51B) sets a second dead time period (Td2) for each of the plurality of switching circuits (10), if the polarity of the load current is positive, it adds a predetermined time (Ta11 + Ta21) to the first dead time period (Td1) by advancing the end time of the high-level period of the second PWM signal to the second switching element (2) and delaying the start time of the high-level period of the first PWM signal to the first switching element (1), and if the polarity of the load current is negative, it adds a predetermined time (Ta12 + Ta22) to the first dead time period (Td1) by advancing the end time of the high-level period of the first PWM signal to the first switching element (1) and delaying the start time of the high-level period of the second PWM signal to the second switching element (2).

[0273] According to this embodiment, it is possible to achieve zero-voltage soft switching while reducing dead time loss and dead time error.

[0274] In the power converter (100C) according to the sixth embodiment, in any one of the first to third embodiments, when the control device (51C) sets a second dead time period (Td2) for each of the plurality of switching circuits (10), if the polarity of the load current is positive, a predetermined time is added to the first dead time period (Td1) by shortening the high-level period of the first PWM signal to the first switching element (1), and if the polarity of the load current is negative, a predetermined time is added to the first dead time period (Td1) by shortening the high-level period of the second PWM signal to the second switching element (2).

[0275] According to this embodiment, zero-voltage soft switching can be achieved.

[0276] 1 First switching element 2 Second switching element 3 Connection point 4 First diode 5 Second diode 6 Third switching element 7 Fourth switching element 8 Switch 81 First terminal 82 Second terminal 9 Resonant capacitor 10 Switching circuit 13 First clamp diode 14 Second clamp diode 11 Power conversion circuit 15 Regenerative capacitor 153 Fifth terminal 154 Sixth terminal 31 First DC terminal 32 Second DC terminal 41 AC terminals 51, 51B, 51C Control device 52, 52D, 52E Signal generation circuit 100, 100A, 100B, 100C Power converter iU, iv, iW Output current (load current) L1 Resonant inductor RA1 AC load SU1, SV1, SW1 First PWM signal SU2, SV2, SW2 Second PWM signal SU6, SU7, SV6, SV7, SW6, SW7 Control signal Ta11 Time Ta12 Time Ta21 Time Ta22 Time Tadu Additional time Tadv Additional time Td1 First dead time period Td2 Second dead time period

Claims

First DC terminal and, The second DC terminal and, A power conversion circuit having a plurality of first switching elements and a plurality of second switching elements, wherein a plurality of switching circuits are connected in parallel to each other, with the plurality of first switching elements and the plurality of second switching elements connected in a one-to-one series relationship, the plurality of first switching elements being connected to the first DC terminal, and the plurality of second switching elements being connected to the second DC terminal, Multiple AC terminals, each corresponding one-to-one to the aforementioned multiple switching circuits, are connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit, and through which load current flows. A plurality of switches, each corresponding one-to-one to the plurality of switching circuits, wherein the first end of each switch is connected to the connection point of the first switching element and the second switching element in the corresponding switching circuit, Multiple resonant capacitors, each corresponding one-to-one to the aforementioned multiple switches, and each connected between the first terminal and the second DC terminal of the corresponding switch, A resonant inductor having a third end and a fourth end, the third end of which is connected to the second end of the plurality of switches, A regenerative capacitor having a fifth end and a sixth end, wherein the fifth end is connected to the first DC terminal or the second DC terminal, and the sixth end is connected to the fourth end of the resonant inductor, A control device that generates a plurality of first PWM signals for controlling the plurality of first switching elements and a plurality of second PWM signals for controlling the plurality of second switching elements, based on a plurality of duty cycle command values ​​of a plurality of phases corresponding one-to-one to the plurality of switching circuits. The system includes a signal generation circuit that provides a control signal to each of the aforementioned multiple switches, which changes the potential between a high level and a low level. The control device is For each of the plurality of switching circuits, a second dead time period is set between the high-level period of the first PWM signal to the first switching element and the high-level period of the second PWM signal to the second switching element, by adding a predetermined time to a first dead time period which is set in advance so that the ON periods of the first switching element and the second switching element do not overlap. The predetermined time is determined according to the current value of the load current, the inductance of the resonant inductor, and the voltage value of the regenerative capacitor. The signal generation circuit generates a control signal for each of the plurality of switches that has a high-level period corresponding to the second dead time period for the corresponding switching circuit among the plurality of switching circuits. The control device is When the difference between the duty cycle command values ​​of any two of the multiple phases is less than a predetermined threshold, a common shift amount is determined such that the duty cycle command value of one of the two phases becomes a value equivalent to 100% or 0%, and each of the multiple phases' duty cycle command values ​​is shifted by the common shift amount to generate the multiple first PWM signals and the multiple second PWM signals. Power converter. 　 The control device determines the common shift amount based on the maximum or minimum value of the carrier signals used to generate the plurality of first PWM signals and the plurality of second PWM signals, and the duty cycle command value of the two phases. The power conversion device according to claim 1. 　 When the duty cycle command values ​​of the multiple phases are shifted by the common shift amount, the control device shortens the on-time of one of the multiple switches. The aforementioned one switch corresponds to a switching circuit among the plurality of switching circuits that is controlled based on the duty cycle command value of the one phase, The power conversion device according to claim 1 or 2. 　 When the control device sets the second dead time period for each of the plurality of switching circuits, If the polarity of the load current is positive, the predetermined time is added to the first dead time period by shortening the high-level period of the second PWM signal to the second switching element. If the polarity of the load current is negative, the predetermined time is added to the first dead time period by shortening the high-level period of the first PWM signal to the first switching element. A power conversion device according to any one of claims 1 to 3. 　 When the control device sets the second dead time period for each of the plurality of switching circuits, When the polarity of the load current is positive, the predetermined time is added to the first dead time period by advancing the end time of the high-level period of the second PWM signal to the second switching element and delaying the start time of the high-level period of the first PWM signal to the first switching element. If the polarity of the load current is negative, the predetermined time is added to the first dead time period by advancing the end time of the high-level period of the first PWM signal to the first switching element and delaying the start time of the high-level period of the second PWM signal to the second switching element. A power conversion device according to any one of claims 1 to 3. 　 When the control device sets the second dead time period for each of the plurality of switching circuits, If the polarity of the load current is positive, the predetermined time is added to the first dead time period by shortening the high-level period of the first PWM signal to the first switching element. If the polarity of the load current is negative, the predetermined time is added to the first dead time period by shortening the high-level period of the second PWM signal to the second switching element. A power conversion device according to any one of claims 1 to 3.

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