Storage node and system

Abstract

Disclosed is a storage node and system, which relates to the field of distributed systems and solves the problem of how to reduce the latency of a storage node in processing data-intensive tasks. The storage node includes a processor and a memory, and the memory includes a processing unit and a memory. After the processor receives a data processing request sent by an application server, it reads data from the memory of the storage node to the memory of the memory according to the data processing request; and the processor also sends at least one instruction to the processing unit of the memory, instructing the processing unit to process the data; after receiving the instruction, the processing unit reads data from the memory of the memory and processes the data; finally, the processor sends the processed data to the application server. Thus, the movement of data on the memory bus is avoided, the "memory wall" problem is solved, and the latency of processing data when the storage node processes data-intensive tasks is effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of distributed systems, and in particular to a storage node and system. Background Art

[0002] In a distributed system, computing nodes can split data-intensive tasks into multiple data processing subtasks according to the storage location of the data, and send each data processing subtask to the corresponding storage node. In this way, the computing power of the storage node is used to process data nearby, avoiding data transmission on the network and input and output (IO) bus, effectively reducing the occupancy rate of network resources and IO bus resources and the delay of data processing. Data-intensive tasks refer to data processing tasks that require the processor to frequently access the memory.

[0003] However, the frequent and large-scale memory access operations of the data processing subtasks pushed down to each storage node increase the latency of the processor in the storage node to process data. In addition, it also leads to competition for memory bus resources in the storage node, increases the latency of other tasks accessing memory, and creates a "memory wall" problem. Therefore, how to reduce the latency of storage nodes processing data-intensive tasks is an urgent problem to be solved. Summary of the invention

[0004] The present application provides a storage node and system, which solves the problem of how to reduce the latency of a storage node in processing data-intensive tasks.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In the first aspect, the present application provides a storage node, which includes a processor and a memory, and the memory includes a processing unit and a memory. After the processor receives a data processing request sent by an application server, it reads data from the memory of the storage node to the memory of the memory according to the data processing request; and the processor also sends at least one instruction to the processing unit of the memory, instructing the processing unit to process the data; after receiving the instruction, the processing unit reads the data from the memory of the memory, processes the data, and feeds back the processed data to the processor of the storage node; finally, the processor sends the processed data to the application server.

[0007] The storage node provided by the embodiment of the present application adds a processing unit in the memory, and the processor of the storage node instructs the processing unit in the memory to process data-intensive tasks, thereby avoiding the movement of data on the memory bus, thereby solving the "memory wall" problem and effectively reducing the data processing delay when the storage node processes data-intensive tasks.

[0008] In one possible implementation, each instruction includes the address where data is located in the memory and the type of operation.

[0009] In another possible implementation, the memory further includes a memory controller, and the memory controller is different from the processing unit.

[0010] In another possible implementation, the memory further includes a cache, and the cache is used to store at least one instruction.

[0011] In another possible implementation, the storage node includes N memories, where N is an integer and N≥1, wherein the processor is further used to determine at least one memory that meets the storage capacity requirements based on the remaining storage capacity of the N memories; the processor is further used to determine a memory that meets the computing requirements from the at least one memory.

[0012] In another possible implementation, the memory includes M processing units, where M is an integer, M≥1, and the memory also includes a status register, which is used to indicate the usage status of the M processing units included in the memory, wherein the processor is used to determine a memory that meets the computing requirements from at least one memory based on the indication information of the status register of each memory.

[0013] Thus, the processor of the storage node selects the appropriate memory allocation to unload data-intensive program segments according to the status of the processing unit indicated by the status register in each memory, avoiding memory congestion and waiting caused by the inability to perceive the memory status, and ensuring the effectiveness of unloading data-intensive program segments.

[0014] In the second aspect, the present application provides a distributed system, which includes an application server and a storage node, the storage node includes a processor and a memory, the memory includes a processing unit and a storage device, wherein: the application server is used to send a data processing request to the storage node; the processor is used to receive the data processing request sent by the application server, and read the data into the storage device of the memory according to the data processing request; the processor is also used to send at least one instruction to the processing unit, the instruction is used to instruct the processing unit to process the data; the processor is also used to send the processed data to the application server; the application server is used to receive the processed data sent by the storage node.

[0015] The distributed system provided by the embodiment of the present application transfers data-intensive subtasks from computing nodes to storage nodes, and uses the computing power of storage nodes to directly complete the calculation of data in the storage nodes, thereby avoiding the performance bottleneck caused by network transmission. Moreover, by adding processing units in the memory, the processor of the storage node instructs the processing unit in the memory to process data-intensive tasks, avoiding the movement of data on the memory bus, thereby solving the "memory wall" problem and effectively reducing the data processing delay when the storage node processes data-intensive tasks.

[0016] In a third aspect, the present application provides a method for processing data, which is applied to a storage node, the storage node includes a processor and a memory, the memory includes a processing unit and a memory, the method includes: the processor receives a data processing request sent by an application server, and reads data to the memory of the memory according to the data processing request; the processor sends at least one instruction to the processing unit, the instruction is used to instruct the processing unit to process the data; the processor sends the processed data to the application server.

[0017] The method for processing data is the same as the corresponding description in the first aspect and will not be repeated here.

[0018] The storage node provided by the embodiment of the present application adds a processing unit in the memory, and the processor of the storage node instructs the processing unit in the memory to process data-intensive tasks, thereby avoiding the movement of data on the memory bus, thereby solving the "memory wall" problem and effectively reducing the data processing delay when the storage node processes data-intensive tasks.

[0019] In a fourth aspect, the present application further provides a computer-readable storage medium, comprising: computer software instructions; when the computer software instructions are executed in a communication device, the communication device executes the method described in the first aspect above.

[0020] In a fifth aspect, the present application further provides a computer program product comprising instructions, which, when executed in a communication device, enables the communication device to execute the method described in the first aspect above.

[0021] In a sixth aspect, the present application provides a chip system, which includes a processor and may also include a memory, for implementing the function of the memory in the above method. The chip system may be composed of a chip, or may include a chip and other discrete devices.

[0022] In addition, the technical effects brought about by the design methods of any of the above aspects can refer to the technical effects brought about by the different design methods in the first aspect, and will not be repeated here.

[0023] In this application, the name of the storage node does not limit the device itself. In actual implementation, these devices may appear with other names. As long as the functions of each device are similar to those of this application, they fall within the scope of the claims of this application and their equivalent technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 An example diagram of the architecture of a distributed system provided in this embodiment;

[0025] Figure 2 A schematic diagram of a memory wall provided for this application;

[0026] Figure 3 An example diagram of the architecture of a distributed system provided in an embodiment of the present application;

[0027] Figure 4 A structural example diagram of a DP-DIMM provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of near data processing provided in an embodiment of the present application;

[0029] Figure 6 A flow chart of a method for processing data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects rather than to limit a specific order.

[0031] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0032] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. In the text description of this application, the character " / " generally indicates that the previous and next associated objects are in an "or" relationship; in the formula of this application, the character " / " indicates that the previous and next associated objects are in a "division" relationship.

[0033] In order to make the description of the following embodiments clear and concise, a brief introduction to the related technology is first given:

[0034] Normally, the processor loads data from the storage to the memory through the IO bus or network, and then the processor reads the data from the memory for processing. However, in the era of big data, the amount of data that needs to be processed is growing explosively, and this traditional data processing architecture requires the transmission of a large amount of data. In a distributed system, for data-intensive applications such as databases, query processing first requires a large number of IO operations to load data into the memory of the computing node, making the IO bus or network a performance bottleneck for the system, causing great performance problems: 1) A large amount of data movement increases the delay of data processing; 2) Data transmission causes competition for IO bus or network resources, affecting data access to other applications in the system and affecting the performance of other applications. Therefore, for data-intensive applications, data transmission should be avoided as much as possible to reduce data movement overhead.

[0035] Near Data Processing / Computing (NDP / NDC) is a method or concept for processing data, which is to move the processing and computing of data to a place close to the data. In this way, the movement of data can be reduced or even avoided as much as possible, and the efficiency of data processing can be improved. According to different processing modes, NDP can be divided into three types: In-Storage Processing (ISP), On-Disk Data Processing (ODDP), and Processing-In Memory (PIM).

[0036] ISP usually refers to transferring data-intensive tasks from computing nodes to storage nodes in a system architecture where computing and storage are separated, using the computing power of storage nodes to directly complete data calculations in the storage nodes, thereby avoiding performance bottlenecks caused by network transmission.

[0037] ODDP refers to transferring computing tasks from the host side to a specific storage device, for example, a solid state drive (SSD), using the computing power of the controller or dedicated processing logic in the storage device to process data locally.

[0038] PIM adds a computing logic unit to the memory module and performs calculations within the memory module, thus avoiding the movement of data on the memory bus.

[0039] Figure 1An example diagram of the architecture of a distributed system provided for this embodiment. The distributed system adopts a shared disk architecture with separated computing and storage, including a data processing layer, a network layer, and a storage layer. The data processing layer includes at least one computing node 101. The computing node 101 is mainly responsible for computing and processing data. For example, database-related computing. The storage layer includes at least one storage node 102. The storage node 102 is used to store data. The network layer can be an InfiniBand (IB) network 103. The computing nodes and storage nodes are interconnected and transmitted data using the IB network.

[0040] In some embodiments, a database server may be used to implement the function of a computing node, or multiple database servers may be used to implement the function of a computing node, which is not limited in this application. A storage node may be used to implement the function of a storage node, or multiple storage servers may be used to implement the function of a storage node, which is not limited in this application.

[0041] The distributed system can use ISP type near data processing technology to process data-intensive tasks. The computing node 101 mainly processes computing-intensive tasks, and pushes some data-intensive tasks to the storage node. For example, the storage node 102 can implement operations such as where predicate filtering, column filtering, and Join connection filtering in the Structured Query Language (SQL) query. The table data is specifically processed in the storage node, thereby reducing the amount of data transmission from the storage node to the computing node.

[0042] The so-called computationally intensive tasks may refer to tasks that require a large amount of calculations on data.

[0043] The so-called data-intensive tasks may refer to tasks that require reading a large amount of data and performing operations on the data.

[0044] When a storage node processes data-intensive tasks, the processor needs to frequently access the memory using load / store instructions through the memory bus.

[0045] like Figure 2As shown in the figure, in the past 20 years, the performance of processors has been rapidly improving at a rate of about 60% per year, while the performance of memory has only been improving at a rate of about 7%, resulting in the current memory speed lagging far behind the speed of processors. There is a serious performance gap between memory and processor, which makes it difficult to give full play to the advantages of processors, causing the memory system to become the performance bottleneck of the computing system. Especially in memory-intensive high-performance computing (HPC) scenarios, the memory speed seriously limits the system performance. In addition, the internal bus between the memory and the processor also faces problems such as low bandwidth and high latency. The cost of data transmission is high, which seriously affects the performance of the computing system. This memory bottleneck that limits system performance is usually called the "Memory Wall".

[0046] Therefore, memory bus bandwidth and data processing latency become performance bottlenecks for storage nodes to process data-intensive tasks. In addition, a large number of memory accesses will also cause competition for memory bus resources in the memory system, increasing the memory access latency of other tasks. This "memory wall" problem restricts the performance of data processing in storage nodes.

[0047] The storage node provided by the embodiment of the present application adds a processing unit in the memory, and the processor of the storage node instructs the processing unit in the memory to process data-intensive tasks, thereby avoiding the movement of data on the memory bus, thereby solving the "memory wall" problem and effectively reducing the latency of the storage node in processing data-intensive tasks.

[0048] The implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0049] Figure 3An example diagram of the architecture of a distributed system provided in an embodiment of the present application. The distributed system includes a computing node 301 and a storage node 302. The computing node 301 includes a processor 3011, a memory 3012, a data analysis module 3013, and a subtask dispatcher module 3014. In some embodiments, the data analysis module 3013 and the subtask dispatcher module 3014 can be a logical unit. The functions of the data analysis module 3013 and the subtask dispatcher module 3014 are performed by the processor 3011. The storage node 302 includes components such as a processor 3021, a memory 3022, a memory controller 3023, a storage medium 3024 (such as a hard disk drive (HDD) or SSD) and an IO controller 3025. The memory 3022 includes dual-inline memory modules (Dual-Inline-Memory-Modules, DIMM) and data processing dual-inline memory modules (data processing Dual-Inline-Memory-Modules, DP-DIMM). The difference between DIMM and DP-DIMM is that DP-DIMM contains a processing unit, while DIMM does not contain a processing unit.

[0050] The computing node 301 is mainly used to process computing-intensive tasks and run big data analysis programs (such as Online Analytical Processing (OLAP)). In some embodiments, the computing node 301 can be an application server (such as a database server, etc.). A distributed system can include multiple computing nodes 301, which jointly process data and share a storage system. The storage system is mainly responsible for storing data and responding to data read and write requests from upper-level computing nodes. The storage system can include multiple storage nodes 302.

[0051] The storage node 302 is used to run the storage processing logic software, is responsible for the persistent storage of data, and ensures the reliability and availability of data.

[0052] Figure 3 This is just a schematic diagram. The distributed system can also include other network devices (such as switches or routers) for transmitting data between computing nodes and storage nodes. Figure 3 The embodiment of the present application does not limit the number of computing nodes and storage nodes included in the distributed system.

[0053] For big data analysis applications, the computing node 301 needs to read massive data from the storage node 302 and process the massive data. Therefore, the computing node 301 includes data-intensive tasks when processing big data analysis applications, such as full table scan operations in OLAP applications. In order to avoid increasing the delay of data processing due to the transmission of massive data in the network between the computing node and the storage node, the data analysis module 3013 of the computing node 301 can analyze the big data analysis application, filter out data-intensive tasks, and split the data-intensive tasks into multiple data processing subtasks (or data-intensive subtasks) according to the storage location of the data through the subtask distribution module 3014, and send each data-intensive subtask to the corresponding storage node 302.

[0054] In some embodiments, the computing node 301 may send a data processing request to the storage node 302. The data processing request is used to instruct the storage node 302 to perform a data-intensive subtask. It should be noted that the data processing request is not an IO request. The data processing request is a message that pushes the data-intensive subtask down to the storage node. The data processing request may include a processing type, data location information, data calculation information, and description information. The processing type may refer to data intensive. The data location information is used to indicate the location information of the data storing the data-intensive subtask. For example, if the data of the data-intensive subtask is stored in a file system, the data location information includes information such as the file name. If the data of the data-intensive subtask is stored in a KV storage system, the data location information includes a K value (key). The data calculation information includes calculation instructions for the data-intensive subtask. The description information includes format information for processing data of the data-intensive subtask.

[0055] For example, assume that the data-intensive subtask is a data compression task. The data calculation information includes instructions related to data compression. The description information includes a compression format for compressing the data. The compression format may be RAR.

[0056] After the processor 3021 of the storage node 302 receives the data processing request sent by the computing node 301, the processor 3021 sends a read request to the IO controller 3025 according to the data location information, and controls the IO controller 3025 to read the data of the data-intensive subtask from the local storage medium 3024 (such as: disk) and store it in the memory 3022. In some embodiments, if the processor 3021 determines that the data of the data-intensive subtask needs to be processed by the memory 3022, the data can be stored in the DP-DIMM. In other embodiments, if the processor 3021 determines that the data of the data-intensive subtask is processed by itself, the data can be stored in the DIMM or DP-DIMM. The processor 3021 controls the memory controller 3023 to read the data from the memory 3022 and transmit it to the processor 3021. The processor 3021 performs corresponding calculations on the data according to the data calculation information, and returns the final calculation result to the computing node 301. Therefore, the computing power of the storage node is used to process data nearby, avoiding data transmission on the network and IO bus, effectively reducing the occupancy rate of network resources and IO bus resources and the delay of data processing during data transmission.

[0057] When processing data-intensive subtasks, the processor 3021 of the storage node 302 not only requires a large number of IO bus operations, but also requires a large number of memory accesses. Therefore, the "memory wall" problem becomes a performance bottleneck for the storage node to process data-intensive subtasks.

[0058] In other embodiments, when the processor 3021 of the storage node 302 processes a data-intensive subtask, in order to avoid the "memory wall" problem, the processor 3021 may offload the data-intensive kernel (or memory-intensive kernel) in the data-intensive subtask to the DP-DIMM. The DP-DIMM processes the data-intensive kernel, thereby avoiding the processor 3021 from frequently accessing the memory 3022 and reducing the transmission of data on the memory bus.

[0059] In this embodiment, DP-DIMM refers to a memory in which a processing unit is integrated in DIMM. The processing unit in DP-DIMM can perform specific calculations on data, greatly reducing the access of processor 3021 in storage node 302 to memory 3022. Multiple DP-DIMMs can be equipped in each storage node 302. DP-DIMM can be inserted into a memory slot and directly connected to a memory bus.

[0060] like Figure 4As shown, it is a structural example diagram of a DP-DIMM provided in an embodiment of the present application. The DP-DIMM includes a processing unit 401 and a memory 402. In some embodiments, the memory 402 may refer to a memory unit, on which at least one memory particle (such as a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM)) is integrated. Depending on the storage capacity of the memory unit in the DP-DIMM, one or more processing units 401 may be integrated in the DP-DIMM. The processing unit 401 may receive at least one instruction (such as a data-intensive program segment) sent by the processor 3021, which is used to instruct the processing unit 401 to process the data of the data-intensive program segment. Each instruction includes the address where the data is located in the memory and the operation type. The operation types include, but are not limited to, addition, subtraction, multiplication and division. In other embodiments, the processing unit 401 receives an instruction, reads data from the memory 402, processes the data, and can feed the processed data back to the processor 3021, or store the processed data in the memory 402, waiting for the processor 3021 to obtain the processed data from the memory 402. The processor 3021 can send the processed data to the computing node 301.

[0061] In some embodiments, the storage node 302 also includes a network card, which can read data from the memory and send the processed data to the computing node 301 via Remote Direct Memory Access (RDMA).

[0062] Furthermore, the DP-DIMM may also include a cache 403 and a memory controller 404. The cache is used to store at least one instruction sent by the processor 3021. The memory controller 404 is used to determine the physical address of the data in the memory 402 according to the at least one instruction, obtain the data from the memory 402 according to the physical address, and transmit the data to the processing unit 401.

[0063] In some embodiments, the memory controller 404 may be integrated into the DP-DIMM, but the memory controller 404 and the processing unit 401 are two different components.

[0064] In some embodiments, the storage node 302 may include N DP-DIMMs, each DP-DIMM includes M processing units, N and M are both integers, N≥1, M≥1. After receiving the data-intensive subtask, the processor 3021 determines the storage capacity requirement and computing requirement required to process the data-intensive subtask, and the processor 3021 may determine at least one DP-DIMM that meets the storage capacity requirement based on the remaining storage capacity of the N DP-DIMMs, and then the processor 3021 determines a DP-DIMM that meets the computing requirement from the at least one DP-DIMM.

[0065] In some other embodiments, the DP-DIMM may further include a status register 405, and the status register 405 is used to indicate the use status of the M processing units included in the DP-DIMM. The processor 3021 may determine a DP-DIMM that meets the computing requirement from at least one DP-DIMM according to the indication information of the status register of each DP-DIMM.

[0066] In this embodiment, the M processing units 401, the memory controller 404, the status register 405 and the cache 403 may be integrated together to be called an on-chip processor.

[0067] For example, for an on-chip processor having four processing units, "1111" indicates that each processing unit is occupied, and "1001" indicates that processing unit 1 and processing unit 4 are occupied, and processing unit 2 and processing unit 3 are available.

[0068] It should be noted that a DP-DIMM may include multiple on-chip processors, and the present application does not limit the number of on-chip processors. Each on-chip processor may be connected to the memory 402 .

[0069] The pluggable DIMM-based DP-DIMM provided by the embodiment of the present application, that is, a multi-core processor or a single instruction multiple data stream (Single Instruction Multiple Data, SIMD) processor is integrated in the DIMM, and the calculation of data-intensive program segments is completed directly in the DIMM. If a SIMD processor is used, multiple processing units can be used at the same time to achieve parallel computing. Compared with Oracle Exadata, the processor occupancy of the storage node can be reduced by 20%, and more processor resources can be reserved for other storage services. At the same time, the execution time of data-intensive subtasks is reduced by more than 50%.

[0070] In some embodiments, if the processor 3021 does not determine an available DP-DIMM, in order to avoid data processing delays caused by waiting for the DP-DIMM, the data-intensive program segment will not be offloaded to the DP-DIMM, but the data-intensive program segment will be processed using traditional processor computing methods.

[0071] like Figure 5 As shown, it is a schematic diagram of a near data processing provided by an embodiment of the present application. The application server pushes down the data-intensive subtask to the storage node storing the corresponding data. When the storage node processes the data-intensive subtask, it pushes down the data-intensive program segment to the DP-DIMM, and the DP-DIMM processes the data-intensive program segment.

[0072] In order to facilitate the use of DP-DIMM by the processor of the storage node, the present application provides a programming interface for DP-DIMM. For example, the programming interface of DP-DIMM may be CreatePIMContext(). When the processor of the storage node executes the statement CreatePIMContext(), it selects a suitable DP-DIMM to unload the data-intensive program segment, and stores the data of the data-intensive program segment in the selected DP-DIMM. If there is no suitable DP-DIMM, the unloading will not be performed. The data-intensive program segment that needs to be unloaded to the DP-DIMM for execution can be defined using PIMKernelBegin() and PIMKernelEnd().

[0073] As an example, the following is an example of offloading the convolution operation in a neural network algorithm to DP-DIMM for execution.

[0074]

[0075]

[0076] Figure 6 A flow chart of a method for processing data provided in an embodiment of the present application. Figure 3 The computing node 301 and the storage node 302 shown in the figure are used as examples for explanation. The computing node 301 may refer to an application server. The storage node 302 includes a processor 3021 and a memory 3022. The memory 3022 includes a DIMM and a DP-DIMM. The DP-DIMM included in the memory 3022 includes a processing unit and a memory. The DP-DIMM included in the memory 3022 may be as follows: Figure 4 The DP-DIMM shown. The processing unit can be Figure 4 The processing unit 401 is shown. The memory may be Figure 4 The memory 402 shown. Figure 6Said method comprises the following steps.

[0077] S601: An application server sends a data processing request to a storage node.

[0078] S602: The processor of the storage node receives a data processing request.

[0079] S603: The processor reads data into a memory of the memory according to the data processing request.

[0080] In some embodiments, the processor reads data from a storage medium (eg, a disk) of a storage node according to a data processing request, and then stores the data in a memory of the memory. It is assumed here that the memory refers to the DP-DIMM described in the above embodiments.

[0081] S604: The processor sends at least one instruction to the processing unit.

[0082] Instructions are used to instruct the processing unit to process data.

[0083] S605: The processing unit reads data from the storage device in the memory.

[0084] S606: The processing unit processes the data.

[0085] S607: The processing unit feeds back the processed data to the processor.

[0086] S608: The processor receives the processed data fed back by the processing unit.

[0087] S609: The processor sends the processed data to the application server.

[0088] For the specific implementation method of processing data, please refer to the description of the above embodiments and will not be elaborated here.

[0089] Therefore, by adding processing units to the memory, the processor of the storage node instructs the processing unit in the memory to process data-intensive tasks, avoiding the movement of data on the memory bus, effectively improving the processing speed of the storage node in processing data-intensive subtasks, and reducing the latency of data processing. The amount of data transmission between the storage node and the computing node is greatly reduced, and application performance is improved. For data-intensive tasks, such as OLAP, the amount of data transmission between the computing node and the storage node can be reduced by more than 5 times, and the performance can be improved by 5-10 times.

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A storage node, characterized in that: The storage node includes a processor and a memory, the memory includes a processing unit and a storage, the memory also includes a memory controller, and the memory controller is different from the processing unit, wherein: The processor is used to receive a data processing request sent by an application server, and read data into the memory of the memory according to the data processing request; The processor is further used to send at least one instruction to the processing unit, wherein the instruction is used to instruct the processing unit to process the data; The processor is further configured to send the processed data to the application server.

2. The storage node according to claim 1, characterized in that: Each of the instructions includes the address where the data is located in the memory and an operation type.

3. The storage node according to claim 1, characterized in that: The memory further includes a cache, and the cache is used to store the at least one instruction.

4. The storage node according to any one of claims 1 to 3, characterized in that: The storage node includes N memories, where N is an integer, N≥1, wherein: The processor is further configured to determine at least one memory that meets the storage capacity requirement according to the remaining storage capacity of the N memories; The processor is further configured to determine a memory that meets the computing requirement from the at least one memory.

5. The storage node according to claim 4, characterized in that: The memory includes M processing units, where M is an integer, M≥1, and the memory also includes a status register, which is used to indicate the usage status of the M processing units included in the memory, wherein: The processor is used to determine a memory that meets the computing requirement from the at least one memory according to the indication information of the status register of each memory.

6. A distributed system, characterized in that: The distributed system includes an application server and a storage node, the storage node includes a processor and a memory, the memory includes a processing unit and a storage, the memory also includes a memory controller, and the memory controller is different from the processing unit, wherein: The application server is used to send a data processing request to the storage node; The processor is used to receive a data processing request sent by an application server, and read data into the memory of the memory according to the data processing request; The processor is further used to send at least one instruction to the processing unit, wherein the instruction is used to instruct the processing unit to process the data; The processor is also used to send the processed data to the application server; The application server is used to receive the processed data sent by the storage node.

7. A method for processing data, characterized in that The method is applied to a storage node, the storage node includes a processor and a memory, the memory includes a processing unit and a storage, the memory also includes a memory controller, the memory controller is different from the processing unit, and the method includes: The processor receives a data processing request sent by the application server, and reads data into the memory of the memory according to the data processing request; The processor sends at least one instruction to the processing unit, where the instruction is used to instruct the processing unit to process the data; The processor sends the processed data to the application server.

8. The distributed system according to claim 6 or the method according to claim 7, characterized in that: Each of the instructions includes the address where the data is located in the memory and an operation type.

9. The distributed system according to claim 6 or the method according to claim 7, characterized in that: The memory further includes a cache, and the cache is used to store the at least one instruction.

10. A computer-readable storage medium, characterized in that: include: Computer software instructions; When the computer software instructions are executed in a computer device or a chip built in the computer device, the computer device is caused to execute the method according to any one of claims 7 to 9.

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