Memory controller and memory system comprising the same

Abstract

Memory controllers and memory systems including the same are disclosed. The memory controller is configured to control a memory module, the memory controller comprising: processing circuitry configured to: perform ECC decoding of a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome; determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome; and output a decode status flag indicative of the type of error.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0114283, filed on September 17, 2019, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Some example embodiments of the present disclosure relate to a memory, and more particularly, to a memory controller and a memory system including the same. BACKGROUND

[0003] Memory devices can be implemented using semiconductors including, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Memory devices are generally classified into volatile memory devices and non-volatile memory devices.

[0004] A volatile memory device refers to a memory device in which stored data is lost when a power supply is turned off. On the other hand, a non-volatile memory device refers to a memory device that retains stored data when a power supply is turned off. Because a dynamic random access memory (DRAM), which is one type of volatile memory device, has a high access speed, the DRAM is widely used as a working memory, a buffer memory, a main memory, etc. of a computing system. SUMMARY

[0005] Some example embodiments provide a memory controller capable of efficiently determining a type of an error occurring in a memory module.

[0006] Some example embodiments provide a memory system including a memory controller capable of efficiently determining a type of an error occurring in a memory module.

[0007] According to some example embodiments, a memory controller configured to control a memory module is provided, the memory controller including: processing circuitry configured to: perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome; determine a type of an error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome; and output a decode status flag indicating the type of the error.

[0008] According to some example embodiments, a memory system is provided, the memory system comprising: a memory module; and a memory controller including processing circuitry configured to: perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first corrector and a second corrector; determine the type of error in the read codeword based on the second corrector and a decision corrector, the decision corrector corresponding to the sum of the first and second correctors; and output a decoding status flag indicating the type of error.

[0009] According to some example embodiments, a memory controller is provided, configured to control a memory module. The memory controller includes: processing circuitry configured to: perform ECC encoding on a user dataset and metadata using a parity generation matrix to generate error location parity data, first error size parity data, and second error size parity data; output an output codeword to the memory module, the output codeword including the user dataset, metadata, error location parity data, first error size parity data, and second error size parity data; perform ECC decoding on a read codeword from the memory module using a first portion of the parity matrix to generate a first corrector and a second corrector; determine the type of error in the read codeword based on the second corrector and a decision corrector, the decision corrector corresponding to the sum of the first and second correctors; and output a decoding status flag indicating the type of error.

[0010] According to some example embodiments, the memory controller can perform ECC decoding on a read codeword from a memory module using a first portion of the parity check matrix to generate a first corrector and a second corrector; the type of error in the codeword can be selectively determined based on the second corrector and a decision corrector corresponding to the sum of the first and second correctors. Therefore, the memory controller can improve the speed and efficiency of error determination. Attached Figure Description

[0011] The above and other features of this disclosure will become clearer by referring to the accompanying drawings and describing some exemplary embodiments of this disclosure in detail.

[0012] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments.

[0013] Figure 2 This illustrates some example embodiments. Figure 1 A block diagram of the memory controller in a memory system.

[0014] Figure 3 The illustration shows the relationship with some example embodiments. Figure 1The dataset corresponding to multiple burst lengths in the memory system.

[0015] Figure 4 This illustrates some example embodiments. Figure 1 A block diagram of one of the data chips in the memory module.

[0016] Figure 5 Illustrations based on some example embodiments Figure 4 The first storage array of the data chip.

[0017] Figure 6 This illustrates some example embodiments. Figure 2 A block diagram of an example ECC engine in the example.

[0018] Figure 7 Showing stored Figure 6 The parity generation matrix in the memory of the ECC engine.

[0019] Figure 8 The basic offset submatrix used to generate the offset submatrix in the first parity submatrix is ​​shown.

[0020] Figure 9 Show Figure 7 The zero submatrix in the parity check generation matrix.

[0021] Figure 10 Show Figure 7 The identity submatrix in the parity check generation matrix.

[0022] Figure 11 Illustrations based on some example embodiments Figure 6 An example of an ECC encoder in an ECC engine.

[0023] Figure 12 Showing stored Figure 6 The parity check matrix in the memory of the ECC engine.

[0024] Figure 13 The offset submatrix is ​​shown.

[0025] Figure 14 Illustrations based on some example embodiments Figure 6 An example of an ECC decoder in an ECC engine.

[0026] Figure 15 Show Figure 14 The operation of the error size syndrome generator in the ECC decoder.

[0027] Figure 16 Show Figure 14The operation of the shift error size corrector generator and adder in the ECC decoder.

[0028] Figure 17 Examples are shown for a read word corresponding to a data chip, an associated sub-corrector of a decision corrector, and an associated sub-corrector of a second corrector.

[0029] Figure 18 Show Figure 14 The ECC decoder in the code determines the type of error based on the decision corrector and the second corrector.

[0030] Figure 19 This is a flowchart illustrating a method for determining the type of error in a memory controller according to some example embodiments.

[0031] Figure 20 This is a flowchart illustrating a method of operating a memory system including a memory module and a memory controller for controlling the memory module according to some example embodiments.

[0032] Figure 21 This is a block diagram illustrating a memory module that can be used by a memory system according to some example embodiments.

[0033] Figure 22 This is a block diagram illustrating a memory system with four-rank memory modules according to some example embodiments.

[0034] Figure 23 This is a block diagram illustrating a mobile system 900 including a memory module according to some example embodiments. Detailed Implementation

[0035] Some exemplary embodiments of this disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals denote the same elements.

[0036] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments.

[0037] Reference Figure 1 The memory system 20 may include a memory controller 100 and / or a memory module MM. The memory module MM may include multiple memory chips 200a to 200k, 200pa, and / or 200pb. The multiple memory chips 200a to 200k, 200pa, and / or 200pb may include multiple data chips 200a to 200k, a first parity check chip 200pa, and / or a second parity check chip 200pb.

[0038] The memory controller 100 controls the overall operation of the memory system 20. The memory controller 100 controls the overall data exchange between the host and multiple memory chips 200a to 200k, 200pa, and / or 200pb. For example, the memory controller 100 can write data to the multiple memory chips 200a to 200k, 200pa, and / or 200pb, and / or read data from the multiple memory chips 200a to 200k, 200pa, and / or 200pb in response to a request from the host. Additionally, the memory controller 100 can issue operation commands to the multiple memory chips 200a to 200k, 200pa, and / or 200pb to control them.

[0039] In some example embodiments, each of the plurality of memory chips 200a to 200k, 200pa, and / or 200pb may include volatile memory cells. For example, each of the plurality of memory chips 200a to 200k, 200pa, and / or 200pb may be implemented as dynamic random access memory (DRAM).

[0040] In some example embodiments, the number of data chips 200a to 200k may be 16. However, the number of data chips 200a to 200k is not limited to this. In some example embodiments, each of the data chips 200a to 200k may be referred to as a data memory, and each of the parity check chips 200pa and 200pb may be referred to as an error correction code (ECC) memory or redundant memory.

[0041] The memory controller 100 can send address ADDR and / or command CMD to the memory module MM, and / or exchange codeword CW with the memory module MM.

[0042] The memory controller 100 may include an error correction code (ECC) engine 130, which may perform ECC encoding (“performing ECC encoding” may also be referred to as “ECC encoding”) on the user dataset and / or metadata to generate a parity dataset, and / or may provide codewords including the user dataset, metadata, and / or parity dataset to the memory module MM during write operations of the memory system 20. The user dataset may be stored in data chips 200a to 200k, a first portion of the parity dataset and / or metadata may be stored in a first parity chip 200pa, and / or a second portion of the parity dataset may be stored in a second parity chip 200pb.

[0043] Additionally, the ECC engine 130 can use the first part of the parity check matrix to perform ECC decoding on the codeword CW read from the memory module MM ("performing ECC decoding" may also be referred to as "ECC decoding") to generate a first syndrome and a second syndrome. The type of error (which may represent a single error or multiple errors, also referred to as "error type") can be determined based on the second syndrome and a decision syndrome corresponding to the sum of the first and second syndromes, and / or a decoding status flag indicating the determined result can be output.

[0044] ECC engine 130 may output a decoding status flag indicating that the user dataset includes correctable errors in response to a determination that the corrector has a non-zero logic level, and may generate a third corrector indicating the location of correctable errors based on a second part of the parity check matrix and the codeword CW, and / or correctable errors in the correctable user dataset to output a corrected user dataset. According to some example embodiments, operations described herein as being performed by memory controller 100 and / or ECC engine 130 may be performed by processing circuitry. As used herein, the term "processing circuitry" may refer to, for example, hardware including logic circuitry, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0045] Since the probability that the codeword CW does not contain errors or contains uncorrectable errors is much higher than the probability that the codeword CW contains correctable errors, the ECC engine 130 can determine whether the codeword CW does not contain errors or contains uncorrectable errors more quickly and with less computation based on the decision corrector compared to the case where the codeword CW contains correctable errors. Therefore, the ECC engine 130 can improve the speed and / or efficiency of error determination.

[0046] Figure 2 This illustrates some example embodiments. Figure 1 A block diagram of the memory controller in a memory system.

[0047] Reference Figure 2The memory controller 100 may include processing circuitry (e.g., a central processing unit (CPU)) 110 (hereinafter referred to as CPU 110), a host interface 120, a data register 125, an ECC engine 130, a command buffer 190, and / or an address buffer 195. The ECC engine 130 may include an ECC encoder 140, an ECC decoder 150, and / or a memory 180.

[0048] Host interface 120 can receive requests (REQ) and / or user datasets (SDQ) from the host, generate metadata (MDT) associated with the user datasets (SDQ), provide the user datasets (SDQ) to data register 125, and / or provide the metadata (MDT) to ECC encoder 140. Data register 125 can continuously (or sequentially) output the user datasets (SDQ) to ECC engine 130.

[0049] ECC encoder 140 can perform ECC encoding on user dataset SDQ and metadata MDT using a parity generation matrix to generate a first codeword CW1. ECC decoder 150 can output a decoding status flag DSF to CPU 110 using a portion of the parity matrix, and / or provide user dataset SDQ and / or corrected user dataset C_SDQ to CPU 110 using the parity matrix. Memory 180 can store the parity generation matrix and the parity matrix.

[0050] CPU 110 can receive user dataset SDQ or corrected user dataset C_SDQ, and / or control host interface 120, data register 125, ECC engine 130, command buffer 190, and / or address buffer 195. Command buffer 190 can store the command CMD corresponding to the request REQ, and under the control of CPU 110, send the command CMD to memory module MM. Address buffer 195 can store address ADDR, and under the control of CPU 110, send the address ADDR to memory module MM.

[0051] Figure 3 The illustration shows the relationship with some example embodiments. Figure 1 The dataset corresponding to multiple burst lengths in the memory system.

[0052] Reference Figure 3 Each of the data chips 200a to 200k and the parity chips 200pa and 200pb can perform burst operations. Here, a burst operation refers to the operation of writing or reading a large amount of data by sequentially incrementing or decrementing an initial address provided from the memory controller 100. The basic unit of a burst operation may be referred to as the burst length BL.

[0053] Reference Figure 3Each dataset from DQ_BL1 to DQ_BLk, corresponding to multiple burst lengths, can be input to each of the data chips 200a to 200k and output from each of the data chips 200a to 200k.

[0054] Each dataset in datasets DQ_BL1 through DQ_BLk may include data segments DQ_BL_SG11 through DQ_BL_SG14 and DQ_BL_SG21 through DQ_BL_SG24 corresponding to each of the multiple burst lengths. In one example, each data segment may include data DQ1, DQ2, DQ3, and DQ4. Datasets DQ_BL1 through DQ_BLK may correspond to user dataset SDQ. Figure 3 It is assumed that the burst length is 4, and that the burst operation is performed twice. When two burst operations are performed in each of the data chips 200a to 200k, the metadata MDT and error locating parity data PRTL corresponding to multiple burst lengths can be input to / output from the first parity chip 200pa, and the first error magnitude parity data PRTM1 and the second error magnitude parity data PRTM2 corresponding to multiple burst lengths can be input to / output from the second parity chip 200pb.

[0055] Figure 4 This illustrates some example embodiments. Figure 1 A block diagram of one of the data chips in the memory module.

[0056] Reference Figure 4 The data chip 200a may include control logic circuitry 210, address register 220, bank control logic circuitry 230, row address multiplexer 240, column address latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, input / output (I / O) gating circuitry 290, data input / output (I / O) buffer 295, and / or refresh counter 245.

[0057] The memory cell array 300 may include a first memory array 310 to an eighth memory array 380 (e.g., the first memory array to the eighth memory array 310, 320, 330, 340, 350, 360, 370 and 380).

[0058] The row decoder 260 may include first memory bank row decoders 260a to 260h respectively connected to the first memory bank array 310 to the eighth memory bank array 380, the column decoder 270 may include first memory bank column decoders 270a to 270h respectively connected to the first memory bank array 310 to the eighth memory bank array 380, and the sense amplifier unit 285 may include first memory bank sense amplifiers 285a to 285h respectively connected to the first memory bank array 310 to the eighth memory bank array 380.

[0059] First memory arrays 310 to eighth memory arrays 380, first memory row decoders 260a to eighth memory row decoders 260h, first memory column decoders 270a to eighth memory column decoders 270h, and first memory sense amplifiers 285a to eighth memory sense amplifiers 285h can form first to eighth memory arrays. Each memory array in the first memory arrays 310 to eighth memory arrays 380 may include multiple word lines WL, multiple bit lines BTL, and multiple memory cells MC formed at the intersection of word lines WL and bit lines BTL.

[0060] Despite Figure 4 The data chip 200a is shown as including eight memory cells, but the data chip 200a may include any number of memory cells.

[0061] Address register 220 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from memory controller 100. Address register 220 can provide the received bank address BANK_ADDR to memory control logic circuit 230, provide the received row address ROW_ADDR to row address multiplexer 240, and provide the received column address COL_ADDR to column address latch 250.

[0062] The memory bank control logic circuit 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first memory bank row decoders 260a to the eighth memory bank row decoder 260h, corresponding to the memory bank address BANK_ADDR, can be activated in response to the memory bank control signal, and one of the first memory bank column decoders 270a to the eighth memory bank column decoder 270h, corresponding to the memory bank address BANK_ADDR, can be activated in response to the memory bank control signal.

[0063] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 can be applied to the first memory bank row decoders 260a to the eighth memory bank row decoders 260h.

[0064] The activated bank row decoder in the first bank row decoder 260a to the eighth bank row decoder 260h can decode the row address RA output from the row address multiplexer 240 and can activate the word line WL corresponding to the row address RA. For example, the activated bank row decoder can generate a word line drive voltage and can apply the word line drive voltage to the word line WL corresponding to the row address RA.

[0065] Column address latch 250 can receive column address COL_ADDR from address register 220 and can temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode, column address latch 250 can generate a column address incremented from the received column address COL_ADDR. Column address latch 250 can apply the temporarily stored or generated column address to first bank column decoders 270a to eighth bank column decoders 270h.

[0066] The activated memory bank column decoders in the first to eighth memory bank column decoders 270a and 270h can decode the column address COL_ADDR output from the column address latch 250 and control the I / O strobe circuit 290 to output data corresponding to the column address COL_ADDR.

[0067] I / O gating circuit 290 may include circuitry for gating input / output data. I / O gating circuit 290 may also include a read data latch for storing data output from the first memory array 310 to the eighth memory array 380, and a write control device for writing data to the first memory array 310 to the eighth memory array 380.

[0068] Data read from one of the memory arrays 310 to 380 can be sensed by a sensing amplifier connected to the memory array from which data will be read, and can be stored in a read data latch.

[0069] After the ECC engine 130 performs ECC decoding on the data (e.g., codeword CW), the data stored in the read data latch can be provided to the memory controller 100 via the data I / O buffer 295. The dataset DQ_BL to be written to one of the memory arrays 310 to 380 can be provided from the memory controller 100 to the data I / O buffer 295. The data I / O buffer 295 can then provide the dataset DQ_BL to the I / O strobe circuit 290.

[0070] Control logic circuitry 210 can control the operation of data chip 200a. For example, control logic circuitry 210 can generate control signals for data chip 200a to perform write and / or read operations. Control logic circuitry 210 may include command decoder 211 for decoding commands CMD received from memory controller 100 and mode register 212 for setting the operating mode of data chip 200a. According to some example embodiments, operations described herein as being performed by control logic circuitry 210 may be performed by processing circuitry.

[0071] Each parity check chip in parity check chips 200pa and 200pb may have the same or substantially the same configuration as data chip 200a. Each parity check chip in parity check chips 200pa and 200pb may input / output corresponding parity check data.

[0072] Figure 5 Illustrations based on some example embodiments Figure 4 The first storage array of the data chip.

[0073] Reference Figure 5 The first memory bank array 310 includes multiple word lines WL1 to WL2m (where m is a natural number greater than 2), multiple bit lines BTL1 to BTL2n (where n is a natural number greater than 2), and multiple memory cells MC disposed near the intersections of the word lines WL1 to WL2m and the bit lines BTL1 to BTL2n. In some example embodiments, each memory cell in the multiple memory cells MC may include a DRAM cell structure. The multiple word lines WL1 to WL2m to which the multiple memory cells MC are connected may be referred to as rows of the first memory bank array 310, and the multiple bit lines BL1 to BL2n to which the multiple memory cells MC are connected may be referred to as columns of the first memory bank array 310.

[0074] Figure 6 This illustrates some example embodiments. Figure 2 A block diagram of an example ECC engine in the example.

[0075] Reference Figure 6The ECC engine 130 includes an ECC encoder 140, an ECC decoder 150, and / or a memory 180. The memory 180 may be referred to as ECC memory 180.

[0076] The memory 180 is connected to the ECC encoder 140 and / or the ECC decoder 150, and can store the parity generation matrix PGM and / or the parity check matrix PCM.

[0077] ECC encoder 140 can perform ECC encoding on user dataset SDQ and metadata MDT using parity generator matrix PGM to generate parity dataset SPRT, which includes error location parity data PRTL, first error size parity data PRTM1, and second error size parity data PRTM2, and can output codeword CW1 including user dataset SDQ, metadata MDT, and parity dataset SPRT.

[0078] ECC decoder 150 can receive read codeword CW2 from memory module MM, which includes user dataset SDQ, metadata MDT, and parity dataset SPRT. ECC decoder 150 can perform ECC decoding on read codeword CW2 using the first part of parity matrix PCM to generate a decoding status flag DSF indicating that user dataset SDQ includes correctable errors while outputting user dataset SDQ.

[0079] ECC decoder 150 can, in response to an indication that the user dataset SDQ includes a decoded status flag DSF with correctable errors, correct errors in the user dataset SDQ by using the second part of the parity check matrix PCM, and can output the corrected user dataset C_SDQ.

[0080] Figure 7 Showing stored Figure 6 The parity generation matrix in the memory of the ECC engine.

[0081] Reference Figure 7 The parity generation matrix PGM may include a first parity submatrix HS. 11 Second parity check submatrix HS 12 and / or the third parity check submatrix HS 13 .

[0082] First parity check submatrix HS 11This includes multiple offset sub-matrices OSM1 to OSM2k corresponding to data chips 200a to 200k, and two zero sub-matrices ZSM1 and ZSM2 corresponding to parity check chips 200pa and 200pb. Each sub-matrix in the offset sub-matrices OSM1 to OSM2k and the zero sub-matrices ZSM1 and ZSM2 contains p×p elements (p is a natural number greater than 1).

[0083] Second parity check submatrix HS 12 It includes multiple identity submatrices ISM1,1 to ISM1,(k+1) and multiple zero submatrices ZSM1,1 to ZSM1,(k+1). Each submatrix in the identity submatrices ISM1,1 to ISM1,(k+1) and the zero submatrices ZSM1,1 to ZSM1,(k+1) includes p×p elements. Furthermore, the identity submatrices ISM1,1 to ISM1,(k+1) and the zero submatrices ZSM1,1 to ZSM1,(k+1) are arranged alternately (e.g., arranged or placed in an alternating order).

[0084] The third parity check submatrix HS 13 It comprises multiple zero submatrices ZSM2,1 to ZSM2,(k+1) and multiple identity submatrices ISM2,1 to ISM2,(k+1). Each submatrix in the zero submatrices ZSM2,1 to ZSM2,(k+1) and the identity submatrices ISM2,1 to ISM2,(k+1) comprises p×p elements. Furthermore, the zero submatrices ZSM2,1 to ZSM2,(k+1) and the identity submatrices ISM2,1 to ISM2,(k+1) are arranged alternately.

[0085] Figure 8 The basic offset submatrix is ​​shown, which can be used to generate the offset submatrix in the first parity submatrix.

[0086] Reference Figure 8 The basic offset submatrix OSMb can include (p+3) high-level elements. The basic offset submatrix OSMb can be based on primitive polynomials (such as x...). 16 +x 12 +x 3 The p-th order primitive polynomial is obtained by adding x and 1. If the p-th order primitive polynomial changes, then the elements of each of the offset submatrices OSM1 to OSM2k can change.

[0087] The offset submatrix OSM1 in the offset submatrixes OSM1 to OSM2k can be obtained by raising the basic offset submatrix OSMb to a power. The offset submatrix OSM2 in the offset submatrixes OSM1 to OSM2k can be obtained by multiplying the "offset submatrix OSM1" and the "submatrix obtained by raising the offset power of the basic offset submatrix OSMb".

[0088] Furthermore, the gaps between the two offset sub-matrices OSM(2i-1) and OSM(2i) associated with a (memory) chip in offset sub-matrices OSM1 to OSM2k can be regular. Here, i is one of 1 to 8. That is, offset sub-matrix OSM4 can be obtained by multiplying "offset sub-matrix OSM3" and "the sub-matrix obtained by raising the offset power of the basic offset sub-matrix OSMb".

[0089] Figure 9 Show Figure 7 The zero submatrix in the parity check generation matrix.

[0090] Reference Figure 9 In the zero submatrix ZSM corresponding to each of the zero submatrixes ZSM1 and ZSM2, zero submatrixes ZSM1,1 to ZSM1,(k+1) and zero submatrixes ZSM2,1 to ZSM2,(k+1), each element is zero.

[0091] Figure 10 Show Figure 7 The identity submatrix in the parity check generation matrix.

[0092] Reference Figure 10 Each identity submatrix ISM, corresponding to each of the identity submatrixes ISM1,1 to ISM1,(k+1) and ISM2,1 to ISM2,(k+1), comprises p high-level elements arranged diagonally. All other elements are zero.

[0093] exist Figures 7 to 10 In this context, p can correspond to 16, and can also correspond to the number of bits in the dataset DQ_BL input to / output from each of the data chips 200a to 200k during a burst operation. Additionally, the first parity submatrix HS... 11 The number of non-zero elements in the matrix can be greater than that in the second parity check submatrix HS. 12 The number of non-zero elements or the third parity check submatrix HS 13 The number of non-zero elements in the array.

[0094] Figure 11 Illustrations based on some example embodimentsFigure 6 An example of an ECC encoder in an ECC engine.

[0095] Reference Figure 11 The ECC encoder 140 includes an error location parity generator 141, a first error size parity generator 143, a second error size parity generator 145, and / or a buffer 147. According to some example embodiments, the operations described herein performed by the ECC encoder 140, the error location parity generator 141, the first error size parity generator 143, the second error size parity generator 145, and / or the buffer 147 (e.g., providing codeword CW1 to the memory module MM) can be performed by processing circuitry.

[0096] Error location parity generator 141 can be achieved by using the first parity submatrix HS 11 ECC encoding is performed on the user dataset SDQ and metadata MDT to generate error location parity data PRTL, which can be used to determine the location of errors, and the error location parity data PRTL is provided to buffer 147.

[0097] Error location parity generator 141 can be achieved by using the first parity submatrix HS 11 Matrix multiplication is performed on the user dataset SDQ and metadata MDT to generate error location parity data PRTL. If the vector representations of the user dataset SDQ and metadata MDT correspond to ms, and the vector representation of the error location parity data PRTL corresponds to p... L Then p L =HS 11 [ms 0] T Here, T represents the transpose matrix, and 0 represents the zero matrix.

[0098] The first error size parity generator 143 can be used by employing the second parity submatrix HS. 12 ECC encoding is performed on the user dataset SDQ, metadata MDT, and error location parity data PRTL to generate first error size parity data PRTM1, which can be used to determine the number of errors, and the first error size parity data PRTM1 is provided to buffer 147.

[0099] The first error size parity generator 143 can be obtained by using the second parity submatrix HS. 12 Matrix multiplication is performed on the user dataset SDQ, metadata MDT, and error location parity data PRTL to generate the first error size parity data PRTM1. If the vector representation of the first error size parity data PRTM1 corresponds to p... M1 Then pM1 =HS 12 [ms p L 0] T .

[0100] The second error size parity generator 145 can be used by employing the third parity submatrix HS. 13 ECC encoding is performed on the user dataset SDQ, metadata MDT, and error location parity data PRTL to generate a second error size parity data PRTM2 that can be used to determine the number of errors, and the second error size parity data PRTM2 is provided to buffer 147.

[0101] The second error size parity generator 145 can be obtained by using the third parity submatrix HS. 13 Matrix multiplication is performed on the user dataset SDQ, metadata MDT, and error location parity data PRTL to generate a second error size parity data PRTM2. If the vector representation of the second error size parity data PRTM2 corresponds to p... M2 Then p M2 =HS 13 [ms p L 0] T .

[0102] Buffer 147 can receive user dataset SDQ, metadata MDT, error location parity data PRTL, first error size parity data PRTM1, and second error size parity data PRTM2, and provide the codeword CW1 (also referred to as output codeword CW1 or write codeword CW1) including user dataset SDQ, metadata MDT, error location parity data PRTL, first error size parity data PRTM1, and second error size parity data PRTM2 to memory module MM.

[0103] Figure 12 Showing stored Figure 6 The parity check matrix in the memory of the ECC engine.

[0104] Reference Figure 12 The parity check matrix PCM may include a first parity check submatrix HS. 21 Second parity check submatrix HS 22 and the third parity check submatrix HS 23 .

[0105] First parity check submatrix HS 21This includes multiple offset sub-matrices OSM1 to OSM2k corresponding to data chips 200a to 200k, and two zero sub-matrices ZSM1 and ZSM2 corresponding to parity check chips 200pa and 200pb. Each sub-matrix in the offset sub-matrices OSM1 to OSM2k and the zero sub-matrices ZSM1 and ZSM2 includes p×p elements.

[0106] Second parity check submatrix HS 22 It includes multiple identity submatrices ISM1,1 to ISM1,(k+1) and multiple zero submatrices ZSM1,1 to ZSM1,(k+1). Each submatrix in the identity submatrices ISM1,1 to ISM1,(k+1) and the zero submatrices ZSM1,1 to ZSM1,(k+1) includes p×p elements. Furthermore, the identity submatrices ISM1,1 to ISM1,(k+1) and the zero submatrices ZSM1,1 to ZSM1,(k+1) are arranged alternately.

[0107] The third parity check submatrix HS 23 It includes multiple zero submatrices ZSM2,1 to ZSM2,(k+1) and multiple offset submatrices OSM. Each submatrix in the zero submatrices ZSM2,1 to ZSM2,(k+1) and the offset submatrix OSM includes p×p elements. In addition, the zero submatrices ZSM2,1 to ZSM2,(k+1) and the offset submatrix OSM are arranged alternately.

[0108] Reference Figure 7 and Figure 12 The first parity check submatrix HS 21 Can be combined with the first parity check submatrix HS 11 Same or similar, second parity check submatrix HS 22 Can be combined with the second parity check submatrix HS 12 Same or similar. Third parity check submatrix HS 23 The first parity check submatrix HS of the parity check generator matrix PGM can be obtained by... 11 Second parity check submatrix HS 12 and the third parity check submatrix HS 13 It is obtained by performing linear combination operations. Since linear combination operations on the elements in the rows of the matrix do not change the ECC structure, the third parity submatrix HS is obtained. 23 It can be used as a corrector. Additionally, Figure 6 The ECC encoder 140 and ECC decoder 150 can share the parity generation matrix PGM, and perform ECC encoding and ECC decoding respectively. According to some example embodiments, the parity generation matrix PCM can be equivalent to or similar to... Figure 6 The parity generation matrix PGM in the model.

[0109] Figure 13 Show Figure 12 The offset submatrix in.

[0110] Reference Figure 13 The offset submatrix OSM can be obtained by raising the offset ofs to the power of the basic offset submatrix OSMb.

[0111] Reference Figure 12 and Figure 13 The first parity check submatrix HS 21 The number of non-zero elements in the matrix can be greater than that in the second parity check submatrix HS. 22 The number of non-zero elements or the third parity check submatrix HS 23 The number of non-zero elements in the matrix. Therefore, Figure 6 The ECC decoder 150 in the middle can be used by using the second parity submatrix HS 22 and the third parity check submatrix HS 23 The first and second correctors are generated, and the codeword is used to determine whether it contains a correctable error before determining the error location. Therefore, the ECC decoder 150 can determine errors with higher speed and / or efficiency.

[0112] Figure 14 Illustrations based on some example embodiments Figure 6 An example of an ECC decoder in an ECC engine.

[0113] Reference Figure 14 The ECC decoder 150 includes an error size corrector generator 151, a shift error size corrector generator 152, an error location corrector generator 153, a data corrector 155, an adder 156, and / or a decoding status flag generator 154. According to some example embodiments, the operations described herein performed by the ECC decoder 150, the error size corrector generator 151, the shift error size corrector generator 152, the error location corrector generator 153, the data corrector 155, the adder 156, and / or the decoding status flag generator 154 can be performed by processing circuitry.

[0114] Error size corrector generator 151 can generate error size corrector by reading codeword CW2 and second parity check submatrix HS. 22 Perform matrix multiplication to generate the first corrector SDR_M, which indicates the number of errors. If the vector representation of the read codeword CW2 corresponds to r... T The vector representation of the first corrector SDR_M corresponds to S M0 Then S M0 =HS 22 r T .

[0115] The shift error size corrector generator 152 can generate the shift error size corrector by analyzing the read codeword CW2 and the third parity check submatrix HS. 23 Perform matrix multiplication to generate a second corrector SDR_MS that indicates the number of errors. If the vector representation of the second corrector SDR_MS corresponds to S... MS Then S MS =HS 23 r T Adder 156 can sum the first corrector SDR_M and the second corrector SDR_MS to generate a decision corrector SDR_D. If the vector representation of the decision corrector SDR_D corresponds to S... D Then S D =S M0 +S MS .

[0116] The decoding status flag generator 154 can generate an enable signal EN and a decoding status flag DSF that indicate whether the user dataset in the read codeword CW2 contains correctable errors, based on the logic levels of the second corrector SDR_MS and the decision corrector SDR_D.

[0117] The decoding status flag generator 154 can enable the enable signal EN in response to the determination that the corrector SDR_D has a non-zero logic level, and can generate a decoding status flag DSF indicating that the user dataset read from codeword CW2 includes correctable errors.

[0118] The decoding status flag generator 154 can disable the enable signal EN in response to the determination that the corrector SDR_D has a zero logic level, and can generate a decoding status flag DSF indicating whether the user dataset read from codeword CW2 includes uncorrectable errors or does not include errors.

[0119] The decoding status flag generator 154 may output a decoding status flag DSF indicating that the user dataset of the codeword CW2 includes uncorrectable errors in response to a determination that the corrector SDR_D has a zero logic level and the second corrector SDR_MS has a non-zero logic level.

[0120] Error location corrector generator 153 can be activated in response to an enabled signal EN, generate a third corrector SDR_L indicating the location of a correctable error in the read codeword CW2, and provide the third corrector SDR_L to the data corrector 155. If the vector representation of the third corrector SDR_L corresponds to S... L Then S L =HS 21 r T .

[0121] Data corrector 155 can selectively correct correctable errors in the user dataset of read codeword CW2 to output corrected user dataset C_SDQ or user dataset SDQ (e.g., output corrected user dataset C_SDQ or user dataset SDQ to a device and / or host outside the memory controller (e.g., memory controller 100) and / or memory system (e.g., memory system 20)).

[0122] Conventional ECC decoders perform calculations to determine the location of errors detected in a codeword, regardless of the type of error detected. Since the probability of a codeword containing a correctable error is lower than the probability of a codeword containing no errors or containing uncorrectable errors, many of the calculations performed by conventional ECC decoders to determine the location of errors are unnecessary, leading to excessive resource consumption (e.g., power consumption, processor usage, etc.) and latency. However, according to some example embodiments, the error location corrector generator 153 is activated to calculate the location of the error by generating a third corrector SDR_L only when the user dataset SDQ contains correctable errors. Therefore, unnecessary calculations performed by conventional ECC decoders are avoided, thereby reducing resource consumption (e.g., power consumption, processor usage, etc.) and latency. Thus, ECC decoder 150 can determine and / or correct errors with greater speed and / or efficiency.

[0123] Figure 15 Show Figure 14 The operation of the error size corrector generator in the ECC decoder.

[0124] Reference Figure 14 and Figure 15 The error size corrector generator 151 can generate the error size by analyzing the read codeword CW2 and the second parity check submatrix HS. 22 Perform matrix multiplication to generate a first corrector SDR_M that indicates the number of errors. In other words, the first corrector SDR_M can be generated via S... M0 =HS 22 r T It is generated. Due to the second parity submatrix HS 22The system comprises multiple identity submatrices ISM1,1 to ISM1,(k+1) and multiple zero submatrices ZSM1,1 to ZSM1,(k+1). Each submatrix in the identity submatrices ISM1,1 to ISM1,(k+1) and the zero submatrices ZSM1,1 to ZSM1,(k+1) consists of p×p elements, and the identity submatrices ISM1,1 to ISM1,(k+1) and the zero submatrices ZSM1,1 to ZSM1,(k+1) are arranged alternately. This reduces the number of XOR operations used to generate the first corrector SDR_M. Consequently, the computational complexity for generating the decoded state flag DSF is reduced.

[0125] Figure 16 Show Figure 14 The operation of the shift error size corrector generator and adder in the ECC decoder.

[0126] Reference Figure 14 and Figure 16 The shift error size corrector generator 152 can generate the shift error size by analyzing the read codeword CW2 and the third parity check submatrix HS. 23 Perform matrix multiplication to generate the second corrector SDR_MS. The second corrector SDR_MS can be generated via S... MS =HS 23 r T The adder 156 can sum the first corrector SDR_M and the second corrector SDR_MS to generate the decision corrector SDR_D. That is, the decision corrector SDR_D can be obtained through S... D =S M0 +S MS To obtain.

[0127] Figure 17 Examples are shown for a read word corresponding to a data chip, an associated sub-corrector of a determination corrector, and an associated sub-corrector of a second corrector.

[0128] Reference Figure 17 Determine the corrector S D The associated sub-corrector S D _sub can be accessed by reading the 32-bit read word RWORD S from the read codeword CW2 corresponding to a data chip. MS Second parity check submatrix HS 22 The identity submatrix ISM (e.g., identity submatrix ISM1,1) and the third parity check submatrix HS 23 The offset submatrix OSM is obtained by performing matrix multiplication, and the second corrector S MS The associated sub-corrector S MS_sub can be read from the 32-bit read word RWORD S in the read codeword CW2. MS The third parity check submatrix HS 23 The zero submatrix ZSM (e.g., zero submatrix ZSM2,1) and the offset submatrix OSM are obtained by performing matrix multiplication.

[0129] Figure 18 Show Figure 14 The ECC decoder in the system can determine the type of error based on the decision corrector and the second corrector.

[0130] Reference Figure 18 The ECC decoder 150 can be based on the decision corrector S corresponding to the data chip. D The sub-syndrome S D Whether _sub has a zero value (i.e., zero logic level) is used to determine whether the dataset read from the data chip contains correctable errors.

[0131] Determine the corrector S D The sub-syndrome S D _sub has a zero value and the second corrector S MS The sub-syndrome S MS _sub has a zero value indicating that the dataset read from the corresponding data chip does not include errors; this is denoted as "NE". The judgment corrector S D The sub-syndrome S D _sub has a zero value and the second corrector S MS The sub-syndrome S MS A non-zero value (i.e., a non-zero logic level) in _sub indicates that the dataset read from the corresponding data chip contains uncorrectable errors, which is denoted as "UE". The correction factor S is determined. D The sub-syndrome S D _sub has a non-zero value indicating that the dataset read from the corresponding data chip includes correctable errors, which is denoted as "CE".

[0132] Figure 19 This is a flowchart illustrating a method for determining the type of error in a memory controller according to some example embodiments.

[0133] Reference Figures 1 to 19 A method is provided for determining the type of error in a memory controller 100, which controls a memory module MM including multiple data chips, a first parity chip, and a second parity chip. According to this method, the memory controller 100 can read read codewords CW2 (operation S110) including user datasets, metadata, and parity datasets from the multiple data chips, the first parity chip, and the second parity chip.

[0134] The ECC decoder 150 of the ECC engine 130 in the memory controller 100 can read the codeword CW2 and the second parity submatrix HS. 22 Perform matrix multiplication to generate the first corrector SDR_M (operation S120).

[0135] The ECC decoder 150 can read the codeword CW2 and the third parity submatrix HS. 23 Perform matrix multiplication to generate the second corrector SDR_MS (operation S130).

[0136] The ECC decoder 150 can generate a decision corrector SDR_D by summing the first corrector SDR_M and the second corrector SDR_MS (operation S140).

[0137] The ECC decoder 150 can determine the type of error in reading the user dataset in the codeword CW2 based on the logic levels of the decision corrector SDR_D and the second corrector SDR_MS on a data chip-by-data chip basis (e.g., for each data chip) (operation S150).

[0138] ECC decoder 150 may output a decoding status flag (DSF) to CPU 110 in response to determining that the corrector SDR_D has a zero logic level, indicating whether the user dataset read from codeword CW2 includes uncorrectable errors or does not contain errors. ECC decoder 150 may also output a decoding status flag (DSF) to CPU 110 in response to determining that the corrector SDR_D has a non-zero logic level, indicating that the user dataset read from codeword CW2 includes correctable errors, and correct errors in the user dataset and output the corrected user dataset.

[0139] Figure 20 This is a flowchart illustrating a method of operating a memory system including a memory module and a memory controller for controlling the memory module according to some example embodiments.

[0140] Reference Figures 1 to 18 and Figure 20A method is provided for operating a memory system 20 including a memory module MM and a memory controller 100. The memory module MM includes multiple data chips, a first parity chip, and a second parity chip. The memory controller 100 can control the memory module MM. According to the method, the ECC encoder 140 of the ECC engine 130 in the memory controller 100 can perform ECC encoding on a user dataset and metadata based on a parity generation matrix to generate a parity dataset including first parity data (e.g., error location parity data PRTL), second parity data (e.g., first error size parity data PRTM1), and third parity data (e.g., second error size parity data PRTM2) (operation S210).

[0141] The memory controller 100 can store codeword CW1, which includes user dataset, metadata, and parity dataset, in multiple data chips, a first parity chip, and a second parity chip (operation S220).

[0142] The memory controller 100 can read read codewords CW2, including user dataset, metadata, and parity dataset, from multiple data chips, a first parity chip, and a second parity chip (operation S230).

[0143] The ECC decoder 150 of the ECC engine 130 can read the codeword CW2 and the second parity check submatrix HS. 22 Perform matrix multiplication to generate the first corrector SDR_M (operation S240).

[0144] The ECC decoder 150 can read the codeword CW2 and the third parity submatrix HS. 23 Perform matrix multiplication to generate the second corrector SDR_MS (operation S250).

[0145] The ECC decoder 150 can generate a decision corrector SDR_D by summing the first corrector SDR_M and the second corrector SDR_MS (operation S260).

[0146] The ECC decoder 150 can determine the type of error in the user dataset read from the codeword CW2 based on the logic levels of the judgment corrector SDR_D and the second corrector SDR_MS, on a data chip basis (operation S270).

[0147] Figure 21 This is a block diagram illustrating a memory module that can be used by a memory system according to some example embodiments.

[0148] Reference Figure 21The memory module 500 includes a control device 590 (RCD, registered clock driver) disposed in or mounted on the circuit board 501, multiple semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d and 604a to 604d, multiple data buffers (DB) 541 to 545 and 551 to 554, module resistor units 560 and 570, a serial presence detection (SPD) chip 580 and / or a power management integrated circuit (PMIC) 585.

[0149] Control device 590 can control semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d and 604a to 604d, and PMIC 585 under the control of memory controller 100. For example, control device 590 can receive address ADDR, command CMD and / or clock signal CK from memory controller 100.

[0150] SPD chip 580 may be a programmable read-only memory (PROM) (e.g., electrically erasable PROM (EEPROM)). SPD chip 580 may include initial information and / or device information DI of memory module 500. In some example embodiments, SPD chip 580 may include initial information and / or device information DI of memory module 500 (such as module form, module configuration, storage capacity, module type, and / or execution environment, etc.).

[0151] When the memory system including memory module 500 is started, memory controller 100 can read device information DI from SPD chip 580 and identify memory module 500 based on device information DI. Memory controller 100 can control memory module 500 based on device information DI from SPD chip 580. For example, memory controller 100 can identify the type of semiconductor memory device included in memory module 500 based on device information DI from SPD chip 580.

[0152] Here, the circuit board 501, which is a printed circuit board, can extend between a first edge portion 503 and a second edge portion 505 in a second direction D2 perpendicular to the first direction D1. The first edge portion 503 and the second edge portion 505 can extend in the first direction D1.

[0153] The control device 590 may be disposed at the center of the circuit board 501. Multiple semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d may be arranged in multiple rows between the control device 590 and the first edge portion 503, and between the control device 590 and the second edge portion 505. According to some example embodiments, operations described herein as being performed by the control device 590 may be performed by processing circuitry.

[0154] In this configuration, semiconductor memory devices 601a to 601e and 602a to 602e may be arranged along multiple rows between the control device 590 and the first edge portion 503. Semiconductor memory devices 603a to 603d and 604a to 604d may be arranged along multiple rows between the control device 590 and the second edge portion 505. Semiconductor memory devices 601a to 601d, 602a to 602d, 603a to 603d, and 604a to 604d may be referred to as data chips, and semiconductor memory devices 601e and 602e may be referred to as a first parity check chip and a second parity check chip, respectively.

[0155] Each of the plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d and 604a to 604d can be connected to a corresponding data buffer in data buffers 541 to 545 and 551 to 554 via a data transmission line for receiving / transmitting data signal DQ and data strobe signal DQS.

[0156] The control device 590 can provide command / address signals (e.g., CA) to semiconductor memory devices 601a to 601e via command / address transmission line 561, and can provide command / address signals to semiconductor memory devices 602a to 602e via command / address transmission line 563.

[0157] Additionally, the control device 590 can provide command / address signals to semiconductor memory devices 603a to 603d via command / address transmission line 571, and can also provide command / address signals to semiconductor memory devices 604a to 604d via command / address transmission line 573.

[0158] Command / address transmission lines 561 and 563 may be connected together to a module resistor unit 560 located adjacent to the first edge portion 503, and command / address transmission lines 571 and 573 may be connected together to a module resistor unit 570 located adjacent to the second edge portion 505.

[0159] Each of the module resistor units 560 and 570 may include a termination resistor Rtt / 2 connected to the termination voltage Vtt. In this case, the arrangement of the module resistor units 560 and 570 reduces the number of module resistor units, thereby reducing the area where the termination resistor is placed.

[0160] In addition, each of the plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d and 604a to 604d may be a DRAM device.

[0161] The SPD chip 580 is positioned adjacent to the control device 590, and the PMIC 585 may be disposed between the semiconductor memory device 603d and the second edge portion 505. The PMIC 585 can generate a power supply voltage VDD based on the input voltage VIN, and can provide the power supply voltage VDD to the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d.

[0162] Despite Figure 21 The diagram shows PMIC 585 positioned adjacent to the second edge portion 505, but in some example embodiments, PMIC 585 may be positioned in the central portion of the circuit board 501 adjacent to the control device 590.

[0163] Figure 22 This is a block diagram illustrating a memory system with four columns of memory modules according to some example embodiments.

[0164] Reference Figure 22 The memory system 700 may include a memory controller 710 and / or memory modules 720 and 730. Although in Figure 22 Two memory modules are depicted, but according to some example embodiments, more or fewer memory modules may be included in the memory system 700.

[0165] The memory controller 710 can control the memory modules 720 and / or 730 to execute commands supplied from the processor and / or host. The memory controller 710 can be implemented using processing circuitry (e.g., a processor), and / or can be implemented using a host, application processor, or system-on-a-chip (SoC).

[0166] For signal integrity, the source terminal can be implemented using a resistor RTT on the bus 740 of the memory controller 710. The resistor RTT can be connected to the power supply voltage VDDQ. The memory controller 710 may include a transmitter 711 and a receiver 713, wherein the transmitter 711 can send signals to at least one of the memory modules 720 and 730, and the receiver 713 can receive signals from at least one of the memory modules 720 and 730. The memory controller 710 may include an ECC engine 715, and the ECC engine 715 may employ... Figure 6 The ECC engine 130.

[0167] Therefore, the ECC engine 715 includes an ECC encoder and an ECC decoder, and the ECC decoder can use a first part of the parity check matrix to perform ECC decoding on read codewords from at least one of the memory modules 720 and 730 to generate a first corrector and a second corrector, and can determine the type of error in the read codeword based on the second corrector and a decision corrector corresponding to the sum of the first corrector and the second corrector.

[0168] If the read codeword contains correctable errors, the ECC decoder can generate a third corrector indicating the location of the correctable error based on the second part of the parity check matrix, and can correct the correctable error based on the third corrector. Therefore, the ECC decoder can improve the speed and efficiency of error determination.

[0169] Memory modules 720 and 730 may be referred to as first memory module 720 and second memory module 730. First memory module 720 and second memory module 730 may be connected to memory controller 710 via bus 740. Each memory module in first memory module 720 and second memory module 730 may correspond to... Figure 1 The memory module MM is included. The first memory module 720 may include memory columns RK1 and RK2, and the second memory module 730 may include memory columns RK3 and RK4. Although in Figure 22 Each memory module is depicted as comprising two memory columns, but according to some example embodiments, each memory module may include more or fewer memory columns.

[0170] Each of the first memory module 720 and the second memory module 730 may include multiple data chips, a first parity chip, and a second parity chip.

[0171] Figure 23 This is a block diagram illustrating a mobile system 900 including a memory module according to some example embodiments.

[0172] Reference Figure 23The mobile system 900 may include processing circuitry 910 (e.g., an application processor, a memory controller (MCT) and / or an application processor including an MCT 911), a connectivity module 920, a memory module 950, a non-volatile memory device 940, a user interface 930 and / or a power supply 970.

[0173] The processing circuitry 910 can execute applications (such as web browsers, game applications, video players, etc.). The connectivity module 920 can perform wired and / or wireless communication with external devices.

[0174] The memory module (MM) 950 may store data processed by the processing circuitry 910 and / or operate as working memory. The memory module 950 may include a plurality of semiconductor memory devices (MDs) 951, 952, 953 to 95q (where q is a positive integer greater than three) and / or a control device 961. According to some example embodiments, operations described herein as being performed by the control device 961 may be performed by the processing circuitry.

[0175] Semiconductor memory devices 951, 952, 953 to 95q may include multiple data chips, a first parity check chip, and a second parity check chip. Therefore, a processing circuit (e.g., MCT) can use a first portion of the parity check matrix to perform ECC decoding on a read codeword from memory module 950 to generate a first corrector and a second corrector, and can selectively determine the type of error in the codeword based on the second corrector and a decision corrector corresponding to the sum of the first and second correctors.

[0176] Mobile System 900 or its components can be installed using various types of packaging.

[0177] Some example embodiments can be applied to various systems including memory modules and memory controllers containing ECC engines.

[0178] The various operations of the methods described above can be performed by any suitable device (such as processing circuitry) capable of performing the operations. For example, the operations of the methods described above can be performed by various hardware and / or software implemented in some form of hardware (e.g., processor, ASIC, etc.).

[0179] The software may include an ordered list of executable instructions for implementing logical functions and may be implemented in any “processor-readable medium” for use by or in conjunction with an instruction execution system, device, or apparatus (such as a single-core or multi-core processor or a system containing a processor).

[0180] The blocks or operations of methods, algorithms, and functions described in conjunction with some of the example embodiments disclosed herein may be implemented directly in hardware, as software modules executed by a processor, or a combination of both. If implemented in software, the functions may be stored as one or more instructions or code on or transferred through a tangible, non-transitory computer-readable medium. Software modules may reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0181] While this disclosure has been specifically shown and described with reference to some exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of this disclosure as defined by the claims.

Claims

1. A memory controller configured to control a memory module, the memory controller comprising: The processing circuit is configured as follows: The first part of the parity check matrix is ​​used to perform error correction code decoding on the read codeword to generate the first and second correctors, wherein the read codeword comes from the memory module; The type of error in the read codeword is determined based on the second corrector and the decision corrector, where the decision corrector corresponds to the sum of the first and second correctors; and Output a decoding status flag indicating the type of error.

2. The memory controller according to claim 1, wherein, The processing circuit is configured as follows: In response to the determination that the corrector has a non-zero logic level, the output indicates the decoding status flag of the user dataset containing the codeword to be read, which includes correctable errors. A third corrector is generated based on the second part of the parity check matrix and the read codewords to indicate the location of correctable errors; as well as Use a third corrector to correct correctable errors to obtain a corrected user dataset.

3. The memory controller according to claim 1, wherein, The processing circuit is configured to: in response to determining that the corrector has a zero logic level and the second corrector has a zero logic level, output an indication that the user dataset of the read codeword does not include a decoding status flag indicating that the error is not included.

4. The memory controller according to claim 1, wherein, The processing circuit is configured to output a decoding status flag indicating that the user dataset containing the codewords read includes uncorrectable errors, in response to the determination that the corrector has a zero logic level and the second corrector has a non-zero logic level.

5. The memory controller according to claim 1, wherein, The codewords to be read include the user dataset, metadata associated with the user dataset, error location parity data, first error size parity data, and second error size parity data.

6. The memory controller according to claim 5, wherein: The memory module includes multiple data chips, a first parity check chip, and a second parity check chip; User datasets are read from the multiple data chips; Metadata and error location parity data are read from the first parity chip; as well as The first error size parity check data and the second error size parity check data are read from the second parity check chip.

7. The memory controller according to claim 1, wherein, The parity check matrix includes a first parity check submatrix, a second parity check submatrix, and a third parity check submatrix.

8. The memory controller according to claim 7, wherein: The second parity check submatrix includes multiple identity submatrices and multiple first zero submatrices. Each of the multiple identity submatrices and the multiple first zero submatrices has p×p elements. The multiple identity submatrices and the multiple first zero submatrices are arranged alternately, and p is a natural number greater than 1. The third parity check submatrix includes multiple second zero submatrixes and multiple first offset submatrixes, each of the multiple second zero submatrixes and the multiple first offset submatrixes having p×p elements, and the multiple second zero submatrixes and the multiple first offset submatrixes are arranged alternately; The first parity check submatrix includes multiple second offset submatrixes and two third zero submatrixes, wherein the multiple second offset submatrixes are different from each other and correspond to multiple data chips included in the memory module; and The first part of the parity check matrix includes the second parity check submatrix and the third parity check submatrix.

9. The memory controller according to claim 8, wherein, The processing circuit is configured as follows: The first parity submatrix is ​​generated by performing matrix multiplication on the read codeword and the second parity submatrix. The second parity check matrix is ​​generated by performing matrix multiplication on the read codeword and the third parity check matrix; and The decision calibrator is generated by summing the first calibrator and the second calibrator.

10. The memory controller according to claim 9, wherein, The processing circuit is configured to generate a third corrector indicating the location of a correctable error by performing matrix multiplication on the read codeword and the first parity check matrix in response to the determination that the corrector has a non-zero logic level.

11. The memory controller according to claim 1, wherein, The processing circuit is configured as follows: The parity generation matrix is ​​used to perform error correction coding on the user dataset and metadata to generate error location parity data, first error size parity data and second error size parity data; as well as The output codeword is sent to the memory module. The output codeword includes the user dataset, metadata, error location parity data, first error size parity data, and second error size parity data.

12. The memory controller according to claim 11, wherein, The parity check generation matrix includes a first parity check submatrix, a second parity check submatrix, and a third parity check submatrix.

13. The memory controller according to claim 12, wherein, The processing circuit is configured as follows: Error-correcting code encoding is performed on the user dataset and metadata using the first parity submatrix to generate error-location parity data; First error size parity data is generated by performing matrix multiplication on the second parity submatrix with the user dataset, metadata, and error location parity data. as well as The second error size parity data is generated by performing matrix multiplication on the third parity submatrix with the user dataset, metadata, and error location parity data.

14. The memory controller according to claim 12, wherein: The second parity check submatrix includes multiple first unit submatrices and multiple first zero submatrices. Each of the multiple first unit submatrices and multiple first zero submatrices has p×p elements. The multiple first unit submatrices and multiple first zero submatrices are arranged alternately, and p is a natural number greater than 1. The third parity check submatrix includes multiple second zero submatrixes and multiple second unit submatrixes, each of the multiple second zero submatrixes and multiple second unit submatrixes having p×p elements, and the multiple second zero submatrixes and multiple second unit submatrixes are arranged alternately; as well as The first parity check submatrix includes multiple offset submatrices and two third zero submatrices, wherein the multiple offset submatrices are different from each other and correspond to multiple data chips included in the memory module.

15. A memory system comprising: Memory module; as well as The memory controller includes processing circuitry, which is configured to: The first part of the parity check matrix is ​​used to perform error correction code decoding on the read codeword to generate the first and second correctors, wherein the read codeword comes from the memory module; The type of error in the read codeword is determined based on the second corrector and the decision corrector, where the decision corrector corresponds to the sum of the first and second correctors; and Output a decoding status flag indicating the type of error.

16. The memory system according to claim 15, wherein, The processing circuit is configured as follows: In response to the determination that the corrector has a non-zero logic level, the output indicates the decoding status flag of the user dataset containing the codeword to be read, which includes correctable errors. A third corrector is generated based on the second part of the parity check matrix and the read codewords to indicate the location of correctable errors; as well as Use a third corrector to correct correctable errors to obtain a corrected user dataset.

17. The memory system according to claim 15, wherein, The processing circuit is configured to: in response to determining that the corrector has a zero logic level and the second corrector has a zero logic level, output an indication that the user dataset of the read codeword does not include a decoding status flag indicating that the error is not included.

18. The memory system according to claim 15, wherein, The processing circuit is configured to output a decoding status flag indicating that the user dataset containing the codewords read includes uncorrectable errors, in response to the determination that the corrector has a zero logic level and the second corrector has a non-zero logic level.

19. The memory system according to claim 15, wherein: The parity check matrix includes a first parity check submatrix, a second parity check submatrix, and a third parity check submatrix; The second parity check submatrix includes multiple identity submatrices and multiple first zero submatrices. Each of the multiple identity submatrices and the multiple first zero submatrices has p×p elements. The multiple identity submatrices and the multiple first zero submatrices are arranged alternately, and p is a natural number greater than 1. The third parity check submatrix includes multiple second zero submatrixes and multiple first offset submatrixes, each of the multiple second zero submatrixes and the multiple first offset submatrixes having p×p elements, and the multiple second zero submatrixes and the multiple first offset submatrixes are arranged alternately; The first parity check submatrix includes multiple second offset submatrixes and two third zero submatrixes, wherein the multiple second offset submatrixes are different from each other and correspond to multiple data chips included in the memory module; as well as The first part of the parity check matrix includes the second parity check submatrix and the third parity check submatrix.

20. A memory controller configured to control a memory module, the memory controller comprising: The processing circuit is configured as follows: The parity generation matrix is ​​used to perform error correction coding on the user dataset and metadata to generate error location parity data, first error size parity data and second error size parity data; The output codeword is output to the memory module. The output codeword includes the user dataset, metadata, error location parity data, first error size parity data, and second error size parity data. The first part of the parity check matrix is ​​used to perform error correction code decoding on the read codeword to generate the first and second correctors, wherein the read codeword comes from the memory module; The type of error in the read codeword is determined based on the second corrector and the decision corrector, where the decision corrector corresponds to the sum of the first and second correctors; and Output a decoding status flag indicating the type of error.

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