Isolation power chip based on wafer level packaging and preparation method thereof

Abstract

The present disclosure provides an isolated power chip based on wafer-level packaging, including: a micro-transformer based on RDL, whose primary coil is connected to a DC power supply and outputs a DC voltage input by the DC power supply; a transmitting chip connected to the primary coil of the micro-transformer based on RDL, used to receive the DC voltage and convert it into an AC signal for transmission to the secondary coil of the micro-transformer based on RDL; a receiving chip connected to the secondary coil of the micro-transformer based on RDL, used to convert the AC signal into a DC signal, generate a control signal capable of stabilizing the output voltage according to load changes, and encode the control signal for digital isolation. The present disclosure also provides a method for preparing an isolated power chip based on wafer-level packaging.

Description

Technical Field

[0001] The present disclosure relates to the technical field of isolated power supplies, and in particular to an isolated power supply chip based on wafer-level packaging and a preparation method thereof. Background Art

[0002] The application range of isolated power chips is very wide, especially when the equipment needs to work under some extreme conditions, the isolated power chip plays a vital role in ensuring the safety and reliability of the equipment. In order to achieve safe and reliable communication between two points, the two points need to be isolated from each other, without interfering with each other, and transmit energy in one direction to prevent the existence of DC current and ground loops, and ensure the safety of human body and equipment.

[0003] Traditional isolated power supplies have problems such as low efficiency, large size, high electromagnetic noise and high cost. Therefore, in applications where size and cost are limited, it is still a great challenge to efficiently transmit hundreds of milliwatts of power through isolation devices. Compared with traditional optocoupler isolation devices, fully integrated isolated power supply chips based on micro-transformers have the advantages of good isolation performance, high magnetic interference immunity, small size and monolithic integration.

[0004] The core component that limits the efficiency of fully integrated isolated power chips is the chip transformer. Under high-frequency working conditions, the quality factor (Q) of the transformer is lower due to large substrate leakage, which makes it less efficient. At present, the implementation scheme of fully integrated isolated power chips [reference W. Qin et al., "An 800mW Fully Integrated Galvanic Isolated Power Transfer System Meeting CISPR 22 Class-B Emission Levels with 6dB Margin," 2019 IEEE International Solid-State Circuits Conference-(ISSCC), San Francisco, CA, USA, 2019], such as Figure 1As shown, the scheme combines and packages multiple chips, including a transformer chip 100 made by a back-end silicon-based process, and a transmitter chip 200 and a receiver chip 300 made by a high-voltage BCD process. Multiple bare chips are interconnected and packaged by gold wire bonding 30 in the packaging substrate 10 and the plastic filling 20. It adopts the form of SOIC (Small outline integrated circuit, small outline integrated circuit package) plastic packaging, and the package size is large, so the power density of the isolated power chip is low; the micro transformer chip that needs to be made by an additional back-end process has large leakage and loss of the transformer substrate and low Q value, resulting in low output power and conversion efficiency of the isolated power chip; the interconnection by gold wire bonding will cause instability to the system due to the parasitic inductance of the bonding wire, introduce more electromagnetic noise, and also increase the size of the package.

[0005] In summary, traditional isolated power supply packaging has high cost, low power density, low conversion efficiency, and the parasitic inductance caused by the bonding wires has an adverse effect on the electrical performance of the system. Therefore, how to achieve greater transmission efficiency and output power under the constraints of chip size, thereby improving power density, is an issue that needs to be solved urgently. Summary of the invention

[0006] 1. Technical issues to be resolved

[0007] Based on the above problems, the present disclosure provides an isolated power chip based on wafer-level packaging and a preparation method thereof to alleviate technical problems in the prior art such as high cost, low power density, low conversion efficiency of isolated power packaging, and adverse effects of parasitic inductance caused by bonding wires on the electrical performance of the system.

[0008] (II) Technical solution

[0009] The present invention provides an isolated power chip based on wafer-level packaging, comprising: a micro-transformer based on RDL (Redistributable layer, multi-layer redistribution layer), whose primary coil is connected to a DC power supply and outputs a DC voltage input by the DC power supply; a transmitting chip, connected to the primary coil of the micro-transformer based on RDL, for receiving the DC voltage and converting it into an AC signal for transmission to the secondary coil of the micro-transformer based on RDL; a receiving chip, connected to the secondary coil of the micro-transformer based on RDL, for converting the AC signal into a DC signal, generating a control signal capable of stabilizing the output voltage according to load changes, and encoding the control signal for digital isolation.

[0010] In the embodiment of the present disclosure, the RDL-based micro-transformer includes: a primary coil, which is processed based on RDL; a secondary coil, which is processed based on RDL; and interconnection lines, including interconnection lines made based on RDL and connected to the port of the transmitting chip, which are led out from one side of the primary coil; and interconnection lines made based on RDL and connected to the port of the receiving chip, which are led out from one side of the secondary coil.

[0011] In the embodiments of the present disclosure, the coil winding structure of the primary coil and the secondary coil is a single helix or double helix structure; the primary coil and the secondary coil are in the same plane or in different planes corresponding to parallel stacking; the coil winding shapes of the primary coil and the secondary coil include: circle, ellipse, rectangle, regular N-gon, N≥4.

[0012] In the embodiment of the present disclosure, the transmitting chip 200 includes: a cross-coupled oscillator, and a decoding circuit; the decoding circuit is used to decode the encoded control signal into a switching signal to control the cross-coupled oscillator to be turned on or off.

[0013] In the embodiment of the present disclosure, the cross-coupled oscillator includes: a first MOS tube and a second MOS tube, the gate of the first MOS tube is connected to the drain of the second MOS tube through a first voltage-dividing capacitor, and the gate of the second MOS tube is connected to the drain of the first MOS tube through a second voltage-dividing capacitor; a DC bias voltage, one end of which is connected to the gate of the first MOS tube through a first bias resistor; and the other end of which is connected to the gate of the second MOS tube through a second bias resistor; and a switch MOS tube, the drain of which is respectively connected to the source of the first MOS tube and the second MOS tube, the source of the switch MOS tube is grounded, and the gate of the switch MOS tube is connected to the output end of the decoding circuit.

[0014] In the embodiment of the present disclosure, the receiving chip includes: a rectifier circuit and a feedback control circuit; the feedback control circuit includes: a feedback controller, which is used to sample the change of the output voltage to generate a control signal for stabilizing the output voltage and encode the control signal; the control method adopted by the feedback controller includes: a pulse width modulation control method, a pulse frequency modulation control method, or a mixed mode control method of the above two; and a digital transformer, the encoded control signal is digitally isolated and transmitted through an input port of the digital transformer, and the other input port is a second ground terminal; the first output port of the digital transformer is interconnected with the transmitting chip through RDL, and the second output port of the digital transformer is connected to the first ground terminal.

[0015] Another aspect of the present disclosure provides a method for preparing an isolated power chip based on wafer-level packaging, which is used to prepare any of the above-mentioned isolated power chips, and the preparation method includes: operation S1: installing a transmitting chip and a receiving chip on a substrate; operation S2: preparing an isolation medium and an RDL layer above the substrate and the chip and processing them into a micro-transformer, and performing lead-out and signal port interconnection; and operation S3: preparing an external interface on the surface of the micro-transformer to complete the preparation of the isolated power chip based on wafer-level packaging.

[0016] In the embodiment of the present disclosure, the installation method includes digging a groove in the substrate and embedding the chip, or attaching the chip to the outer surface of the substrate; the substrate is made of a material selected from glass, silicon or FR4;

[0017] The RDL layer is made of a material selected from copper, aluminum or gold; the isolation dielectric layer is made of a material selected from glass, silicon, FR4, polyimide, epoxy resin or plastic.

[0018] In the embodiment of the present disclosure, the RDL layer includes at least one wiring layer, which is used to respectively manufacture the primary coil, the secondary coil, and the interconnection structure of the micro-transformer.

[0019] In the embodiment of the present disclosure, the RDL layer includes a first wiring layer, a second wiring layer and a third wiring layer; the primary coil of the microtransformer is made by the first wiring layer; the secondary coil of the microtransformer is made by the third wiring layer; a plurality of first through holes are arranged between the first wiring layer above the chip and the chip, a plurality of second through holes are arranged between the second wiring layer and the first wiring layer and the primary coil, and a plurality of third through holes are arranged between the second wiring layer and the third wiring layer and the secondary coil; the primary coil is connected to the second wiring layer through the second through hole, and then connected to the port of the transmitting chip through the first through hole, and the secondary coil is connected to the second wiring layer through the third through hole, and then connected to the port of the receiving chip through the second through hole and the first through hole.

[0020] (III) Beneficial effects

[0021] It can be seen from the above technical solutions that the isolated power chip based on wafer-level packaging and the preparation method thereof disclosed in the present invention have at least one or part of the following beneficial effects:

[0022] (1) The chip is embedded on a substrate, which reduces the package size, thereby improving the power density and adopting wafer-level packaging technology, thereby reducing costs;

[0023] (2) RDL micro-transformers based on glass substrates can achieve higher coupling coefficients and, through thick metal and wide line width RDL, achieve higher Q values ​​than transformers using back-end silicon-based processes, thereby improving the power conversion efficiency of isolated power supplies;

[0024] (3) The RDL routing inside the package replaces the gold wire bonding, effectively shortening the return path from the power supply to the ground, avoiding the system instability caused by the bonding wire, and reducing some electromagnetic noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a side view of the traditional fully integrated isolated power chip packaging structure.

[0026] Figure 2 The system composition block diagram of the isolated power chip based on wafer-level packaging according to the embodiment of the present disclosure.

[0027] Figure 3 It is a schematic diagram of the comparative structure of a traditional fully integrated isolated power chip and an isolated power chip based on wafer-level packaging according to an embodiment of the present disclosure.

[0028] Figure 4a It is a schematic diagram of the three-dimensional structure of an isolated power chip based on wafer-level packaging according to an embodiment of the present disclosure.

[0029] Figure 4b The present disclosure is a schematic side view of the structure of an isolated power chip based on wafer-level packaging according to an embodiment.

[0030] Figure 5 It is a schematic diagram of the Q value simulation results of the micro-transformer in the isolated power chip based on wafer-level packaging according to an embodiment of the present disclosure.

[0031] Figure 6 The present invention is a schematic diagram of the preparation process of the isolated power chip based on wafer-level packaging according to an embodiment of the present invention.

[0032] [Description of the main component symbols of the embodiment of the present disclosure in the accompanying drawings]

[0033] 40-substrate;

[0034] 50-isolation medium;

[0035] 60-solder ball;

[0036] 100-micro transformer;

[0037] 200-transmitter chip;

[0038] 210- Cross-coupled oscillator;

[0039] 220-decoding circuit;

[0040] 300-receiving chip;

[0041] 310-rectifier circuit;

[0042] 320- feedback control circuit;

[0043] 321-Feedback controller;

[0044] 322-digital transformer;

[0045] V DD - DC power supply;

[0046] V B - DC bias voltage;

[0047] GND1-first ground terminal;

[0048] GND2-second ground terminal;

[0049] L P -Primary coil;

[0050] L S - Secondary coil;

[0051] TX P TX N - Transmitter chip port;

[0052] RX P RX N -Receive chip port;

[0053] V C1 -Input port of the decoding circuit;

[0054] V C2 - a first output port of the digital transformer;

[0055] V ISO - output voltage;

[0056] V1-first through hole;

[0057] V2-second through hole;

[0058] V3-third through hole;

[0059] V4 - fourth via. DETAILED DESCRIPTION

[0060] The present invention provides an isolated power supply chip based on wafer-level packaging and a preparation method thereof. The wafer-level packaging method is adopted to embed and integrate the transmitting and receiving chips with a micro-transformer based on RDL on a substrate, thereby reducing the cost, reducing the package size, and improving the power density of the isolated power supply. The isolated power supply does not use a single transformer chip, but uses the RDL on the package to design and manufacture the micro-transformer. The RDL-based micro-transformer with higher Q and coupling coefficient is realized through the compact structure of the RDL and high-performance metal wires, so as to improve the transmission efficiency of the transformer, thereby improving the power conversion efficiency of the isolated power supply. The RDL interconnection replaces the traditional gold wire bonding, so as to further reduce the package size, while avoiding the instability of the system caused by the parasitic inductance of the bonding wire, and shortening the return path from the power supply to the ground to reduce a part of the electromagnetic noise.

[0061] In the process of realizing the present disclosure, the inventor found that with the development of wafer-level packaging technology, multiple bare chips can be interconnected through multiple layers of rewiring layers to effectively reduce the package size, thereby reducing costs, and without the need for traditional gold wire bonding interconnection methods, effectively improving the reliability of the system. The technology of integrating multiple bare chips on a single package under smaller size conditions has been realized, so the present disclosure provides an isolated power chip and its transformer based on wafer-level packaging, which achieves greater transmission efficiency and output power under chip size constraints, and improves power density.

[0062] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0063] In an embodiment of the present disclosure, an isolated power supply chip based on wafer level packaging is provided, Figure 2 , Figure 4a , Figure 4b As shown, the isolated power chip includes:

[0064] The RDL-based micro transformer has a primary coil connected to a DC power source and outputs a DC voltage input by the DC power source;

[0065] A transmitting chip, connected to the primary coil of the RDL-based micro-transformer, for receiving the DC voltage and converting it into an AC signal for transmission to the secondary coil of the RDL-based micro-transformer;

[0066] The receiving chip is connected to the secondary coil of the RDL-based micro-transformer, and is used to convert the AC signal into a DC signal, generate a control signal capable of stabilizing the output voltage according to load changes, and encode the control signal for digital isolation.

[0067] The RDL-based micro-transformer 100 has a primary coil connected to the transmitting chip and a secondary coil connected to the receiving chip, serving as an isolation device for transmitting AC oscillation power signals.

[0068] The primary coil and secondary coil of the RDL-based micro transformer are processed based on RDL; the coil winding structure of the primary coil and the secondary coil is a single helix or double helix structure; the primary coil and the secondary coil are in the same plane or in different planes corresponding to parallel stacking; the coil winding shapes of the primary coil and the secondary coil include: circle, ellipse, rectangle, regular N-gon, N≥4. The interconnection line includes an interconnection line connected to the port of the transmitting chip based on RDL and led out from one side of the primary coil; and an interconnection line connected to the port of the receiving chip based on RDL and led out from one side of the secondary coil.

[0069] The RDL-based micro-transformer 100 comprises:

[0070] Primary coil L P , presenting a planar double helix structure;

[0071] Secondary coil L S , presenting a planar double helix structure, corresponding to the primary coil and stacked in parallel; and

[0072] Interconnection wire, including primary coil L P The port (TX) connected to the transmitter chip is led out on one side. P and TX N ) interconnection line (also connected to the first ground terminal GND1); the secondary coil L S One side leads to the receiving chip port (RX P and RX N ) (also connected to the second ground terminal GND2).

[0073] The transmitting chip 200 includes: a cross-coupled oscillator 210 and a decoding circuit 220;

[0074] The decoding circuit 220 decodes the encoded control signal (narrow pulse) into a switch signal, and drives the switch MOS tube to control the cross-coupled oscillator 210 to turn on or off.

[0075] The cross-coupled oscillator 210 comprises:

[0076] A first MOS tube and a second MOS tube, wherein the gate of the first MOS tube is connected to the drain of the second MOS tube via a first voltage-dividing capacitor, and the gate of the second MOS tube is connected to the drain of the first MOS tube via a second voltage-dividing capacitor;

[0077] DC bias voltage VB , one end is connected to the gate of the first MOS tube through a first bias resistor; the other end is connected to the gate of the second MOS tube through a second bias resistor.

[0078] The drain of the switch MOS tube is connected to the source of the first MOS tube and the source of the second MOS tube respectively, the source of the switch MOS tube is grounded, and the gate of the switch MOS tube is connected to the output of the decoding circuit 220 .

[0079] The receiving chip 300 includes: a rectifier circuit 310 and a feedback control circuit 320;

[0080] The feedback control circuit 320 includes:

[0081] A feedback controller 321, used for sampling the change of the output voltage to generate a control signal for stabilizing the output voltage, and encoding the control signal; and

[0082] The digital transformer 322, the encoded control signal can be digitally isolated and transmitted through the first input port of the digital transformer, and the other input port is the second ground terminal GND2; the first output port V C2 The input port V of the decoding circuit 220 C1 The second output port of the digital transformer is connected to the first ground terminal GND1.

[0083] The feedback controller generally adopts a control method including: a pulse-width modulation (PWM) control method, a pulse-frequency modulation (PFM) control method, or a mixed mode control method thereof.

[0084] In order to save area and cost, preferably, the digital transformer 322 can be manufactured on-chip as a planar transformer by using top layer and second top layer thick metal.

[0085] In summary, the transmitting chip 200 inputs the DC power supply V DD The DC voltage is inverted into an oscillating power signal (preferably a high-frequency oscillating power signal) and transmitted from TX P and TX N The port outputs to the primary coil L of the RDL-based micro-transformer 100 P The receiving chip and the secondary coil L of the RDL-based micro-transformer S Connected to its port RX P and RX N The receiving chip 200 generates and transmits the secondary coil L of the RDL-based micro-transformer 100.S The high-frequency oscillation power signal is rectified and modulated to stabilize the output voltage V ISO During this process, a control signal for a stable output voltage is generated according to the load change, and the control signal is encoded for digital isolation.

[0086] Another aspect of the present disclosure also provides a method for preparing an isolated power chip based on wafer-level packaging, in which a micro-transformer based on RDL is fully integrated with the chip. Figure 3 As shown, traditional fully integrated isolated DC-DC chip packaging solutions such as SOIC solutions, ball grid array packaging (BGA) solutions based on gold wire bonding, and flip chip solutions based on flip chip soldering all require at least three bare chips, including a transmitting chip, a receiving chip, and a transformer chip. The transformer chip implemented using the back-end process of the silicon substrate increases the package size and cost. At the same time, the silicon substrate has large losses at high frequencies, and the parasitic inductance caused by the bonding wires has a certain adverse effect on the electrical performance. The wafer-level fan-out packaging technology used in the present invention uses the RDL in the package to make a transformer and realize interconnection. Only two bare chips (transmitting chip, receiving chip) are required and no gold wire bonding is required, which greatly reduces the size of the package, reduces costs, and improves the power density and reliability of the converter. Refer to Figure 4a , Figure 4b The schematic diagram of the structure of the isolated power chip based on wafer-level packaging with fully integrated RDL-based micro-transformer and chip is shown. The packaging structure of the isolated power chip provided by the embodiment of the present disclosure includes a transformer 100, a transmitting chip 200, a receiving chip 300, a substrate 40, an isolation medium 50 and solder balls 60 of a ball grid array.

[0087] In the embodiment of the present disclosure, Figure 4a , Figure 4b , Figure 6 As shown, a method for preparing an isolated power chip based on wafer-level packaging is provided, which is used to prepare the above-mentioned isolated power chip based on wafer-level packaging, and the preparation method comprises:

[0088] Operation S1: mounting a transmitting chip and a receiving chip on a substrate;

[0089] The above-mentioned installation method includes digging grooves in the substrate and embedding the transmitting chip and the receiving chip respectively, or attaching the transmitting chip and the receiving chip to the outer surface of the substrate; in the embodiment of the present disclosure, the installation method of digging grooves in the substrate and embedding the chips is used as an example. The two chips are embedded and attached to a grooved substrate 40, and the preparation material of the substrate is selected from glass, silicon or FR4, etc.;

[0090] The transmitting chip 200 and the receiving chip 300 are both designed and manufactured using silicon-based technology;

[0091] Several pads and circuit areas are prepared on the upper surfaces of the transmitting chip 200 and the receiving chip 300.

[0092] Operation S2: preparing an isolation dielectric and an RDL layer above the substrate and the chip and processing them into a micro transformer, and performing lead-out and signal port interconnection.

[0093] The number of wiring layers included in the RDL layer is at least one, preferably two or three, for respectively making the primary coil, secondary coil, and interconnection structure of the micro transformer. In the embodiment disclosed in the present invention, the RDL layer (multi-layer rewiring layer) includes a first wiring layer RDL1, a second wiring layer RDL2, and a third wiring layer RDL3; the first wiring layer RDL1 is used to make the primary coil L of the micro transformer P The secondary coil L of the micro transformer is made by the third wiring layer RDL3 S A plurality of first through holes V1 are arranged between the first wiring layer RDL1 located above the chip and the chip (transmitting chip, receiving chip), and the second wiring layer RDL2 and the first wiring layer RDL1 and the primary coil L P A plurality of second through holes V2 are arranged between the second wiring layer RDL2 and the third wiring layer RDL3 and the secondary coil Ls; the primary coil is connected to the second wiring layer RDL2 through the second through hole V2, and then connected to the port TX of the transmitting chip 200 through the first through hole V1. P and TX N The secondary coil is connected to the second wiring layer RDL2 through the third through hole V3, and then connected to the port RX of the receiving chip 300 through the through holes V2 and V1. P and RX N The above-mentioned through holes are all conductive vias.

[0094] During this operation, the isolation medium 50 also plays a supporting and isolating role in the micro-transformer preparation process.

[0095] The RDL layer is made of a material selected from copper wire, aluminum wire or gold wire; the isolation dielectric layer is made of a material selected from glass, silicon, FR4, polyimide, epoxy resin or plastic;

[0096] Operation S3: preparing an external interface on the surface of the micro-transformer to complete an isolated power chip based on wafer-level packaging.

[0097] Finally, a BGA solder ball 60 is prepared on the third wiring layer RDL3 as an external interface, and a through hole V4 is provided between the solder ball and the third wiring layer RDL3. The BGA solder ball includes any one of a tin ball, a nickel-palladium-gold ball, and a nickel ball.

[0098] Since the RDL-based micro-transformer 100 is manufactured on different layers of the chip, and the isolated power chip proposed in the present disclosure eliminates at least one transformer chip, the micro-transformer is manufactured through the RDL layer. The thickness of the RDL layer can be thickened by the thickness of the prepared metal wire and the line width can be widened to effectively improve the Q value of the transformer, thereby expanding the design space of parameters such as the inductance value and Q value of the transformer.

[0099] The Q value and coupling coefficient of the transformer are proportional to the transmission efficiency. Under the condition of size constraints, by optimizing the transformer coil inner diameter R, number of turns N, line spacing s, line width w and line thickness t parameters, the spacing h between the primary and secondary coils of the transformer is determined according to the withstand voltage characteristics of the dielectric material used; within the resonant frequency range of the isolated power supply, the best transmission efficiency is achieved.

[0100] In the embodiment of the present disclosure, the resonance frequency of the isolated power supply is Wherein, C is the gate equivalent capacitance of the first MOS transistor and the second MOS transistor in the cross-coupled oscillator 210; and L is the equivalent inductance of the micro-transformer.

[0101] In the specific embodiment of the present disclosure, a micro transformer based on RDL is prepared in an area of ​​2mm×4mm, and its specific parameters are R=880μm, N=3.5, s=80μm, w=100μm, t=10μm and h=30μm. Through electromagnetic simulation software, Figure 5 As shown, the Q values ​​of the primary coil and the secondary coil of the transformer are 11.6 and 9.6 respectively in the range of 180-210 MHz, which is significantly improved compared with the Q value of the chip transformer in the reference literature at 200 MHz of 6.8.

[0102] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that in the drawings or the main text of the specification, the implementation methods that are not shown or described are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in this field can simply change or replace them. For example, in the present embodiment, the setting of the first wiring layer RDL1, the second wiring layer RDL2 and the third wiring layer RDL3 to make the transformer and the interconnection line is only used to illustrate the specific implementation method of the present disclosure. Other implementation methods based on the inventive concept of the present disclosure should be included in the scope of protection of this application, for example, the primary coil L is made by the second wiring layer RDL2 and the third wiring layer RDL3 respectively. P and the secondary coil L S , or by setting two wiring layers, four wiring layers, etc., to achieve the preparation of the micro transformer.

[0103] It is worth mentioning that the present invention can preferably use a substrate made of glass material. Since the tangent loss angle of the glass substrate is 2 to 3 times smaller than that of the traditional silicon substrate, the in-package transformer designed with 3 layers of rewiring layers in the package has a higher Q and coupling coefficient, and can therefore efficiently transmit power of more than 1 W.

[0104] In addition, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and those skilled in the art can simply change or replace them, for example:

[0105] (1) The planar transformer 100 is implemented by a coil with a double helix structure, and can also be implemented by a single helix structure or a multi-helix polygonal coil;

[0106] (2) The filled isolation medium 50 can also be replaced by the same material as the substrate to achieve a complete embedded package.

[0107] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

[0108] Based on the above description, those skilled in the art should have a clear understanding of the isolated power chip based on wafer-level packaging and the preparation method thereof disclosed in the present invention.

[0109] In summary, the present disclosure provides an isolated power chip based on wafer-level packaging and a preparation method thereof, and proposes a new solution for an isolated power chip. The wafer-level packaging method is adopted to embed the transmitting and receiving chips with a micro-transformer based on a multi-layer rewiring layer on a substrate, thereby reducing the cost, reducing the package size, and improving the power density of the isolated power supply. Secondly, the solution proposed by the present invention does not require a single transformer chip, and adopts the RDL design on the package to manufacture a micro-transformer. The compact structure of the RDL and the high-performance metal wire realize the RDL-based micro-transformer with a higher quality factor (Q) and coupling coefficient to improve the transmission efficiency of the transformer, thereby further improving the power conversion efficiency of the isolated power supply. Finally, the proposed solution replaces the traditional gold wire bonding with RDL interconnection, further reduces the package size, and avoids the instability of the bonding wire caused by parasitic inductance to the system, and shortens the return path from the power supply to the ground to reduce part of the electromagnetic noise. The present invention proposes that the isolated power chip is used in occasions where size and cost are limited, and efficiently transmits watt-level power and has higher efficiency.

[0110] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure.

[0111] Moreover, the shapes and sizes of the components in the figures do not reflect the real size and proportion, but only illustrate the contents of the embodiments of the present disclosure. In addition, in the claims, any reference symbols between brackets shall not be constructed as limiting the claims.

[0112] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0113] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0114] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0115] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and set in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into multiple submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose. Furthermore, in a unit claim that lists several devices, several of these devices may be embodied by the same hardware item.

[0116] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. An isolated power chip based on wafer-level packaging, comprising: A micro transformer processed based on an RDL layer, wherein the primary coil is connected to a DC power supply and outputs a DC voltage input by the DC power supply, wherein the RDL layer includes a first wiring layer, a second wiring layer and a third wiring layer; the primary coil of the micro transformer is made by the first wiring layer; and the secondary coil of the micro transformer is made by the third wiring layer; A transmitting chip, connected to the primary coil of the RDL-based micro-transformer, for receiving the DC voltage and converting it into an AC signal for transmission to the secondary coil of the RDL-based micro-transformer; The receiving chip is connected to the secondary coil of the RDL-based micro-transformer, and is used to convert the AC signal into a DC signal, generate a control signal capable of stabilizing the output voltage according to load changes, and encode the control signal for digital isolation.

2. The isolated power chip according to claim 1, wherein the RDL-based micro-transformer comprises: The primary coil is processed based on RDL; The secondary coil is processed based on RDL; as well as The interconnection lines include an interconnection line produced based on RDL and connected to a port of a transmitting chip, which is led out from one side of the primary coil; and an interconnection line produced based on RDL and connected to a port of a receiving chip, which is led out from one side of the secondary coil.

3. The isolated power chip according to claim 2, wherein: The coil winding structure of the primary coil and the secondary coil is a single helix or double helix structure; The primary coil and the secondary coil are in the same plane or in different planes corresponding to parallel stacking; The coil winding shapes of the primary coil and the secondary coil include: circle, ellipse, rectangle, regular N-gon, N≥4.

4. The isolated power chip according to claim 1, wherein the transmitting chip comprises: Cross-coupled oscillators, and decoding circuits; The decoding circuit is used to decode the encoded control signal into a switch signal to control the cross-coupled oscillator to be turned on or off.

5. The isolated power chip according to claim 4, wherein the cross-coupled oscillator comprises: A first MOS tube and a second MOS tube, wherein the gate of the first MOS tube is connected to the drain of the second MOS tube via a first voltage-dividing capacitor, and the gate of the second MOS tube is connected to the drain of the first MOS tube via a second voltage-dividing capacitor; A DC bias voltage, one end of which is connected to the gate of the first MOS tube through a first bias resistor; and the other end of which is connected to the gate of the second MOS tube through a second bias resistor; as well as The drain of the switch MOS tube is connected to the source of the first MOS tube and the source of the second MOS tube respectively, the source of the switch MOS tube is grounded, and the gate of the switch MOS tube is connected to the output end of the decoding circuit.

6. The isolated power supply chip according to claim 1, wherein the receiving chip comprises: Rectification circuit, and feedback control circuit; The feedback control circuit comprises: A feedback controller, used to sample the change of the output voltage to generate a control signal for stabilizing the output voltage, and encode the control signal; the control mode adopted by the feedback controller includes: pulse width modulation control mode, pulse frequency modulation control mode, or a mixed mode control mode of the above two modes; and A digital transformer, wherein the encoded control signal is digitally isolated and transmitted through one input port of the digital transformer, and the other input port is a second ground terminal; The first output port of the digital transformer is interconnected with the transmitting chip through the RDL, and the second output port of the digital transformer is connected to the first ground terminal.

7. A method for preparing an isolated power chip based on wafer-level packaging, used for preparing the isolated power chip according to any one of claims 1 to 6 above, the preparation method comprising: Operation S1: mounting a transmitting chip and a receiving chip on a substrate; Operation S2: preparing an isolation dielectric and RDL layer on the substrate and the chip and processing them into a micro transformer, and performing lead-out and signal port interconnection; and Operation S3: preparing an external interface on the surface of the micro-transformer to complete the preparation of the isolated power chip based on wafer-level packaging.

8. The preparation method according to claim 7, wherein: The installation method includes digging a groove in the substrate and embedding the chip therein, or attaching the chip to the outer surface of the substrate; The substrate is made of glass, silicon or FR4; The RDL layer is made of a material selected from: copper, aluminum or gold; The isolation dielectric layer is made of a material selected from glass, silicon, FR4, polyimide, epoxy resin, or plastic.

9. The preparation method according to claim 8, wherein the RDL layer comprises at least one wiring layer for respectively manufacturing the primary coil, the secondary coil, and the interconnection structure of the micro-transformer.

10. According to the preparation method of claim 9, the RDL layer includes a first wiring layer, a second wiring layer and a third wiring layer; the primary coil of the micro transformer is made by the first wiring layer; the secondary coil of the micro transformer is made by the third wiring layer; a plurality of first through holes are arranged between the first wiring layer above the chip and the chip, a plurality of second through holes are arranged between the second wiring layer and the first wiring layer and the primary coil, and a plurality of third through holes are arranged between the second wiring layer and the third wiring layer and the secondary coil; the primary coil is connected to the second wiring layer through the second through hole, and then connected to the port of the transmitting chip through the first through hole, and the secondary coil is connected to the second wiring layer through the third through hole, and then connected to the port of the receiving chip through the second through hole and the first through hole.

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