Semiconductor packaging structure

Abstract

The utility model discloses a semiconductor packaging structure, which comprises a horizontally arranged diode chip, an upper electrode electrically connected with the upper surface of the diode chip, a lower electrode electrically connected with the lower surface of the diode chip, and an epoxy packaging body coated on the outer side of the diode chip, the end, connected with the diode chip, of the upper electrode is provided with an upper connecting part horizontally arranged above the diode chip, an upper thinning area is formed below the upper connecting part, and the end, connected with the diode chip, of the lower electrode is provided with a lower connecting part horizontally arranged below the diode chip. A lower thinning area is formed above the lower connecting portion, and the diode chips located in the upper thinning area and the lower thinning area are respectively connected with the upper connecting portion of the upper electrode and the lower connecting portion of the lower electrode in a welding mode through a welding layer. According to the utility model, the packaging volume of the epoxy packaging body can be reduced, the heat dissipation efficiency and the heat dissipation uniformity are improved, and the stability of the performance in the use process can be improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor power devices, in particular to a semiconductor packaging structure. Background Art

[0002] A diode is an electronic device made of semiconductor materials (silicon, selenium, germanium, etc.). A diode has two electrodes, the positive electrode, also called the anode, and the negative electrode, also called the cathode. When a forward voltage is applied between the two electrodes of the diode, the diode is turned on, and when a reverse voltage is applied, the diode is turned off. The conduction and cutoff of the diode are equivalent to the on and off of the switch. At present, many axial diodes have large packaging volumes, and the chip is covered over a large area, resulting in poor heat dissipation efficiency and uniformity. Utility Model Content

[0003] The utility model aims to provide a semiconductor packaging structure, which can reduce the packaging volume of the epoxy packaging body, improve the heat dissipation efficiency and heat dissipation uniformity, and improve the stability of performance during use.

[0004] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a semiconductor packaging structure, comprising: a horizontally arranged diode chip, an upper electrode electrically connected to the upper surface of the diode chip, a lower electrode electrically connected to the lower surface of the diode chip, and an epoxy packaging body coated on the outside of the diode chip, the upper electrode having an end connected to the diode chip having an upper connecting portion horizontally arranged above the diode chip, and an upper thinning area is formed below the upper connecting portion, the lower electrode having an end connected to the diode chip having a lower connecting portion horizontally arranged below the diode chip, and a lower thinning area is formed above the lower connecting portion, the diode chips located in the upper thinning area and the lower thinning area are respectively welded to the upper connecting portion of the upper electrode and the lower connecting portion of the lower electrode through a welding layer, and the other ends of the upper electrode and the lower electrode are first pin portions and second pin portions extending horizontally to the outside of the epoxy packaging body.

[0005] The further improved scheme in the above technical scheme is as follows:

[0006] 1. In the above solution, the lower surface of the first lead portion whose upper surface is flush with the upper connection portion is lower than the lower surface of the diode chip, and the upper surface of the second lead portion whose lower surface is flush with the lower connection portion is higher than the upper surface of the diode chip.

[0007] 2. In the above solution, the first pin portion of the upper electrode and the second pin portion of the lower electrode are both cylindrical and coaxially arranged.

[0008] 3. In the above solution, the connection between the first pin portion and the upper connection portion, and the connection between the second pin portion and the lower connection portion are both located inside the epoxy package.

[0009] 4. In the above solution, the connection between the first pin portion and the upper connecting portion, and the connection between the second pin portion and the lower connecting portion are both configured to be arc-shaped.

[0010] 5. In the above solution, the upper surface of the diode chip is the positive electrode surface, the lower surface is the negative electrode surface, the upper electrode is the positive electrode, and the lower electrode is the negative electrode.

[0011] 6. In the above solution, the welding layer is a solder paste layer.

[0012] Due to the application of the above technical solution, the utility model has the following advantages and effects compared with the prior art:

[0013] The utility model discloses a semiconductor packaging structure, wherein an end of an upper electrode connected to a diode chip has an upper connection portion horizontally arranged above the diode chip, an upper thinning area is formed below the upper connection portion, and an end of a lower electrode connected to the diode chip has a lower connection portion horizontally arranged below the diode chip, a lower thinning area is formed above the lower connection portion, the diode chips located in the upper thinning area and the lower thinning area are respectively welded to the upper connection portion of the upper electrode and the lower connection portion of the lower electrode through a welding layer, the other ends of the upper electrode and the lower electrode are the first pin portion and the second pin portion horizontally extending to the outside of the epoxy packaging body, which can reduce the packaging volume of the epoxy packaging body to meet the design requirements of miniaturization, and reduce the distance between the entire surface of the chip and the external environment to improve the heat dissipation efficiency and the uniformity of heat dissipation, and can also reduce the structural stress when the pins are bent during use, thereby improving the stability of performance during use. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Attached Figure 1 It is a structural schematic diagram of the semiconductor packaging structure of the utility model.

[0015] In the above figures: 1. diode chip; 2. upper electrode; 21. upper connecting portion; 22. upper thinning area; 23. first pin portion; 3. lower electrode; 31. lower connecting portion; 32. lower thinning area; 33. second pin portion; 4. epoxy package; 5. welding layer. DETAILED DESCRIPTION

[0016] The utility model is further described below in conjunction with the accompanying drawings and embodiments:

[0017] Embodiment 1: A semiconductor packaging structure comprises: a horizontally arranged diode chip 1, an upper electrode 2 electrically connected to the upper surface of the diode chip 1, a lower electrode 3 electrically connected to the lower surface of the diode chip 1, and an epoxy packaging body 4 coated on the outside of the diode chip 1, wherein the end of the upper electrode 2 connected to the diode chip 1 has an upper connecting portion 21 horizontally arranged above the diode chip 1, and an upper thinning area 22 is formed below the upper connecting portion 21, and the end of the lower electrode 3 connected to the diode chip 1 has a lower connecting portion 31 horizontally arranged below the diode chip 1, and a lower thinning area 32 is formed above the lower connecting portion 31, and the diode chip 1 located in the upper thinning area 22 and the lower thinning area 32 are respectively welded to the upper connecting portion 21 of the upper electrode 2 and the lower connecting portion 31 of the lower electrode 3 through a welding layer 5, and the other ends of the upper electrode 2 and the lower electrode 3 are a first pin portion 23 and a second pin portion 33 horizontally extending to the outside of the epoxy packaging body 4.

[0018] The lower surface of the first pin portion 23 whose upper surface is flush with the upper connection portion 21 is lower than the lower surface of the diode chip 1, and the upper surface of the second pin portion 33 whose lower surface is flush with the lower connection portion 31 is higher than the upper surface of the diode chip 1;

[0019] The first pin portion 23 of the upper electrode 2 and the second pin portion 33 of the lower electrode 3 are both cylindrical and coaxially arranged; the connection between the first pin portion 23 and the upper connecting portion 21 and the connection between the second pin portion 33 and the lower connecting portion 31 are both located in the epoxy package 4.

[0020] Embodiment 2: A semiconductor packaging structure comprises: a horizontally arranged diode chip 1, an upper electrode 2 electrically connected to the upper surface of the diode chip 1, a lower electrode 3 electrically connected to the lower surface of the diode chip 1, and an epoxy packaging body 4 coated on the outside of the diode chip 1, wherein the end of the upper electrode 2 connected to the diode chip 1 has an upper connecting portion 21 horizontally arranged above the diode chip 1, and an upper thinning area 22 is formed below the upper connecting portion 21, and the end of the lower electrode 3 connected to the diode chip 1 has a lower connecting portion 31 horizontally arranged below the diode chip 1, and a lower thinning area 32 is formed above the lower connecting portion 31, and the diode chip 1 located in the upper thinning area 22 and the lower thinning area 32 are respectively welded to the upper connecting portion 21 of the upper electrode 2 and the lower connecting portion 31 of the lower electrode 3 through a welding layer 5, and the other ends of the upper electrode 2 and the lower electrode 3 are a first pin portion 23 and a second pin portion 33 horizontally extending to the outside of the epoxy packaging body 4.

[0021] The connection between the first pin portion 23 and the upper connection portion 21, and the connection between the second pin portion 33 and the lower connection portion 31 are both arranged in an arc shape; the upper surface of the diode chip 1 is the positive electrode surface, and the lower surface is the negative electrode surface; the upper electrode 2 is the positive electrode, and the lower electrode 3 is the negative electrode; the welding layer 5 is a solder paste layer.

[0022] When the above-mentioned semiconductor packaging structure is adopted, it can not only reduce the packaging volume of the epoxy package to meet the miniaturized design requirements, but also reduce the distance between the entire surface of the chip and the external environment to improve the heat dissipation efficiency and uniformity of heat dissipation. It can also reduce the structural stress when the pins are bent during use, thereby improving the stability of performance during use.

[0023] The above embodiments are only for illustrating the technical concept and features of the utility model, and their purpose is to enable people familiar with the technology to understand the content of the utility model and implement it accordingly, and they cannot be used to limit the protection scope of the utility model. Any equivalent changes or modifications made according to the spirit of the utility model should be included in the protection scope of the utility model.

Claims

1. A semiconductor packaging structure, comprising: A horizontally arranged diode chip (1), an upper electrode (2) electrically connected to the upper surface of the diode chip (1), a lower electrode (3) electrically connected to the lower surface of the diode chip (1), and an epoxy package (4) wrapped around the outside of the diode chip (1), characterized in that: the end of the upper electrode (2) connected to the diode chip (1) has an upper connecting portion (21) horizontally arranged above the diode chip (1), an upper thinning area (22) is formed below the upper connecting portion (21), and the end of the lower electrode (3) connected to the diode chip (1) has an upper connecting portion (21) horizontally arranged above the diode chip (1), and an upper thinning area (22) is formed below the upper connecting portion (21). A lower connecting portion (31) is horizontally arranged below a diode chip (1); a lower thinning area (32) is formed above the lower connecting portion (31); the diode chip (1) located in the upper thinning area (22) and the lower thinning area (32) is respectively welded to the upper connecting portion (21) of the upper electrode (2) and the lower connecting portion (31) of the lower electrode (3) through a welding layer (5); the other ends of the upper electrode (2) and the lower electrode (3) are first pin portions (23) and second pin portions (33) extending horizontally to the outside of an epoxy package (4).

2. The semiconductor package structure according to claim 1, wherein: The lower surface of the first pin portion (23) whose upper surface is flush with the upper connecting portion (21) is lower than the lower surface of the diode chip (1), and the upper surface of the second pin portion (33) whose lower surface is flush with the lower connecting portion (31) is higher than the upper surface of the diode chip (1).

3. The semiconductor package structure according to claim 2, wherein: The first pin portion (23) of the upper electrode (2) and the second pin portion (33) of the lower electrode (3) are both cylindrical and coaxially arranged.

4. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The connection point between the first pin portion (23) and the upper connection portion (21), and the connection point between the second pin portion (33) and the lower connection portion (31) are both located inside the epoxy packaging body (4).

5. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The connection point between the first pin portion (23) and the upper connection portion (21), and the connection point between the second pin portion (33) and the lower connection portion (31) are both arranged in an arc shape.

6. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The upper surface of the diode chip (1) is a positive electrode surface, and the lower surface is a negative electrode surface; the upper electrode (2) is a positive electrode, and the lower electrode (3) is a negative electrode.

7. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The welding layer (5) is a solder paste layer.

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