A bias circuit structure for multiple voltages

Abstract

The present invention provides a bias circuit structure applied to multiple voltages, in the field of electronic circuit technology, including a first current reference module that changes with the power supply voltage and a second current reference module that does not change with the power supply voltage; the output end of the first current reference module is a current reference NTC with a negative temperature coefficient, and the output end of the second current reference module is a current reference PTC with a positive temperature coefficient; the output end of the first current reference module and the output end of the second current reference module are in a parallel structure, and the output end of the first current reference module and the output end of the second current reference module after the parallel connection serve as the output end of the bias circuit structure. The present invention realizes that the bias current has a certain correlation with the voltage, and its change is small with the temperature change, and it is not sensitive to temperature.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a bias circuit structure applied to multiple voltages. Background Art

[0002] Any circuit system needs to work at a stable operating point, which is referred to as a static operating point in the present invention. Such a module is required in the circuit system to provide a bias current or a bias voltage. For example, the common-source common-gate tube in the common-source common-gate structure requires a voltage bias to ensure that it works in the amplification area, and the operational amplifier and the comparator require the tail current of the PTAT to bias the static operating point. At the same time, in order to avoid the zero state when the reference voltage source is started, the bias circuit also needs to include a startup circuit. In chip circuit design, the reference source is related to the success or failure of the integrated circuit design. The power supply voltage provided by the external power supply system is often taken from the adapter, which not only contains noise, but also makes it difficult to provide the chip with a special required reference, so the reference source can only be generated by the internal circuit of the chip.

[0003] The reference sources are mainly current sources and voltage sources. In integrated circuits, the most commonly used voltage reference is the bandgap reference Bandgap, which can provide a high-precision voltage of about 1.25V. There are many studies on Bandgap and the technology is mature. After technical compensation, when the power supply voltage range is wide, the temperature coefficient in the temperature range of -45℃ to 125℃ can reach 3ppm / ℃. This shows that Bandgap can be insensitive to both power supply and voltage. Current reference is also one of the most commonly used modules in integrated circuit design. For current reference, it is mostly obtained by dividing the Bandgap voltage reference by a resistor with a precise resistance value, and then mirrored to each module through a current mirror. The current obtained in this way will introduce a temperature coefficient, causing the reference to be sensitive to temperature. There are two commonly used bias circuits: power supply-independent and power supply-dependent. The bias related to the power supply introduces resistance in the circuit. Since the resistor has a first-order temperature coefficient, a second-order temperature coefficient, or even a higher-order temperature coefficient, the bias voltage output by the circuit is greatly affected by temperature, and its temperature curve may not meet the requirements in circuit design. The bias circuit that is independent of the power supply can adapt to a wider power supply voltage input range. However, this circuit structure also has a temperature coefficient and cannot achieve a zero temperature coefficient. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a bias circuit structure applied to multiple voltages, which realizes that the bias current has a certain correlation with the voltage, and its change is small with temperature changes, and is insensitive to temperature.

[0005] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0006] The present solution provides a bias circuit structure applied to multiple voltages, including a first current reference module that changes with the power supply voltage and a second current reference module that does not change with the power supply voltage; the output end of the first current reference module is a current reference NTC with a negative temperature coefficient, and the output end of the second current reference module is a current reference PTC with a positive temperature coefficient; the output end of the first current reference module and the output end of the second current reference module are in a parallel structure, and the output end of the first current reference module and the output end of the second current reference module after the parallel connection serve as the output end of the bias circuit structure.

[0007] Further, the first current reference module includes a resistor R1, a capacitor C1, PMOS field effect transistors MP1 and MP2, and NMOS field effect transistors MN1 and MN2;

[0008] One end of the resistor R1 is connected to a power supply, the other end of the resistor R1 is connected to the drain of the NMOS field effect transistor MN1, the gate of the NMOS field effect transistor MN1 is respectively connected to the drain of the NMOS field effect transistor MN1 and the gate of the NMOS field effect transistor MN2, the source of the NMOS field effect transistor MN1 is grounded, the source of the NMOS field effect transistor MN2 is grounded, the drain of the NMOS field effect transistor MN2 is connected to the drain of the PMOS field effect transistor MP1, the source of the PMOS field effect transistor MP1 is connected to a power supply, the gate of the PMOS field effect transistor MP1 is respectively connected to one end of the capacitor C1, the gate of the PMOS field effect transistor MP2 and the drain of the NMOS field effect transistor MN2, the other end of the capacitor C1 is connected to a power supply, the drain of the PMOS field effect transistor MP2 is the output end of the first current reference module, and is connected in parallel with the output end of the second current reference module, and the source of the PMOS field effect transistor MP2 is connected to a power supply.

[0009] Furthermore, the resistance current expression of the first current reference module is as follows:

[0010]

[0011] Among them, I NTC represents the resistance current of the first current reference module, VCC represents the power supply voltage, VGS MN1 represents the gate-source voltage of the NMOS field effect transistor MN1, and R1 represents the resistor.

[0012] Furthermore, the expression of the resistance current temperature coefficient of the first current reference module is as follows:

[0013]

[0014]

[0015] in, Represents the first current reference module resistance current I NTC Regarding the partial derivative coefficient of current and temperature, R and R1 both represent resistance, T represents temperature, and VGS MN1 It represents the gate-source voltage of NMOS field effect tube MN1, VCC represents the power supply voltage, TCR represents the temperature coefficient, It represents the rate of change of resistance with temperature.

[0016] Furthermore, the second current reference module includes a startup circuit unit and a core reference unit connected to the startup circuit unit.

[0017] Furthermore, the startup circuit unit includes a resistor R2, a PMOS field effect transistor MP3, and NMOS field effect transistors MN3 and MN4;

[0018] The source of the PMOS field effect transistor MP3 is connected to a power supply, the gate of the PMOS field effect transistor MP3 is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, the drain of the PMOS field effect transistor MP3 is respectively connected to the gate of the NMOS field effect transistor MN4 and the drain of the NMOS field effect transistor MN3, the source of the NMOS field effect transistor MN3 is grounded, the source of the NMOS field effect transistor MN4 is grounded, and the drain of the NMOS field effect transistor MN4 and the gate of the NMOS field effect transistor MN3 are both connected to the core reference unit.

[0019] Furthermore, the core reference unit includes a capacitor C2, a resistor R3, PMOS field effect transistors MP4-MP9 and NMOS field effect transistors MN5-MN11;

[0020] The source of the PMOS field effect transistor MP4 is connected to a power supply, the gate of the PMOS field effect transistor MP4 is respectively connected to the drain of the NMOS field effect transistor MN4, the gate of the PMOS field effect transistor MP5, the gate of the PMOS field effect transistor MP6 and the gate of the PMOS field effect transistor MP7, the drain of the PMOS field effect transistor MP4 is respectively connected to the drain of the NMOS field effect transistor MN5, the gate of the NMOS field effect transistor MN3, the gate of the NMOS field effect transistor MN5, the gate of the NMOS field effect transistor MN6 and the gate of the NMOS field effect transistor MN8, the NMOS field effect transistor MN The source of the NMOS field effect tube MN5 is grounded, the source of the NMOS field effect tube MN6 is connected to the drain of the NMOS field effect tube MN7, the source of the NMOS field effect tube MN8 is connected to the drain of the NMOS field effect tube MN9, the source of the PMOS field effect tube MP5 is connected to the power supply, the drain of the PMOS field effect tube MP5 is respectively connected to the drain of the NMOS field effect tube MN6, the gate of the NMOS field effect tube MN7 and the gate of the NMOS field effect tube MN9, the source of the NMOS field effect tube MN7 is grounded, and the source of the NMOS field effect tube MN9 is connected to one end of the resistor R3. The other end of the resistor R3 is grounded, the source of the PMOS field effect transistor MP6 is connected to the power supply, the drain of the PMOS field effect transistor MP6 is connected to the drain of the NMOS field effect transistor MN8, the source of the NMOS field effect transistor MN8 is connected to the drain of the NMOS field effect transistor MN9, the source of the PMOS field effect transistor MP7 is connected to the power supply, the drain of the PMOS field effect transistor MP7 is respectively connected to the drain of the NMOS field effect transistor MN10, the gate of the NMOS field effect transistor MN10 and the gate of the NMOS field effect transistor MN11, the source of the NMOS field effect transistor MN10 is connected to the power supply, and the drain of the PMOS field effect transistor MP7 is respectively connected to the drain of the NMOS field effect transistor MN10, the gate of the NMOS field effect transistor MN10 and the gate of the NMOS field effect transistor MN11. The gate of the PMOS field effect tube MP8 is connected to the gate of the PMOS field effect tube MP9 and one end of the capacitor C2 respectively, the other end of the capacitor C2 is connected to the power supply, the source of the PMOS field effect tube MP9 is connected to the power supply, the drain of the PMOS field effect tube MP9 is the output end of the second current reference module, and is connected in parallel with the drain of the PMOS field effect tube MP2.

[0021] Furthermore, the PMOS field effect transistor MP5 and the PMOS field effect transistor MP6 are current mirrors; the NMOS field effect transistor MN6, the NMOS field effect transistor MN7, the NMOS field effect transistor MN8 and the NMOS field effect transistor M9 are cascode structures.

[0022] Furthermore, the current expression of the second current reference module is as follows:

[0023]

[0024] Among them, I PTC represents the current of the second current reference module, R3 represents the resistance, β MN7 Represents the gain factor of NMOS field effect transistor MN7, β MN9 Represents the gain factor of NMOS field effect transistor MN9.

[0025] Beneficial effects of the present invention:

[0026] (1) The present invention proposes a bias circuit structure for multiple voltages, using a novel current reference combination structure, mainly for some special circuit requirements, that is, wide power supply voltage and requiring internal bias current to have a certain correlation with the power supply voltage and a good temperature coefficient. The present invention can ensure a certain correlation with the power supply and a certain temperature characteristic under multiple power supply voltage conditions, and the implementation scheme is simple.

[0027] (2) The first current reference module generates a current that varies with the power supply voltage, that is, it is sensitive to the power supply voltage and due to the temperature coefficient of the resistor, it is a current with a negative temperature coefficient. The second current reference module generates a current that does not vary with the power supply voltage, that is, it is insensitive to the power supply voltage and has a positive temperature coefficient. The present invention combines the two currents into one current, thereby obtaining a current that is insensitive to the power supply and temperature.

[0028] (3) If different power supply voltage sensitivities are required in the application, the multiplier of the MOS tube can be adjusted to achieve this. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the circuit structure of the first current reference module in the present invention.

[0030] Figure 2 Schematic diagram of the circuit structure of the second current reference module in the present invention.

[0031] Figure 3 Schematic diagram of the temperature characteristic curve in this embodiment. DETAILED DESCRIPTION

[0032] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0033] Example

[0034] A bias circuit refers to a circuit that can provide stable and accurate voltage bias or current bias when the manufacturing process, system power supply voltage, or external temperature changes. It is widely used in various electronic circuits, including analog circuits, mixed analog and digital circuits, and pure digital circuits. The present invention proposes a bias circuit that can be applied to multiple voltages. It adopts a novel combination structure and, for certain special circuits, achieves a certain correlation between the bias current and the voltage. The bias current has a small change with temperature and is insensitive to temperature. Figure 1-Figure 2 As shown, it includes a first current reference module that changes with the power supply voltage and a second current reference module that does not change with the power supply voltage; the output end of the first current reference module is a current reference NTC with a negative temperature coefficient, and the output end of the second current reference module is a current reference PTC with a positive temperature coefficient; the output end of the first current reference module and the output end of the second current reference module are in a parallel structure, and the output end of the first current reference module and the output end of the second current reference module after the parallel connection serve as the output end of the bias circuit structure.

[0035] like Figure 1 As shown, the first current reference module includes a resistor R1, a capacitor C1, PMOS field effect transistors MP1 and MP2, and NMOS field effect transistors MN1 and MN2; one end of the resistor R1 is connected to a power supply, the other end of the resistor R1 is connected to the drain of the NMOS field effect transistor MN1, the gate of the NMOS field effect transistor MN1 is respectively connected to the drain of the NMOS field effect transistor MN1 and the gate of the NMOS field effect transistor MN2, the source of the NMOS field effect transistor MN1 is grounded, the source of the NMOS field effect transistor MN2 is grounded, and the The drain of the field effect transistor MN2 is connected to the drain of the PMOS field effect transistor MP1, the source of the PMOS field effect transistor MP1 is connected to the power supply, the gate of the PMOS field effect transistor MP1 is respectively connected to one end of the capacitor C1, the gate of the PMOS field effect transistor MP2 and the drain of the NMOS field effect transistor MN2, the other end of the capacitor C1 is connected to the power supply, the drain of the PMOS field effect transistor MP2 is the output end of the first current reference module, and is connected in parallel with the output end of the second current reference module, and the source of the PMOS field effect transistor MP2 is connected to the power supply.

[0036] In this embodiment, the purpose of the first current reference module is to generate a current with a negative temperature coefficient, using a temperature coefficient (TCR) to describe the change of resistance with temperature:

[0037]

[0038] in, It represents the rate of change of resistance value with temperature, and R represents resistance.

[0039] The resistor current I in the first current reference module:

[0040]

[0041] Among them, I NTC represents the resistor current in the first current reference module, VCC represents the power supply voltage, VGS MN1 represents the gate-source voltage of the NMOS field effect transistor MN1, and R1 represents the resistor.

[0042] The partial derivative of the resistor current I in the first current reference module with respect to temperature is:

[0043]

[0044] in, Represents the first current reference module resistance current I NTC Regarding the partial derivative coefficient of current and temperature, R and R1 both represent resistance, T represents temperature, and VGS MN1 It represents the gate-source voltage of NMOS field effect tube MN1, VCC represents the power supply voltage, TCR represents the temperature coefficient, The temperature coefficient of current is calculated by expressing the rate of change of resistance with temperature.

[0045] The temperature coefficient of the current is calculated:

[0046]

[0047] in, Represents the first current reference module resistance current I NTC Regarding the partial derivative coefficient of current and temperature, R and R1 both represent resistance, T represents temperature, and VGS MN1 It represents the gate-source voltage of NMOS field effect tube MN1, VCC represents the power supply voltage, TCR represents the temperature coefficient, It represents the rate of change of resistance with temperature.

[0048] like Figure 2 As shown, the second current reference module includes a startup circuit unit and a core reference unit connected to the startup circuit unit.

[0049] like Figure 2 As shown, the startup circuit unit includes a resistor R2, a PMOS field effect transistor MP3, and NMOS field effect transistors MN3 and MN4; the source of the PMOS field effect transistor MP3 is connected to a power supply, the gate of the PMOS field effect transistor MP3 is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, the drain of the PMOS field effect transistor MP3 is respectively connected to the gate of the NMOS field effect transistor MN4 and the drain of the NMOS field effect transistor MN3, the source of the NMOS field effect transistor MN3 is grounded, the source of the NMOS field effect transistor MN4 is grounded, and the drain of the NMOS field effect transistor MN4 and the gate of the NMOS field effect transistor MN3 are both connected to the core reference unit.

[0050] In this embodiment, since the second current reference module is a self-biased structure, the structure has a degenerate state, so the circuit cannot start automatically, so a startup circuit needs to be added. When the power supply is powered on, no current flows through the core reference part, the gate voltage of the NMOS field effect tube MN3 is low, the NMOS field effect tube MN3 is in a closed state, and the gate end of the PMOS field effect tube MP3 is grounded through a resistor. At this time, the PMOS field effect tube MP3 is immediately turned on, and the gate voltage of the NMOS field effect tube MN4 is high. At this time, the NMOS field effect tube MN4 is turned on. After the NMOS field effect tube MN4 is turned on, the gate voltage of the PMOS field effect tubes MP5 and MP6 is pulled down. At this time, the PMOS field effect tubes MP5 and MP6 are turned on, and current is drawn from the power supply, and the core reference part starts normally. At this time, the gate voltage of the NMOS field effect tube MN3 increases, exceeds the threshold voltage of the NMOS field effect tube MN3, and the NMOS field effect tube MN4 will be turned on, and the gate voltage of the NMOS field effect tube MN4 will be pulled down, and the startup circuit stops working.

[0051] like Figure 2As shown, the core reference unit includes a capacitor C2, a resistor R3, PMOS field effect transistors MP4-MP9 and NMOS field effect transistors MN5-MN11; the source of the PMOS field effect transistor MP4 is connected to a power supply, the gate of the PMOS field effect transistor MP4 is respectively connected to the drain of the NMOS field effect transistor MN4, the gate of the PMOS field effect transistor MP5, the gate of the PMOS field effect transistor MP6 and the gate of the PMOS field effect transistor MP7, the drain of the PMOS field effect transistor MP4 is respectively connected to the drain of the NMOS field effect transistor MN5, the gate of the NMOS field effect transistor MN3, the gate of the NMOS field effect transistor MN5, the gate of the NMOS field effect transistor MN6 and the gate of the NMOS field effect transistor MP7. The gate of the OS field effect tube MN6 is connected to the gate of the NMOS field effect tube MN8, the source of the NMOS field effect tube MN5 is grounded, the source of the NMOS field effect tube MN6 is connected to the drain of the NMOS field effect tube MN7, the source of the NMOS field effect tube MN8 is connected to the drain of the NMOS field effect tube MN9, the source of the PMOS field effect tube MP5 is connected to the power supply, the drain of the PMOS field effect tube MP5 is respectively connected to the drain of the NMOS field effect tube MN6, the gate of the NMOS field effect tube MN7 and the gate of the NMOS field effect tube MN9, and the source of the NMOS field effect tube MN7 is grounded. , the source of the NMOS field effect transistor MN9 is connected to one end of the resistor R3, the other end of the resistor R3 is grounded, the source of the PMOS field effect transistor MP6 is connected to the power supply, the drain of the PMOS field effect transistor MP6 is connected to the drain of the NMOS field effect transistor MN8, the source of the NMOS field effect transistor MN8 is connected to the drain of the NMOS field effect transistor MN9, the source of the PMOS field effect transistor MP7 is connected to the power supply, the drain of the PMOS field effect transistor MP7 is respectively connected to the drain of the NMOS field effect transistor MN10, the gate of the NMOS field effect transistor MN10 and the gate of the NMOS field effect transistor MN11, the The source of the NMOS field effect transistor MN10 is grounded, the source of the NMOS field effect transistor MN11 is grounded, the drain of the NMOS field effect transistor MN11 is connected to the drain of the PMOS field effect transistor MP8, the source of the PMOS field effect transistor MP8 is connected to a power supply, the gate of the PMOS field effect transistor MP8 is respectively connected to the gate of the PMOS field effect transistor MP9 and one end of the capacitor C2, the other end of the capacitor C2 is connected to a power supply, the source of the PMOS field effect transistor MP9 is connected to the power supply, and the drain of the PMOS field effect transistor MP9 is the output end of the second current reference module and is connected in parallel with the drain of the PMOS field effect transistor MP2.

[0052] In this embodiment, the PMOS field effect transistor MP5 and the PMOS field effect transistor MP6 are current mirrors; the upper current mirror method is adopted to make the same current flow through the NMOS field effect transistors MN7 and MN9.

[0053] In this embodiment, the NMOS field effect transistors MN6, MN7, MN8 and M9 are of a common source and common gate structure, which can suppress the channel length modulation effect and make the currents flowing through the NMOS field effect transistors MN7 and MN9 more matched.

[0054] In this embodiment, the gate-source voltage expression of the NMOS field effect transistor MN7 is as follows:

[0055]

[0056] Among them, VGS MN7 represents the gate-source voltage of NMOS field effect tube MN7, VT represents the threshold voltage of NMOS field effect tube, β MN7 Represents the gain factor of NMOS field effect transistor MN7.

[0057] The expression of the gate-source voltage of the NMOS field effect tube MN9 is as follows:

[0058]

[0059] Among them, VGS MN9 Represents the gate-source voltage of NMOS field effect tube MN7, β MN9 Represents the gain factor of NMOS field effect transistor MN9.

[0060] So the current of the second current reference module can be solved:

[0061]

[0062] Among them, I PTC represents the current of the second current reference module, R3 represents the resistance, β MN7 Represents the gain factor of NMOS field effect transistor MN7, β MN9 Represents the gain factor of NMOS field effect transistor MN9.

[0063] In this embodiment, the first current reference module generates a current that varies with the power supply voltage and has a negative temperature coefficient. The second current reference module generates a current that does not vary with the power supply voltage and has a positive temperature coefficient. The present invention combines the two currents into one current, thereby obtaining a current that is insensitive to power supply and temperature.

[0064] In this embodiment, the first current reference module is a simple current reference, which uses the current on the MOS tube mirror resistor R1. The MOS tubes have the same width-to-length ratio. The current gain of the circuit can be adjusted by changing the multiplier values ​​of MN1 and MN2.

[0065] In this embodiment, by changing the resistance values ​​of resistors R1 and R3, a current size different from the example (such as: when the temperature is 25 degrees Celsius and the power supply voltage is 5 volts, the current is 14.475 microamperes) is generated, and the multiplier value of MN1 and MN2 in the first current reference module can be changed to adjust the current gain.

[0066] In this embodiment, the circuit is simulated, such as Figure 3 As shown, the temperature range is set at -40℃~105℃. It can be seen that the temperature coefficient of PTC is 9.86n A / ℃, the temperature coefficient of NTC is -10.2n A / ℃, and the combined current temperature coefficient is -0.96n A / ℃.

Claims

1. A bias circuit structure for multiple voltages, characterized in that: It includes a first current reference module that changes with the power supply voltage and a second current reference module that does not change with the power supply voltage; the output end of the first current reference module is a current reference NTC with a negative temperature coefficient, and the output end of the second current reference module is a current reference PTC with a positive temperature coefficient; The output end of the first current reference module and the output end of the second current reference module are in a parallel structure, and the output end of the first current reference module and the output end of the second current reference module after the parallel connection serve as the output end of the bias circuit structure; The first current reference module includes a resistor R1, a capacitor C1, PMOS field effect transistors MP1 and MP2, and NMOS field effect transistors MN1 and MN2; One end of the resistor R1 is connected to a power supply, the other end of the resistor R1 is connected to the drain of the NMOS field effect transistor MN1, the gate of the NMOS field effect transistor MN1 is respectively connected to the drain of the NMOS field effect transistor MN1 and the gate of the NMOS field effect transistor MN2, the source of the NMOS field effect transistor MN1 is grounded, the source of the NMOS field effect transistor MN2 is grounded, the drain of the NMOS field effect transistor MN2 is connected to the drain of the PMOS field effect transistor MP1, the source of the PMOS field effect transistor MP1 is connected to a power supply, the gate of the PMOS field effect transistor MP1 is respectively connected to one end of the capacitor C1, the gate of the PMOS field effect transistor MP2 and the drain of the NMOS field effect transistor MN2, the other end of the capacitor C1 is connected to a power supply, the drain of the PMOS field effect transistor MP2 is the output end of the first current reference module, and is connected in parallel with the output end of the second current reference module, and the source of the PMOS field effect transistor MP2 is connected to a power supply; The second current reference module includes a startup circuit unit and a core reference unit connected to the startup circuit unit; The startup circuit unit includes a resistor R2, a PMOS field effect transistor MP3, and NMOS field effect transistors MN3 and MN4; The source of the PMOS field effect transistor MP3 is connected to a power supply, the gate of the PMOS field effect transistor MP3 is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, the drain of the PMOS field effect transistor MP3 is respectively connected to the gate of the NMOS field effect transistor MN4 and the drain of the NMOS field effect transistor MN3, the source of the NMOS field effect transistor MN3 is grounded, the source of the NMOS field effect transistor MN4 is grounded, and the drain of the NMOS field effect transistor MN4 and the gate of the NMOS field effect transistor MN3 are both connected to the core reference unit; The core reference unit includes a capacitor C2, a resistor R3, PMOS field effect transistors MP4-MP9 and NMOS field effect transistors MN5-MN11; The source of the PMOS field effect transistor MP4 is connected to a power supply, the gate of the PMOS field effect transistor MP4 is respectively connected to the drain of the NMOS field effect transistor MN4, the gate of the PMOS field effect transistor MP5, the gate of the PMOS field effect transistor MP6 and the gate of the PMOS field effect transistor MP7, the drain of the PMOS field effect transistor MP4 is respectively connected to the drain of the NMOS field effect transistor MN5, the gate of the NMOS field effect transistor MN3, the gate of the NMOS field effect transistor MN5, the gate of the NMOS field effect transistor MN6 and the gate of the NMOS field effect transistor MN8, the NMOS field effect transistor MN The source of the NMOS field effect tube MN5 is grounded, the source of the NMOS field effect tube MN6 is connected to the drain of the NMOS field effect tube MN7, the source of the NMOS field effect tube MN8 is connected to the drain of the NMOS field effect tube MN9, the source of the PMOS field effect tube MP5 is connected to the power supply, the drain of the PMOS field effect tube MP5 is respectively connected to the drain of the NMOS field effect tube MN6, the gate of the NMOS field effect tube MN7 and the gate of the NMOS field effect tube MN9, the source of the NMOS field effect tube MN7 is grounded, and the source of the NMOS field effect tube MN9 is connected to one end of the resistor R3. The other end of the resistor R3 is grounded, the source of the PMOS field effect transistor MP6 is connected to the power supply, the drain of the PMOS field effect transistor MP6 is connected to the drain of the NMOS field effect transistor MN8, the source of the NMOS field effect transistor MN8 is connected to the drain of the NMOS field effect transistor MN9, the source of the PMOS field effect transistor MP7 is connected to the power supply, the drain of the PMOS field effect transistor MP7 is respectively connected to the drain of the NMOS field effect transistor MN10, the gate of the NMOS field effect transistor MN10 and the gate of the NMOS field effect transistor MN11, the source of the NMOS field effect transistor MN10 is connected to the power supply, and the drain of the PMOS field effect transistor MP7 is respectively connected to the drain of the NMOS field effect transistor MN10, the gate of the NMOS field effect transistor MN10 and the gate of the NMOS field effect transistor MN11. The gate of the PMOS field effect tube MP8 is connected to the gate of the PMOS field effect tube MP9 and one end of the capacitor C2 respectively, the other end of the capacitor C2 is connected to the power supply, the source of the PMOS field effect tube MP9 is connected to the power supply, the drain of the PMOS field effect tube MP9 is the output end of the second current reference module, and is connected in parallel with the drain of the PMOS field effect tube MP2.

2. The bias circuit structure for multiple voltages according to claim 1, characterized in that: The resistance current expression of the first current reference module is as follows: Among them, I NTC represents the resistance current of the first current reference module, VCC represents the power supply voltage, VGS MN1 represents the gate-source voltage of the NMOS field effect transistor MN1, and R1 represents the resistor.

3. The bias circuit structure for multiple voltages according to claim 2, characterized in that: The expression of the resistance current temperature coefficient of the first current reference module is as follows: in, Represents the first current reference module resistance current I NTC Regarding the partial derivative coefficient of current temperature, R and R1 both represent resistance, T represents temperature, and VGS MN1 It represents the gate-source voltage of NMOS field effect tube MN1, VCC represents the power supply voltage, TCR represents the temperature coefficient, It represents the rate of change of resistance with temperature.

4. The bias circuit structure for multiple voltages according to claim 3, characterized in that: The PMOS field effect transistor MP5 and the PMOS field effect transistor MP6 are current mirrors; the NMOS field effect transistor MN6, the NMOS field effect transistor MN7, the NMOS field effect transistor MN8 and the NMOS field effect transistor M9 are cascode structures.

5. The bias circuit structure for multiple voltages according to claim 4, characterized in that: The current expression of the second current reference module is as follows: Among them, I PTC represents the current of the second current reference module, R3 represents the resistance, β MN7 Represents the gain factor of NMOS field effect transistor MN7, β MN9 Represents the gain factor of NMOS field effect transistor MN9.

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