Data emergency storage method and system for chip faults and computer equipment

Abstract

The invention provides a data emergency storage method and system for a chip fault and computer equipment, and the method comprises the steps: predicting a chip fault probability and a fault region, transferring data in a possible fault region of a chip to other data storage regions before the chip breaks down, and changing a storage path of to-be-stored data of the chip at the same time, according to the chip data backup storage method, the chip data backup storage method and the chip data backup storage device, the chip data are protected in advance before the chip breaks down, damage caused by the fact that the chip data are not uploaded when the chip breaks down is avoided, and the problems that in the prior art, chip data backup storage timeliness is poor, and chip data protection storage is not timely enough are solved. The problem that an existing chip data backup technology depends on an additional server and a transmission network is further solved, independence and efficiency of chip data emergency storage are improved, and data protection cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip data emergency storage, and in particular to a data emergency storage method, system and computer equipment for chip failure. Background Art

[0002] A chip refers to an integrated circuit integrated on a small piece of silicon wafer, composed of multiple interconnected electronic components (such as transistors, resistors and capacitors), and is the processing and storage unit of modern digital computers.

[0003] At present, with the iteration of chip software and hardware technology, the chip's anti-interference ability, computing efficiency, service life and scope of application are constantly improving. However, the improvement of chip performance makes its working environment more stringent. The chip's operating frequency, operating voltage and operating current are getting higher and higher. This high-voltage working environment is also accompanied by the high-frequency switching action of the chip, which makes it easy to generate electromagnetic interference and ringing phenomena, causing abnormal chip function, circuit interruption, short circuit or even damage, resulting in a huge risk of chip data being damaged and unrecoverable. Therefore, how to store data in an emergency before and after a chip failure occurs is the research focus of existing technologies.

[0004] The existing chip data emergency storage method uses cloud synchronization operations to regularly upload chip data to cloud server backup, thereby ensuring that most of the backup data can be saved when the chip fails. However, since data upload depends on network quality and server performance, its timeliness is poor. In addition, this technology cannot protect the chip data that has not been uploaded in the event of a sudden chip failure. There is always some data corruption, and the protection and storage of chip data is not timely enough. Summary of the invention

[0005] The purpose of this application is to improve the timeliness of data backup storage, so that in the event of a sudden chip failure, the unuploaded data in the storage chip failure area can be protected in time, and the problem of the prior art being unable to protect the unuploaded chip data in the event of a sudden chip failure, there is always some data corruption, and the protection and storage of chip data is not timely enough.

[0006] In order to achieve the above objectives, in a first aspect, the present application provides a data emergency storage method for chip failure, the method comprising the following steps:

[0007] Get the current state of the chip and the data to be stored;

[0008] Based on the current state of the chip, predict the total chip failure probability by using a preset chip failure prediction program;

[0009] When the total chip failure probability is greater than a preset probability threshold, predicting a chip failure area based on the current state of the chip;

[0010] Based on the current data to be stored, obtaining a current data storage area and a current data storage path of the chip;

[0011] Based on the chip fault area, adjusting the current data storage area and the current data storage path to obtain a new data storage area and a new data storage path;

[0012] Transferring the stored data in the fault area to the new data storage area;

[0013] The current data to be stored is stored in the new data storage area through the new data storage path.

[0014] In the above implementation, by predicting the chip failure probability and the failure area, before the chip fails, the data in the possible failure area of ​​the chip is transferred to other data storage areas, and at the same time, the storage path of the chip data to be stored is changed to avoid the area where the chip may fail. The chip data is protected in advance before the chip fails, avoiding the problem that when the chip fails, the unuploaded data in the chip failure area is destroyed and cannot be restored. The problem of poor timeliness of chip data backup storage and insufficient timeliness of chip data protection storage in the prior art is solved, and the problem of existing chip data backup technology relying on additional servers and transmission networks is further solved, which improves the independence and efficiency of chip data emergency storage and reduces the cost of data protection.

[0015] In a possible implementation, the current state of the chip includes a current operating state of the chip and a current temperature state of the chip; and obtaining the current state of the chip includes:

[0016] Get the current operation data and temperature data of the chip;

[0017] Based on the current operation data of the chip, obtaining several chip current data operation types and chip current operation data amounts;

[0018] Based on a number of the chip's current data operation types and the chip's current operation data volume, obtaining the chip's current operation state through a preset chip state evaluation strategy;

[0019] The current temperature data of the chip is processed by a preset chip template to obtain the current temperature distribution information of the chip as the current temperature state of the chip.

[0020] It should be noted that the current data operation type of the chip includes the operation type corresponding to each chip processing program; the chip template is the surface structure template of the chip; the chip status evaluation strategy obtains the current operation status of the chip by analyzing the type of the current data operation type of the chip and the range of the current operation data volume, wherein a chip operation status corresponds to a set of data operation types and a range of operation data volume.

[0021] In this implementation, the current operating state of the chip is obtained through multi-dimensional information of the current data operation type and the current operating data volume of the chip, which improves the accuracy of obtaining the current operating state of the chip. In addition, by processing the original temperature data of the chip, the current temperature distribution information of the chip is obtained, which can more accurately analyze the temperature state of the chip compared to the original temperature data of the chip.

[0022] In a possible implementation, predicting the total failure probability of the chip based on the current operating state of the chip includes:

[0023] Based on the current operating state of the chip, query the first failure probability of the corresponding historical operating state in a preset historical database;

[0024] Get the historical temperature status of the chip;

[0025] By sorting out the current temperature state of the chip and the historical temperature state of the chip, the chip temperature state change information is obtained, and then split into a plurality of chip area sub-temperature state change information;

[0026] Based on the temperature state change information of the chip regions, predict the temperature change trends of the chip regions;

[0027] Calculating the second failure probabilities of the plurality of chip regions based on the temperature change trends of the plurality of chip regions;

[0028] Calculating a plurality of chip region sub-failure probabilities based on a plurality of chip region second failure probabilities and the first failure probabilities;

[0029] The sub-failure probabilities of the chip regions are taken as the total failure probability of the chip.

[0030] It should be noted that the historical database includes all historical fault information corresponding to the historical operating status of the chip. By calculating the proportion of the number of fault information corresponding to each fault type in the historical fault information corresponding to the historical operating status of the chip, the failure probability of each fault type corresponding to the historical operating status can be obtained as the first failure probability.

[0031] It should also be noted that the chip temperature state change information is the data change information of the chip temperature state in the time dimension, and the data change information includes the temperature change range and the temperature change direction; the chip area temperature change trend includes the change trend of the chip area temperature change range, the change trend of the chip area temperature change direction and the change trend of the chip area temperature value.

[0032] In this implementation, by calculating the sub-fault probability of each area of ​​the chip separately, the accuracy of fault probability calculation and fault location is improved, and the accuracy and comprehensiveness of chip fault prediction are improved.

[0033] In a possible implementation, the calculating the second failure probabilities of the plurality of chip regions based on the temperature change trends of the plurality of chip regions includes:

[0034] The deviation value between the temperature change trend of any chip area and the preset temperature change data is calculated, and then the deviation value is normalized to obtain the second failure probability of the chip area.

[0035] It should be noted that the deviation value includes positive and negative deviation values. A positive deviation value indicates that the temperature change trend of the chip area is higher than the preset temperature change data, and a negative deviation value indicates that the temperature change trend of the chip area is lower than the preset temperature change data. The larger the positive deviation value, the higher the calculated second fault probability, and the larger the negative deviation value, the lower the calculated second fault probability.

[0036] In this implementation, the deviation value is normalized to standardize the obtained second failure probability, which facilitates comprehensive analysis and processing of the second failure probability and improves the accuracy of the calculated sub-failure probability of each chip area and the total chip failure probability.

[0037] In a possible implementation, acquiring the current data storage area and current data storage path of the chip based on the current data to be stored includes:

[0038] Based on the current data to be stored, obtaining a data task and a data operation type of the current data to be stored;

[0039] Based on the data task, obtaining the data source and task target of the current data to be stored;

[0040] Based on the data operation type, screening out a plurality of first data storage areas from all data storage areas of the chip;

[0041] Based on the data source, screening out a current data storage area from a plurality of the first data storage areas;

[0042] Obtaining a chip processing area where the task target is located;

[0043] Based on the chip processing area and the current data storage area, a current data storage path is constructed.

[0044] In this implementation, the current data storage area is obtained through the operation type and data source of the current data to be stored, and the current data storage path is determined based on the chip processing area and the current data storage area, thereby enhancing the accuracy of locating the current data storage area and the current data storage path and improving the efficiency of emergency data storage.

[0045] In a possible implementation, adjusting the current data storage area and the current data storage path based on the chip fault area to obtain a new data storage area and a new data storage path includes:

[0046] Based on the chip fault area and the total chip fault probability, screening out a plurality of second data storage areas from all the data storage areas of the chip;

[0047] Obtaining a number of current free space amounts of a number of the second data storage areas;

[0048] Filter out the new data storage area with the largest current free space from the plurality of second data storage areas;

[0049] A new data storage path is constructed based on the chip processing area and the new data storage area.

[0050] It should be noted that, based on the sub-fault probabilities of several chip areas in the total failure probability, when the sub-fault probability of any chip area is greater than a preset probability threshold, the chip area is treated as a risk area, and then based on all fault areas and all risk areas, a data storage area that neither overlaps with, intersects with, nor is adjacent to the fault area and the risk area is screened out from all data storage areas of the chip as the second data storage area.

[0051] In this implementation, by screening new data storage areas that are not associated with fault areas and risk areas and have the largest amount of free space as areas for emergency data storage, both the storage needs of current data to be stored and the transfer needs of stored data are ensured, and the security of the new data storage area is guaranteed, thereby avoiding data damage and data loss caused by chip failures and improving the success rate and data integrity of emergency data storage.

[0052] In a possible implementation manner, after storing the current data to be stored in the new data storage area through the new data storage path, the method further includes:

[0053] In response to new input data, acquiring data content of the new input data and data association information between the new input data and the current data to be stored;

[0054] Storing the data content in the new data storage area through the new data storage path;

[0055] Based on the data association information, concatenate the new input data with the current data to be stored to obtain target storage data;

[0056] The storage location of the target storage data in the new data storage area is adjusted to optimize the data storage structure.

[0057] It should be noted that the data association information includes data sequence association information and data interaction association information between the data content of the new data and the current data to be stored. After the step of storing the current data to be stored in the new data storage area through the new data storage path, the current data to be stored is already in the new data storage area. The splicing of the new input data and the current data to be stored means splicing the new input data and the current data to be stored in the new data storage area.

[0058] In this implementation, new input data and current data to be stored are spliced ​​together through data association information, thereby ensuring the association between stored data, improving the integrity of emergency stored data, and avoiding problems such as storage data confusion and storage data anomalies.

[0059] In a second aspect, the present application provides a data emergency storage system for chip failure, the system comprising:

[0060] A first information acquisition module is used to obtain the current state of the chip and the current data to be stored;

[0061] A failure probability prediction module, which is preset with a chip failure prediction program and is used to predict the total failure probability of the chip through the chip failure prediction program based on the current state of the chip;

[0062] A fault area prediction module, used for predicting a chip fault area based on a current state of the chip when the total fault probability of the chip is greater than a preset probability threshold;

[0063] A second information acquisition module is used to acquire a current data storage area and a current data storage path of the chip based on the current data to be stored;

[0064] An adjustment module, configured to adjust the current data storage area and the current data storage path based on the chip fault area to obtain a new data storage area and a new data storage path;

[0065] A data transfer module, used for transferring the stored data in the fault area to the new data storage area;

[0066] The data storage module is used to store the current data to be stored in the new data storage area through the new data storage path.

[0067] In a possible implementation, the data emergency storage system for chip failure further includes a data splicing module, which is used to implement the following steps:

[0068] In response to new input data, acquiring data content of the new input data and data association information between the new input data and the current data to be stored;

[0069] Storing the data content in the new data storage area through the new data storage path;

[0070] Based on the data association information, concatenate the new input data with the current data to be stored to obtain target storage data;

[0071] The storage location of the target storage data in the new data storage area is adjusted to optimize the data storage structure.

[0072] In a third aspect, the present application provides a computer device, including a processor and a memory, wherein the memory is used to store a computer program, and when the processor calls the computer program, the method described in the first aspect or any possible implementation method of the first aspect is implemented.

[0073] According to the first aspect, the second aspect and the third aspect of the present application, a data emergency storage method, system and computer device for chip failures provided have at least the following advantages compared with the prior art:

[0074] First, before a chip fails, the present application transfers data from a possible fault area to other storage areas and changes the path of the data to be stored to avoid possible fault areas, thereby protecting the data in advance and preventing data damage. The method and system provided by the present application do not rely on additional servers and transmission networks, improve the independence and efficiency of emergency data storage, and reduce data protection costs.

[0075] Second, this application improves the accuracy of obtaining the current operating status of the chip by obtaining multi-dimensional information such as the chip's current data operation type and operating data volume.

[0076] Third, the present application obtains more accurate temperature distribution information by processing the original temperature data of the chip, thereby more accurately analyzing the temperature status of the chip.

[0077] Fourth, the present application calculates the sub-fault probability of each area of ​​the chip separately and normalizes the deviation value, thereby improving the accuracy of fault probability calculation and positioning and enhancing the comprehensiveness of fault prediction.

[0078] Fifth, the present application determines the current data storage area and path according to the operation type and data source of the data to be stored, thereby improving the efficiency and accuracy of emergency data storage.

[0079] Sixth, the present application selects a new data storage area that is independent of the fault area and the risk area and has the largest amount of free space, ensuring data storage requirements and security and avoiding data damage and loss.

[0080] Seventh, the present application ensures the relevance between stored data by splicing new input data with current data to be stored, thereby improving the integrity of emergency storage data and avoiding data confusion and anomalies. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 It is a flowchart of a data emergency storage method for chip failure provided by an embodiment of the present application;

[0082] Figure 2 It is a structural schematic diagram of a data emergency storage system for chip failure provided by an embodiment of the present application;

[0083] Figure 3 It is a structural schematic diagram of a computer device for implementing a data emergency storage method for chip failure provided by an embodiment of the present application;

[0084] Among them: 200, data emergency storage system for chip failure; 210, first information acquisition module; 220, fault probability prediction module; 230, fault area prediction module; 240, second information acquisition module; 250, adjustment module; 260, data transfer module; 270, data storage module; 280, data splicing module. DETAILED DESCRIPTION

[0085] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0086] The following detailed descriptions are all exemplary descriptions, and are intended to provide further detailed descriptions of the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments, and are not intended to limit the present application; the terms "including" and "having" in the specification and claims of the present application and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0087] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0088] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0089] Before describing the present application in detail with reference to the accompanying drawings and in combination with the embodiments, the terms and application scenarios involved in the present application are first described.

[0090] The data emergency storage method for chip failure provided in the embodiment of the present application can be applied to the application environment of data emergency storage of the chip. The method can be applied to terminals and servers, and can also be applied to systems including terminals and servers, and the method and system are implemented through data interaction between terminals and servers. Among them, the terminal can be a hardware device or software interface that allows users to interact with computer systems, embedded systems or chip systems, such as: a computer device including a processor, memory and storage device; a portable computing device with touch screen operation; a computer software for simulating the functions of a hardware terminal.

[0091] The chip described in the present application can be any semiconductor package structure with an integrated circuit, for example: a microprocessor, a memory chip, a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an analog chip, a power management chip (PMIC), and a system-on-chip (SoC).

[0092] Figure 1 1 is a flow chart of a data emergency storage method for chip failure provided by an embodiment of the present application. Figure 1 The present application provides a data emergency storage method for chip failure, comprising the following steps:

[0093] S101, obtaining the current state of the chip and the current data to be stored.

[0094] Specifically, the current state of the chip in step S101 includes the current operating state of the chip and the current temperature state of the chip.

[0095] It should be noted that this embodiment obtains the current operation data of the chip and the current temperature data of the chip by receiving the chip detection data (monitoring data) collected in real time by the chip detection program, and then obtains the current operation state of the chip and the current temperature state of the chip. Then, the data content that has been currently input into the chip but has not yet been stored is obtained as the current data to be stored. Among them, the current operation state of the chip is used to indicate the current working state of the chip, and the working state includes: no working state, low load state, normal load state, high load state and overload state. When the chip is in a high load state or an overload state, it will easily fail.

[0096] S102: Based on the current state of the chip, predict the total chip failure probability by using a preset chip failure prediction program.

[0097] Optionally, the total short circuit probability of the chip is used as the total failure probability of the chip, and the total short circuit probability includes the sub-short circuit probability of each short circuit-prone area of ​​the chip, wherein the short circuit-prone area includes each area between the VDD (positive power supply terminal) and the GND (ground terminal) of the chip.

[0098] It should be noted that when a chip has a short circuit failure, the risk of damaging the chip's current stored data and stored data is the greatest, so the total chip short circuit probability can be treated as the total chip failure probability.

[0099] S103: When the total chip failure probability is greater than a preset probability threshold, predicting a chip failure area based on the current state of the chip.

[0100] S104: Based on the current data to be stored, obtain the current data storage area and current data storage path of the chip.

[0101] S105 . Based on the chip fault area, adjust the current data storage area and the current data storage path to obtain a new data storage area and a new data storage path.

[0102] S106: Transfer the stored data in the fault area to the new data storage area.

[0103] S107: Store the current data to be stored in the new data storage area through the new data storage path.

[0104] Optionally, the step S101 of obtaining the current state of the chip includes:

[0105] Get the current operation data and temperature data of the chip;

[0106] Based on the current operation data of the chip, obtaining several chip current data operation types and chip current operation data amounts;

[0107] Based on a number of the chip's current data operation types and the chip's current operation data volume, obtaining the chip's current operation state through a preset chip state evaluation strategy;

[0108] The current temperature data of the chip is processed by a preset chip template to obtain the current temperature distribution information of the chip as the current temperature state of the chip.

[0109] It should be noted that the current data operation type of the chip includes the operation type corresponding to each chip processing program, for example: image optimization type, data retrieval type, text extraction type and algorithm operation type.

[0110] Specifically, the current temperature data of the chip is distributed and arranged in the surface structure template of the chip, so as to obtain the current temperature distribution information of the chip and use it as the current temperature state of the chip.

[0111] Optionally, predicting the total failure probability of the chip based on the current operating state of the chip in step S102 includes:

[0112] Based on the current operating state of the chip, query the first failure probability of the corresponding historical operating state in a preset historical database;

[0113] Get the historical temperature status of the chip;

[0114] By sorting out the current temperature state of the chip and the historical temperature state of the chip, the chip temperature state change information is obtained, and then split into a plurality of chip area sub-temperature state change information;

[0115] Based on the temperature state change information of the chip regions, predict the temperature change trends of the chip regions;

[0116] Calculating the second failure probabilities of the plurality of chip regions based on the temperature change trends of the plurality of chip regions;

[0117] Calculating a plurality of chip region sub-failure probabilities based on a plurality of chip region second failure probabilities and the first failure probabilities;

[0118] The sub-failure probabilities of the chip regions are taken as the total failure probability of the chip.

[0119] Specifically, the historical database includes all historical fault information corresponding to the historical operating status of the chip. By calculating the proportion of the number of fault information corresponding to each fault type in the historical fault information corresponding to the historical operating status of the chip, the failure probability of each fault type corresponding to the historical operating status can be obtained as the first failure probability.

[0120] It should be noted that the chip temperature state change information is the data change information of the chip temperature state in the time dimension, and the data change information includes the temperature change range and the temperature change direction; the chip area temperature change trend includes the change trend of the chip area temperature change range, the change trend of the chip area temperature change direction and the change trend of the chip area temperature value.

[0121] Optionally, the total short circuit probability of the chip is used as the total failure probability of the chip, and the total short circuit probability includes the sub-short circuit probabilities of each short circuit-prone area of ​​the chip, specifically including:

[0122] Based on the current operating state of the chip, query the first failure probability of the corresponding historical operating state in a preset historical database;

[0123] Based on the historical operating state, query the fault probability of the short-circuit fault type in the first fault probability corresponding to the historical operating state as the third fault probability of the short-circuit fault type corresponding to the operating state of each chip;

[0124] Get the historical temperature status of the chip;

[0125] Arrange the current temperature state of the chip and the historical temperature state of the chip in chronological order to obtain chip temperature state change information, and then split it into several chip area sub-temperature state change information;

[0126] Based on the temperature state change information of the chip regions, predicting the temperature change trends of the chip regions by a linear fitting strategy;

[0127] Based on all chip regions, a number of short-circuit-prone regions are screened, wherein the short-circuit-prone regions are chip regions preset in the terminal;

[0128] Calculating the fourth fault probabilities of the plurality of short-circuit prone areas based on the temperature change trends corresponding to the plurality of short-circuit prone areas;

[0129] Calculating a plurality of short-circuit-prone area sub-short-circuit probabilities based on the fourth fault probabilities of the plurality of short-circuit-prone areas and the third fault probabilities;

[0130] The sub-short circuit probabilities of several of the short circuit prone areas are taken as the total short circuit probability.

[0131] Optionally, the calculating the second failure probabilities of the plurality of chip regions based on the temperature change trends of the plurality of chip regions includes:

[0132] The deviation value between the temperature change trend of any chip area and the preset temperature change data is calculated, and then the deviation value is normalized to obtain the second failure probability of the chip area.

[0133] Specifically, based on the changing trend of the temperature change range, the changing trend of the temperature change direction and the changing trend of the temperature value of any chip area, the predicted temperature change distribution information of the chip area is fitted and calculated, and then the deviation value between the predicted temperature change distribution information and the preset temperature change data is calculated, and then the deviation value is normalized to obtain the second failure probability of the chip area.

[0134] Optionally, the calculating the fourth fault probability of a plurality of short-circuit prone areas based on the temperature change trends corresponding to the plurality of short-circuit prone areas includes:

[0135] The deviation value between the temperature change trend of any short-circuit-prone area and the preset temperature change data is calculated, and then the deviation value is normalized to obtain the fourth fault probability of the short-circuit-prone area.

[0136] Specifically, based on the changing trend of the temperature change range, the changing trend of the temperature change direction and the changing trend of the temperature value of any short-circuit-prone area, the predicted temperature change distribution information of the short-circuit-prone area is fitted and calculated, and then the deviation value between the predicted temperature change distribution information and the preset temperature change data is calculated, and then the deviation value is normalized to obtain the fourth failure probability of the short-circuit-prone area.

[0137] Optionally, the step S104 of acquiring the current data storage area and current data storage path of the chip based on the current data to be stored includes:

[0138] Based on the current data to be stored, obtaining a data task and a data operation type of the current data to be stored;

[0139] Based on the data task, obtaining the data source and task target of the current data to be stored;

[0140] Based on the data operation type, screening out a plurality of first data storage areas from all data storage areas of the chip;

[0141] Based on the data source, screening out a current data storage area from a plurality of the first data storage areas;

[0142] Obtaining a chip processing area where the task target is located;

[0143] Based on the chip processing area and the current data storage area, a current data storage path is constructed.

[0144] It should be noted that each first data storage area corresponds to data of one or more data operation types; the data operation type of each current data to be stored corresponds to the data operation type of each current operation data, and the two are divided according to the same division standard.

[0145] It should also be noted that the data sources of the data to be stored include external input data sources, internal retrieved data sources and external retrieved data sources. Among them, the external input data source can be the source of data input from the outside by the user; the internal retrieved data source can be the source of data when the chip retrieves internal data for tasks such as data modification / operation / application / adjustment; the external retrieved data source can be the source of data when the chip retrieves data from the cloud or other databases for use.

[0146] Specifically, when the data source is an external input data source, the current data storage area may be the data storage area with the largest amount of free space among several first data storage areas; when the data source is an internally retrieved data source, the current data storage area may be the data storage area that stores the retrieved data; when the data source is an externally retrieved data source, the current data storage area may be a new data storage area that does not store any data.

[0147] Optionally, the step S105 of adjusting the current data storage area and the current data storage path based on the chip fault area to obtain a new data storage area and a new data storage path includes:

[0148] Based on the chip fault area and the total chip fault probability, screening out a plurality of second data storage areas from all the data storage areas of the chip;

[0149] Obtaining a number of current free space amounts of a number of the second data storage areas;

[0150] Filter out the new data storage area with the largest current free space from the plurality of second data storage areas;

[0151] A new data storage path is constructed based on the chip processing area and the new data storage area.

[0152] Specifically, based on the sub-fault probabilities of several chip areas in the total failure probability, when the sub-fault probability of any chip area is greater than a preset probability threshold, the chip area is treated as a risk area, and then based on all fault areas and all risk areas, a data storage area that neither overlaps with, intersects with, nor is adjacent to the fault area and the risk area is screened out from all data storage areas of the chip as the second data storage area.

[0153] Optionally, after storing the current data to be stored in the new data storage area through the new data storage path in step S107, the method further includes:

[0154] In response to new input data, acquiring data content of the new input data and data association information between the new input data and the current data to be stored;

[0155] Storing the data content in the new data storage area through the new data storage path;

[0156] Based on the data association information, concatenate the new input data with the current data to be stored to obtain target storage data;

[0157] The storage location of the target storage data in the new data storage area is adjusted to optimize the data storage structure.

[0158] It should be noted that the data association information includes data sequence association information and data interaction association information between the data content of the new data and the current data to be stored. After the step of storing the current data to be stored in the new data storage area through the new data storage path, the current data to be stored is already in the new data storage area. The splicing of the new input data and the current data to be stored means splicing the new input data and the current data to be stored in the new data storage area.

[0159] Figure 2 is a schematic diagram of a data emergency storage system for chip failure provided by an embodiment of the present application, with reference to Figure 2 The embodiment of the present application provides a data emergency storage system 200 for chip failure, including a first information acquisition module 210, a failure probability prediction module 220, a failure area prediction module 230, a second information acquisition module 240, an adjustment module 250, a data transfer module 260 and a data storage module 270, wherein:

[0160] The first information acquisition module 210 is used to obtain the current state of the chip and the current data to be stored;

[0161] The failure probability prediction module 220 is preset with a chip failure prediction program, which is used to predict the total failure probability of the chip through the chip failure prediction program based on the current state of the chip;

[0162] The fault region prediction module 230 is used to predict the chip fault region based on the current state of the chip when the total fault probability of the chip is greater than a preset probability threshold;

[0163] The second information acquisition module 240 is used to acquire the current data storage area and current data storage path of the chip based on the current data to be stored;

[0164] The adjustment module 250 is used to adjust the current data storage area and the current data storage path based on the chip fault area to obtain a new data storage area and a new data storage path;

[0165] The data transfer module 260 is used to transfer the stored data in the fault area to the new data storage area;

[0166] The data storage module 270 is used to store the current data to be stored in the new data storage area through the new data storage path.

[0167] Optionally, the data emergency storage system for chip failure further includes a data splicing module 280, which is used to implement the following steps:

[0168] In response to new input data, acquiring data content of the new input data and data association information between the new input data and the current data to be stored;

[0169] Storing the data content in the new data storage area through the new data storage path;

[0170] Based on the data association information, concatenate the new input data with the current data to be stored to obtain target storage data;

[0171] The storage location of the target storage data in the new data storage area is adjusted to optimize the data storage structure.

[0172] Figure 3It is a structural schematic diagram of a computer device for implementing a data emergency storage method for chip failure provided by an embodiment of the present application. The computer device includes a processor, a memory, a communication interface, a display unit and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by the processor to implement a chip detection method during the operation of a chip. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input system of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0173] Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0174] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0175] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope recorded in this specification.

[0176] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the present application. It should be noted that, for a person of ordinary skill in the art, several improvements and substitutions may be made without departing from the concept of the present application, and these improvements and substitutions shall also be regarded as the protection scope of the present invention. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data emergency storage method for chip failure, characterized in that: include: Get the current state of the chip and the data to be stored; Based on the current state of the chip, predict the total chip failure probability by using a preset chip failure prediction program; When the total chip failure probability is greater than a preset probability threshold, predicting a chip failure area based on the current state of the chip; Based on the current data to be stored, obtaining a current data storage area and a current data storage path of the chip; Based on the chip fault area, adjusting the current data storage area and the current data storage path to obtain a new data storage area and a new data storage path; Transferring the stored data in the fault area to the new data storage area; The current data to be stored is stored in the new data storage area through the new data storage path.

2. The data emergency storage method for chip failure according to claim 1, characterized in that: The current state of the chip includes the current operating state of the chip and the current temperature state of the chip; and obtaining the current state of the chip includes: Get the current operation data and temperature data of the chip; Based on the current operation data of the chip, obtaining several chip current data operation types and chip current operation data amounts; Based on a number of the chip's current data operation types and the chip's current operation data volume, obtaining the chip's current operation state through a preset chip state evaluation strategy; The current temperature data of the chip is processed by a preset chip template to obtain the current temperature distribution information of the chip as the current temperature state of the chip.

3. The data emergency storage method for chip failure according to claim 2, characterized in that: The predicting the total failure probability of the chip based on the current operating state of the chip includes: Based on the current operating state of the chip, query the first failure probability of the corresponding historical operating state in a preset historical database; Get the historical temperature status of the chip; By sorting out the current temperature state of the chip and the historical temperature state of the chip, the chip temperature state change information is obtained, and then split into a plurality of chip area sub-temperature state change information; Based on the temperature state change information of the chip regions, predict the temperature change trends of the chip regions; Calculating the second failure probabilities of the plurality of chip regions based on the temperature change trends of the plurality of chip regions; Calculating a plurality of chip region sub-failure probabilities based on a plurality of chip region second failure probabilities and the first failure probabilities; The sub-failure probabilities of the chip regions are taken as the total failure probability of the chip.

4. The data emergency storage method for chip failure according to claim 3, characterized in that: The calculating the second failure probabilities of the plurality of chip regions based on the temperature change trends of the plurality of chip regions comprises: The deviation value between the temperature change trend of any chip area and the preset temperature change data is calculated, and then the deviation value is normalized to obtain the second failure probability of the chip area.

5. The data emergency storage method for chip failure according to claim 1, characterized in that: The obtaining of the current data storage area and the current data storage path of the chip based on the current data to be stored includes: Based on the current data to be stored, obtaining a data task and a data operation type of the current data to be stored; Based on the data task, obtaining the data source and task target of the current data to be stored; Based on the data operation type, screening out a plurality of first data storage areas from all data storage areas of the chip; Based on the data source, screening out a current data storage area from a plurality of the first data storage areas; Obtaining a chip processing area where the task target is located; Based on the chip processing area and the current data storage area, a current data storage path is constructed.

6. The data emergency storage method for chip failure according to claim 5, characterized in that: The adjusting the current data storage area and the current data storage path based on the chip fault area to obtain a new data storage area and a new data storage path includes: Based on the chip fault area and the total chip fault probability, screening out a plurality of second data storage areas from all the data storage areas of the chip; Obtaining a number of current free space amounts of a number of the second data storage areas; Filter out the new data storage area with the largest current free space from the plurality of second data storage areas; A new data storage path is constructed based on the chip processing area and the new data storage area.

7. The data emergency storage method for chip failure according to claim 1, characterized in that: After storing the current data to be stored in the new data storage area through the new data storage path, the method further includes: In response to new input data, acquiring data content of the new input data and data association information between the new input data and the current data to be stored; Storing the data content in the new data storage area through the new data storage path; Based on the data association information, concatenate the new input data with the current data to be stored to obtain target storage data; The storage location of the target storage data in the new data storage area is adjusted to optimize the data storage structure.

8. A data emergency storage system for chip failure, characterized in that: The system comprises: A first information acquisition module is used to obtain the current state of the chip and the current data to be stored; A failure probability prediction module, which is preset with a chip failure prediction program and is used to predict the total failure probability of the chip through the chip failure prediction program based on the current state of the chip; A fault area prediction module, used for predicting a chip fault area based on a current state of the chip when the total fault probability of the chip is greater than a preset probability threshold; A second information acquisition module is used to acquire a current data storage area and a current data storage path of the chip based on the current data to be stored; An adjustment module, configured to adjust the current data storage area and the current data storage path based on the chip fault area to obtain a new data storage area and a new data storage path; A data transfer module, used for transferring the stored data in the fault area to the new data storage area; The data storage module is used to store the current data to be stored in the new data storage area through the new data storage path.

9. A data emergency storage system for chip failure according to claim 8, characterized in that: The system also includes a data splicing module, which is used to implement the following steps: In response to new input data, acquiring data content of the new input data and data association information between the new input data and the current data to be stored; Storing the data content in the new data storage area through the new data storage path; Based on the data association information, concatenate the new input data with the current data to be stored to obtain target storage data; The storage location of the target storage data in the new data storage area is adjusted to optimize the data storage structure.

10. A computer device, characterized in that: The method comprises a processor and a memory, wherein the memory is used to store a computer program, and when the processor calls the computer program, the method described in any one of claims 1 to 7 is implemented.

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