A data storage management method for embedded NOR FLASH chip

Abstract

The present invention discloses a data storage management method for an embedded NOR FLASH chip, which divides the storage space of the NOR FLASH chip into three parts: an index table area, a flag management table area, and a data storage area; through the data occupation flag in the index table area, the data processing flag in the flag management table area, and the data weight, the data to be erased is searched, and its address is placed in the area to be erased; when the Flash storage space is insufficient, the data in the data storage area is erased in sequence according to the data address of the area to be erased. The data storage management method is run when the system CPU is in an idle state, and the data that has been processed and has the lowest data weight in the Flash storage space is erased in advance, thereby reserving sufficient storage space for system data writing, reducing the system waiting time when batch data is erased, and greatly improving the data writing efficiency of the Flash chip.

Description

Technical Field

[0001] The invention belongs to the technical field of computer data storage, and in particular relates to a data storage management method of a NOR FLASH chip applicable to an embedded system. Background Art

[0002] With the widespread application of IoT devices in different industries, IoT embedded devices need to collect and store a large amount of different types of sensor data. NOR FLASH flash memory is widely used in IoT devices due to its relatively low cost. However, the read and write principle of NOR FLASH memory determines that it must be erased before writing data, and the minimum erase unit is a sector or a page, which leads to a slow write speed and greatly reduces the data storage performance of the system. At present, the data storage area of ​​the embedded system usually adopts a simple sequential management, that is, the data is managed in a first-write-first-erase manner, and different types of data are not flexibly partitioned, which poses a risk of early erasure of important data.

[0003] Therefore, it is urgent to design a data storage management method for embedded NOR FLASH chips, which can classify and manage the stored data on the one hand, and recycle the used storage resources during the system idle time on the other hand, so as to improve the data storage performance of the embedded system. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] Based on this, the present invention discloses a data storage management method for an embedded NOR FLASH chip. The method can pre-erase the Flash data storage space during a period of CPU idle time before writing data to the Flash memory. When data needs to be written, it can be written directly, shortening the data writing time. In particular, the writing efficiency can be greatly improved when writing data in batches, and the stored data can be classified and managed according to weights.

[0006] (II) Technical solution

[0007] The present invention discloses a data storage management method for an embedded NOR FLASH chip, the data storage management method comprising:

[0008] Step S1: Divide the storage space of the NOR FLASH chip into three parts: an index table area, a flag management table area, and a data storage area, and retrieve the first index table data in the index table area. The index table structure of the index table area includes an index number, a flag of whether the corresponding data area is occupied, and an address of the corresponding flag management table. The data items of the flag management table include a flag management area number, a flag of whether the data is processed, a corresponding weight of the data, and an address of the corresponding data storage area;

[0009] Step S2: judging whether the corresponding data area is occupied by the flag of the index table, if the corresponding data area is not occupied, executing step S6; if the corresponding data area is occupied, executing the next step;

[0010] Step S3: Enter the corresponding flag management table area and read the flag of whether the data in the flag management table has been processed; if it has been processed, execute step S5; if it has not been processed, execute the next step;

[0011] Step S4: Determine whether the current data weight is the lowest according to the weight statistics table; if not, proceed to step S6; if yes, proceed to the next step;

[0012] Step S5: putting the data storage address corresponding to the mark into the area to be erased;

[0013] Step S6: Determine whether the traversal of the index table in the current round of retrieval in the index table area is complete, if not, execute step S2 to continue to search the next index table, if yes, execute the next step;

[0014] Step S7: sorting the data to be erased according to the order of the timestamps in the data area, and placing the address of the first collected data at the beginning of the area to be erased;

[0015] Step S8: Determine whether the amount of data to be erased s is greater than or equal to the size of the required erase space n. If yes, erase the data storage area corresponding to the data address of the area to be erased; if no, change the size of the space to be erased to ns, and change the next index number to be searched to the first index number value of the next round of search, and execute step S2 to continue searching the next index table; if yes, execute the next step;

[0016] Step S9: erasing the data storage area corresponding to the data address of the area to be erased;

[0017] Step S10: Change the corresponding data occupied flag in the index table to unoccupied.

[0018] Furthermore, executing step S2 to continue searching the next index table includes: first searching the index number flag corresponding to the next index number, and then executing step S2.

[0019] Furthermore, the weight statistics table in step S4 is a data table stored in the last sub-sector of the Flash.

[0020] Furthermore, the area to be erased described in step S5 is two cache areas allocated from the SRAM of the processor, one of which stores the storage address of processed data, and the other stores the data storage address of unprocessed data with the lowest data weight. When erasing the data storage area, erase it first according to the storage address of the processed data.

[0021] Furthermore, in step S6, the index tables in the index table area are traversed and searched. When the number of index tables is relatively large, the number of index tables to be searched in each round is set according to the size of the data space to be erased, and multiple rounds of searches are performed.

[0022] Furthermore, in step S8, when the first index number value of the next round of retrieval is greater than the maximum index number of the index table, the first index number value of the next round of retrieval is changed to 0, and a new round of retrieval is performed from the beginning of the index table.

[0023] Furthermore, when erasing the data storage area corresponding to the data address of the area to be erased, it is necessary to determine whether the data storage area crosses sectors in the Flash memory based on the data address. If it does not cross sectors, the entire sector content where the data frame is located is read into the 4K cache area, and the data frame to be erased is deleted in the cache area, and then the entire sector is erased, and then the data in the cache area is written to the sector at one time; if the data frame to be erased crosses sectors in the Flash memory, it is necessary to perform the above operations in the two spanning sectors in sequence to erase the data frame.

[0024] On the other hand, the present invention also discloses an embedded system, comprising: at least one processor and at least one NOR FLASH memory communicatively connected to the processor, the internal SRAM of the processor is required to have a large enough capacity, and when the Flash is sector erased, at least one 4K cache area can be allocated to cache the contents of a sector, and there is enough margin to allocate two cache areas for the address of the data to be erased; the data storage management method of the embedded NOR FLASH chip as described in any one of the above items can be executed in the NOR FLASH memory.

[0025] (III) Beneficial effects

[0026] Compared with the prior art, the present invention has the following beneficial effects: the data storage management method re-divides the storage space of NOR FLASH into regions and sets corresponding data flags to classify and manage the data in the storage area. In combination with the new storage management method, the allocated storage resources can be flexibly recovered during the idle time of the system CPU, which can effectively reduce the system waiting time during batch data erasing and improve the data writing efficiency of the NOR FLASH chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The features and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the present invention in any way. In the accompanying drawings:

[0028] Figure 1It is a schematic diagram of the structure of the index table area and the flag management table area in the present invention and the corresponding address mapping relationship.

[0029] Figure 2 It is a schematic diagram of the weight statistics table and data storage area in the present invention.

[0030] Figure 3 The figure is a flow chart of the data storage management method of the embedded NOR FLASH chip in the present invention. DETAILED DESCRIPTION

[0031] The present invention will be clearly and completely described below in conjunction with the accompanying drawings and embodiments. The technical problems solved by the technical solution of the present invention and the beneficial effects are also described. It should be pointed out that the described embodiments are only intended to facilitate the understanding of the present invention and do not have any limiting effect on it.

[0032] Figure 1-3 As shown, the embodiment of the present invention discloses a data storage management method of an embedded NOR FLASH chip, comprising the following steps:

[0033] Step S1: Divide the storage space of the Nor Flash chip into three parts: an index table area, a flag management table area, and a data storage area, and retrieve the first index table data in the index table area;

[0034] The index table structure of the index table area includes an index number, a flag indicating whether the corresponding data area is occupied, and an address of a corresponding flag management table. The data items of the flag management table include a flag management area number, a flag indicating whether the data is processed, a corresponding weight of the data, and an address of a corresponding data storage area.

[0035] like Figure 1 As shown, taking the SPI FLASH memory M25PE16 as an example, the total capacity of the memory chip is 2M bytes, which is divided into 32 sectors, each sector is further divided into 16 sub-sectors, each sub-sector contains 16 pages, and each page is 256 bytes. In the embodiment of the present invention, the address range 0 to 0EFFFh of the memory chip M25PE16 is allocated as the index table area, the address range 0F000h to 22FFFh is allocated as the flag management area, and the address 23000h is used as the data storage area. The embodiment starts to retrieve the data of the first index table from address 0.

[0036] Step S2: judging whether the corresponding data area is occupied by the flag of the index table, if the corresponding data area is not occupied, executing step S6; if the corresponding data area is occupied, executing the next step;

[0037] In this embodiment, the data item content of an index table occupies 6 bytes, and searching the second index table starts from address 6, and the same applies to the following polling searches.

[0038] Step S3: If the flag in the index table shows that the corresponding data area is occupied, enter the corresponding flag management table area and read the flag of whether the data in the flag management table has been processed; if it has been processed, execute step S5; if it has not been processed, execute the next step;

[0039] The starting address of the flag management table is 0F000h. Entering the corresponding flag management table area to read the flag means reading from this address downwards.

[0040] Step S4: If the flag in the flag management table shows that the data has not been processed, determine whether the current data weight is the lowest according to the weight statistics table; if not, execute step S6; if yes, execute the next step;

[0041] In this embodiment, the data weight statistics table is stored in the address segment 1FF000h-1FF004h in the last sub-sector of the Flash, and the data weight is set from 1 to 5 in sequence according to the importance of the data frame.

[0042] Step S5: If the data has been processed or the weight of the currently unprocessed data is the lowest, the data storage address corresponding to the flag is placed in the area to be erased;

[0043] Specifically, when setting the area to be erased, two data spaces are allocated in the cache area, one for storing the storage address of processed data, and the other for storing the data storage address of unprocessed data with the lowest data weight. When erasing the data storage area, the storage address of the processed data is erased first.

[0044] Step S6: If the flag in the index table shows that the corresponding data area is not occupied or the weight of the currently unprocessed data is not the lowest, then determine whether the traversal of the index table in this round of retrieval of the index table area is completed. If not, execute step S2 to continue to search the next index table. If yes, execute the next step;

[0045] The step S2 is executed to continue searching the next index table, including: firstly searching the index number flag corresponding to the next index number, and then executing step S2;

[0046] Specifically, it also includes the traversal search of the index tables in the index table area in step S6. When the number of index tables is relatively large, the number of index tables searched in each round can be set according to the size of the data space to be erased, and multiple rounds of search can be performed. According to the partition setting of the Flash storage space in this embodiment, the index area can contain a maximum of 10,000 index tables. If all index tables are searched at one time, the time overhead is relatively large. Therefore, the number of index tables searched in each round is set to 300, and the number of storage of each type of data frame is 60 (such as Figure 2 As shown, five types of data frames are set, corresponding to the number of data weights of five priorities 1-5 respectively).

[0047] Step S7: after all index tables in the index table area are searched, the data to be erased are sorted in the order of the timestamps in the data area, and the address of the first collected data is placed at the head of the area to be erased;

[0048] Step S8: Determine whether the amount of data to be erased s is greater than or equal to the size of the required erase space n. If yes, erase the data storage area corresponding to the data address of the area to be erased; if no, change the size of the space to be erased to ns, and change the next index number to be searched to the first index number value of the next round of search, and execute step S2 to continue searching the next index table; if yes, execute the next step;

[0049] Specifically, after multiple rounds of searching the index table, if the first index number value of the next round of searching is greater than the maximum index number 10000 of the index table, the first index number value of the next round of searching is changed to 0, and a new round of searching is performed from the beginning of the index table.

[0050] Step S9: if the amount of data to be erased s is greater than or equal to the size n of the required erase space, then the data storage area corresponding to the data address of the area to be erased is erased;

[0051] Specifically, it also includes that when erasing the data storage area corresponding to the data address of the area to be erased, it is necessary to determine whether the data storage area crosses sectors in the Flash memory based on the data address. If it does not cross sectors, the entire sector content where the data frame is located is read into the 4K cache area, and the data frame to be erased is deleted in the cache area, and then the entire sector is erased, and then the data in the cache area is written to the sector at one time; if the data frame to be erased crosses sectors in the Flash memory, it is necessary to perform the above operations in the two spanning sectors in sequence to erase the data frame.

[0052] Step S10: After the data storage area corresponding to the data address of the to-be-erased area is erased, the corresponding data occupation flag in the index table is changed to unoccupied.

[0053] In summary, steps S1-S10 of this embodiment are executed in a loop when the system CPU is in an idle state, and the processed data and the data with the lowest data weight in the Flash storage space are erased in advance, thereby reserving sufficient storage space for system data writing, reducing the system waiting time during batch data erasure, and greatly improving the data writing efficiency of the Flash chip.

[0054] In the actual testing process of the software program, the method of this embodiment greatly improves the efficiency of batch data writing of the embedded Flash chip and reduces the system waiting time when erasing batch data, and has high application value.

[0055] Finally, it is noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data storage management method for an embedded NOR FLASH chip, characterized in that: The data storage management method includes: Step S1: Divide the storage space of the NOR FLASH chip into three parts: an index table area, a flag management table area, and a data storage area, and retrieve the first index table data in the index table area. The index table structure of the index table area includes an index number, a flag of whether the corresponding data area is occupied, and an address of the corresponding flag management table. The data items of the flag management table include a flag management area number, a flag of whether the data is processed, a corresponding weight of the data, and an address of the corresponding data storage area. Step S2: judging whether the corresponding data area is occupied by the flag of the index table, if the corresponding data area is not occupied, executing step S6; if the corresponding data area is occupied, executing the next step; Step S3: Enter the corresponding flag management table area and read the flag of whether the data in the flag management table has been processed; if it has been processed, execute step S5; if it has not been processed, execute the next step; Step S4: Determine whether the current data weight is the lowest according to the weight statistics table; if not, proceed to step S6; if yes, proceed to the next step; Step S5: putting the data storage address corresponding to the mark into the area to be erased; Step S6: Determine whether the traversal of the index table in the current round of retrieval in the index table area is complete, if not, execute step S2 to continue to search the next index table, if yes, execute the next step; Step S7: sorting the data to be erased according to the order of the timestamps in the data area, and placing the address of the first collected data at the beginning of the area to be erased; Step S8: Determine whether the amount of data to be erased s is greater than or equal to the size of the required erase space n. If yes, erase the data storage area corresponding to the data address of the area to be erased; if no, change the size of the space to be erased to ns, and change the next index number to be searched to the first index number value of the next round of search, and execute step S2 to continue searching the next index table; if yes, execute the next step; Step S9: erasing the data storage area corresponding to the data address of the area to be erased; Step S10: Change the corresponding data occupied flag in the index table to unoccupied.

2. The data storage management method of the embedded NOR FLASH chip according to claim 1, characterized in that: The step S2 is executed to continue searching the next index table, including: firstly searching the index number mark corresponding to the next index number, and then executing the step S2.

3. The data storage management method of the embedded NOR FLASH chip according to claim 1, characterized in that: The weight statistics table in step S4 is a data table stored in the last sub-sector of the Flash.

4. The data storage management method of the embedded NOR FLASH chip according to claim 1, characterized in that: The area to be erased described in step S5 is two cache areas allocated from the SRAM of the processor, one of which stores the storage address of processed data, and the other stores the data storage address of unprocessed data with the lowest data weight. When erasing the data storage area, erase it first according to the storage address of the processed data.

5. The data storage management method of the embedded NOR FLASH chip according to claim 1, characterized in that: In step S6, the index tables in the index table area are traversed and searched. When the number of index tables is relatively large, the number of index tables to be searched in each round is set according to the size of the data space to be erased, and multiple rounds of searches are performed.

6. The data storage management method of the embedded NOR FLASH chip according to claim 1, characterized in that: In step S8, when the first index number value of the next round of retrieval is greater than the maximum index number of the index table, the first index number value of the next round of retrieval is changed to 0, and a new round of retrieval is performed from the beginning of the index table.

7. The data storage management method of the embedded NOR FLASH chip according to claim 1, characterized in that: When erasing the data storage area corresponding to the data address of the area to be erased, it is necessary to determine whether the data storage area crosses sectors in the Flash memory based on the data address. If it does not cross sectors, the entire sector content where the data frame is located is read into the 4K cache area, and the data frame to be erased is deleted in the cache area, and then the entire sector is erased, and then the data in the cache area is written to the sector at one time; if the data frame to be erased crosses sectors in the Flash memory, it is necessary to perform the above operations in the two spanning sectors in sequence to erase the data frame.

8. An embedded system, characterized in that: include: At least one processor and at least one NOR FLASH memory communicatively connected to the processor, the internal SRAM of the processor is required to have a large enough capacity, and when the Flash is sector-erased, at least one 4K buffer area can be allocated to cache the contents of a sector, and there is enough margin to allocate two buffer areas for the address of the data to be erased; the data storage management method of the embedded NOR FLASH chip as claimed in any one of claims 1 to 7 can be executed in the NOR FLASH memory.

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