Split-gate flash memory and manufacturing method thereof

Abstract

The present invention provides a split-gate flash memory and a manufacturing method thereof. By heat-treating a semiconductor substrate, an oxidation protection layer that at least covers the sidewalls of a gate structure is formed. The oxidation protection layer formed by the heat treatment has a high density and can play a good blocking role for electrons in the gate structure, thereby preventing the loss of electrons in the gate structure. Furthermore, the oxidation protection layer cooperates with the gate sidewall on its sidewall, which can further increase the blocking of electrons in the gate structure, thereby effectively preventing the loss of electrons in the gate structure, thereby improving the data retention capability and reliability of the split-gate flash memory. In addition, when the semiconductor substrate is heat-treated, the doped ions in the source and drain regions of the semiconductor substrate can also be activated, so the annealing process for activating the doped ions can be omitted, saving the process and process time, and improving the process efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a split-gate flash memory and a manufacturing method thereof. Background Art

[0002] Flash memory has become a hot topic in the research of non-volatile memory due to its convenience, high storage density and good reliability. Since the first flash memory product came out in the 1980s, with the development of technology and the demand for storage in various electronic products, flash memory has been widely used in mobile and communication devices such as mobile phones, notebooks, PDAs and USB flash drives. Flash memory is a non-volatile memory. Its operating principle is to control the switching of the gate channel by changing the critical voltage of the transistor or storage unit to achieve the purpose of storing data, so that the data stored in the memory will not disappear due to power interruption. Flash memory is a special structure of electrically erasable and programmable read-only memory. Today, flash memory has occupied most of the market share of non-volatile semiconductor memory and has become the fastest growing non-volatile semiconductor memory.

[0003] Generally speaking, flash memory is a split-gate structure or a stacked-gate structure or a combination of the two structures. Due to its special structure, the split-gate flash memory has unique performance advantages over the stacked-gate flash memory in both programming and erasing. Therefore, the split-gate structure is particularly widely used due to its high programming efficiency. However, in the existing manufacturing method of the split-gate flash memory, the isolation performance of the sidewall of the gate structure is relatively weak, which leads to the loss of electrons in the gate structure (floating gate in the gate structure), thereby affecting the data retention ability and reliability of the memory. Summary of the invention

[0004] The object of the present invention is to provide a split-gate flash memory and a manufacturing method thereof, so as to effectively improve the data retention capability of the split-gate flash memory.

[0005] To achieve the above object, the present invention provides a method for manufacturing a split-gate flash memory, comprising: providing a semiconductor substrate, a gate structure formed on the semiconductor substrate, a portion of the semiconductor substrate exposed on both sides of the gate structure, and a source and drain region in which ions are not activated formed in the exposed semiconductor substrate;

[0006] Thermally treating the semiconductor substrate to form an oxidation protection layer that at least covers the sidewalls of the gate structure and activates doping ions in the source and drain regions;

[0007] A gate spacer is formed, wherein the gate spacer covers the sidewall of the oxidation protection layer.

[0008] Optionally, in the method for manufacturing the split-gate flash memory, the material of the oxidation protection layer is silicon oxide, and the heat treatment is thermal oxidation treatment.

[0009] Optionally, in the method for manufacturing the split-gate flash memory, the process gas for the thermal oxidation treatment includes oxygen, the process temperature is 900° C. to 1000° C., and the process time is 5 s to 15 s.

[0010] Optionally, in the method for manufacturing the split-gate flash memory, the material of the oxidation protection layer is silicon oxynitride, and the heat treatment is nitride oxidation treatment.

[0011] Optionally, in the manufacturing method of the split-gate flash memory, the process gas for the nitrogen oxidation treatment includes at least one of nitrous oxide, nitrogen oxide and nitrogen dioxide, the process temperature is 900° C. to 1200° C., and the process time is 5s to 15s.

[0012] Optionally, in the method for manufacturing the split-gate flash memory, before heat treating the semiconductor substrate, a mask sidewall is formed on the gate structure;

[0013] Furthermore, after the mask sidewalls are formed, a word line gate is also formed, and the word line gate penetrates the mask sidewalls and the gate structure in a thickness direction.

[0014] Optionally, in the manufacturing method of the split-gate flash memory, after forming the word line gate, the gate sidewall also covers the sidewall of the mask sidewall away from the word line gate;

[0015] Furthermore, when the oxidation protection layer is formed, the oxidation protection layer also covers the surface of the semiconductor substrate on both sides of the gate structure and the surface of the word line gate.

[0016] Optionally, in the manufacturing method of the split-gate flash memory, the gate sidewall includes a first gate sidewall, a second gate sidewall and a third gate sidewall stacked in sequence, the first gate sidewall covers the sidewall of the mask sidewall away from the word line gate and the sidewall of the oxidation protection layer, wherein the material of the first gate sidewall and the material of the third gate sidewall are both silicon oxide, and the material of the second gate sidewall is silicon nitride.

[0017] Optionally, in the method for manufacturing the split-gate flash memory, the gate structure includes a floating gate oxide layer, a floating gate layer, an inter-gate dielectric layer, and a control gate layer stacked in sequence from bottom to top.

[0018] Based on the same inventive concept, the present invention also provides a split gate flash memory, the split gate flash memory comprising:

[0019] A semiconductor substrate, a gate structure is formed on the semiconductor substrate, a portion of the semiconductor substrate is exposed on both sides of the gate structure, and a source and drain region is formed in the exposed semiconductor substrate;

[0020] An oxidation protection layer, wherein the oxidation protection layer at least covers a side wall of the gate structure;

[0021] A gate sidewall spacer covers a sidewall of the oxidation protection layer.

[0022] In the split-gate flash memory and its manufacturing method provided by the present invention, an oxidation protection layer that at least covers the sidewalls of the gate structure is formed by heat-treating the semiconductor substrate. The oxidation protection layer formed by the heat treatment has a high density and can play a good blocking role for the electrons in the gate structure, thereby preventing the loss of electrons in the gate structure. Furthermore, the oxidation protection layer cooperates with the gate sidewall on its sidewall, which can further increase the blocking of electrons in the gate structure, thereby effectively preventing the loss of electrons in the gate structure, thereby improving the data retention capability and reliability of the split-gate flash memory. In addition, when the semiconductor substrate is heat-treated, the doped ions in the source and drain regions of the semiconductor substrate can also be activated, so the annealing process for activating the doped ions can be omitted, saving process steps and process time, and improving process efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic flow chart of a method for manufacturing a split-gate flash memory according to an embodiment of the present invention;

[0024] Figures 2 to 8 It is a schematic diagram of a structure formed in a method for manufacturing a split-gate flash memory according to an embodiment of the present invention;

[0025] The reference numerals are described as follows:

[0026] 100-semiconductor substrate; 110-gate structure; 111-floating gate oxide layer; 112-floating gate layer; 113-intergate dielectric layer; 114-control gate layer; 120-hard mask layer; 130-mask sidewall; 140-word line gate; 150-source and drain region; 160-oxidation protection layer; 170-gate sidewall; 171-first gate sidewall; 172-second gate sidewall; 173-third gate sidewall. DETAILED DESCRIPTION

[0027] The following is a further detailed description of the split gate flash memory and the manufacturing method thereof proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0028] Step S1: providing a semiconductor substrate, on which a gate structure is formed, with portions of the semiconductor substrate exposed on both sides of the gate structure, and source and drain regions that are not ion activated being formed in the exposed semiconductor substrate;

[0029] Step S2: thermally treating the semiconductor substrate to form an oxidation protection layer that at least covers the sidewalls of the gate structure and activates doping ions in the source and drain regions;

[0030] Step S3: forming a gate sidewall spacer, wherein the gate sidewall spacer covers the sidewall of the oxidation protection layer.

[0031] Figures 2 to 8 FIG. 1 is a schematic diagram of a structure formed in a method for manufacturing a gate-splitting flash memory according to an embodiment of the present invention. Figures 2 to 8 The above steps are described in more detail.

[0032] refer to Figure 2 to Figure 6 As shown, in step S1, a semiconductor substrate 100 is provided, a gate structure 110 is formed on the semiconductor substrate 100, a portion of the semiconductor substrate 100 is exposed on both sides of the gate structure 110, and an ion-inactivated source and drain region 150 (such as Figure 6 The semiconductor substrate 100 may be single crystal, polycrystalline or amorphous silicon or silicon germanium, or may be silicon on insulator SOI. In this embodiment, the semiconductor substrate 100 is a silicon substrate.

[0033] like Figure 6 As shown, a gate structure 110 is formed on the semiconductor substrate 100, and the gate structure 110 includes a floating gate oxide layer 111, a floating gate layer 112, an inter-gate dielectric layer 113 and a control gate layer 114 stacked in sequence from top to bottom. The specific formation method includes: first, as Figure 2 As shown, a floating gate oxide layer 111 (GOX) is formed on the semiconductor substrate 100 by low pressure chemical vapor deposition (LPCVD), thermal oxidation or molecular beam epitaxy; the floating gate oxide layer 111 covers the global surface of the semiconductor substrate 100, and the floating gate oxide layer 111 includes but is not limited to silicon dioxide, preferably silicon dioxide, which is beneficial to enhancing the interface adhesion between layers and is used to isolate the semiconductor substrate 100 from the floating gate layer 112. The thickness can be determined according to specific process requirements, for example, 10 angstroms to 80 angstroms.

[0034] In this embodiment, the floating gate layer 112 can be undoped polysilicon, doped polysilicon doped with phosphorus, etc., metal nanocrystals, silicon germanium nanocrystals or other suitable conductive materials, and can be formed by a deposition process, such as a chemical vapor deposition process. The floating gate layer 112 is used to form a floating gate (FG), which can capture or lose electrons, so that the finally formed flash memory can have storage and erasing functions, and its thickness can be determined according to specific process requirements.

[0035] In this embodiment, the thickness of the floating gate layer 112 can range from 400 angstroms to 500 angstroms. The above numerical range is only for example and does not limit the thickness of the floating gate layer 112 of the present invention. The thickness of the floating gate layer 112 can be set to a reasonable value according to the size requirements of the specific device.

[0036] like Figure 2 As shown, the inter-gate dielectric layer 113 may be an ONO layer. Specifically, the inter-gate dielectric layer 113 may be an ONO sandwich structure of three layers of oxide-nitride-oxide stacked from bottom to top. It should be understood by those skilled in the art that the inter-gate dielectric layer 113 may also be an insulating structure such as a layer of nitride, a layer of oxide, or a layer of oxide formed on a layer of nitride. The inter-gate dielectric layer 113 may be formed using methods including but not limited to: a low-pressure chemical vapor deposition method, a chemical vapor deposition method, and a physical vapor deposition method. Taking the inter-gate dielectric layer 113 as an example of an ONO layer, a uniform silicon oxide layer is formed by a low-pressure chemical vapor deposition method, and then a silicon nitride layer is formed on the silicon oxide layer by a low-pressure chemical vapor deposition method, and then another silicon oxide layer is formed by a low-pressure chemical vapor deposition method. The thickness of the silicon oxide layer may range from 40 to 60 angstroms, the thickness of the silicon nitride layer may range from 35 to 45 angstroms, and the thickness of the other silicon oxide layer may range from 50 to 70 angstroms. The material of the control gate layer 114 may also include doped polysilicon, and the control gate layer 114 may be formed by a chemical vapor deposition method.

[0037] like Figure 3 As shown, after the gate structure 110 is formed, a hard mask layer 120 is formed on the gate structure 110, and the hard mask layer 120 has an opening, and the opening exposes a portion of the gate structure 110. And, as Figure 4As shown, a mask sidewall 130 is formed on the sidewall of the opening. The material of the mask sidewall 130 is silicon oxide and is formed by a low-pressure vapor deposition (LPCVD) process of tetraethyl orthosilicate (TEOS). After the mask sidewall 130 is deposited, the device can be rapidly annealed to improve the step coverage and compactness of the mask sidewall 130. The process temperature for depositing the mask sidewall 130 can be 300°C to 800°C, the annealing temperature can be 800°C to 1200°C, and the annealing time can be 30s to 100s. The annealing temperature in this embodiment can be 1150°C.

[0038] Next, continue to refer to Figure 4 Shown and combined Figure 5 As shown, with the mask sidewall 130 and the hard mask layer 120 as masks, the gate structure 110 at the bottom of the opening is etched to form a word line opening, and polysilicon is filled in the word line opening and the polysilicon is doped to form a word line gate 140. The top surface of the word line gate 140 can be higher than the top surface of the gate structure 110, and the top surface of the word line gate 140 can be lower than the top surface of the mask sidewall 130. In this way, during the subsequent heat treatment process, the top surface of the oxide layer formed due to the oxidation of part of the word line gate 140 can be nearly flush with the top surface of the mask sidewall 130, so as to provide a relatively flat process surface for subsequent processes.

[0039] In addition, before forming the word line gate 140, a tunneling oxide layer may be formed on the sidewall of the word line opening to isolate the word line gate 140 from the gate structure 110. In this embodiment, in order to better illustrate the core concept of the present invention, the description of the tunneling oxide layer is omitted. Figures 2 to 8 The illustration of tunneling through the oxide layer is omitted.

[0040] like Figure 6 As shown, after forming the word line gate 140, the hard mask layer 120 can be removed by a dry etching process and / or a wet etching process to expose the gate structure 110 at the bottom of the hard mask layer 120. Furthermore, the gate structure 110 is etched by a dry etching process to remove the exposed gate structure 110. After the gate structure 110 is etched, a surface of a portion of the semiconductor substrate 100 is exposed, that is, a portion of the semiconductor substrate 100 on both sides of the gate structure 110 is exposed.

[0041] After that, continue to refer to Figure 6As shown, an ion implantation process can be used to perform ion implantation (LDD) on the semiconductor substrate 100 in the implantation region on both sides of the gate structure 110 to form a source and drain region 150, and the ions in the source and drain region 150 are in an inactive state. The type of the ion implantation can be N-type or P-type, and the N-type ion species can include boron, indium or gallium, and the P-type ion species can include phosphorus, arsenic or antimony, etc.

[0042] refer to Figure 7 As shown, in step S2, the semiconductor substrate 100 is heat-treated to form an oxidation protection layer 160 that at least covers the sidewalls of the gate structure 110, and activates the doped ions in the source and drain regions 150. The oxidation protection layer 160 can protect the gate structure 110, increase the isolation performance of the gate structure 110, and prevent the loss of electrons in the gate structure 110. Furthermore, since the oxidation protection layer 160 is formed by heat treatment, it has a higher density than the oxidation protection layer formed by the chemical vapor deposition process, etc., and can play a better blocking role for the electrons in the gate structure. In addition, the oxidation protection layer cooperates with the gate sidewall formed subsequently, which can further effectively prevent the loss of electrons in the gate structure 110 and improve the data retention capability and reliability of the split-gate flash memory.

[0043] In this embodiment, the thickness of the oxidation protection layer 160 is 30 angstroms to 40 angstroms. The inventors have found that if the thickness of the oxidation protection layer 160 is too thin, such as less than 30 angstroms, the protection effect of the oxidation protection layer 160 on the gate structure 110 is not obvious, and the electrons in the gate structure may flow out; if the thickness of the oxidation protection layer 160 is too thick, such as greater than 40 angstroms, it will take a long process cycle to form, which may affect the diffusion of doped ions in the source and drain regions 150. Therefore, in this embodiment, the thickness of the oxidation protection layer 160 is 30 angstroms to 40 angstroms, such as 20 angstroms, 25 angstroms or 30 angstroms.

[0044] In this embodiment, Figure 7As shown, the material of the oxidation protection layer 160 is silicon oxide, and the oxidation protection layer 160 also covers the surface of the semiconductor substrate 100 exposed on both sides of the gate structure 110 and the surface of the word line gate 140. Wherein, the heat treatment is a thermal oxidation treatment, that is, the oxidation protection layer 160 is formed by a thermal oxidation process (Rapid Thermal Oxidation, RTO). Specifically, an oxidation furnace or a rapid thermal annealing chamber oxidation furnace or a rapid thermal annealing chamber is used, and the process gas used includes oxygen in an environment where the process temperature is 900°C to 1000°C, such as 900°C, 950°C or 1000°C. The gas flow rate of the oxygen can be, for example, 15sccm to 20sccm, and the process time is 5s to 15s. The oxidation protection layer 160 formed by the thermal oxidation treatment has good compactness and can effectively prevent the loss of electrons in the gate structure 110. In addition, during the thermal oxidation treatment, the oxygen content in the process chamber is more than 90% to improve the compactness of the oxidation protection layer 160. During the thermal oxidation process, oxygen penetrates into the sidewalls of the gate structure 110 away from the word line gate 140 (the sidewalls of the floating gate and the sidewalls of the control gate), thereby oxidizing the sidewall surface of the gate structure 110, the surface of the word line gate 140 and the exposed surface of the semiconductor substrate 100, thereby forming silicon oxide, and the silicon oxide is used to form an oxidation protection layer 160. The oxidation protection layer 160 formed by silicon oxide has a high density and can prevent the loss of electrons in the floating gate layer 112.

[0045] In another embodiment, the material of the oxidation protection layer 160 is silicon oxynitride, and the heat treatment is nitridation treatment, that is, a rapid thermal nitridation process is used to form the oxidation protection layer 160. The process gas of the nitridation treatment includes at least one of nitrous oxide, nitrogen oxide and nitrogen dioxide, the process temperature is 900° C. to 1200° C., for example, 900° C., 1000° C. or 1200° C., and the process time is 5s to 15s, so that silicon oxynitride is formed on the sidewall of the gate structure 110, the surface of the semiconductor substrate 100 and the surface of the word line gate 140, and the oxidation protection layer 160 is formed by using silicon oxynitride.

[0046] In addition, when the semiconductor substrate 100 is heat treated, the doped ions in the source and drain regions 150 in the semiconductor substrate 100 can also be activated, so the annealing process for activating the doped ions can be omitted, thus saving process steps and process time, and improving process efficiency.

[0047] refer to Figure 8As shown, in step S3, a gate spacer 170 is formed, and the gate spacer 170 covers the sidewall of the oxidation protection layer 160. The gate spacer 170 also covers the sidewall of the mask spacer 130 away from the word line gate 140. In this embodiment, the gate spacer 170 includes a first gate spacer 171, a second gate spacer 172 and a third gate spacer 173 stacked in sequence, the first gate spacer 171 covers the sidewall of the mask spacer 130 away from the word line gate 140 and the sidewall of the oxidation protection layer 160, wherein the materials of the first gate spacer 171 and the third gate spacer 173 are both silicon oxide, and the material of the second gate spacer 172 is silicon nitride. The gate spacer 170 can further protect the sidewall of the gate structure to prevent the gate structure 110 from being damaged in subsequent etching processes or ion implantation processes. In addition, the gate structure 110 can further prevent the loss of electrons in the floating gate layer 112 , and cooperate with the oxidation protection layer 160 to effectively prevent the loss of electrons in the gate structure 110 , thereby improving the data retention capability of the memory.

[0048] In this embodiment, the first gate sidewall 171 and the third gate sidewall 173 can be formed, for example, by a TEOS low pressure vapor deposition (LPCVD) process to further prevent the loss of electrons in the floating gate layer 111. At the same time, because the first gate sidewall 171 and the oxidation protection layer 160 are both made of silicon oxide, the stress between the two can be reduced. The thickness of the first gate sidewall 171 can be 40 angstroms to 50 angstroms, and the thickness of the third gate sidewall 173 can be 50 angstroms to 80 angstroms. The second gate sidewall 172 can be formed by a chemical vapor deposition process, and the thickness of the second gate sidewall 172 can be 20 angstroms to 40 angstroms.

[0049] Based on the same inventive concept, the present invention also provides a split-gate flash memory, such as Figure 8 As shown, the split-gate flash memory includes: a semiconductor substrate 100, a gate structure 110 is formed on the semiconductor substrate 100, a portion of the semiconductor substrate 100 is exposed on both sides of the gate structure 110, and a source and drain region 150 is formed in the exposed semiconductor substrate 100; an oxidation protection layer 160, the oxidation protection layer 160 at least covers the side wall of the gate structure 110; and a gate sidewall 170, the gate sidewall 170 covers the side wall of the oxidation protection layer 160.

[0050] In this embodiment, the material of the oxidation protection layer 160 may be silicon oxide. In another embodiment, the material of the oxidation protection layer may be silicon oxynitride. The oxidation protection layer 160 cooperates with the gate sidewall 170 to effectively prevent the loss of electrons in the gate structure 110 and improve the data retention capability and reliability of the split-gate flash memory.

[0051] In summary, in the split-gate flash memory and its manufacturing method provided by the embodiment of the present invention, an oxidation protection layer that at least covers the sidewalls of the gate structure is formed by heat-treating the semiconductor substrate. The oxidation protection layer formed by the heat treatment has a high density and can play a good blocking role for the electrons in the gate structure, thereby preventing the loss of electrons in the gate structure. Furthermore, the oxidation protection layer cooperates with the gate sidewalls on its sidewalls to further increase the blocking of electrons in the gate structure, thereby effectively preventing the loss of electrons in the gate structure, and further improving the data retention capability and reliability of the split-gate flash memory. In addition, when the semiconductor substrate is heat-treated, the doped ions in the source and drain regions of the semiconductor substrate can also be activated, so the annealing process for activating the doped ions can be omitted, saving process steps and process time, and improving process efficiency.

[0052] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a split-gate flash memory, characterized in that: The manufacturing method of the split gate flash memory comprises: Providing a semiconductor substrate, on which a gate structure is formed, with portions of the semiconductor substrate exposed on both sides of the gate structure, and source and drain regions that are not ion-activated being formed in the exposed semiconductor substrate; Thermally treating the semiconductor substrate to form an oxidation protection layer that at least covers the sidewalls of the gate structure and activates doping ions in the source and drain regions; A gate spacer is formed, wherein the gate spacer covers the sidewall of the oxidation protection layer.

2. The method for manufacturing a split gate flash memory according to claim 1, wherein: The material of the oxidation protection layer is silicon oxide, and the heat treatment is thermal oxidation treatment.

3. The method for manufacturing a split gate flash memory as claimed in claim 2, characterized in that: The process gas of the thermal oxidation treatment includes oxygen, the process temperature is 900° C. to 1000° C., and the process time is 5s to 15s.

4. The method for manufacturing a split gate flash memory according to claim 1, wherein: The material of the oxidation protection layer is silicon oxynitride, and the heat treatment is nitridation treatment.

5. The method for manufacturing a split gate flash memory as claimed in claim 4, characterized in that: The process gas for the nitrogen oxidation treatment includes at least one of nitrous oxide, nitrogen oxide and nitrogen dioxide, the process temperature is 900° C. to 1200° C., and the process time is 5s to 15s.

6. The method for manufacturing a split gate flash memory according to claim 1, wherein: Before heat treating the semiconductor substrate, a mask sidewall is formed on the gate structure; Furthermore, after the mask sidewalls are formed, a word line gate is also formed, and the word line gate penetrates the mask sidewalls and the gate structure in a thickness direction.

7. The method for manufacturing a split gate flash memory according to claim 6, wherein: After forming the word line gate, the gate spacer also covers the side wall of the mask spacer away from the word line gate; Furthermore, after the oxidation protection layer is formed, the oxidation protection layer also covers the surface of the semiconductor substrate on both sides of the gate structure and the surface of the word line gate.

8. The method for manufacturing a split gate flash memory as claimed in claim 7, characterized in that: The gate sidewall includes a first gate sidewall, a second gate sidewall and a third gate sidewall stacked in sequence, the first gate sidewall covers the sidewall of the mask sidewall away from the word line gate and the sidewall of the oxidation protection layer, wherein the material of the first gate sidewall and the material of the third gate sidewall are both silicon oxide, and the material of the second gate sidewall is silicon nitride.

9. The method for manufacturing a split gate flash memory according to claim 1, wherein: The gate structure comprises a floating gate oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer which are stacked in sequence from bottom to top.

10. A split gate type flash memory formed by the manufacturing method of the split gate type flash memory according to any one of claims 1 to 9, characterized in that: The gate-split flash memory comprises: A semiconductor substrate, a gate structure is formed on the semiconductor substrate, a portion of the semiconductor substrate is exposed on both sides of the gate structure, and a source and drain region is formed in the exposed semiconductor substrate; An oxidation protection layer, wherein the oxidation protection layer at least covers a side wall of the gate structure; A gate sidewall spacer covers a sidewall of the oxidation protection layer.

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