A half-band filter

Abstract

The present invention discloses a half-band filter, which comprises a read-write control module, a filtering calculation module, a data cache space and a filter coefficient memory; the read-write control module is used to control the writing of to-be-filtered data input into the half-band filter into the data cache space, and counts with a value of 2 as the change value of a single count to generate a read address; the read-write control module is used to read the to-be-filtered data from the data cache space using the read address generated by counting according to the relationship between the number of to-be-filtered data written into the data cache space and a transposition enable count threshold, and transmit the read to-be-filtered data to the filtering calculation module in sequence; the filtering calculation module is used to control the to-be-filtered data output by the data cache space and the filter coefficients output by the filter coefficient memory in the same order as that of the data cache space to perform filtering calculation; wherein the difference between the number of taps of the half-band filter and the value 1 is equal to the transposition enable count threshold.

Description

Technical Field

[0001] The present invention relates to the technical field of finite impulse response filters, and in particular to a half-band filter. Background Art

[0002] Among digital filters, FIR (Finite Impulse Response) filters are finite-length unit pulse impulse response digital filters, the most fundamental components in digital signal processing systems. They can maintain a strictly linear phase-frequency characteristic while maintaining arbitrary amplitude-frequency characteristics. Their unit sample response is also finite in length. Therefore, FIR filters are widely used in fields such as communications, image processing, and pattern recognition. The order of an FIR filter refers to the number of harmonics filtered; the length of an FIR filter reflects the frequency band of the filter. The sum of the FIR filter order and the value 1 equals the number of FIR filter coefficients, which is also equal to the number of filter taps. The number of FIR taps represents the memory required by the filter, the number of calculations required, and the amount of signal that the filter can filter out. In practice, more taps mean more stopband attenuation, less ripple, and narrower filtering. A filter's passband represents the signal frequency components that can pass through the filter without attenuation; its stopband represents the signal frequency components that are attenuated by the filter.

[0003] FIR (Finite Impulse Response) filters are used in scenarios such as speech recognition, high-definition recording, and audio decoding. They are paired with high-performance analog-to-digital conversion systems to filter high-frequency noise in the input audio signal and extract the oversampled signal to obtain a high-quality signal. In the time domain, the FIR filter based on the multiplier structure uses registers to continuously cache the continuously input signal and complete the filtering process through real-time multiplication and addition operations. During this filtering process, the frequency of the clock signal used by the FIR filter to extract data is equal to the clock frequency of the input signal. Therefore, the data cached by the FIR filter is easily filled with data that does not need to be filtered, increasing the hardware overhead required for the filtering calculation. In addition, during each filtering calculation, it is difficult to capture the data that needs to be filtered in each clock cycle, which in turn increases the power consumption of the FIR filter. Summary of the Invention

[0004] To address the above technical deficiencies, the present invention discloses a half-band filter. By controlling the change in the count value of a related address counter to a value of 2 within a single clock cycle, the filter extracts all input data to be filtered at intervals and performs filtering calculations in real time, thereby achieving effective filtering results while consuming fewer resources. The specific technical solution is as follows:

[0005] A half-band filter comprises a read-write control module, a filter calculation module, a data cache space, and a filter coefficient memory; the read-write control module is used to control the writing of to-be-filtered data input into the half-band filter into the data cache space, and to count the change value under a single counting operation using a value of 2 to generate a read address; the read-write control module is used to periodically read the to-be-filtered data from the data cache space using the read address generated by the counting based on the relationship between the number of to-be-filtered data written into the data cache space and a transposition enable count threshold, and to sequentially transmit the read to-be-filtered data to the filter calculation module; the filter coefficient memory is used to sequentially output required filter coefficients to the filter calculation module in the order in which the read-write control module reads the to-be-filtered data from the data cache space after the read-write control module starts reading the to-be-filtered data from the data cache space; the filter calculation module is used to control the filtering calculation of the to-be-filtered data output from the data cache space and the filter coefficients output from the filter coefficient memory; wherein the difference between the number of taps of the half-band filter and the value 1 is equal to the transposition enable count threshold.

[0006] Furthermore, the read-write control module also includes a reference address counter; the reference address counter is used to perform a self-increment operation and generate a reference address every time two data to be filtered are written to the data cache space, triggering the read-write control module to use the reference address to read the data to be filtered from the data cache space, and at the same time record it as entering a filtering cycle and determining to start a filtering calculation; wherein, the reference address is the first read address that needs to be traversed in the data cache space to start the current filtering calculation; the change value of the count value generated by a self-increment operation of the reference address counter is a value of 2; wherein, the sampling rate of the half-band filter is 2 times.

[0007] Furthermore, the half-band filter is also provided with a system clock source for generating a system clock pulse to drive the read-write control module to periodically read the data to be filtered from the data cache space, or periodically write the data to be filtered into the data cache space; wherein, the time to complete a write operation of a data to be filtered is a pulse period of a system clock pulse; the time to complete a read operation of a data to be filtered is a pulse period of a system clock pulse.

[0008] Furthermore, the method of periodically reading out the data to be filtered from the data cache space using the read address generated by counting based on the size relationship between the number of data to be filtered written into the data cache space and the transposition enable count threshold, and transmitting the read data to be filtered to the filtering calculation module in sequence includes: the read-write control module is used to read out the data to be filtered in the pre-read address from the data cache space when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold; wherein, the read-write control module is used to transmit the data to be filtered to the filtering calculation module whenever a data to be filtered is read out; wherein, the pre-read address is obtained by counting starting from a corresponding reference address in each filtering cycle; the reference address in a filtering cycle is the first pre-read address read by the read-write control module in the filtering cycle; and a filtering cycle is greater than the sum of the pulse periods of two system clock pulses.

[0009] Furthermore, the read-write control module includes a pre-address counter and a read address selector; when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold, the read address selector selects the pre-address generated by the pre-address counter and outputs it to the data cache space; the pre-address counter is configured to, when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold, start from the reference address in the current filtering cycle and perform a self-decrement operation each time a system clock pulse is detected, thereby triggering the read-write control module to read the data to be filtered from the pre-address obtained from each self-decrement operation; the pre-address counter is configured to, when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold, obtain a new pre-address after each self-decrement operation within a filtering cycle or a filtering calculation; wherein, the initial count value of the pre-address counter in each filtering cycle is the reference address of the reference address counter in the filtering cycle; and each time the pre-address counter performs a self-decrement operation, the change in the count value generated is a value of 2.

[0010] Furthermore, within a filtering cycle, when it is detected that the difference between half of the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to twice the number of times the pre-address counter performs the aforementioned decrement operation, the pre-address counter updates the difference between the currently obtained pre-address read address and the value 1 to the pre-address read address when the next system clock pulse arrives to allow the read-write control module to read the data to be filtered in the pre-address read address, and marks the pre-address read address as an intermediate pre-address read address; the pre-address counter is further used to, after obtaining the intermediate pre-address read address, continue to perform the aforementioned decrement operation starting from the difference between the intermediate pre-address read address and the value 1 to obtain a new pre-address read address; wherein, the difference between the intermediate pre-address read address and the value 1 is allowed to be updated as the pre-address read address.

[0011] Furthermore, when the number of to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold, the filter coefficient memory is used to, within each filtering cycle, start from the starting storage address set by the half-band filter, perform a self-addition operation on the starting storage address, and then output the filter coefficient in the storage address obtained by the self-addition to the filtering calculation module, until the address offset of the storage address obtained by the self-addition relative to the starting storage address is equal to half of the sum of the number of taps of the half-band filter and the value 1, and then record the latest storage address as the intermediate calculation storage address, perform a self-decrement operation on the intermediate calculation storage address, and then output the filter coefficient in the storage address obtained by the self-decrement to the filtering calculation module. Output to the filtering calculation module until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the sum of the number of taps of the half-band filter and the value 1, and repeat in sequence until the number of filter coefficients output from the filter coefficient memory in the current filtering cycle is equal to the number of to-be-filtered data read from the data cache space in the current filtering cycle; wherein the number of taps of the half-band filter is an odd number; wherein, in the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, the storage address increases by a value of 2; and in the process of performing the self-decrement operation on the intermediate calculation storage address, each time the self-decrement operation is performed, the storage address decreases by a value of 2.

[0012] Furthermore, the filtering calculation module is used to control the multiplication operation of the data to be filtered output by the data cache space and the filter coefficients in the same reading order output by the filter coefficient memory when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold, and input the result into the adder for accumulation processing to obtain the processed filtering result within each filtering cycle; wherein, the multiplication operation within each filtering cycle is implemented by time-sharing multiplexing of a multiplier; the same reading order is the order in which the data to be filtered is read within each filtering cycle; wherein, the filtering calculation module includes an adder and a multiplier.

[0013] Furthermore, the method of periodically reading the data to be filtered from the data cache space according to the relationship between the amount of the data to be filtered written into the data cache space and the transposition enable count threshold value, and transmitting the read data to be filtered to the filtering calculation module in sequence includes: the read-write control module includes a first folding address counter and a second folding address counter; when the amount of the data to be filtered written into the data cache space is greater than the transposition enable count threshold value, the first folding address counter is used to perform a self-decrement operation on the first folding read address in each filtering cycle to generate a new first folding read address, so as to obtain the first folding read address. The read-write control module is triggered to read the data to be filtered from the first folded read address obtained by each self-decrement operation; when the amount of data to be filtered in the write data cache space is greater than the transposition enable count threshold, the second folded address counter is also used to perform a self-increment operation on the second folded read address in each filtering cycle to generate a new second folded read address to trigger the read-write control module to read the data to be filtered from the second folded read address obtained by each self-increment operation; wherein, the change value of the count value generated by the self-decrement operation of the first folded address counter is a value of 2; wherein, the change value of the count value generated by the self-increment operation of the second folded address counter is a value of 2.

[0014] Furthermore, within a filtering cycle, after the difference between half of the difference between the number of taps of the half-band filter and the numerical value 1 and the numerical value 1 is equal to twice the number of times the first folding address counter performs the self-decrement operation, the first folding address counter stops performing the aforementioned self-decrement operation on the first folding read address, and updates the difference between the currently obtained first folding read address and the numerical value 1 to the first folding read address, then keeps the updated first folding read address unchanged, and marks the first folding read address as the intermediate calculation cache address; and, after the difference between half of the difference between the number of taps of the half-band filter and the numerical value 1 and the numerical value 1 is equal to twice the number of times the second folding address counter performs the self-increment operation, the second folding address counter stops performing the aforementioned self-increment operation on the second folding read address, and keeps the second folding read address unchanged.

[0015] Furthermore, the first folding address counter is configured to perform a self-decrement operation on the first folding read address every time two system clock pulses are detected to obtain a new first folding read address, and the pulse periods of two adjacent system clock pulses constitute a folding address read cycle; when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold, under the control of the read-write control module, first read the data to be filtered in the first folding read address to the filter calculation module, and then read the data to be filtered in the second folding read address to the filter calculation module, and repeat this process in one filtering cycle until the number of data to be filtered read is equal to half of the sum of the number of taps of the half-band filter and the value 1, and then read a data to be filtered from the intermediate calculation cache address when the next system clock pulse arrives, wherein the intermediate calculation cache address is an address position between the most recently obtained second folding read address and the most recently obtained first folding read address; wherein the second folding address counter is configured to perform a self-increment operation in the folding address read cycle to obtain a new second folding read address every time two consecutive system clock pulses arrive.

[0016] Furthermore, the read-write control module also includes a read address selector; when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold, the read address selector selects the first folding read address generated by the first folding address counter and the second folding read address output generated by the second folding address counter to trigger the read-write control module to read the two data to be filtered in the corresponding addresses within the folding address read cycle.

[0017] Furthermore, the read-write control module is used to configure the reference address generated by the reference address counter as the first folded read address when the number of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold, and to configure the sum of the reference address and the numerical value 1 as the second folded read address.

[0018] Furthermore, when the count value of the reference address counter is the difference between the number of taps of the half-band filter and the value 2, the read-write control module updates the filter starting address to the count value currently obtained by the reference address counter in the next system clock pulse, and updates the filter starting address to the reference address; when the count value of the reference address counter is the difference between the number of taps of the half-band filter and the value 1, the read-write control module updates the sum of the filter starting address and the value 1 to the count value currently obtained by the reference address counter in the next system clock pulse, and updates the sum of the filter starting address and the value 1 to the reference address; wherein, the filter starting address is set to the value 0, and the number of taps of the half-band filter is an odd number.

[0019] Furthermore, when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold, before the read-write control module determines that the reference address is configured as the first folding read address, if the read-write control module determines that the reference address is equal to the filtering start address, the filtering target address is updated to the reference address, and the updated reference address is configured as the starting address of the first folding read address. Then, the first folding address counter is used to perform a self-decrement operation on the first folding read address starting from the starting address of the first folding read address; when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold, before the read-write control module determines that the reference address is configured as the second folding read address, if the read-write control module determines that the reference address is equal to the filtering target address, the filtering start address is updated to the reference address, and the sum of the updated reference address and the value 1 is configured as the starting address of the second folding read address. Then, the second folding address counter is used to perform a self-increment operation on the second folding read address starting from the starting address of the second folding read address.

[0020] Furthermore, the process of the first folding address counter performing a self-decrement operation on the first folding read address includes: configuring the starting address of the first folding read address as the first folding read address, and whenever the first folding read address is decremented to the filtering starting address, the difference between the filtering target address and the numerical value 1 is updated to the first folding read address at the next system clock pulse; whenever the first folding read address is decremented to the sum of the filtering starting address and the numerical value 1, the filtering target address is updated to the first folding read address at the next system clock pulse; the process of the second folding address counter performing a self-increment operation on the second folding read address includes: configuring the starting address of the second folding read address as the second folding read address, and whenever the second folding read address is added to the filtering target address, the sum of the filtering starting address and the numerical value 1 is updated to the second folding read address at the next system clock pulse; whenever the second folding read address is added to the difference between the filtering target address and the numerical value 1, the filtering starting address is updated to the second folding read address at the next system clock pulse.

[0021] Furthermore, in each folding address read cycle, the address offset of the first folding read address corresponding to the first folding read address read relative to the filtering starting address is equal to the address offset of the second folding read address corresponding to the second folding read address read; wherein, the filtering target address is an address pre-configured in the data cache space, which is the address with the largest sequence among the addresses participating in the read operation in each filtering cycle; wherein, the filtering starting address is an address pre-configured in the data cache space, which is the address with the smallest sequence among the addresses read in each filtering cycle; wherein, the difference between the filtering target address and the filtering starting address is equal to the difference between the number of taps of the half-band filter and the value 1.

[0022] Furthermore, when the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold, the filter coefficient memory is used to perform a self-addition operation on the starting storage address matched by the half-band filter within each filtering cycle, starting from the starting storage address, each time two system clock pulses are detected, and then the filter coefficients in the storage address obtained by the self-addition operation are read out from the filter coefficient memory in sequence to the filtering calculation module until the address offset of the storage address obtained by the self-addition operation relative to the starting storage address is equal to half of the sum of the number of taps of the half-band filter and the value 1, and the latest storage address obtained is recorded as the intermediate calculation storage address; wherein, in the process of performing the self-addition operation on the starting storage address, each time a self-addition operation is performed, a storage address is generated, and the change value of the storage address generated by two adjacent self-addition operations is the value 2.

[0023] Furthermore, the filtering calculation module is used to, when the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold, first control the data to be filtered in the first folding read address output by the data cache space to be added with the data to be filtered in the second folding read address output by the data cache space in each folding address read cycle; then multiply the result of the addition with the filter coefficients in the same reading order output by the filter coefficient memory; then input the multiplication result into the adder for accumulation processing, and repeat this in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address, then control the filter coefficients in the intermediate calculation storage address to be multiplied with the data to be filtered in the intermediate pre-read address, and then input the multiplication result into the adder for accumulation processing to obtain the processed filtering result in the corresponding filtering cycle; wherein, in each filtering cycle, the multiplication operation is implemented by a multiplier in time-sharing multiplexing; the filtering calculation module includes an adder and a multiplier.

[0024] Furthermore, the read-write control module controls the writing of the data to be filtered input into the half-band filter into the data cache space in a manner including: an incremental counter is set inside the read-write control module, and the read-write control module is used to start from the cache head address of the data cache space, and each time a data to be filtered is written, control the incremental counter to add an offset to the current cache address to obtain the cache address of the next written data to be filtered, until the address offset of the currently obtained cache address relative to the cache head address is equal to the number of taps of the half-band filter, and the cache head address is updated to the currently obtained cache address, so that the subsequently written data to be filtered overwrites the data to be filtered originally stored in the cache head address, and determines that a round of continuous cache address traversal of the data cache space is completed; wherein, the continuous cache address is composed of address units whose number is the number of taps of the half-band filter.

[0025] Furthermore, the read-write control module is also used to, after completing a round of continuous cache address traversal, if new data to be filtered is continued to be written to the continuous cache addresses according to the system clock pulse control, set the incremental counter to the incremental initial value, and starting from the cache first address, each time a data to be filtered is written, the currently written data to be filtered overwrites the data to be filtered originally stored in the cache address, and control the incremental counter to add an offset to the current cache address to obtain the cache address of the next written data to be filtered, until the address offset of the currently obtained cache address relative to the cache first address is equal to the difference between the number of taps of the half-band filter and the value 1, update the cache first address to the currently obtained cache address, and adjust the count value of the incremental counter to the incremental initial value; wherein, the incremental initial value set by the incremental counter represents the address order of the cache first address in the data cache space; each count value generated by the incremental counter represents the address order of the cache address written in the corresponding system clock pulse in the data cache space.

[0026] Compared with the prior art, the present invention selects, based on the size relationship between the difference between the number of taps of the half-band filter and the value 1 and the number of data to be filtered written into the data cache space, to perform a folding calculation of first adding two data to be filtered and then multiplying by the filter coefficient when the data amount reaches the number of taps of the half-band filter, and selects to perform a direct calculation of first multiplying by the filter coefficient and then accumulating when the data amount does not reach the number of taps of the half-band filter. Regardless of the state, one data to be filtered and the filter coefficient are extracted at intervals of one read address to perform periodic filtering calculation. Therefore, within one filtering cycle, compared with the prior art, only half of the input data to be filtered are used to participate in the filtering calculation, and the frequency of change of the read address in each filtering calculation or each filtering cycle is half the frequency of the system clock pulse, thereby reducing the interference degree of invalid data originally written into the data cache space.

[0027] On the other hand, in the read-write control module, the reset of the count value of the counter used to control the reading and writing of the data cache space can establish a connection with the aforementioned filtering starting address and the aforementioned filtering target address, so that the self-increment or self-decrement operation of the count value of the corresponding counter can be limited to the modulus value (the number of different states represented in the counter) defined by the difference between the number of taps of the half-band filter and the value 1, so that among the filter coefficients obtained synchronously with the data to be filtered, the last filter coefficient involved in the calculation is more easily captured into the filtering calculation module and obtained with fewer read operations, indirectly reducing the power consumption of the FIR filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A module connection block diagram of a half-band filter disclosed in one embodiment of the present invention.

[0029] Figure 2 It is a schematic diagram of the internal structural principle of a read-write control module disclosed in another embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the dynamic changes in data flow of a 7-tap half-band filter. DETAILED DESCRIPTION

[0031] The following describes the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The present invention provides drawings to further illustrate the various embodiments. These drawings form part of the disclosure and are primarily used to illustrate the embodiments and, in conjunction with the relevant descriptions in the specification, to explain the operating principles of the embodiments.

[0032] Unless otherwise defined, the technical terms or scientific terms involved in the present invention should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "the" and the like involved in this application do not indicate a quantitative limitation and may represent the singular or the plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions, such as: a process, method, system product or device that includes a series of steps or modules is not limited to the listed steps or units, but may also include steps or modules that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The terms "first", "second", "third" and the like involved in this application are merely used to distinguish similar correspondences and do not represent a specific order for the objects.

[0033] It should be noted that the self-increment operation of the counter disclosed in the present invention is an addition counting operation of the counter inside the half-band filter, which is limited to counting by two, and the count values ​​before and after the change are configured as addresses; the self-decrement operation of the counter is a subtraction counting operation of the counter inside the half-band filter, which is limited to counting by two; therefore, the self-increment operation and the self-decrement operation of a counter generate addresses along different directions, and the two consecutively generated addresses are separated by an idle address, and this idle address is adjacent to the two consecutively generated addresses and distributed in the same cache space.

[0034] The count value of the relevant counter disclosed in the present invention is used to generate an address, so the value 0, the value 1, the count value and its related values ​​can be used to represent the serial number of the actual storage address of the corresponding input and output data in the data cache space or the filter coefficient memory. In order to simplify the description, any embodiment of the present invention simplifies the address indicated by the count value, value, sum value or difference value to directly use the count value, value, sum value or difference value to represent it.

[0035] An embodiment of the present invention discloses a half-band filter that can extract and filter the mono or dual-channel audio signal of an audio device with less hardware resources according to the filtering algorithm requirements of the actual application field (audio or video). Figure 1As shown, the half-band filter includes a read-write control module, a filter calculation module, a data cache space, and a filter coefficient memory. The half-band filter is pre-configured with the number of taps and decimation rate, and supports external software parameters or program intervention and modification, but the number of taps is limited to odd numbers. Specifically, the half-band filter is internally provided with a dedicated parameter configuration register for storing relevant performance parameters of various types of half-band filters, including but not limited to the bit width of input and output data, the bit width of the filter coefficients, the number of taps and order of the half-band filter, the number of filter coefficients, the length of the filter, the decimation rate of the filter, the filtering period required for a single filtering operation, the effective time point of the chip select signal, the high time point of the enable signal, the starting address or the starting reading time point of the filter coefficient memory read address, that is, determining the start and end time points and corresponding address intervals for reading and calculating the filter coefficients; wherein the number of taps of the half-band filter is equal to the sum of the order of the half-band filter and the value 1. In the present invention, the bit width of each data to be filtered written into the data cache space is pre-configured by a specific register, and the bit width occupied by each data to be filtered is less than or equal to the maximum bit width allowed for reading and writing by the data cache space.

[0036] In this embodiment, the half-band filter is a special FIR filter. The order of the half-band filter can only be an even number, so the number of taps of the half-band filter is an odd number. Except for the middle value of 0.5, the filter coefficients of the half-band filter at the remaining even-numbered address positions (odd items) are all 0.

[0037] In this embodiment, the read / write control module counts the change in value under a single counting operation using a value of 2 to generate the read address required for the half-band filter to perform filtering calculations. Each counting operation generates a read address, and the address offset between two adjacent generated addresses is a value of 2. Compared to other types of FIR filters in the prior art, half of the read address can be used to limit the address range for reading the data cache space, thereby meeting the extraction requirements of the half-band filter, including starting extraction, looping extraction to repeatedly read the same address, and stopping extraction. A single counting operation includes a self-increment operation or a self-decrement operation of the counter built into the read / write control module, specifically adding or subtracting one count to the count value.

[0038] It should be noted that during hardware implementation, read addresses are counted by a dedicated counter using the same clock, or divided by the actual data rate. It is also important to note that the start address and start time of the read operation must be determined before reading data. The data cache is implemented using SRAM, or static random-access memory (SRAM).

[0039] A read-write control module is used to control the writing of the to-be-filtered data input into the half-band filter into the data cache space. Specifically, the read-write control module, as the data read-write logic, can write the input data into the data cache space according to the decimation rate of the half-band filter at the corresponding clock timing generated by counting; at the same time, it can generate the read address required for the filtering calculation by adding two to the count according to the number of taps of the half-band filter and the amount of to-be-filtered data written in real time; wherein, when the filtering calculation module performs a filtering calculation on a batch of to-be-filtered data, the read-write control module is allowed to continue to control the writing of a new batch of to-be-filtered data into the data cache space.

[0040] like Figure 1 As shown, port I1 of the read-write control module is used to transmit a clock signal to the data cache space, and is configured as a driving clock signal for reading data in an associated read address in the data cache space; port I2 of the read-write control module is used to transmit a chip select signal to the data cache space, and the chip select signal is used to start selecting an address interval in the data cache space that needs to be read or enter a working state; port I3 of the read-write control module is used to transmit an enable signal to the data cache space, and the enable signal is used to distinguish between read enable and write enable; port I4 of the read-write control module is used to transmit the associated read address generated by the count of the read-write control module to the data cache space; port I5 of the read-write control module is used to write the data to be filtered into the data cache space; port O6 of the read-write control module is used to receive the data to be filtered read from the data cache space, and the read data transmitted by the data cache space will be transmitted to the filtering calculation module by other ports of the read-write control module, wherein the data transmitted to the filtering calculation module, such as Figure 1 fir_rdata is shown below.

[0041] The read-write control module is used to periodically read the data to be filtered from the data cache space to the filtering calculation module based on the relationship between the number of data to be filtered written into the data cache space and the transposition enable count threshold, using the read address generated by the count, and transmit the read data to be filtered to the filtering calculation module in sequence; it is worth noting that in some embodiments, each data to be filtered is immediately transmitted to the filtering calculation module when it is read. If the data to be filtered is obtained from an adjacent read address, it is easy to read out some invalid data that was inserted previously.

[0042] When the read / write control module determines the relationship between the amount of to-be-filtered data written into the data cache space and the transposition enable count threshold, this embodiment deems the amount of to-be-filtered data written into the data cache space to be equal to the amount of to-be-filtered data input into the half-band filter. This does not include newly written data to-be-filtered by the filtering calculation module during a filtering calculation. Determining the relationship between the amount of to-be-filtered data written into the data cache space and the transposition enable count threshold is to detect whether the amount of to-be-filtered data input into the half-band filter meets a certain count threshold, which is used to determine the filtering calculation method currently to be adopted by the half-band filter. Compared to the prior art, this embodiment sets the difference between the number of taps of the half-band filter and a value of 1 as the transposition enable count threshold, extracting and filtering data in the same batch, allowing the read / write control module to more quickly enter the filtering calculation method with a larger amount of to-be-filtered data written into the data cache space, thereby reducing the amount of computation, particularly when the number of taps is large.

[0043] It should be noted that the relationship between the amount of data to be filtered written into the data cache space and the transposition enable count threshold is determined by a specific enable signal and received by the read-write control module, corresponding to Figure 2 The selection signal Thr_sel, of course, this specific enable signal can be obtained by the read-write control module by counting the number of external data input to the half-band filter or the number of data written to the data cache space, that is, it is determined by the size relationship between the difference between the number of taps of the half-band filter and the value 1 and the number of data to be filtered written into the data cache space.

[0044] A filtering calculation module is used to control the filtering calculation of the to-be-filtered data output by the data cache space and the filter coefficients output by the filter coefficient memory. In this embodiment, the read addresses of both can be obtained by synchronously counting with a value of 2 as a variable value. Based on this data extraction method, in the filtering calculation performed by the half-band filter, the calculation method for different filtering stages is divided in real time based on the relationship between the amount of to-be-filtered data written into the data cache space and the transposition enable count threshold. In this embodiment, the difference between the number of taps of the half-band filter and the value 1 is set as the transposition enable count threshold. Compared with the calculation process in the filtering stage of the prior art, the time and resources consumed are reduced.

[0045] The filter coefficient memory is also used to store the filter coefficients required by the half-band filter that needs to be reused, wherein the filter coefficient memory can be implemented using ROM, that is, using Read-Only Memory (ROM). Figure 1As shown, the filter coefficient memory transmits the filter coefficient to the filtering calculation module through its port rom_out.

[0046] A filter coefficient memory is used to output the required filter coefficients to the filtering calculation module in sequence, starting from the starting storage address corresponding to the half-band filter, in the order in which the read-write control module reads the data to be filtered from the data cache space after the read-write control module starts to read the data to be filtered from the data cache space; it is worth noting that the order in which the filtering calculation module reads the storage addresses of the filter coefficients from the filter coefficient memory is the same as the order in which the read-write control module reads the cache addresses of the data to be filtered from the data cache space, so that the filter coefficients at the corresponding address positions (odd or even numbered address positions, the base addresses involved are pre-configured and obtained by self-addition or self-subtraction on this basis) output by the data to be filtered output by the data cache space can be filtered once within the same filtering cycle.

[0047] It should be noted that in this embodiment, the time consumed for performing a filtering calculation on a piece of input data to be filtered is one filtering cycle. The filtered data output by the data cache and the filter coefficients output by the filter coefficient memory ensure that a complete filtering calculation is performed within the same filtering cycle. In this embodiment, the half-band filter is designed as a pipeline structure. Therefore, each time the filtering calculation module performs a filtering calculation, the read-write control module continues to control the writing of the newly input half-band filter data to be filtered into the data cache but does not participate in the filtering calculation.

[0048] Compared with the prior art, the present invention selects to perform corresponding filtering calculations when the number of data to be filtered written into the data cache space reaches a corresponding threshold value based on the size relationship between the difference between the number of taps of the half-band filter and the value 1 and the number of data to be filtered written into the data cache space. In addition, no matter in which state, one data to be filtered and its corresponding output filter coefficient are extracted at intervals of one read address to perform periodic filtering calculations. Therefore, within one filtering cycle, compared with the prior art, only half of the input data to be filtered is used to participate in the filtering calculation. The frequency of change of the read address in each filtering calculation or each filtering cycle is half the frequency of the system clock pulse, thereby reducing the interference degree of invalid data originally written into the data cache space.

[0049] In some embodiments, when the amount of data to be filtered written into the data cache space is greater than the transposition enable count threshold, a high-level folding selection signal is generated, corresponding to Figure 2The selection signal Thr_sel=1, the data path of the corresponding counter in the read-write control module is selected to transmit a read address generated by the counter; when the number of to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold, a low-level folding selection signal is generated, corresponding to Figure 2 The selection signal Thr_sel=0 enables the data path of the corresponding counter in the read-write control module to generate another read address; therefore, the read timing of the read-write control module for reading the data cache space is determined by the counting timing generated by the specific counter selected by the half-band filter.

[0050] Based on the above embodiment, the read / write control module includes a reference address counter, which can be specifically disposed within the read / write control module and serves as a counting logic component for obtaining a starting read address of the data to be filtered required for each filtering calculation. The reference address counter is configured to perform a self-increment operation each time two data to be filtered are written to the data cache space from outside the half-band filter, or each time the filtering calculation module begins a filtering calculation. After the self-increment operation is performed on the count value of the reference address counter, a reference address is generated, which triggers the read / write control module to read the data to be filtered from the data cache space using the reference address, thereby marking the entry of a filtering cycle and determining the start of a filtering calculation. In this embodiment, the decimation factor of the half-band filter is set to 2. The change in the count value generated by one self-increment operation of the reference address counter is 2, completing a count increment by two. In some embodiments, the address offset between the reference addresses obtained in two adjacent filtering cycles is equal to 2, because the address offset between the reference addresses obtained in two adjacent filtering cycles can be set equal to the decimation factor of the half-band filter. After the filtering calculation module is triggered to perform filtering calculation on the data to be filtered output from the data cache space using the reference address, when the filtering calculation module calculates a filtering result, it is determined that the half-band filter has passed a filtering cycle since the two data to be filtered were written, and a filtering calculation has been completed, including the two system clock pulses required to write the two data to be filtered, the total cycle of sequentially reading the data to be filtered from the data cache space (the specific value is related to the number of data to be filtered that need to be read from the data cache space in one filtering calculation), and the cycle required for the multiplication and accumulation calculation included in the filtering calculation. A filtering cycle set in the embodiment is greater than two system clock pulses. Therefore, in order to ensure the execution of a periodic filtering calculation, this embodiment sets the length of the interconnected reading, writing and calculation cycles to achieve the acquisition of effective filtering results. Therefore, after each filtering cycle, the filtering calculation module outputs a filtering result; that is, when the filtering calculation module outputs a filtering result, this embodiment determines that the half-band filter has gone through a filtering cycle since the two data to be filtered were written, and determines that only one filtering calculation is completed within a filtering cycle; wherein, the reference address is the read address of the first data to be filtered output by the data cache space within the filtering cycle.It is worth noting that while performing a filtering calculation in the current filtering cycle, it is allowed to continue writing new data to be filtered into the data cache space to start the next filtering cycle. The half-band filter disclosed in this embodiment is composed of a digital logic circuit. The pipeline structure of the half-band filter determines that the reading, writing and calculation of the input data to be filtered are performed synchronously, so as to realize that there is a partially overlapping timing interval between two adjacent filtering cycles. It should be supplemented that the initial count value set in the reference address counter can be a value of 0 or a value of 1, and this embodiment chooses to configure the initial count value set in the reference address counter to a value of 0. In summary, this embodiment determines that the half-band filter has the periodic counting rules required for performing a filtering calculation under the condition of a 2x decimation rate, thereby realizing the effective division of the cycle consumed by the filtering calculation of the half-band filter.

[0051] It should be noted that the half-band filter is also provided with a system clock source for counting and generating system clock pulses, corresponding to Figure 1 The clock signal output by port I1 of the read-write control module in this embodiment is designed as a system clock source as the counting clock of the half-band filter, which is used to generate system clock pulses. The pulse period of the system clock pulse is generated by timing its incoming clock transition edges. The pulse period is specifically the time interval between two adjacent pulses generated by the system clock source. In this embodiment, the time required to complete a write operation on a piece of data to be filtered is the pulse period of a system clock pulse; the time required to complete a read operation on a piece of data to be filtered is the pulse period of a system clock pulse. Therefore, the half-band filter is configured to configure the time it takes to write a piece of externally input data to be filtered to the data cache space to be equal to one pulse period. The half-band filter is also configured to configure the time it takes to read a piece of data to be filtered from the data cache space to be equal to one pulse period. The piece of data to be filtered is the information of a sampling point sampled externally by the half-band filter, and in this embodiment, is also the data read from the data cache space by the read-write control module. The amount of filtered data written into the data buffer is equal to the amount of filtered data sampled externally by the half-band filter, representing the amount of filtered data required for a single filtering calculation. However, previously written but overwritten filtered data is not included in this calculation. Therefore, one filtering cycle is greater than the sum of the pulse periods of two system clock pulses.

[0052] Preferably, when the number of data to be filtered written into the data cache space is represented by the change value of the count value of the reference address counter, based on the timing rule that the reference address counter adds two counts every time two data to be filtered are written, the transposition enable count threshold is represented by the number of taps of the half-band filter, so that the size relationship between the transposition enable count threshold and the number of data to be filtered written into the data cache space is equivalent to the size relationship between the number of taps of the half-band filter and the change value of the count value of the reference address counter, which facilitates the counting of the number of data to be filtered written into the data cache space. This preferred example is that in the application scenario where the number of taps of the half-band filter is odd or even, it is beneficial to use the reference address counter to accurately count the number of data to be filtered actually written into the data cache space in each filtering cycle.

[0053] Preferably, when the count value of the reference address counter is the difference between the number of taps of the half-band filter and the value 2, the read-write control module updates the filter starting address to the count value currently obtained by the reference address counter in the next system clock pulse, thereby updating the filter starting address to the reference address, and allowing the reference address counter to perform a self-increment operation starting from the updated reference address; wherein, the filter starting address is an address pre-configured in the data cache space, and is the address with the smallest sequence among the addresses participating in the read operation in each filtering cycle. It can be represented by the value 0 or the value 1, and in this preferred example it is set to the value 0. The reference address counter has an initial count value. Under the premise that the number of taps of the half-band filter is an odd number, the initial count value of the reference address counter is correspondingly set to a value of 1, wherein the initial count value is a count value set before the reference address counter starts counting. Therefore, the count value of the reference address counter can be incremented by a value of 2 to the difference between the number of taps of the half-band filter and the value 2, and then the read-write control module updates the filtering starting address to the count value currently obtained by the reference address counter at the next system clock pulse, so that when the count value of the reference address counter changes to the odd number, the filter starting address is updated. The number of taps of the half-band filter jumps back to the initial count value before the reference address counter jumps back to the initial count value, and then starts to increase from the filtering starting point address, so that the reference address counter has a sufficient counting range to cover the valid address interval limited by the number of taps of the half-band filter, and also avoids the reference address counter from overflowing the count value when increasing by 2 in each filtering cycle, or avoids the read-write control module from reading data in an invalid address. It should be noted that the modulus value (the maximum number of counting states that can be represented) of the reference address counter is equal to the difference between the number of taps of the half-band filter and the value 1.

[0054] Preferably, when the count value of the reference address counter is the difference between the number of taps of the half-band filter and the value 1, the read-write control module will update the sum of the filter starting address and the value 1 to the count value currently obtained by the reference address counter at the next system clock pulse, and update the sum of the filter starting address and the value 1 to the reference address; wherein, the count value of the reference address counter can be understood as the reference address it generates; the filter starting address is an address pre-configured in the data cache space, and as the address with the smallest order among the addresses participating in the read operation in each filtering cycle, it can be represented by the value 0 or the value 1, and in this preferred embodiment it is set to the value 0. wherein, the initial count value of the reference address counter is the count value set before the reference address counter starts counting, in order to match Figure 3 As described above, under the premise that the number of taps of the half-band filter is an odd number, this preferred example sets the initial count value of the reference address counter to the value 0. Then, the count value of the reference address counter can be incremented by 2 in each filtering cycle to the difference between the number of taps of the half-band filter and the value 1. Then, the read-write control module updates the sum of the filtering starting address and the value 1 to the current count value obtained by the reference address counter at the next system clock pulse. When the filtering starting address is equal to the value 0 and the number of taps of the half-band filter is an odd number, the reference address counter can be incremented by 2 in each filtering cycle to the difference between the number of taps of the half-band filter and the value 2. Then, referring to the aforementioned preferred example, the read-write control module updates the filtering starting address to the current count value obtained by the reference address counter at the next system clock pulse. Then, when the filtering starting address is equal to the initial count value (equal to the value 0), this preferred example is repeated to adjust the count value of the reference address counter. This allows the reference address counter to have a sufficient counting range to cover the valid address interval defined by the number of taps of the half-band filter, and also prevents the reference address counter from reading data at invalid addresses (outside the read address interval defined by the number of taps of the half-band filter) when incrementing by a value of 2 in each filtering cycle. It should be noted that the modulus value of the reference address counter (the maximum number of counting states that can be represented) is equal to the difference between the number of taps of the half-band filter and the value 1.

[0055] In conjunction with the foregoing embodiment, it can be seen that the method of periodically reading the data to be filtered from the data cache space using the read address generated by counting based on the size relationship between the number of data to be filtered written into the data cache space and the transposition enable count threshold, and transmitting the read data to be filtered to the filtering calculation module includes: when the read-write control module determines that the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold, the read-write control module sequentially reads the data to be filtered in the pre-read address from the data cache space, which can be done based on establishing the counting timing of the reference address counter, meeting the requirement of a two-fold decimation multiple, and transmits the read data to be filtered to the filtering calculation module; wherein the transposition enable count threshold is preferably set to the number of taps of the half-band filter, so that in this embodiment, the number of taps of the half-band filter can be used as the modulus value of the counter to divide the read address and read cycle, so that the address counted by the relevant counter does not exceed the read address range defined by the number of taps of the half-band filter. It should be noted that the pre-read address is obtained by counting from a reference address within each filtering cycle, specifically determined by the real-time count value of the reference address counter, and is counted once for each filtering calculation or each filtering cycle. A reference address within each filtering cycle is the first pre-read address to participate in a read operation within that filtering cycle, so that the data to be filtered in the pre-read address corresponding to the reference address is transmitted to the filtering calculation module according to the corresponding read timing. This divides the effective read address and the read data to be filtered of the read / write control module for each filtering calculation, ensuring that the input data is continuously acquired and used for continuous filtering calculations.

[0056] As an implementation method of a half-band filter with a tap number equal to 7, Figure 2As shown, the read-write control module includes a pre-address counter and a read address selector; when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold, the read address selector enables the count value generated by the pre-address counter to be output to the data cache space, so as to read the data to be filtered in the corresponding address; specifically, when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold, in some embodiments, the selection signal Thr_sel is set to a low level, enabling the data path between the pre-address counter and the port I4 of the read-write control module, so as to output the count value generated by the pre-address counter to the data cache space, thereby allowing the pre-address counter to provide a pre-read address to the data cache space. The pre-address counter is used to, when the number of to-be-filtered data in the write data cache space is less than or equal to the transposition enable count threshold, start from the reference address in the current filtering cycle and perform a self-decrement operation each time a system clock pulse is detected, and then trigger the read-write control module to read the to-be-filtered data in the pre-address address after each self-decrement operation from the data cache space, and then transmit the data to the filtering calculation module in sequence; wherein, each time the pre-address counter is self-decremented, the change value of the count value generated is a value of 2, and a pre-address read address is obtained after each self-decrement operation, which is achieved in a cycle of one filtering calculation process, and the pre-address read address obtained by each self-decrement operation of the pre-address counter is transmitted to the read-write control module to realize reading half of the data written to the data cache according to a double extraction multiple.

[0057] To address the situation where the pre-address counter generates count values ​​within different filtering cycles, this embodiment configures the initial count value of the pre-address counter within each filtering cycle to be the reference address generated by the reference address counter within the corresponding filtering cycle. Specifically, the reference address counter performs a single increment operation to generate the reference address within a filtering cycle, which serves as the initial count value (starting count value) required for the pre-address counter to perform multiple decrement operations within the filtering cycle to assist the filtering calculation module in performing a filtering calculation (to output data from multiple consecutive pre-read addresses to the filtering calculation module). In this embodiment, the initial count value within the reference address counter is configured as 0, so the reference address set within the data cache space can be configured as 0. Because the pre-read address is counted from a reference address within each filtering cycle, i.e., the pre-read address can be set as the reference address and is the first pre-read address to participate in a read operation within a filtering cycle or a filtering calculation process, the read / write control module can read the data to be filtered starting from address 0 within a filtering cycle, thereby improving the coverage of the address range for read data. In this embodiment, in each filtering cycle, two consecutive system clock pulses are first used to write two data to be filtered into the data cache space in sequence, and then the data is read from the data cache space to the filtering calculation module in a manner of generating a read address by adding two to the count. When a filtering calculation is started, the reference address counter, in addition to adding two to the count operation of the two data to be filtered initially written, does not perform any counting operation in the same filtering cycle, but maintains the count value until new data to be filtered is written and the next filtering cycle is entered.

[0058] exist Figure 3 In an embodiment of the present invention, when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold, the reference address may be when the number of data to be filtered written into the data cache space is less than or equal to 6 (the number of taps of the half-band filter is equal to 7, and the difference between the number of taps of the half-band filter and the value 1 is equal to the transposition enable count threshold). Figure 3 The initial address of the first filter cycle (filter cycle with serial number 1) is 0, the second filter cycle (filter cycle with serial number 2) is 2, and the third filter cycle (filter cycle with serial number 3) is 4. At this time, 5 data to be filtered have been written, and the order from the latest to the earliest is X5, X4 ( Figure 3 Not shown), X3, X2 ( Figure 3 not shown) and X1.

[0059] exist Figure 3In an embodiment, when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold, that is, when the number of data to be filtered written into the data cache space is less than or equal to 6 (the number of taps of the half-band filter is equal to 7, and the difference between the number of taps of the half-band filter and the value 1 is equal to the transposition enable count threshold), the reference address is the initial address, the reference address of the fourth filtering cycle (the filtering cycle with sequence number 4) is 6, the difference between the number of taps of the half-band filter and the value 1 has been reached, and 7 data to be filtered have been written, and the numbers from the latest written to the earliest written are X7, X6 ( Figure 3 Not shown), X5, X4 ( Figure 3 Not shown), X3, X2 ( Figure 3 (not shown) and X1, if the reference address counter continues to perform a self-increment operation on the currently obtained reference address (count value), the new reference address generated becomes the value 8. Under the premise that the initial count value set in the reference address counter is configured as the value 0, the number of addresses traversed is already 7, which exceeds the number of taps of the half-band filter. Therefore, the reference address of the fifth filtering cycle (filtering cycle with serial number 5) is configured as the value 1. Then, after the fifth filtering cycle (filtering cycle with serial number 5), 9 data to be filtered have been written, and the numbers written from the latest to the earliest are X9, X8 ( Figure 3 Not shown), X7, X6 ( Figure 3 Not shown), X5, X4 ( Figure 3 Not shown), X3, X2 ( Figure 3 Not shown) and X1, where the smaller the i in Xi, the earlier it is written but the later it is read.

[0060] In some embodiments, there is always a new data entry at address 0 of the data cache space. Figure 3 The window and occupies the first position of the window, in particular, Figure 3 In the first filtering cycle, the outside of the half-band filter only writes one to-be-filtered data X1 to the data cache space. Accordingly, the reference address in the first filtering cycle is 0, which may be pre-configured by the read-write control module. When a filtering calculation is started, the filtering calculation module performs filtering calculation using the to-be-filtered data and outputs a filtering result y1. In the first filtering cycle, since only one to-be-filtered data is written, the reference address counter does not perform a counting operation. Therefore, the initial count value of the reference address counter is configured as the reference address, and further configured as the first pre-read address participating in the read operation in the filtering cycle or the filtering calculation process.

[0061] As a second embodiment of a half-band filter with a tap number equal to 7, the read-write control module includes a pre-address counter, which is used to start from the reference address corresponding to the current filtering cycle and perform a self-decrement operation each time a system clock pulse is detected when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold. Specifically, the pre-address counter is used to start from the reference address corresponding to the current filtering cycle and perform a self-decrement operation each time a system clock pulse is detected. Specifically, the self-decrement operation is performed from the reference address corresponding to the conversion in the read-write control module in the current filtering cycle. Optionally, before performing the first self-decrement operation, a delay period is required to allow the written data to be filtered to be stably cached in the data cache space; at the same time, each The pre-read address after each decrement operation is transmitted to the data cache space, triggering the read / write control module to read the to-be-filtered data in the pre-read address after each decrement operation from the data cache space, and then sequentially transmit the data to the filtering calculation module. In this embodiment, the initial count value set for the pre-read address counter is a reference address, which can be a value of 0. The pre-read address counter acts as a decrementing counter. Each time the pre-read address counter performs a decrement operation, the corresponding count value changes by a value of 2. The count value generated after each decrement operation is configured as the pre-read address, such that the new pre-read address obtained after the current decrement operation is one read address away from the previous decrement operation. Therefore, the pre-read address counter can traverse the data cache space address unit by address unit with a value of 2 as the address offset step, thereby reading half of the data in the data cache at a double decimation rate, but within an address range defined by the number of taps of the half-band filter.

[0062] It is worth noting that, in each filtering cycle, when it is detected that the difference between half of the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to twice the number of times the pre-address counter performs the aforementioned self-decrement operation, at this time, the address offset of the newly generated pre-address read address relative to the reference address in the current filtering cycle is equal to twice the number of times the pre-address counter performs the aforementioned self-decrement operation, then the pre-address counter updates the difference between the currently obtained pre-address read address and the value 1 as the pre-address read address to allow the read-write control module to read the data to be filtered in the pre-address read address, so as to give it the right to participate in the half-band filter. An opportunity for filtering calculation is performed, and the preamble read address is marked as an intermediate preamble read address; at this time, the operation of updating the difference between the currently obtained preamble read address and the value 1 as the preamble read address is different from the aforementioned self-decrement operation (each time the self-decrement operation is performed, the corresponding change in the count value is the value 2), but the preamble address counter decrements the currently obtained preamble read address by one and updates the decrement result (count value) as the latest preamble read address; in some embodiments, the preamble read address can be updated by a set operation, or the intermediate preamble read address can be obtained by decrementing the currently obtained preamble read address by one when the next system clock pulse arrives. Then, the pre-address counter is further configured to, after obtaining the intermediate pre-read address, first decrement the intermediate pre-read address by one to obtain a difference between the intermediate pre-read address sequence number and the value 1, and continue to perform the aforementioned self-decrement operation starting from the difference between the intermediate pre-read address and the value 1 (each time the self-decrement operation is performed, the corresponding change in the count value generated is the value 2, i.e., a subtract-by-two counting operation) to obtain a new pre-read address until the newly obtained pre-read address is the value 1; wherein, the difference between the intermediate pre-read address sequence number and the value 1 is allowed to be updated as the pre-read address, i.e., the difference between the intermediate pre-read address sequence number and the value 1 is allowed to be used as the new pre-read address to participate in the filtering calculation of the half-band filter.

[0063] As a third embodiment of a half-band filter with a tap number equal to 7, in this embodiment, the filter coefficients stored at the even-numbered address positions in the filter coefficient memory are all 0 and do not need to be output to the filter calculation module for calculation. In order to perform a filter calculation, in the implementation scenario where the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address matched by the half-band filter, perform a self-increment operation on the starting storage address every other system clock pulse, and then read the corresponding stored filter coefficients to the filter calculation module in sequence according to the storage address obtained by self-increment, specifically, each self-increment operation increments the obtained storage address by two, so that within the same system clock pulse, the address offset step of the storage address is equal to the address offset step of the aforementioned pre-read address, and changes under the same system clock source until the address offset of the storage address obtained by self-increment relative to the starting storage address is equal to half the sum of the tap number of the half-band filter and the value 1. It should be noted that within a filtering cycle, the order in which the filter coefficients required for the same filtering calculation are read is the same as the order in which the data to be filtered are read, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half the sum of the number of taps of the currently multiplexed half-band filter and the value 1. The filter coefficient memory then records the most recently obtained storage address as the intermediate calculation storage address, decrements the intermediate calculation storage address, and sequentially reads the corresponding stored filter coefficients to the filtering calculation module according to the decremented storage address until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half the sum of the number of taps of the half-band filter and the value 1. This process is repeated until the number of filter coefficients output from the filter coefficient memory within the current filtering cycle (corresponding to the start of the current filtering calculation) is equal to the number of data to be filtered participating in the filtering calculation within the current filtering cycle, and is also equal to the number of data to be filtered read within the current filtering cycle, which may vary depending on the actual number of filtering calculations performed or the filtering cycle. It should be noted that, in the process of performing a self-increment operation on the starting storage address, each time the self-increment operation is performed, the address corresponding to the trigger storage address automatically increases by a value of 2; in the process of performing a self-decrement operation on the intermediate calculation storage address, each time the self-decrement operation is performed, the address corresponding to the trigger storage address automatically decreases by a value of 2; wherein, the intermediate calculation storage address is set in the filter coefficient memory, and is the address with the largest sequence among the storage addresses of the filter coefficient, that is, the tail address of the address interval for storing the corresponding filter coefficient.

[0064] exist Figure 3 In the third filtering cycle, starting from the address position with the initial address being the value 4, from left to right, the data in the fifth row of boxes are sequentially the data to be filtered in the pre-read address after the self-decrement operation read by the read-write control module from the data cache space. From left to right, the data in the squares closer to the left are read earlier, and the corresponding address position is the pre-read address obtained by the earlier self-decrement; the data in the squares closer to the right are read later, and the corresponding address position is the pre-read address obtained by the later self-decrement. Preferably, the data in one square is read for each system clock pulse. Similarly, the data in the sixth row of boxes are the filter coefficients in the storage addresses after the self-addition operation read out from the filter coefficient memory, starting from the address position corresponding to the square h1, that is, the starting storage address corresponding to the half-band filter. From left to right, the data in the squares closer to the left are read earlier, and the corresponding address positions are the storage addresses obtained by self-addition earlier; the data in the squares closer to the right are read later, and the corresponding address positions are the storage addresses obtained by self-addition later, until the square h5 is self-added, wherein the address offset of each self-addition is equal to the value 2; at this time, the address offset of the address position corresponding to the square h5 relative to the address position corresponding to the square h1 is equal to the value 4, which is equal to half of the sum of the number of taps of the half-band filter (value 7) and the value 1 (equal to the value 4), and the filter coefficient memory configures the address position corresponding to the square h5 is the intermediate calculation storage address; then starting from the square h5, the intermediate calculation storage address is decremented until it reaches the square h3, wherein the address offset of each decrement is equal to the value 2; at this time, the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is less than half of the sum of the number of taps of the half-band filter (value 7) and the value 1 (equal to the value 4), at this time, in the sixth row of boxes, the filter coefficients h1, h3, h5 and h3 read from left to right just correspond to the to-be-filtered data X5, X3, X2 and X1 participating in the filtering calculation in the fifth row of boxes, wherein X5 is the to-be-filtered data in the pre-read address read out first, and X1 is the to-be-filtered data in the pre-read address read out last; then the number of filter coefficients read from the filter coefficient memory in the third filtering cycle satisfies the number of to-be-filtered data participating in the filtering calculation in the third filtering cycle.

[0065] In a 7-tap half-band filter, if the number of to-be-filtered data written into the data buffer is not less than or equal to the transposition enable count threshold during the third filtering cycle, the pre-address counter begins decrementing the pre-address address (counting by two) starting from the pre-address address at which data X5 is located. After the pre-address counter performs one decrement operation (counting by two once), the difference between half the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to twice the number of times the pre-address counter performs the aforementioned decrement operation. At this point, the pre-address counter currently obtains the pre-address address at which data X3 is located. Upon the arrival of the next system clock pulse, the difference between the currently obtained pre-address address and the value 1 is updated to the pre-address address, i.e., the pre-address address at which data X2 is located, and the pre-address address is marked as the intermediate pre-address address. The intermediate pre-address counter then decrements the pre-address address by one to obtain the difference between the intermediate pre-address address and the value 1, i.e., the pre-address address at which data X1 is located. It should be noted that the address offset between the pre-read address at X5 and the pre-read address at X3 is equal to the value 2 (the change in the count value generated by each self-decrement operation (minus two count) of the pre-address counter), the address offset between the pre-read address at X3 and the pre-read address at X2 is equal to the value 1 (the change in the count value generated by the pre-address counter minus one count operation), and the address offset between the pre-read address at X2 and the pre-read address at X1 is equal to the value 1 (the change in the count value generated by the pre-address counter minus one count operation), where the order of the pre-read address at X2 is the intermediate pre-read address sequence number; i in Xi represents the pre-read address sequence number, and i is an integer.

[0066] On the basis of the above embodiment, the filtering calculation module is used to control the multiplication of the data to be filtered output by the data cache space and the filter coefficients in the same reading order output by the filter coefficient memory when the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold, and input the result into the adder for accumulation processing to obtain a filtering result after processing within each filtering cycle; wherein, the multiplication operation within each filtering cycle is implemented by a multiplier in time-sharing multiplexing, minimizing the multiplier resources; wherein, under the premise that the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold, the number of multiplication operations within a filtering cycle is equal to the number of data to be filtered or the number of filter coefficients required for the current filtering calculation, but does not exceed the number of taps of the half-band filter. The filtering calculation module includes an adder and a multiplier, which constitute a calculation method of performing multiplication first and then performing addition. Corresponding to Figure 3In the third filtering cycle, the filtering result y5 obtained is equal to the sum of the product of X5 and h1, the product of X3 and h3, the product of X2 and h5, and the product of X1 and h3. The number of multiplication operations in the third filtering cycle is equal to 4. The transposition enable count threshold is equal to the difference between the number of taps of the half-band filter and the value 1.

[0067] As a fourth implementation method of a half-band filter with a tap number equal to a value of 7, when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold, the read-write control module is used to first configure the reference address generated by the reference address counter as the first folded read address in each filtering cycle; and configure the sum of the reference address and the value 1 as the second folded read address, which is equivalent to adding an address offset to the reference address to offset one address relative to the reference address so as to achieve non-overlap with the first folded read address; optionally, the read control module is also used to configure the sum of the first folded read address and the second folded read address as a post-read address, and read the data to be filtered in the post-read address from the data cache space according to the corresponding read timing, and transmit it to the filtering calculation module.

[0068] Specifically, the reference address counter disclosed in this embodiment is further configured to continue to perform a self-increment operation on the count value when the number of to-be-filtered data in the write data cache space is greater than the transposition enable count threshold; and the change in the count value generated by the reference address counter in each self-increment operation is a value of 2, and the reference address obtained after the self-increment operation is configured as the starting address of the first folding read address (the first folding read address read in a filtering cycle) in each filtering cycle; in some embodiments, it can be equivalent to that every time two to-be-filtered data are written, that is, a filtering calculation is started, the reference address counter is incremented by two, and further, every time a filtering calculation is started, the reference address counter is incremented by two. It is worth noting that if the number of to-be-filtered data in the write data cache space is greater than the transposition enable count threshold, the reference address counter may still perform a self-increment operation to record the sequence number of the current filtering cycle or the number of written to-be-filtered data. Therefore, when the number of data to be filtered written into the data cache space exceeds the transposition enable count threshold, the reference address counter provides a corresponding starting read address for the data to be filtered that needs to be extracted and filtered in each filtering cycle as the starting address information of the data for actual filtering calculation.

[0069] Specifically, the read-write control module includes a first folding address counter; when the number of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold, the first folding address counter is used to perform a self-decrement operation on the first folding read address in each filtering cycle to generate a new first folding read address, so as to trigger the read-write control module to read the to-be-filtered data in the first folding read address after each self-decrement operation from the data cache space, until the number of self-decrement operations reaches a first preset folding sampling number, but still allowing new to-be-filtered data to be written into the data cache space, but the new to-be-filtered data is not counted in the to-be-filtered data required for the current filtering calculation, but is recorded as the to-be-filtered data required for the next filtering calculation. The change in the count value generated by one self-decrement operation of the first folding address counter is a value of 2, that is, each time the first folding address counter performs a self-decrement operation, the corresponding count value is reduced by a value of 2.

[0070] Before the read-write control module determines to configure the reference address generated by the reference address counter as the first folding read address, which is equivalent to configuring the reference address as the starting address of the first folding read address (the first first folding read address that needs to be read in the corresponding filtering cycle or participating in the corresponding filtering calculation), the read-write control module is used to update the filtering target address to the reference address when it is determined that the reference address is equal to the filtering starting address, and then configure the updated reference address as the starting address of the first folding read address, so that the first folding read address can be deducted from a reasonable address offset value during the self-decrement operation to obtain the data to be filtered in the valid address obtained by the self-decrement operation, thereby avoiding obtaining invalid data and losing data associated with the current filtering cycle or the current filtering calculation.

[0071] It should be noted that the filtering target address is an address pre-configured in the data cache space, and is the address of the address with the largest order of reads among the addresses participating in the read operation in each filtering cycle. The filtering target address is greater than the filtering starting address, and the difference between the filtering target address and the filtering starting address is equal to the difference between the number of taps of the half-band filter and the value 1. Generally, when the filtering starting address is set to the value 0, the filtering target address is set to the difference between the number of taps of the half-band filter and the value 1. This can be applied to the scenario where the first address read by the read-write control module in a filtering calculation is an address position marked with the value 0, and the first folding address counter can start decrementing from the difference between the number of taps of the half-band filter and the value 1; or when the filtering starting address is set to the value 1, the filtering target address is set to the number of taps of the half-band filter. This can be applied to the scenario where the first address read by the read-write control module in a filtering calculation is an address position marked with the value 1, and the first folding address counter can start decrementing from the number of taps of the half-band filter. Then, the first folding address counter is used to perform a self-decrementing operation on the first folding read address starting from the starting address of the first folding read address, so as to realize orderly data reading operations based on the double decimation rate specified by the currently multiplexed non-half-band filter. The process of the first folding address counter performing the self-decrementing operation on the first folding read address includes: configuring the starting address of the first folding read address as the first folding read address, and whenever the first folding read address is decremented to the filtering starting address, the difference between the filtering target address and the value 1 is updated as the first folding read address in the next system clock pulse, so that the first folding read address can realize address loop traversal within the address range limited by the number of taps of the half-band filter, so as to timely traverse to the latest written data to be filtered. It is worth noting that because the previously cached data can be read into the filtering calculation module in a timely manner, the newly written data can overwrite the address unit where the previously cached data is located in the data cache space. After decrementing to the filtering starting address and completing the loop, or adding to the filtering target address and completing the loop, the first folding address counter continues to perform the self-decrementing operation on the first folding read address.

[0072] It should be noted that the first folding address counter performs a self-decrement operation on the first folding read address once every two consecutive system clock pulses to obtain a new first folding read address, which is also consistent with the counting timing of the reference address counter. These two consecutive system clock pulses are recorded as a folding address read cycle, wherein the first folding address counter performs a self-increment operation, and its count value is increased by a value of 2. Therefore, when the amount of to-be-filtered data in the write data cache space is greater than the transposition enable count threshold, under the control of the read / write control module, within a folding address read cycle, the to-be-filtered data at the first folding read address is read to the filtering calculation module, and the to-be-filtered data at the second folding read address is read to the filtering calculation module. Alternatively, the to-be-filtered data at the first folding read address may be read to the filtering calculation module simultaneously with the to-be-filtered data at the second folding read address.

[0073] On the other hand, the read / write control module includes a second folding address counter; when the number of to-be-filtered data written to the data cache space is greater than the transposition enable count threshold, the second folding address counter is further configured to perform a self-increment operation on the second folding read address within each filtering cycle to generate a new second folding read address, thereby triggering the read / write control module to read the to-be-filtered data at the second folding read address after each self-increment operation from the data cache space, until the number of self-increment operations reaches a second preset folding sampling number, while still allowing new to-be-filtered data to be written to the data cache space. However, the new to-be-filtered data is not counted as to-be-filtered data required for the current filtering calculation, but is instead recorded as to-be-filtered data required for the next filtering calculation. The change in the count value generated by each self-increment operation of the second folding address counter is a value of 2, i.e., each time the second folding address counter performs a self-increment operation, the corresponding count value generated increases by a value of 2 relative to the previous count value.

[0074] Before the read-write control module determines to configure the reference address as the second folding read address, which is equivalent to configuring the sum of the reference address and the value 1 as the starting address of the second folding read address (the first second folding read address that needs to be read in the corresponding filtering cycle or participating in the corresponding filtering calculation), the read-write control module is used to, when it is determined that the reference address generated by the reference address counter in the current filtering calculation or the current filtering cycle is equal to the filtering target address, update the filtering starting address to the reference address by the second folding address counter, and then configure the sum of the reference address and the value 1 as the starting address of the second folding read address, so as to avoid overlap with the starting address of the first folding read address and avoid reading the same data to be filtered. It is also convenient for the second folding read address to add a reasonable address offset value during the self-increment operation to obtain the data to be filtered in the valid address obtained by the self-increment operation, so as to avoid obtaining invalid data and losing data associated with the current filtering cycle or the current filtering calculation.

[0075] Then, the second folding address counter is used to perform a self-increment operation on the second folding read address starting from the starting address of the second folding read address, wherein the change value of the count value generated by the second folding address counter self-increasing once is a value of 2, so that the second folding read address is increased by a value of 2 in one self-increment operation relative to the previous self-increment operation, so as to realize a data reading operation in a folded manner towards an address offset direction different from the first folding read address. Then, the process of the second folding address counter performing a self-increment operation on the second folding read address includes: configuring the starting address of the second folding read address as the second folding read address, and whenever the second folding read address is self-added to the difference between the filtering target address and the value 1, the filtering starting address is updated to the second folding read address when the next system clock pulse arrives, so that the second folding read address can realize address loop traversal within the address range limited by the number of taps of the half-band filter, which can not only traverse to the latest written data to be filtered, but also reduce the allocation amount of the cache address, and then insert it into the uncovered area of ​​the first folding read address to realize loop traversal of the read address, and completely traverse the address range limited by the number of taps of the half-band filter without overlap within the same filtering cycle.

[0076] It should be noted that, at the read timing corresponding to the number of taps of the half-band filter, or at the counting timing corresponding to the reference address counter, the second folding address counter is configured to perform a self-increment operation on the second folding read address once every two consecutive system clock pulses to obtain a new second folding read address, and these two consecutive system clock pulses are recorded as a folding address read cycle. When the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold, under the control of the read-write control module, within the folding address read cycle (equivalent to two consecutive system clock pulses), the data to be filtered in the first folding read address is first read to the filter calculation module, and then the data to be filtered in the second folding read address is read to the filter calculation module. This reading is repeated within each filtering cycle until the number of data to be filtered read within one filtering cycle is equal to half the sum of the number of taps of the half-band filter and the value 1. Then, when the next system clock pulse arrives, one data to be filtered is read from the intermediate calculation cache address, wherein the intermediate calculation cache address is an address position between the most recently obtained second folding read address and the most recently obtained first folding read address. In this embodiment, in each folding address reading cycle, the address offset of the first folding read address corresponding to the first folding read address read relative to the filtering starting address is equal to the address offset of the second folding read address corresponding to the second folding read address read relative to the filtering target address, so as to realize folding calculation of the data to be filtered at the second folding read address input into the filtering calculation module within one filtering cycle and the data to be filtered at the first folding read address symmetrical in address position.

[0077] As an embodiment, the read-write control module includes a read address selector; when the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold, the read address selector selects the first folding read address generated by the first folding address counter and the second folding read address output generated by the second folding address counter to trigger the read-write control module to read the two data to be filtered in the corresponding addresses within the folding address read cycle. Figure 2In the embodiment shown, the read-write control module further includes an address adder; the read address selector outputs the first folding read address generated by the selected first folding address counter and the second folding read address generated by the selected second folding address counter through the address adder. Specifically, the two input ends of the address adder are respectively connected to the count output end set by the second folding address counter and the count output end set by the first folding address counter, and the output end of the address adder is connected to an input end of the read address selector; the address adder is used to add the second folding read address fir_raddr2 generated by the second folding address counter to the first folding address in the folding address read cycle. The first folding read address fir_raddr1 generated by the counter is added to generate a post-read address fir_raddr_after within the folding address read cycle, which is equivalent to adding an offset address equal to the second folding read address to the first folding read address, and the sum is equal to the post-read address, which is output by the address adder to the read address selector; it should be noted that after the first folding read address fir_raddr1 as the base address and the second folding read address fir_raddr2 as the offset address enter the address adder, a physical address is synthesized, and the logical sum of the output is formed by left shifting or right shifting the address segment to form a physical address with a bit width different from the input address.

[0078] The read / write control module disclosed in this embodiment generates a high-level folding selection signal when the number of the to-be-filtered data in the write data cache space is greater than the transposition enable count threshold, corresponding to Figure 2 The selection signal Thr_sel=1, the read address selector selects the post-read address generated by the address adder and outputs it to the data cache space, specifically by Figure 1 and Figure 2 The data is transmitted out of the port I4 so that the read-write control module can read the two data to be filtered in the corresponding address during the folding address read cycle, namely the data to be filtered in the first folding read address and the data to be filtered in the second folding read address.

[0079] It should be added that the address offset between the starting address of the second folded read address and the starting address of the first folded read address is equal to the difference between the number of taps of the half-band filter and the value 1, so that under the premise that the direction of traversal of the second folded read address is different from the traversal direction of the first folded read address, each address in the same address range is traversed together, for example, by updating the first folded read address to traverse from the first address to the last address, and by updating the second folded read address to traverse from the last address to the first address, the traversal of the same address range is completed completely with the same traversal step size.

[0080] In the above embodiment, in each folding address reading cycle, the address offset of the first folding read address corresponding to the first folding read address read relative to the filtering starting address is equal to the address offset of the second folding read address corresponding to the second folding read address read relative to the filtering target address, forming a head-to-tail address symmetric form of a half-band filter structure centered on the address position last read within a filtering cycle or a filtering calculation, that is, the first folding read address and the second folding read address in each folding address reading cycle are symmetric about the center of the address position last read within a filtering cycle.

[0081] Preferably, within a filtering cycle or a filtering calculation, the difference between half the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to the first preset folding sampling number and is also equal to twice the number of times the first folding address counter performs a self-decrement operation. In this case, half the difference between the number of taps of the half-band filter and the value 1 is equal to the second preset folding sampling number. Then, the first folding read address obtained by decrementing the first folding read address is decremented by one to obtain the difference between the first folding read address and the value 1 and update it as the first folding read address. The updated first folding read address is then maintained unchanged and marked as the intermediate calculation cache address. Furthermore, after the difference between half the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to twice the number of times the second folding address counter performs a self-increment operation, the second folding address counter stops performing the aforementioned self-increment operation on the second folding read address and maintains the second folding read address unchanged. It should be noted that, since within a folding address reading cycle, the data to be filtered in the first folding read address and the data to be filtered in the second folding read address will be read successively, in order to avoid repeatedly reading the data in the same address without writing new data to be filtered, the self-addition operation on the second folding read address is stopped, and the difference between the currently obtained first folding read address and the value 1 is updated to the first folding read address, and then the first folding read address is kept unchanged as the intermediate calculation cache address in the current filtering cycle, which is also the intermediate address position required for a filtering calculation.

[0082] As an embodiment of a half-band filter with a tap number equal to 7, the reference address corresponds to Figure 3 The initial address of the reference address counter, in this embodiment, the count value of the reference address counter in each filtering cycle is configured as the reference address in each filtering cycle as the updated reference address; the reference address in the first filtering cycle is 0, which is the initial count value of the reference address counter. Figure 3In the example, each time a filtering calculation begins, it is considered the beginning of a filtering cycle, and the reference address counter counts once. Except for the first filtering cycle, in which only one data item to be filtered is written, in subsequent filtering cycles, each time two new data items to be filtered are written to the data cache space, a read and filtering calculation is performed. After the first filtering calculation is completed and the filtering result y1 is obtained, that is, after one filtering cycle, in the second filtering cycle, the data in the first row of boxes is shifted two coefficient positions to the right as a whole, becoming the data in the third row of boxes. Compared to the data in the first row of boxes, two new data items are added to occupy the two leftmost grids. At this time, the filtering calculation module begins a new filtering calculation, and the reference address counter counts up by two. The reference address counter increases the reference address in the first filtering cycle by 2, and the reference address in the second filtering cycle is 2. After completing the second filtering calculation and obtaining the filtering result y3, in the third filtering cycle, the data in the third row box is shifted to the right by two coefficient bits as a whole and becomes the data in the fifth row box. Two new data are added relative to the data in the third row box to occupy the two leftmost grids. At this time, the filtering calculation module starts a new filtering calculation (the third filtering calculation), and the reference address counter counts by two. The reference address of the third filtering cycle is offset to the right by two address units relative to the reference address of the second filtering cycle, and the reference address of the third filtering cycle is obtained as a value of 4; thereby: the address offset between the reference addresses obtained in two adjacent filtering cycles is equal to the decimation rate of the half-band filter (twice the decimation rate). At this time, the reference address counter is used to count the shift operation of the read address of the data cache space, which also facilitates the use of the shift register to cache the newly written data to be filtered.After completing the third filtering calculation and obtaining the filtering result y5, in the fourth filtering cycle, the data in the fifth row box is shifted to the right by two coefficient bits as a whole and becomes the data in the seventh row box. Two new data are added to occupy the two leftmost grids relative to the data in the fifth row box. At this time, the filtering calculation module starts a new filtering calculation (the fourth filtering calculation), and the reference address counter counts plus two. The reference address of the fourth filtering cycle is offset to the right by two address units relative to the reference address of the third filtering cycle, and the reference address of the fourth filtering cycle is obtained as a value of 6; after completing the fourth filtering calculation and obtaining the filtering result y7, in the fifth filtering cycle, the data in the seventh row box is shifted to the right by two coefficient bits as a whole. Shift two coefficient positions to become the data in the ninth row of boxes. Compared with the data in the seventh row of boxes, two new data are added to occupy the two leftmost grids. At this time, the number of data to be filtered written into the data buffer is greater than the transpose enable count threshold of the half-band filter, that is, the number of data to be filtered written into the data buffer is greater than 7 (the number of taps of the currently multiplexed FIR filter is equal to 7, and the number of taps of the currently multiplexed FIR filter is equal to the transpose enable count threshold of the currently multiplexed FIR filter). At this time, the filtering calculation module starts a new filtering calculation (the fifth filtering calculation) to obtain the filtering result y9. At this time, the data buffer has stored 9 data to be filtered. Since the address offset of the folding reference address number of the fourth filtering cycle relative to the folding reference address number in the first filtering cycle is the difference between the number of taps of the half-band filter and the numerical value 1, that is, the count value of the reference address counter (the initial count value is equal to the numerical value 0) in the fourth filtering cycle is the difference between the number of taps of the half-band filter and the numerical value 1, the read-write control module updates the sum of the filtering starting address and the numerical value 1 to the count value currently obtained by the reference address counter in the fifth filtering cycle, and updates the sum of the filtering starting address and the numerical value 1 to the reference address, corresponding to the initial address of the fifth filtering cycle; however. Figure 3 The boxes only display the extracted data, corresponding to X9, X3, X7, X5, and X6 in the ninth row of the fifth filter cycle. The filter starting address is 0. It should be noted that the filter starting address is a pre-configured address within the data cache space. It serves as the smallest address among the addresses involved in the read operation within each filter cycle. In this case, the filter starting address is configured to be 0.

[0083] Corresponding to Figure 3 In the window of the extracted data, in the fifth filtering cycle, when the number of taps is 7, according to Figure 2The post-read address fir_raddr_after at the output end of the read address selector shown is equivalent to the first folded read address and the second folded read address transmitted successively. Then, the read-write control module first reads the 7th input data X7 (data at the first folded read address) and the 1st input data X3 (data at the second folded read address) to form a first pair of added parameters and sends them to the filtering calculation module; then reads the 5th input data X5 (data at the first folded read address) and the 3rd input data X3 (data at the second folded read address) to form a second pair of added parameters and sends them to the filtering calculation module; finally, reads the 4th input data X4 (intermediate calculation cache address) and sends it to the filtering calculation module; wherein, the read-write control module successively reads the 7th input data X7 (data at the first folded read address) and the 1st input data X3 (data at the second folded read address) to form a second pair of added parameters and sends them to the filtering calculation module; The data to be filtered in the corresponding first folded read address are read out, which are X9 and X7 in the ninth row box respectively. At this time, the number of self-decrement operations is 1, which is equal to the difference between half of the difference between the number of taps of the half-band filter and the value 1 and the value 1, so the data to be filtered in the two first folded read addresses are obtained; and the read-write control module successively reads out the data to be filtered in the corresponding second folded read address from the data buffer, which are X3 and X5 in the seventh row box. At this time, the number of self-increment operations is 1, so the data to be filtered in the two second folded read addresses are obtained; then the address where X7 is located is subtracted by 1 to obtain the address corresponding to the sixth input data X6, and then stop reading data. The address corresponding to the data X6 is used as the intermediate calculation cache address in the current filtering cycle. Therefore, in the fifth filtering cycle, the data to be filtered read in sequence are X9, X3, X7, X5, and X6, where X9 is the first data to be filtered read and X6 is the last data to be filtered read. At this time, the data to be filtered read from the first folded read address, the data to be filtered read from the intermediate calculation cache address, and the data to be filtered read from the second folded read address already meet the filtering calculation requirements for the tap number matching of the half-band filter. As for the data extraction method for the fourth filtering cycle, the principles of the extraction method for the fifth filtering cycle in this embodiment are similar, so the data extraction process for the fourth filtering cycle will not be described in detail. The intermediate calculation cache address in the fourth filtering cycle is the address location of the data X4.

[0084] It is worth noting that Figure 3 In the fourth filtering cycle and the fifth filtering cycle, the arrangement order of the squares in the seventh row and the ninth row of the box corresponding to the seventh row only represents the order in which the filtered data are read, and does not represent the actual storage order in the data cache space; similarly, Figure 3The arrangement order of the squares in the even-numbered rows does not represent the storage order of the internal filter coefficients in the filter coefficient memory, but only represents the reading order of the filter coefficients and corresponds to the reading order of the data to be filtered in the previous row.

[0085] As a filtering calculation embodiment of a half-band filter with a tap number of 7, when the number of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address that matches the half-band filter, under the control of the read-write control module or driven by the built-in counter, and perform a self-increment operation on the starting storage address once every two system clock pulses are detected, so that the self-increment operation performed on the starting storage address is synchronized with the timing of the self-decrement operation performed by the first folding address counter, or synchronized with the timing of the self-increment operation performed by the second folding address counter; the filter coefficient memory then reads the corresponding stored filter coefficients to the filtering calculation module in sequence according to the storage address obtained by self-increment, until the address offset of the storage address obtained by self-increment relative to the starting storage address is equal to half of the sum of the number of taps of the half-band filter and the value 1, and then the latest storage address is recorded as the intermediate calculation storage. The address is read, and the filtered data and filter coefficients required for processing within the filtering cycle have been read. Specifically, the address counter set in the filter coefficient memory or the address counter designed in the read-write control module counts the address corresponding to the starting storage address by two every two system clock pulses and generates the corresponding address. The address counter can be synchronized with the counting timing of the reference address counter, the second folding address counter, and the first folding address counter or maintain a fixed delay, and can change with the storage address configured to change simultaneously with the first folding read address and the second folding read address read successively within a folding address read cycle. The filter coefficient in the storage address and the filtered data in the first folding read address and the second folding read address in the folding address read cycle are read into the filtering calculation module successively within the same folding address read cycle, forming a set of calculation items that are first added and then multiplied, that is, the sum of the filtered data in the first folding read address and the second folding read address is multiplied by the filter coefficient. In the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, the address corresponding to the storage address is increased by a value of 2. In the filter coefficient memory, except for the intermediate calculation storage address, there are even-numbered addresses that are not read and participate in the filtering calculation. In this embodiment, the filter coefficients are not written at the corresponding even-numbered addresses. Compared with the prior art, the even-numbered addresses except for the intermediate calculation storage address do not need to store data, saving some storage space.

[0086] Based on the above embodiment, the filtering calculation module is configured to, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold, first control the to-be-filtered data in the first folding read address output by the data cache space to be added to the to-be-filtered data in the second folding read address output by the data cache space in each folding address read cycle; then perform a multiplication operation on the result of the addition with the filter coefficients in the same reading order (synchronously changing counting timing) output by the filter coefficient memory; and then input the multiplication result into an adder for accumulation processing. This process is repeated in each filtering cycle until, in a corresponding filtering cycle, when the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address, the filter coefficients in the intermediate calculation storage address are multiplied with the to-be-filtered data in the intermediate cache calculation address output by the data cache space in the same reading order; and then input the multiplication result into the adder for accumulation processing to obtain a processed filtering result in the corresponding filtering cycle, thereby completing one filtering calculation, i.e., completing the filtering calculation in one filtering cycle. In each filtering cycle, the transposition enable count threshold is equal to the difference between the number of taps of the half-band filter and a value of 1. The number of multiplication operations performed within the filtering calculation module is equal to half the difference between the number of taps of the half-band filter and a value of 1. The multiplication operation is implemented by a single multiplier in a time-sharing manner, i.e., one multiplier performs one multiplication operation during each folding address read cycle. The filtering calculation module includes an adder and a multiplier. In this embodiment, the sum of the to-be-filtered data in the first folding read address and the to-be-filtered data in the second folding read address is input into the multiplier. The filter coefficients read in the same cycle are also input into the multiplier to participate in a multiplication operation. The result of the multiplication in the cycle is then transmitted to the adder for accumulation. Therefore, in this embodiment, the filtering calculation module uses the same multiplier resources to perform multiplication operations on newly input to-be-filtered data with the same set of filter coefficients in different filtering cycles, thereby improving the reuse rate of multiplier resources under the conditions of different types of filter reading data.

[0087] Corresponding to Figure 3In the fifth filtering cycle, X9 (the data to be filtered in the first folding read address read for the first time, i.e., the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, i.e., the data to be filtered read for the second time) are a set of folding data, which are added together to obtain the first folding value. At the same time, the filter coefficient h1 is read from the filter coefficient memory; then, X7 (the data to be filtered in the first folding read address read for the second time, i.e., the data to be filtered read for the third time) and X5 (the data to be filtered in the second folding read address read for the second time, i.e., the data to be filtered read for the fourth time) are another set of folding data, which are added together to obtain the second folding value. At the same time, the filter coefficient h3 is read from the filter coefficient memory; then, the filter coefficient h5 in the intermediate calculation storage address is read from the filter coefficient memory. Generally, the filter coefficient in the intermediate calculation storage address is set to a fixed parameter. For these folded data, the filtering calculation module outputs the filter coefficients at the corresponding positions from the filter coefficient memory for multiplication to perform folding calculation. Specifically, the filtering result y9 obtained by the folding calculation is equal to: the product of the sum of X9 (the data to be filtered in the first folding read address read for the first time, that is, the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, that is, the data to be filtered read for the second time) and the filter coefficient h1 read for the first time, the product of the sum of X7 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X5 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) and the filter coefficient h3 read for the second time, and the sum of X6 (the data to be filtered in the read intermediate cache calculation address, that is, the data to be filtered read for the fifth time) and the filter coefficient h5 read for the third time.

[0088] Similarly, in the fourth filtering cycle, X7 (the data to be filtered in the first folding read address read for the first time, that is, the data to be filtered read for the first time) and X1 (the data to be filtered in the second folding read address read for the first time, that is, the data to be filtered read for the second time) are a set of folding data, which are added together to obtain the first folding value. At the same time, the filter coefficient h1 is read from the filter coefficient memory; then, X5 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X3 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) are another set of folding data, which are added together to obtain the second folding value. At the same time, the filter coefficient h3 is read from the filter coefficient memory; then, the filter coefficient h5 in the intermediate calculation storage address is read from the filter coefficient memory, and the filter coefficient in the intermediate calculation storage address is generally set to a fixed parameter. For these folded data, the filtering calculation module outputs the filter coefficients at the corresponding positions from the filter coefficient memory for multiplication to perform folding calculation. Specifically, the filtering result y7 obtained by the folding calculation is equal to: the product of the sum of X7 (the data to be filtered in the first folding read address read for the first time, that is, the data to be filtered read for the first time) and X1 (the data to be filtered in the second folding read address read for the first time, that is, the data to be filtered read for the second time) and the filter coefficient h1 read for the first time, the product of the sum of X5 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X3 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) and the filter coefficient h3 read for the second time, and the sum of X4 (the data to be filtered in the read intermediate cache calculation address, that is, the data to be filtered read for the fifth time) and the filter coefficient h5 read for the third time.

[0089] In summary, compared with the prior art, the aforementioned embodiment, based on the relationship between the difference between the number of taps of the half-band filter and the value 1 and the number of data to be filtered written into the data cache space, selects to perform a folding calculation of first adding two data to be filtered and then multiplying by the filter coefficient when the data amount reaches the number of taps of the half-band filter, and selects to perform a direct calculation of first multiplying by the filter coefficient and then accumulating when the data amount does not reach the number of taps of the half-band filter. In either state, one data to be filtered and the filter coefficient are extracted at intervals of one read address to perform a periodic filtering calculation. Therefore, within one filtering cycle, compared with the prior art, data is intermittently extracted by generating a second folding read address by counting plus two and generating a first folding read address by counting minus two in the aforementioned embodiment, so that only half of the input data to be filtered is used for the filtering calculation. The frequency of change of the read address in each filtering calculation or each filtering cycle is half the frequency of the system clock pulse, thereby reducing the interference degree of invalid data originally written into the data cache space.

[0090] On the other hand, in the read-write control module, the reset of the count value of the counter used to control the reading and writing of the data cache space can establish a connection with the aforementioned filtering starting address and the aforementioned filtering target address, so that the self-increment or self-decrement operation of the count value of the corresponding counter can be limited to the modulus value defined by the difference between the number of taps of the half-band filter and the value 1 (the number of different read addresses represented in the counter), so that among the filter coefficients obtained synchronously with the data to be filtered, the last filter coefficient involved in the calculation is more easily captured into the filtering calculation module and obtained with fewer read operations, indirectly reducing the power consumption of the FIR filter.

[0091] Based on the above embodiment, the read-write control module controls the writing of the to-be-filtered data input into the half-band filter into the data cache space in a manner that includes: the read-write control module is configured to control the writing of one to-be-filtered data input from the external input into the data cache space every other system clock pulse, so that the above embodiment has an implementation condition for determining the relationship between the amount of to-be-filtered data written into the data cache space and the transposition enable count threshold. In this embodiment, the read-write control module is configured to write one to-be-filtered data into the data cache space in the current system clock pulse and read one to-be-filtered data into the next system clock pulse. Optionally, the read-write control module sequentially reads the to-be-filtered data written into the data cache space according to the reference address generated by the reference address counter, the pre-read address generated by the pre-read address counter, the first folding read address generated by the first folding address counter, and the second folding read address generated by the second folding address counter, wherein the reference address, the pre-read address, the first folding read address, and the second folding read address all overlap with the previously determined write address.

[0092] Furthermore, an incremental counter is provided inside the read-write control module, and the read-write control module is used to control the incremental counter to add an offset to the current cache address each time a data to be filtered is written, so as to obtain the cache address of the next data to be filtered to be written, that is, the incremental counter is allowed to count by one according to the system clock pulse from the cache head address until the cache address (count value) generated by the count is equal to the difference between the number of taps of the currently multiplexed half-band filter and the value 1, and the cache head address is updated to the currently obtained cache head address. The address is determined so that the subsequently written data to be filtered overwrites the data to be filtered first stored in the cache first address, and it is determined that a continuous round of cache address traversal is completed for the data cache space, that is, a loop traversal is completed. At this time, it is determined that the number of system clock pulses that have passed since writing a data to be filtered to the cache first address is equal to the number of taps of the currently multiplexed half-band filter; wherein, the continuous cache address is composed of address units whose number is the number of taps of the currently multiplexed half-band filter, so as to meet the number of input data required for filtering calculation under the number of taps of the currently multiplexed half-band filter.

[0093] Specifically, the read-write control module is also used to, after completing a round of continuous cache address traversal, if the new data to be filtered is continued to be written to the continuous cache address according to the system clock pulse control, the incremental counter is set to the incremental initial value, and starting from the cache first address, each time a data to be filtered is written, the currently written data to be filtered will overwrite the data to be filtered originally stored in the cache address, and control the incremental counter to add an offset to the current cache address, that is, the incremental counter counts one and configures the obtained count value as the new cache address, thereby obtaining the next written data to be filtered. The cache address of the data, until the address offset of the currently obtained cache address relative to the cache head address is equal to the difference between the number of taps of the currently multiplexed half-band filter and the value 1, the cache head address is updated to the currently obtained cache address, and the count value of the incremental counter is adjusted to the incremental initial value; it should be noted that the incremental initial value set by the incremental counter represents the address sorting of the cache head address in the data cache space; each count value generated by the incremental counter represents the address sorting of the cache address written in the corresponding system clock pulse in the data cache space. It should be noted that the write address represented by the count value generated by the incremental counter covers the reference address, pre-read address, intermediate pre-read address, first folded read address, second folded read address and intermediate calculation cache address mentioned in the aforementioned embodiment.

[0094] It should be noted that, in view of the implementation process of the above modules of the present invention, an overall system structure is formed in a specific application, such as; Figure 3 The 5-tap half-band filter is taken as an example. By analogy, the design of the N-tap filter is the same and all fall within the protection scope of the present invention.

[0095] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications made based on the spirit and essence of the present invention are intended to be covered by the scope of protection of the present invention.

Claims

1. A half-band filter, characterized in that: The half-band filter includes a read-write control module, a filter calculation module, a data buffer space and a filter coefficient memory; The read / write control module is used to control the writing of the filtered data input to the half-band filter into the data cache space, and to count the change value under a single counting operation with a value of 2 to generate a read address; a read / write control module, configured to periodically read the data to be filtered from the data cache space based on a relationship between the amount of data to be filtered written into the data cache space and a transposition enable count threshold, using a read address generated by counting, and sequentially transmit the read data to be filtered to the filter calculation module; a filter coefficient memory, configured to output the required filter coefficients to the filter calculation module in sequence according to the order in which the read-write control module reads the data to be filtered from the data cache space after the read-write control module starts reading the data to be filtered from the data cache space; A filtering calculation module is used to control the filtering calculation of the to-be-filtered data output by the data buffer space and the filter coefficients output by the filter coefficient memory; wherein the difference between the number of taps of the half-band filter and the value 1 is equal to the transposition enable count threshold; The method of periodically reading the data to be filtered from the data cache space based on the relationship between the amount of the data to be filtered written into the data cache space and the transposition enable count threshold and sequentially transmitting the read data to be filtered to the filtering calculation module includes: The read / write control module is configured to read the data to be filtered in the pre-read address from the data cache space when the amount of the data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold; Wherein, the read-write control module is used for transmitting the data to be filtered to the filtering calculation module whenever a data to be filtered is read out; Among them, the pre-read address is obtained by counting from a corresponding reference address in each filtering cycle; the reference address in a filtering cycle is the first pre-read address read by the read-write control module in the filtering cycle; and a filtering cycle is greater than the sum of the pulse periods of two system clock pulses.

2. The half-band filter according to claim 1, wherein The read-write control module also includes a reference address counter; The reference address counter is used to perform a self-increment operation and generate a reference address every time two pieces of data to be filtered are written into the data cache space, triggering the read-write control module to read the data to be filtered from the data cache space using the reference address, and at the same time recording the entry of a filtering cycle and determining the start of a filtering calculation; The reference address is the first read address that needs to be traversed in the data cache space to start the current filtering calculation; the change in the count value generated by a self-increment operation of the reference address counter is a value of 2; The decimation rate of the half-band filter is 2 times.

3. The half-band filter according to claim 2, wherein: The half-band filter is further provided with a system clock source for generating a system clock pulse to drive the read / write control module to periodically read the data to be filtered from the data cache space or periodically write the data to be filtered into the data cache space; The time required to complete a write operation of the data to be filtered is one pulse period of a system clock pulse; the time required to complete a read operation of the data to be filtered is one pulse period of a system clock pulse.

4. The half-band filter according to claim 3, wherein: The read-write control module includes a pre-address counter and a read address selector; When the amount of the to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold, the read address selector selects the pre-read address generated by the pre-address counter and outputs it to the data cache space; The pre-address counter is configured to, when the amount of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold, start from the reference address in the current filtering cycle and perform a self-decrement operation each time a system clock pulse is detected, and then trigger the read-write control module to read the data to be filtered from the pre-address obtained by each self-decrement operation; The pre-address counter is used to obtain a new pre-address read address after each decrement operation within a filtering cycle or a filtering calculation when the number of data to be filtered in the write data cache space is less than or equal to the transposition enable count threshold; wherein the initial count value of the pre-address counter within each filtering cycle is the reference address of the reference address counter within the filtering cycle; each time the pre-address counter performs a decrement operation, the change in the count value generated is a value of 2.

5. The half-band filter according to claim 4, wherein: In one filtering cycle, when it is detected that the difference between half of the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to twice the number of times the pre-address counter performs the aforementioned decrement operation, the pre-address counter updates the difference between the currently obtained pre-address read address and the value 1 as the pre-address read address when the next system clock pulse arrives, so as to allow the read / write control module to read the data to be filtered in the pre-address read address, and marks the pre-address read address as the intermediate pre-address read address; The pre-address counter is further configured to, after obtaining the intermediate pre-read address, continue to perform the aforementioned self-decrement operation starting from the difference between the intermediate pre-read address and the numerical value 1 to obtain a new pre-read address; wherein the difference between the intermediate pre-read address and the numerical value 1 is allowed to be updated as the pre-read address.

6. The half-band filter according to claim 5, characterized in that When the number of data to be filtered written into the data cache space is less than or equal to the transposition enable count threshold, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address set by the half-band filter, perform a self-addition operation on the starting storage address, and then output the filter coefficients in the storage address obtained by the self-addition to the filtering calculation module, until the address offset of the storage address obtained by the self-addition relative to the starting storage address is equal to half of the sum of the number of taps of the half-band filter and the value 1, then record the latest storage address as the intermediate calculation storage address, perform a self-decrement operation on the intermediate calculation storage address, and then output the filter coefficients in the storage address obtained by the self-decrement to the filtering calculation module, until the address offset of the storage address obtained by the self-decrement relative to the intermediate calculation storage address is equal to half of the sum of the number of taps of the half-band filter and the value 1, and repeat in sequence until the number of filter coefficients output from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered read from the data cache space in the current filtering cycle; wherein the number of taps of the half-band filter is an odd number; In the process of performing the self-increment operation on the starting storage address, the storage address increases by a value of 2 each time the self-increment operation is performed; in the process of performing the self-decrement operation on the intermediate calculation storage address, the storage address decreases by a value of 2 each time the self-decrement operation is performed.

7. The half-band filter according to claim 6, wherein: The filtering calculation module is configured to control, when the amount of to-be-filtered data written into the data cache space is less than or equal to the transposition enable count threshold, the to-be-filtered data outputted from the data cache space and the filter coefficients in the same reading order outputted from the filter coefficient memory to perform a multiplication operation, and input the result into an adder for accumulation processing to obtain a processed filtering result within each filtering cycle; The multiplication operation in each filtering cycle is implemented by a multiplier in time-sharing multiplexing; the same reading order is the order of reading the data to be filtered in each filtering cycle; Wherein, the filtering calculation module includes an adder and a multiplier.

8. The half-band filter according to claim 3, wherein: The method of periodically reading the data to be filtered from the data cache space based on the relationship between the amount of the data to be filtered written into the data cache space and the transposition enable count threshold and sequentially transmitting the read data to be filtered to the filtering calculation module includes: The read-write control module includes a first folding address counter and a second folding address counter; the read-write control module is configured to configure the reference address generated by the reference address counter as the first folding read address, and configure the sum of the reference address and a value 1 as the second folding read address when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold; When the amount of to-be-filtered data in the write data cache space is greater than the transposition enable count threshold, the first folding address counter is configured to perform a self-decrement operation on the first folding read address in each filtering cycle to generate a new first folding read address, so as to trigger the read / write control module to read the to-be-filtered data from the first folding read address obtained by each self-decrement operation; When the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold, the second folding address counter is further configured to perform a self-increment operation on the second folding read address in each filtering cycle to generate a new second folding read address, so as to trigger the read / write control module to read the to-be-filtered data from the second folding read address obtained by each self-increment operation; The change in the count value generated by the first folding address counter's self-decrement operation is 2. The change in the count value generated by one self-increment operation of the second folding address counter is 2.

9. The half-band filter according to claim 8, wherein: Within a filtering cycle, after the difference between half of the difference between the number of taps of the half-band filter and the numerical value 1 and the numerical value 1 is equal to twice the number of times the first folding address counter performs the self-decrement operation, the first folding address counter stops performing the aforementioned self-decrement operation on the first folding read address, and updates the difference between the currently obtained first folding read address and the numerical value 1 to the first folding read address, then keeps the updated first folding read address unchanged, and marks the first folding read address as the intermediate calculation cache address; and, after the difference between half of the difference between the number of taps of the half-band filter and the numerical value 1 and the numerical value 1 is equal to twice the number of times the second folding address counter performs the self-increment operation, the second folding address counter stops performing the aforementioned self-increment operation on the second folding read address, and keeps the second folding read address unchanged.

10. The half-band filter according to claim 9, characterized in that: The first folding address counter is configured to perform a self-decrement operation on the first folding read address every time two system clock pulses are detected to obtain a new first folding read address, and to combine the pulse periods of two adjacent system clock pulses into a folding address read period; When the number of data to be filtered written into the data cache space is greater than the transposition enable count threshold, under the control of the read-write control module, within the folding address read cycle, first read the data to be filtered in the first folding read address to the filtering calculation module, then read the data to be filtered in the second folding read address to the filtering calculation module, and repeat this process within one filtering cycle until the number of data to be filtered read is equal to half of the sum of the number of taps of the half-band filter and the value 1, and then read one data to be filtered from the intermediate calculation cache address when the next system clock pulse arrives, wherein the intermediate calculation cache address is an address position between the most recently obtained second folding read address and the most recently obtained first folding read address; The second folding address counter is used to perform a self-increment operation during the folding address read cycle to obtain a new second folding read address every time two consecutive system clock pulses arrive.

11. The half-band filter according to claim 10, wherein: The read-write control module also includes a read address selector; When the number of data to be filtered in the write data cache space is greater than the transposition enable count threshold, the read address selector selects the first folding read address generated by the first folding address counter and the second folding read address output generated by the second folding address counter to trigger the read-write control module to read the two data to be filtered in the corresponding addresses within the folding address read cycle.

12. The half-band filter according to claim 10, wherein: When the count value of the reference address counter is the difference between the number of taps of the half-band filter and the value 2, the read-write control module updates the filter starting address to the count value currently obtained by the reference address counter at the next system clock pulse, and updates the filter starting address to the reference address; When the count value of the reference address counter is the difference between the number of taps of the half-band filter and the value 1, the read-write control module updates the sum of the filter starting address and the value 1 to the count value currently obtained by the reference address counter at the next system clock pulse, and updates the sum of the filter starting address and the value 1 to the reference address; The filtering starting point address is set to a value of 0, and the number of taps of the half-band filter is an odd number.

13. The half-band filter according to claim 12, wherein: When the amount of to-be-filtered data in the write data cache space is greater than the transposition enable count threshold, before the read-write control module determines to configure the reference address as the first folding read address, if the read-write control module determines that the reference address is equal to the filtering start address, the filtering target address is updated to the reference address, and the updated reference address is configured as the start address of the first folding read address, and then the first folding address counter is used to perform a self-decrement operation on the first folding read address starting from the start address of the first folding read address; When the amount of data to be filtered in the write data cache space is greater than the transposition enable count threshold, before the read-write control module determines to configure the reference address as the second folding read address, if the read-write control module determines that the reference address is equal to the filtering target address, the filtering starting address is updated to the reference address, and then the sum of the updated reference address and the value 1 is configured as the starting address of the second folding read address. Then, the second folding address counter is used to perform a self-increment operation on the second folding read address starting from the starting address of the second folding read address.

14. The half-band filter according to claim 13, wherein: The process of the first folding address counter performing a decrement operation on the first folding read address includes: configuring the starting address of the first folding read address as the first folding read address, and updating the difference between the filtering target address and the value 1 as the first folding read address at the next system clock pulse whenever the first folding read address is decremented to the filtering starting address; and updating the filtering target address to the first folding read address at the next system clock pulse whenever the first folding read address is decremented to the sum of the filtering starting address and the value 1; The process of the second folding address counter performing a self-addition operation on the second folding read address includes: configuring the starting address of the second folding read address as the second folding read address, and whenever the second folding read address is self-added to the filtering target address, updating the sum of the filtering starting address and the numerical value 1 to the second folding read address at the next system clock pulse; whenever the second folding read address is self-added to the difference between the filtering target address and the numerical value 1, updating the filtering starting address to the second folding read address at the next system clock pulse.

15. The half-band filter according to claim 14, characterized in that: In each folding address read cycle, an address offset of a first folding read address corresponding to a first folding read address read relative to the filtering start address is equal to an address offset of a second folding read address corresponding to a second folding read address read; The filtering target address is an address pre-configured in the data cache space, and is the address with the largest order among the addresses participating in the read operation in each filtering cycle; The filtering starting point address is an address pre-configured in the data cache space, and is the smallest address in the order of the addresses read in each filtering cycle; The difference between the filtering target address and the filtering starting address is equal to the difference between the number of taps of the half-band filter and a value of 1.

16. The half-band filter according to claim 10, wherein: When the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold, the filter coefficient memory is used to, within each filtering cycle, start from a starting storage address that matches the half-band filter, and perform a self-addition operation on the starting storage address once every time two system clock pulses are detected, and then sequentially read the filter coefficients in the storage address obtained by the self-addition operation from the filter coefficient memory to the filtering calculation module until the address offset of the storage address obtained by the self-addition operation relative to the starting storage address is equal to half of the sum of the number of taps of the half-band filter and a value of 1, and the most recently obtained storage address is recorded as an intermediate calculation storage address; In the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, a storage address is generated, and the change value of the storage address generated by two adjacent self-increment operations is a value of 2.

17. The half-band filter according to claim 16, wherein: The filtering calculation module is configured to, when the amount of to-be-filtered data written into the data cache space is greater than the transposition enable count threshold, first control the to-be-filtered data in the first folding read address output by the data cache space to be added with the to-be-filtered data in the second folding read address output by the data cache space in each folding address read cycle; then perform a multiplication operation on the result of the addition with the filter coefficients in the same reading order output by the filter coefficient memory; then input the multiplication result into an adder for accumulation processing, and repeat this process in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address; then control the filter coefficients in the intermediate calculation storage address to be multiplied with the to-be-filtered data in the intermediate pre-read address; and then input the multiplication result into the adder for accumulation processing to obtain a processed filtering result in the corresponding filtering cycle; Wherein, in each filtering cycle, the multiplication operation is implemented by a multiplier in time-sharing multiplexing; the filtering calculation module includes an adder and a multiplier.

18. The half-band filter according to claim 17, wherein: The manner in which the read-write control module controls the data to be filtered input into the half-band filter to be written into the data cache space includes: An incremental counter is provided inside the read-write control module. The read-write control module is used to control the incremental counter to add an offset to the current cache address each time a data to be filtered is written, starting from the cache head address of the data cache space, to obtain the cache address of the next data to be filtered written, until the address offset of the currently obtained cache address relative to the cache head address is equal to the number of taps of the half-band filter, the cache head address is updated to the currently obtained cache address, so that the subsequently written data to be filtered overwrites the data to be filtered originally stored at the cache head address, and determines that a round of continuous cache address traversal of the data cache space is completed; wherein, the continuous cache address is composed of address units whose number is the number of taps of the half-band filter.

19. The half-band filter according to claim 18, wherein: The read-write control module is further configured to, after completing a round of traversal of continuous cache addresses, set the incremental counter to an incremental initial value if new data to be filtered is continued to be written to the continuous cache addresses according to system clock pulse control, and starting from the cache first address, overwrite the data to be filtered originally stored in the cache address with the currently written data to be filtered, and control the incremental counter to add an offset to the current cache address to obtain the cache address of the next written data to be filtered, until the address offset of the currently obtained cache address relative to the cache first address is equal to the difference between the number of taps of the half-band filter and the value 1, update the cache first address to the currently obtained cache address, and adjust the count value of the incremental counter to the incremental initial value; Among them, the incremental initial value set by the incremental counter represents the address order of the cache first address in the data cache space; each count value generated by the incremental counter represents the address order of the cache address written in the corresponding system clock pulse in the data cache space.

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