A RISC-V vector memory access processing system and processing method

Abstract

A RISC-V vector memory access processing system and processing method, the processing system includes a scalar-vector dispatch unit that can transmit data to each other, a scalar-vector instruction hysteresis monitoring unit and a scalar-vector memory access unit, and a decoding unit and a system status register connected to the scalar-vector dispatch unit, the decoding unit is also connected to an instruction memory, a vector register and a scalar register; the scalar-vector memory access unit is connected to a data bus and a vector write-back arbitration unit, and the vector write-back arbitration unit is also connected to the vector register and the scalar register. The present invention only adds a small number of hardware function units on the basis of the existing scalar processing system, improves the memory access capability of the scalar processor to vector data, reduces the invalid dispatch-cancellation time of the processor, and greatly improves the processing efficiency of the scalar processor to vector data.

Description

Technical Field

[0001] The present invention belongs to the technical field of processor hardware, and in particular relates to a RISC-V vector memory access processing system and a processing method. Background Art

[0002] With the rapid development of artificial intelligence and big data, scalar processors inside embedded chips usually need to process digital signals such as images and audio in real time and adaptively. The efficiency of parallel processing of big data directly determines the overall performance of the chip. Such tasks usually tend to be computationally intensive, and the performance of traditional general-purpose scalar processors is difficult to meet the real-time vector computing needs.

[0003] The commercial vector processors started late. In order to improve the performance of the processor, the data bus width and data interface protocol are all based on the most advanced standards, which makes such vector processors have problems such as interface mismatch and data bus width mismatch when integrated and used in embedded systems. In addition, such vector processors usually require a deeply customized compiler to bring out their excellent performance, which makes the cost of using such processors high and often unsuitable for product integration of consumer chips.

[0004] Some embedded processor manufacturers have extended the vector instruction set on the existing scalar processor architecture (such as INTEL's MMX and SSE architectures, and ARM's SVE architecture). Although they have certain vector data processing capabilities, the compatibility issues of the old instruction set need to be considered during the initial design, making the newly developed processor architecture more and more complex and redundant. Due to their own costs and integration adaptation difficulties, the processing of vector data is limited and it is difficult to meet more complex data computing scenarios. Another type of manufacturer reserves an extension interface inside the scalar processor to process vector data by extending the vector acceleration unit. Since this type of extension interface is defined by each processor manufacturer rather than a unified industrial standard interface, it is not suitable for large-scale promotion and application. In addition, due to the limitations of the extension interface, this type of processor cannot execute vector instructions.

[0005] RISC-V is an open source instruction set architecture (ISA) based on the principles of the Reduced Instruction Set (RISC). Compared with the architectural definitions of other vector instruction sets (such as ARM's SVE architecture), the RISC-V vector instruction set (RVV) architecture has more independent designs for different functional vector instructions, simpler processing of arbitrary vector lengths, and its encoding and function definition methods are highly consistent with the RISC-V scalar instruction set implementation. Therefore, benefiting from the simplification of the RISC-V vector instruction set design, the memory access logic required for the RISC-V processor to expand the vector path can be implemented more simply and efficiently, but there is currently no general implementation solution for expanding support for RISC-V vector memory access instructions in scalar processors. Summary of the invention

[0006] In order to overcome the technical defects of the prior art, the present invention discloses a RISC-V vector memory access instruction processing method and processing system.

[0007] The present invention discloses a RISC-V vector memory access processing system, comprising a scalar-vector dispatch unit capable of mutually transmitting data, a scalar-vector instruction hysteresis monitoring unit and a scalar-vector memory access unit, and a decoding unit and a system status register connected to the scalar-vector dispatch unit, wherein the decoding unit is also connected to an instruction memory, a vector register and a scalar register; the scalar-vector memory access unit is connected to a data bus and a vector write-back arbitration unit, wherein the vector write-back arbitration unit is also connected to the vector register and the scalar register;

[0008] The specific function of the scalar-vector dispatch unit is to send instructions to other modules at the earliest time point without conflict;

[0009] The specific functions of the scalar-vector instruction hysteresis monitoring unit include vector hazard control, dispatching instructions into FIFO, vector memory access FIFO write enable control and vector memory access FIFO read enable control;

[0010] The specific functions of the scalar-vector memory access unit include memory access location determination, memory access request generation and vector register write-back request control;

[0011] The function of the vector write-back arbitration unit is to send the data sent from the scalar-vector memory access unit to the vector register.

[0012] Specifically, the scalar-vector dispatch unit, the scalar-vector instruction latency monitoring unit, the scalar-vector memory access unit, and the vector write-back arbitration unit modules are all individually customized chips.

[0013] The present invention also discloses a RISC-V vector memory access processing method, comprising the following steps:

[0014] S1. Obtain a vector memory access instruction, which is obtained from an external instruction memory and sent to a decoding unit;

[0015] S2. The decoding unit decodes the vector memory access instruction to obtain complete instruction control information required for subsequent instruction execution, wherein the complete instruction control information includes vector memory access type information, vector register index, and vector memory access base address, and sends the information to the scalar-vector dispatch unit, and simultaneously obtains the write-back source data required for the execution of the vector storage instruction from the vector register;

[0016] S3. If there is a risk, suspend the dispatch of vector arithmetic instructions until the risk-related vector memory access instruction retires;

[0017] When the above hazard does not exist, the scalar-vector dispatch unit hands over the complete instruction control information sent by the decoding unit and the write-back source data in step S2 to the scalar-vector memory access unit;

[0018] At the same time, the instruction control information required for controlling memory access in the complete instruction control information is sent to the scalar-vector instruction hysteresis monitoring unit, the vector switch in the memory access unit is turned on, and step S4 is performed; the instruction control information includes vector memory access type information, vector register index, vector memory access base address, and vector data type obtained from the system status register;

[0019] S4. After the scalar-vector instruction hysteresis monitoring unit receives the instruction control information dispatched by the scalar-vector dispatch unit:

[0020] Continuously send control information related to instructions to be retired, including vector data type, vector memory access type information, vector register index, and vector memory access base address;

[0021] The scalar-vector instruction latency monitoring unit indicates to the scalar-vector memory access unit the vector data type, vector memory access type and vector memory access base address of the memory access instruction to be retired for generating memory access information;

[0022] In this step, after receiving the specific memory access instruction, the scalar-vector memory access unit performs the following memory access status judgment:

[0023] If the specific memory access instruction is a vector load operation, the complete memory access address is calculated according to the vector memory access base address sent by the scalar-vector instruction latency monitoring unit in step S3 and the memory access signal in the memory access offset lookup table; the scalar-vector memory access unit generates a single memory access command including the memory access address information to the memory access data bus,

[0024] If the specific memory access instruction is a vector store operation, the write-back source data obtained in step S2 is sent to the data bus at the same time as the command of the vector load operation;

[0025] Determine the memory access count representing the current memory access location. If the memory access count is the same as the memory access count indicated by the vector data type sent by the scalar-vector instruction latency monitoring unit in step S3, it is called that the vector memory access request is completed, and go to step S5; otherwise, go to step S6;

[0026] S5. The scalar - vector instruction hysteresis monitoring unit receives the instruction of the scalar - vector memory access unit in step S4 to determine the memory access state, and releases the memory access write-back flag when the vector memory access request is completed, informing the scalar - vector dispatch unit that subsequent memory access instructions can be dispatched into the scalar - vector instruction hysteresis monitoring unit, and proceeds to step S7;

[0027] S6. Inform the scalar-vector dispatch unit to suspend the dispatch of memory access instructions, calculate the address and memory access command request required for the next memory access, wait for the data to be written back, and proceed to step S7;

[0028] S7. After the write-back operation is performed in the scalar-vector memory access unit, the write-back is completed and the process proceeds to step S8; otherwise, the process returns to step S4;

[0029] S8. Update the write-back comparison flag for the normal write-back indication of the next instruction.

[0030] Preferably, the risk state in step S3 includes:

[0031] The destination register index corresponding to the current vector register index information is retained in the external monitoring unit; or the current memory access interface is occupied by a vector instruction; or the scalar-vector instruction external monitoring unit is full and needs to wait for write-back; or the scalar-vector dispatch unit determines that the issued instruction has not yet completed the complete write-back.

[0032] Preferably, the write-back operation in step S7 is specifically as follows:

[0033] The register index adder in the scalar-vector memory access unit adds the write-back valid counter and the destination register index sent by the scalar-vector instruction hysteresis monitoring unit in step S3 to obtain a specific vector register index; and generates a write-back request control:

[0034] If the instruction is a vector load instruction, the vector switch state, the data bus return data, the vector register index and the write-back data returned by the data bus are sent to the write-back arbitration unit at the same time;

[0035] The write-back arbitration unit reads the write-back comparison flag and the vector switch state, and sends the data sent from the memory access unit to the vector register corresponding to the specific vector register index number;

[0036] If the instruction is not a vector load instruction but a vector store instruction, it indicates that the data bus has completed the storage of the write-back source data at this time.

[0037] The memory access unit adds 1 to the write-back valid counter in the next cycle. If the write-back valid counter return value is the same as the memory access times indicated by the vector data type in the vector data type, it is called vector memory access write-back completion, and the process goes to step S8, otherwise it goes back to step S4;

[0038] The vector memory access instruction processing method of the present invention has the following advantages:

[0039] The present invention only adds a small number of hardware functional units on the basis of the existing scalar processing system, improves the memory access capability of the scalar processor to vector data, reduces the invalid dispatch-cancellation time of the processor, and greatly improves the processing efficiency of the scalar processor to vector data.

[0040] The present invention retains the original scalar processing mode of the processor while reducing instruction memory access requests caused by the processing of multiple scalar instructions, and greatly reduces the time and power consumption losses caused by the decoding link and the correlation detection link.

[0041] The present invention retains the original external hardware interface and data bus of the processor, which is more conducive to system integration and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A system architecture diagram for monitoring and executing multi-cycle scalar memory access instructions for a typical embedded scalar processor in the prior art;

[0043] Figure 2 A flow chart comparing a scalar memory access solution and a vector memory access solution of the present invention when accessing the same amount of data;

[0044] Figure 3 A schematic diagram of a specific implementation of the RISC-V vector memory access instruction processing system module interface of the present invention;

[0045] Figure 4 A schematic diagram of a specific instruction transmission relationship between the scalar-vector dispatch unit and the scalar-vector instruction hysteresis monitoring unit of the present invention;

[0046] Figure 5 The internal diagram of the write-back control composed of the scalar-vector memory access unit, the scalar-vector dispatch unit and the scalar-vector instruction hysteresis monitoring unit of the present invention;

[0047] Figure 6 It is a scalar multi-cycle instruction control flow chart in the prior art;

[0048] Figure 7 A flowchart of a specific implementation of vector multi-cycle instruction control in the present invention;

[0049] Figure 8 Schematic diagram for unoptimized vector writeback failure;

[0050] Fig. 9 A schematic diagram of a write-back comparison mark and a memory access mark of instructions to be retired in the vector memory access FIFO read enable control of the present invention;

[0051] Fig.10 A schematic diagram of return values ​​and related controls of a memory access request count and a write-back valid count in a continuous clock cycle in the vector memory access method of the present invention;

[0052] Fig.11 A schematic diagram of the return values ​​of each cycle and related control of the memory access request count and write-back valid count in the vector memory access method of the present invention during non-single-cycle write-back;

[0053] Fig.12 Schematic diagram of achieving maximum data path utilization for vector memory access;

[0054] Fig.13 A flowchart of a specific implementation of the vector memory access followed by the scalar memory access process in the present invention;

[0055] Fig.14 It is a schematic diagram of the vector memory access process in the prior art;

[0056] Figure 2 , Figures 8 to 14 In the figure, T1, T2, ... T8 represent a plurality of consecutive clock cycles. DETAILED DESCRIPTION

[0057] The specific embodiments of the present invention are described in further detail below.

[0058] In the prior art, a typical embedded RISC-V scalar processor monitors the data path for executing multi-cycle memory access instructions such as Figure 1 As shown in the figure, since the implementation of the scalar out-of-order instruction monitoring unit is associated with writeback, the instruction dispatched into the scalar out-of-order instruction monitoring unit will be cancelled at the same time as the data writeback operation is completed, and the scalar out-of-order instruction monitoring unit abides by the rule that each scalar memory access instruction can only write back one data. Since the internal hardware structure of the embedded scalar processor determines the path of the calculation data, when performing repeated operations on vector data, the invalid waiting time caused by dispatch-cancellation inside the scalar processor greatly reduces the calculation efficiency of the processor. Figure 2 As shown, when scalar memory access and vector memory access are implemented for the same amount of data, vector memory access reduces instruction memory access requests caused by the processing of multiple scalar instructions, greatly reducing the time and power consumption losses caused by the decoding link and the correlation detection link.

[0059] The present invention improves the above-mentioned scalar processor so that it can perform scalar and vector memory access processing simultaneously. The improved system enables the original scalar processor to have a complete data hardware path for vector instruction dispatching, monitoring and vector data memory access and write-back. Under the premise of the existing data bus and bandwidth, it realizes memory access support for arbitrary scalar and vector data, greatly reduces the impact on computing efficiency caused by invalid waiting cycles, and at the same time improves the processor's parallel processing performance on data.

[0060] To obtain vector memory access execution capabilities in a scalar processor, Figure 3 FIG. 1 shows a specific implementation of the vector memory access processing system of the present invention, based on Figure 1 Hardware modifications are made to the scalar dispatch unit, the scalar out-of-band instruction monitoring unit, and the scalar memory access unit address generation unit to implement the RISC-V vector processing system. Through external monitoring of the vector memory access instructions, it is possible to expand the scalar processor's support for RISC-V vector memory access instructions without changing the scalar processor's data memory access interface and without affecting the scalar processing capability.

[0061] Figure 3 In a specific implementation of the vector memory access processing system shown, it includes a scalar-vector dispatch unit (hereinafter referred to as the dispatch unit) that can transmit data to each other, a scalar-vector instruction hysteresis monitoring unit (hereinafter referred to as the hysteresis monitoring unit) and a scalar-vector memory access unit (hereinafter referred to as the memory access unit), as well as a decoding unit and a system status register connected to the scalar-vector dispatch unit, the decoding unit is also connected to an instruction memory, a vector register and a scalar register; the scalar-vector memory access unit is connected to a data bus and a vector write back arbitration unit, and the vector write back arbitration unit is also connected to the vector register and the scalar register.

[0062] The modules such as the scalar-vector dispatch unit, scalar-vector instruction hysteresis monitoring unit, scalar-vector memory access unit, vector write-back arbitration unit, etc. are all individually customized chip cores, and their internal functions are realized by transistor-level circuits formed by integrated circuit technology. They can be packaged individually or multiple chip cores can be packaged together.

[0063] A typical application scenario of the dispatch unit and the instruction delay monitoring unit is as follows: Figure 4 As shown; a specific implementation of the memory access unit is as follows Figure 5 shown.

[0064] The control flow chart of scalar and vector multi-cycle memory access instructions is as follows Figure 6 and Figure 7 As shown, the difference between vector memory access control and scalar memory access implementation lies in the control of the read and write pointers and the time for determining the empty and full requests. Figure 4 and Figure 5The functional units and connection relationships required to achieve the same function are shown.

[0065] The specific functions of each module are:

[0066] 1. The dispatch unit sends instructions to subsequent modules at the earliest time point without conflict. Its functions include:

[0067] (1) Determine whether there is a hazard, such as the following scenarios: if the destination register index corresponding to the vector register index information is retained in the scalar-vector instruction latency monitoring unit, or the memory access interface is occupied by a vector instruction, or the scalar-vector instruction latency monitoring unit is full and needs to wait for write-back;

[0068] In the above scenario, the dispatch unit determines that the issued instructions have not been fully written back, indicating that there is a hazard, and suspends the dispatch of vector arithmetic instructions until the hazard-related vector memory access instructions retire; if there is no hazard, the vector memory access and vector multi-cycle instructions are dispatched in the first cycle. Figure 1 The vector dispatch process in the lower part is shown, after which the instruction is controlled by the external monitoring unit.

[0069] (2) At the same time as dispatching, the vector destination register index, vector memory access type information, vector memory access base address and vector data type received from the vector status and control register received from the decoder unit are sent to the external monitoring unit. At the same time, the specific vector operand retrieved from the vector register by the decoder unit and the instruction control information are received and sent to the memory access unit.

[0070] The instruction control information includes a write-back flag, an index vector associated with index memory access, and a unit stride required for stride memory access.

[0071] (3) The dispatch unit receives the memory access location judgment from the memory access unit, and when the vector memory access request is completed, it pulls up the first-in first-out cache (FIFO) write pointer of the hysteresis monitoring unit, changes the write-back flag, and allows subsequent memory access instructions to be dispatched into the hysteresis monitoring unit.

[0072] 2. The specific functions of the external monitoring unit include:

[0073] (1) Vector hazard control: Receive instructions dispatched by the dispatch unit and determine whether there are memory access hazards and data hazards. If the destination register index in the instruction to be retired in the current FIFO is the same as the source register index sent by the current dispatch unit, then it is determined that there is a read-after-write data hazard. If the destination register index in the instruction to be retired in the current FIFO is the same as the destination register index sent by the current dispatch unit, then it is determined that there is a write-after-write data hazard. If the memory access request of the instruction to be retired has not been completed, then it is determined that there is a memory access hazard. When a hazard occurs, the pipeline is paused to determine the hazard control and returned to the scalar-vector dispatch unit to pause the value-taking pipeline and wait for the previous instruction to complete.

[0074] (2) Dispatching instructions into FIFO:

[0075] The external monitoring unit contains a multi-cycle instruction monitoring information FIFO. At the beginning of the first cycle memory access, an instruction dispatch enable signal is issued to allocate the FIFO storage space location.

[0076] The FIFO storage space is used to retain the vector data type, vector memory access type information, vector register index, vector memory access base address, and global vector memory access control that the vector memory access instruction depends on.

[0077] The dispatch valid signal cannot be issued at the last memory access, because this will cause the scalar-vector instruction delay monitoring unit to have no relevant information about the vector memory access and cannot control the write back. Due to the first-in-first-out FIFO logic, the empty and full status of the FIFO will not change during the vector memory access process after the vector instruction is dispatched, so the remaining instructions can be guaranteed to exit the pipeline normally.

[0078] (3) Vector memory access FIFO write enable control:

[0079] When an instruction is written back, in order to match the instructions at the time of dispatch, a write-back comparison flag is assigned when the instruction is dispatched into the FIFO. During the vector memory access process, the write-back comparison flag is also saved in the instruction control information when the first memory access command is issued. This flag is called the memory access flag. When a memory access request is generated for the data bus, the memory access flag in the current instruction control information is used as the judgment condition for the write-back comparison and is sent to the data bus at the same time. The memory access flag is returned during write-back to prevent the data returned by the other modules with higher priority from being written back by the processor memory access unit through the bus memory access. During write-back, the write-back comparison flag at the time of dispatch is compared with the write-back comparison flag that is about to be retired to achieve normal write-back of multi-cycle instructions.

[0080] The vector access is dispatched to the external monitoring unit when the first access command is issued. Figure 8As shown, if the write pointer of the FIFO is moved during the first memory access dispatch, and because the read pointer control is only changed when the last memory access is completed, the request flag and the write-back flag do not match during the memory access process, resulting in the write-back being invalid. It is necessary to ensure that the position of the write pointer is not changed during the vector instruction memory access while pulling it high in the first cycle, thereby avoiding triggering the empty and full judgment. The dispatch unit sends a vector instruction dispatch enable signal in the first cycle, and sends a write enable control signal to the FIFO when the vector memory access request is completed.

[0081] Fig. 9 Shown Figure 5 A schematic diagram of the write-back comparison flag and the memory access flag of the instruction to be retired when the instruction flag assigned to the vector instruction is 0 and the instruction flag assigned to the scalar instruction is 1 in the process shown.

[0082] (4) Vector memory access FIFO read enable control:

[0083] like Fig. 9 As shown, a retirement enable signal is issued when the vector write back is completed to ensure that the memory access write back comparison flag before the vector memory access write back is completed will not change. At the same time, the retirement enable signal also indicates that all memory accesses in the vector instruction are completed and the instruction exits from the hysteresis monitoring unit.

[0084] (5) After understanding when to change the control of the scalar-vector instruction latency monitoring unit, you need to ensure that the empty and full signal enable is turned off only during the vector instruction memory access process without affecting other functions. There are several situations to pay attention to:

[0085] ① The cycle of the enable is related to the address of the memory access. The specific number of cycles required for memory access in different address ranges is different. It cannot be pulled up for only one cycle or only acted for one cycle after each enable is reached.

[0086] ② After the vector instruction is dispatched to the scalar-vector instruction external monitoring unit, it will be handed over to external processing. If the vector memory access instruction is followed by a scalar instruction without pausing the pipeline, the vector memory access indication signal that the FIFO write enable control and the vector instruction dispatch depend on will be low, resulting in failure to enable normally. In this case, it is necessary to add a vector switch for the vector instruction in the scalar-vector memory access unit.

[0087] The vector switch prevents the vector memory access instruction from being followed by a scalar instruction, causing the vector memory access dependent vector memory access indication signal to be low, and failing to indicate write back enable normally. Fig. 9 As shown in the last memory access written back to 0, at this time the memory access unit is a scalar memory access, but it needs to be written back to the vector register.

[0088] 3. The memory access unit is used to generate vector memory access related bus requests, and its functions include:

[0089] (1) Perform vector memory access position judgment and vector memory access status judgment;

[0090] The memory access request count is used to indicate the location of the current single memory access in the entire vector memory access, so as to determine the memory access location:

[0091] Each time the handshake request for memory access request with the bus is valid, the memory access request count is increased by 1; because it is implemented by registers, it is initialized to 0, indicating that 1 memory access has been requested. The number of registers in the vector register group is specified by the register group allocation scheme in the vector data type. If the number of registers in the vector register group is specified as 1 / 2 / 4 / 8, when the counter reading is 0 / 1 / 3 / 7 respectively, it indicates that all transfer requests have been issued, and the status at this time is judged as the completion of the vector memory access request. The memory access request count is cleared to 0 in the next clock cycle.

[0092] The write-back valid count is used to indicate the number of vector memory accesses that have been completed, which is controlled by the data bus write-back handshake valid enable. After the data bus memory access write-back handshake, the write-back counter is enabled, and the counter value is increased by 1 in the next cycle. The write-back valid count return value is compared with the number of registers in the vector register group specified by the register group allocation scheme in the vector data type. If the number of registers in the vector register group is specified as 1 / 2 / 4 / 8, when the counter reading is 0 / 1 / 3 / 7 respectively, it indicates that all vector memory access transfers have been completed, and the state at this time is judged as the vector memory access write-back completion, and the write-back valid counter is cleared in the next cycle.

[0093] At the same time, the memory access position judgment and write back position judgment are read to synchronize the vector memory access status externally. When the memory access request count is 0, the vector instruction dispatch is allowed, and the vector switch state is controlled at the same time. That is, the vector switch is turned on when the memory access request count changes from 0 to 1, and the vector switch is turned off when the write back valid counter is cleared. When the vector memory access request is completed, the scalar-vector dispatch unit is instructed to perform FIFO write enable control. When the vector memory access write back is completed, the time point for running the vector instruction retirement is sent to retire from the scalar-vector instruction hysteresis external monitoring unit.

[0094] (2) Memory access request generation:

[0095] Vector load instructions need to retrieve each data from different locations in the data memory in sequence and combine them into a vector in the vector register. Vector store instructions need to take out the vector from the vector register and store it back to different locations in the data memory in sequence. Due to the uncertainty of memory access, the vector memory access address adder adds the offset of a single memory access with the vector memory access base address returned by the hysteresis monitoring unit and the offset of a single memory access to calculate the complete memory access address. The memory access offset lookup table uses the vector memory access type and vector data type from the scalar-vector instruction hysteresis monitoring unit as input. The initial offset is 0. After the memory access request handshake, the memory access request counter count increases and the memory access offset register is enabled to increment. The transmission can be completed in a single cycle, that is, the offset calculation is completed before each memory access command is issued. If it is a vector store instruction, the write-back source data sent by the scalar-vector dispatch unit corresponding to the specific vector register index calculated in the register index adder is sent to the data bus at the same time. Taking a 32-bit vector register as an example, the bus bit width is matched, and some return values ​​are as follows:

[0096] The aligned unit stride memory access offset is 4;

[0097] The aligned stride access offset is the scalar stride sent by the scalar-vector dispatch unit;

[0098] The aligned index access offset is the product of the offset corresponding to the vector data type and the index sent by the scalar-vector dispatch unit.

[0099] If the memory is accessed with a non-aligned unit stride, the corresponding low-order elements are sent to the write-back unit after being aligned downward according to the base address, and the high-order data are retrieved at the next memory access.

[0100] The memory access offset lookup table is related to different embedded memory access bandwidths and bus protocol implementations. The memory access offset register calculates the offset of a single memory access in a vector memory access by receiving the return value of the memory access position judgment. The vector memory access address adder adds the offset of a single memory access with the vector memory access base address and the offset of a single memory access returned by the scalar-vector instruction latency monitoring unit to calculate the complete memory access address, thus realizing memory access support for any vector memory access type and vector data type.

[0101] (3) Vector register write back request control:

[0102] According to the return value of the write-back counter, the destination register index returned by the external monitoring unit is read to generate a specific vector register index.

[0103] When writing back a vector, the specific vector register location where data needs to be written back each time is related to the current memory access phase. The vector register index is calculated by adding the current write-back counter return value to the vector destination register index.

[0104] When receiving the data bus write back request handshake, the data and the specific vector register index and the vector switch state are sent to the write back arbitration unit.

[0105] 4. The function of the vector write-back arbitration unit is to read the vector write-back flag and the vector switch status to indicate that the location where the data is written back is the vector register, and to send the data sent from the scalar-vector memory access unit to the vector register corresponding to the specific vector register index number. Specific functions include:

[0106] (1) During the vector memory access process, the data received at the specific address is sent to the vector register to ensure write-back consistency while preventing the read and write of the vector data from modifying the scalar content. The vector write-back operation is enabled to send the data sent from the memory access unit to the vector register corresponding to the specific vector register index number.

[0107] (2) Since only one memory access write-back can be completed in a single cycle, reading the write-back flag ensures that the received data will not be written back by other multi-cycle instructions dispatched into the vector latency monitoring unit.

[0108] (3) The vector switch status indicates whether the data write-back location is a vector register. The write-back data, enable signal, and register index offset are provided by the memory access unit to prevent vector data from overwriting scalar registers. Since the memory access data returned by the bus is received at most once per cycle, the scalar memory access data and the vector memory access data will not arrive at the same time. In addition, the vector write-back only occupies the memory access path and the vector register write-back interface, and there is no logical conflict between the write-back of the scalar arithmetic instruction and the vector memory access data. Therefore, the vector memory access data and the scalar arithmetic result can be written back at the same time.

[0109] Based on the above vector memory access processing system, the vector memory access processing method described in the present invention is as follows: Figure 2 The lower part includes the following steps:

[0110] Perform step S1 in period T1;

[0111] S1. Obtain a vector memory access instruction, which is obtained from an external instruction memory and sent to a decoding unit.

[0112] The T2 cycle performs step S2 vector decoding;

[0113] S2. The decoding unit decodes the vector memory access instruction, obtains the vector memory access type information, vector register index, and vector memory access base address required for the subsequent instruction execution process, and sends it to the scalar-vector dispatch unit. At the same time, it obtains the write-back source data required for the execution of the vector storage instruction from the vector register.

[0114] The amount of write-back source data obtained is related to the vector data type obtained in the system status register. The register group allocation scheme in the vector data type specifies the number of registers in the vector register group. If the number of registers in the vector register group is specified as 1 / 2 / 4 / 8, then 1 / 2 / 4 / 8 write-back source data starting from the vector register index are obtained at this time;

[0115] The T3 cycle performs the following judgment operations

[0116] S3. If there is a hazard, that is, the destination register index corresponding to the current vector register index information is retained in the hysteresis monitoring unit (that is, the data hazard judgment is valid), or the memory access interface is occupied by a vector instruction (that is, the memory access hazard judgment is valid), or the scalar-vector instruction hysteresis monitoring unit state is full and needs to wait for write-back (the empty and full state is judged as full), when the scalar-vector dispatch unit determines that the issued instruction has not completed the complete write-back, it indicates that there is a hazard, and the dispatch of vector arithmetic instructions is suspended until the vector memory access instruction related to the hazard retires;

[0117] When the hazard does not exist, the dispatch unit delivers the complete instruction control information sent by the decoding unit and the write-back source data in step S1 to the memory access unit;

[0118] At the same time, the vector memory access type information, vector register index, vector memory access base address, and vector data type obtained from the system status register required for controlling memory access in the complete instruction control information are sent to the scalar-vector instruction hysteresis monitoring unit. At the beginning of the first cycle memory access, the FIFO write enable signal in the scalar-vector instruction hysteresis monitoring unit is pulled high to allocate the FIFO storage space location.

[0119] Each FIFO storage space in the instruction hysteresis monitoring unit is used to retain the vector data type, vector memory access type information, vector register index, vector memory access base address, and global vector memory access control that the vector memory access instruction depends on, and a write-back identifier is assigned to ensure that the write-back identifiers of different memory access cycles of a vector memory access instruction remain consistent, and at the same time, the vector switch in the memory access unit is turned on to perform step S4;

[0120] The vector switch is used to instruct the vector write back arbitration unit to write data back to the vector register or scalar register, ensuring write back consistency while preventing the reading and writing of vector data from modifying the scalar register content.

[0121] S4. After the external monitoring unit receives the command control information sent by the dispatching unit:

[0122] The control information related to the instruction to be retired is continuously sent, including vector data type, vector memory access type information, vector register index, vector memory access base address, and global vector memory access control to monitor the complete execution process of multi-cycle instructions.

[0123] The hysteresis monitoring unit receives the vector register index indicated by the dispatch unit, compares it with the destination register index of the instruction to be retired, makes vector memory access hazard and vector arithmetic instruction hazard judgment, and indicates to the scalar-vector dispatch unit whether a hazard exists.

[0124] The latency monitoring unit indicates to the memory access unit the vector data type, vector memory access type and vector memory access base address of the memory access instruction to be retired for generating memory access information.

[0125] The scalar-vector instruction hysteresis monitoring unit indicates the destination register index and write-back comparison flag for write-back control to the scalar-vector memory access unit. The instruction control information used for write-back comparison in the vector memory access process and the write-back flag sent by the scalar-vector instruction hysteresis monitoring unit confirm and match each other to ensure that the data received from the data bus will not be written back by other multi-cycle instructions sent to the scalar-vector instruction hysteresis monitoring unit.

[0126] The scalar-vector instruction hysteresis monitoring unit implements the registration monitoring of the relevant control information of the vector multi-cycle instructions. When implementing it, there is no need to pass the instruction-related control information into the pipeline with the instruction, reducing the width of the pipeline-related registers, and there is no need to worry about the functional conflict of the preceding instruction after the vector type setting instruction updates the system status register.

[0127] In this step, after receiving the specific memory access instruction, the memory access unit makes the following judgment:

[0128] If the specific memory access instruction is a vector load operation, a complete memory access address is calculated according to the vector memory access base address sent by the scalar-vector instruction latency monitoring unit in step S3 and the memory access signal in the memory access offset lookup table;

[0129] If the specific memory access instruction is a vector store operation, the write-back source data obtained in step S2 is sent to the data bus at the same time as the vector load operation request;

[0130] The memory access address is used to request data from a specific address. The memory access address and the specific data correspond one to one. The address calculation method for continuous access of different operation types is inconsistent. Data in different addresses need to be loaded into the vector register.

[0131] The memory access offset lookup table is related to the bus protocol implementation according to different embedded memory access bandwidths. The memory access offset register calculates the offset of a single memory access in a vector memory access by receiving the return value of the memory access position judgment. The vector memory access address adder adds the offset of a single memory access with the vector memory access base address and the offset of a single memory access returned by the scalar-vector instruction hysteresis monitoring unit to calculate the complete memory access address, thus realizing memory access support for any vector memory access type and vector data type.

[0132] Memory access request generation: The scalar-vector memory access unit generates a single memory access request including memory access address information to the memory access data bus. If the specific memory access instruction is a vector memory operation, the write-back source data sent in step S2 corresponding to the specific vector register index calculated in step S7 is simultaneously sent to the data bus; in the next cycle, the memory access counter will increase the memory access count by 1, and the memory access count representing the current memory access position is determined. If the memory access count matches the vector data type sent by the scalar-vector instruction hysteresis monitoring unit in step S3, step S5 is entered, otherwise step S6 is entered.

[0133] The memory access request count is used to indicate the current single memory access position in the entire vector memory access (memory access position judgment). The handshake signal with the dispatch unit is pulled high during the last memory access. At this time, the control related to the complete function of the instruction has been issued, and the pipeline can be opened to request the next instruction. The memory access request count is increased by 1 after each handshake request with the bus is valid; because it is implemented by registers, it is initialized to 0, indicating that the next request is the first specific memory access. The number of registers in the vector register group is specified by the register group allocation scheme in the vector data type. If the number of registers in the vector register group is specified as 1 / 2 / 4 / 8, when the counter reading is 0 / 1 / 3 / 7 respectively, it indicates that all transfer requests have been issued. The state at this time is called vector memory access request completion. The memory access request count is cleared to 0 in the next clock cycle.

[0134] Fig.10 The figure shows the specific return values ​​and related control methods of the memory access request count and write-back valid count in continuous clock cycles when the register group allocation scheme specifies that the number of registers in the vector register group is 4.

[0135] The implementation of memory access request count can meet the architecture's support for any register group allocation. The register group allocation schemes with 1 / 2 / 4 / 8 registers request 1 / 2 / 4 / 8 data bus memory accesses respectively, and the same applies to the write back counter. Since the memory access request count is controlled by the data bus request handshake, it can adapt to various bus protocols and bus data return cycle uncertainties, such as Fig.11 As shown, if the memory access write-back is not received in cycle T4, the issuance of the memory access request is suspended until the memory access write-back signal is received in cycle T5.

[0136] S5. The scalar-vector instruction latency monitoring unit receives the memory access status judgment instruction from the scalar-vector memory access unit, releases the memory access write-back flag when the vector memory access request is completed, and informs the scalar-vector dispatch unit that subsequent memory access instructions can be dispatched into the scalar-vector instruction latency monitoring unit, and enters step S7.

[0137] Steps S4-S5 implement a memory access bus hazard judgment mechanism to execute scalar or vector arithmetic instructions without hardware hazards while vector memory access is in progress, such as Fig.12 As shown, when there is a memory access conflict, the pipeline will be paused, a bubble will be added, and the previous memory access will be completed. Fig.13 As shown, following the FIFO first-in first-out principle, if a scalar memory access is decoded during a vector memory access, the scalar pipeline will be paused to wait for the memory access path to be idle. If a scalar memory access is followed by a vector memory access, the vector memory access will be dispatched to the scalar-vector instruction latency monitoring unit when the scalar memory access request is issued; Fig.14 The comparison of the scheme before optimization shown can avoid the memory access unit being valid after the complete vector memory access write back is completed to reduce memory access bubbles.

[0138] S6. Inform the dispatch unit to suspend the dispatch of memory access instructions, calculate the address and memory access command request required for the next memory access, wait for the data to be written back, and enter step S7.

[0139] In this step, since the hysteresis monitoring unit can realize complete monitoring of the vector multi-cycle memory access, the dispatch of scalar or vector arithmetic instructions is still allowed, and the parallel execution of risk-free instructions is allowed to improve the parallelism of the overall architecture.

[0140] The T4 cycle performs the following judgment operations:

[0141] S7. This step generates a vector register write-back control in the scalar-vector memory access unit.

[0142] The register index adder in the memory access unit adds the write-back valid counter and the destination register index sent by the external monitoring unit in step S3 to obtain a specific vector register index; and generates a write-back request control:

[0143] If the instruction is a vector load instruction, the vector switch state, the data bus return data, the vector register index and the write-back data returned by the data bus are sent to the write-back arbitration unit at the same time.

[0144] The write-back arbitration unit reads the write-back comparison flag and the vector switch state, and sends the data sent from the memory access unit to the vector register corresponding to the specific vector register index number.

[0145] If the instruction is not a vector load instruction but a vector store instruction, it indicates that the data bus has completed the storage of the write-back source data at this time.

[0146] The memory access unit will add 1 to the write-back valid counter in the next cycle. Note that the write-back valid counter has not increased at the time when the data is written back to the vector register. The write-back position judgment compares the write-back valid counter return value with the number of registers in the vector register group specified by the register group allocation scheme in the vector data type. If the number of registers in the vector register group is specified as 1 / 2 / 4 / 8, when the counter reading is 0 / 1 / 3 / 7 respectively, it indicates that all vector memory access transfers have been completed. The state at this time is called vector memory access write-back completion, and jump to S8, otherwise jump to S4;

[0147] S8. At this time, all the data required for the vector memory access instruction has been correctly written back to the vector register, and the instruction retirement enable is sent to the scalar-vector instruction hysteresis monitoring unit, enabling the FIFO read pointer in the scalar-vector instruction hysteresis monitoring unit to retire the vector instruction, and updating the write-back comparison mark for the normal write-back indication of the next instruction, so that the new instruction issued by the scalar-vector instruction hysteresis monitoring unit can be accepted in the next cycle. The write-back counter count is cleared to zero in the next clock cycle. If the next instruction is not a vector instruction, the vector switch is turned off through the vector memory access state in the next clock cycle.

[0148] The hardware implementation of vector memory access related logic is affected by bus protocol, memory access bandwidth, and write-back control. The scalar-vector memory access unit and the scalar-vector instruction hysteresis monitoring unit are combined to realize the complete control logic chain when sending a bus request at most once in a single cycle. It can generate a write-back request control to write back to the specific vector register when the data arrives at the scalar-vector memory access unit, and open the memory access instruction dispatch when the last vector memory access request is issued, ensuring that the vector data is ready when the subsequent instructions arrive. Without changing the data bus implementation method in the scalar unit, it can also complete the judgment of the entire memory access position and the implementation of related control logic.

[0149] The foregoing describes various preferred embodiments of the present invention. Unless the preferred implementation modes in various preferred embodiments are obviously self-contradictory or based on a certain preferred implementation mode, various preferred implementation modes can be arbitrarily superimposed and used in combination. The embodiments and specific parameters in the embodiments are only for clearly describing the invention verification process of the inventor, and are not used to limit the patent protection scope of the present invention. The patent protection scope of the present invention shall still be based on its claims. All equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the protection scope of the present invention.

Claims

1. A RISC-V vector memory access processing system, characterized in that: It includes a scalar-vector dispatch unit, a scalar-vector instruction latency monitoring unit and a scalar-vector memory access unit that can transmit data to each other, and a decoding unit and a system status register connected to the scalar-vector dispatch unit, wherein the decoding unit is also connected to an instruction memory, a vector register and a scalar register; the scalar-vector memory access unit is connected to a data bus and a vector write-back arbitration unit, and the vector write-back arbitration unit is also connected to the vector register and the scalar register; The specific function of the scalar-vector dispatch unit is to send instructions to other modules at the earliest time point without conflict; The specific functions of the scalar-vector instruction hysteresis monitoring unit include vector hazard control, dispatching instructions into FIFO, vector memory access FIFO write enable control and vector memory access FIFO read enable control; The specific functions of the scalar-vector memory access unit include memory access location determination, memory access request generation, and write-back request generation; The function of the vector write-back arbitration unit is to send the data sent from the scalar-vector memory access unit to the vector register.

2. The RISC-V vector memory access processing system according to claim 1, characterized in that: The scalar-vector dispatch unit, the scalar-vector instruction hysteresis monitoring unit, the scalar-vector memory access unit, and the vector write-back arbitration unit modules are all individually customized chips.

3. A RISC-V vector memory access processing method, characterized in that: The steps include: S1. Obtain a vector memory access instruction, which is obtained from an external instruction memory and sent to a decoding unit; S2. The decoding unit decodes the vector memory access instruction to obtain complete instruction control information required for subsequent instruction execution, wherein the complete instruction control information includes vector memory access type information, vector register index, and vector memory access base address, and sends the information to the scalar-vector dispatch unit, and simultaneously obtains the write-back source data required for the execution of the vector storage instruction from the vector register; S3. If there is a risk, suspend the dispatch of vector arithmetic instructions until the risk-related vector memory access instruction retires; When the above hazard does not exist, the scalar-vector dispatch unit delivers the complete instruction control information sent by the decoding unit and the write-back source data in step S2 to the scalar-vector memory access unit; At the same time, the instruction control information required for controlling memory access in the complete instruction control information is sent to the scalar-vector instruction hysteresis monitoring unit, the vector switch in the memory access unit is turned on, and step S4 is performed; the instruction control information includes vector memory access type information, vector register index, vector memory access base address, and vector data type obtained from the system status register; S4. After the scalar-vector instruction hysteresis monitoring unit receives the instruction control information dispatched by the scalar-vector dispatch unit: Continuously send control information related to instructions to be retired, including vector data type, vector memory access type information, vector register index, and vector memory access base address; The scalar-vector instruction latency monitoring unit indicates to the scalar-vector memory access unit the vector data type, vector memory access type and vector memory access base address of the memory access instruction to be retired for generating memory access information; In this step, after receiving the specific memory access instruction, the scalar-vector memory access unit performs the following memory access status judgment: If the specific memory access instruction is a vector load operation, the complete memory access address is calculated according to the vector memory access base address sent by the scalar-vector instruction latency monitoring unit in step S3 and the memory access signal in the memory access offset lookup table; the scalar-vector memory access unit generates a single memory access command including the memory access address information to the memory access data bus, If the specific memory access instruction is a vector store operation, the write-back source data obtained in step S2 is sent to the data bus at the same time as the command of the vector load operation; Determine the memory access count representing the current memory access location. If the memory access count is the same as the memory access count indicated by the vector data type sent by the scalar-vector instruction latency monitoring unit in step S3, it is called that the vector memory access request is completed, and go to step S5; otherwise, go to step S6; S5. The scalar - vector instruction hysteresis monitoring unit receives the instruction of the scalar - vector memory access unit in step S4 to determine the memory access state, and releases the memory access write-back flag when the vector memory access request is completed, informing the scalar - vector dispatch unit that subsequent memory access instructions can be dispatched into the scalar - vector instruction hysteresis monitoring unit, and proceeds to step S7; S6. Inform the scalar-vector dispatch unit to suspend the dispatch of memory access instructions, calculate the address and memory access command request required for the next memory access, wait for the data to be written back, and proceed to step S7; S7. After the write-back operation is performed in the scalar-vector memory access unit, the write-back is completed and the process proceeds to step S8; otherwise, the process returns to step S4; S8. Update the write-back comparison flag for the normal write-back indication of the next instruction.

4. The RISC-V vector memory access processing method as claimed in claim 3, characterized in that: The risk status in step S3 includes: The destination register index corresponding to the current vector register index information is retained in the external monitoring unit; or the current memory access interface is occupied by a vector instruction; or the scalar-vector instruction external monitoring unit is full and needs to wait for write-back; or the scalar-vector dispatch unit determines that the issued instruction has not yet completed the complete write-back.

5. The RISC-V vector memory access processing method according to claim 3, characterized in that: The write-back operation in step S7 is specifically as follows: The register index adder in the scalar-vector memory access unit adds the write-back valid counter and the destination register index sent by the scalar-vector instruction hysteresis monitoring unit in step S3 to obtain a specific vector register index; and generates a write-back request control: If the instruction is a vector load instruction, the vector switch state, the data bus return data, the vector register index and the write-back data returned by the data bus are sent to the write-back arbitration unit at the same time; The write-back arbitration unit reads the write-back comparison flag and the vector switch state, and sends the data sent from the memory access unit to the vector register corresponding to the specific vector register index number; If the instruction is not a vector load instruction but a vector store instruction, it indicates that the data bus has completed the storage of the write-back source data at this time; The memory access unit will add 1 to the write back valid counter in the next cycle. If the write back valid count return value is the same as the number of memory accesses indicated by the vector data type in the vector data type, it is called vector memory access write back completion, and the process goes to step S8, otherwise it returns to step S4.

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