A packaging structure of a high-voltage chip

Abstract

The application provides a packaging structure of a high-voltage chip, which comprises a high-voltage chip, a first copper pad connected to the back surface of the high-voltage chip, a first external pin connected to the first copper pad, a second external pin connected to the active surface of the high-voltage chip, a copper film layer arranged between the high-voltage chip and the first copper pad, and the high-voltage chip being connected to the first copper pad through the copper film layer; a package body is arranged, and the high-voltage chip, the first copper pad, the first external pin, the second external pin and the copper film layer are arranged in the package body, and the first external pin and the second external pin are exposed on the outer surface of the package body.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and in particular to a packaging structure of a high-voltage chip. BACKGROUND

[0002] Semiconductor packaging refers to a process of processing a wafer that has passed testing into an independent chip according to product models and functional requirements. The packaging process is as follows: a wafer from a wafer front-end process is cut into small dies after a scribing process, then the cut dies are attached to small islands of a corresponding substrate frame (lead frame) by using glue, and then the bonding pads of the dies are connected to corresponding leads of the substrate by using ultra-fine metal (gold, tin, copper, aluminum, etc.) wires or conductive resin to form a required circuit; then the independent dies are packaged and protected by a plastic shell, and a series of operations are performed after the plastic packaging; and after the packaging is completed, a finished product test is performed, and the finished product test usually goes through processes of incoming inspection, testing, and packaging, and finally is put into a warehouse for delivery.

[0003] In the prior art, the structure of a high-voltage chip is special, as shown in Figure 1 Figure 1 FIG. 1 is a structure diagram of a high-voltage chip in the prior art, and a recessed area is arranged around the edge of the active surface and the edge of the back surface of the high-voltage chip. The structure is designed in this shape so that the chip can withstand high pressure.

[0004] When the back surface of the chip is attached to the first copper gasket connected to the lead, the chip is usually attached to the first copper gasket by using a dispensing method, but in this way, the glue is easy to overflow from the four sides of the chip and reach the recessed annular area around the back surface of the chip, and even when the glue is excessive or the attachment pressure is too large, the glue is easy to be squeezed out and contact the side wall and the active surface of the chip, as shown in Figure 2 and Figure 3 Figure 2 FIG. 2 is a structure diagram of a small amount of glue overflow, Figure 3 FIG. 3 is a structure diagram of a large amount of glue overflow, and when the glue contacts the side wall and the active surface of the chip, the active surface or the side wall of the chip is easy to be conductive with the back surface, which is easy to cause a chip leakage phenomenon, thereby causing the chip to fail. SUMMARY

[0005] The present application provides a packaging structure of a high-voltage chip that avoids causing the chip to fail due to leakage.

[0006] The technical solution adopted by the present application is as follows:

[0007] ​​The packaging structure of the high-voltage chip comprises a high-voltage chip, a first copper pad connected to the back surface of the high-voltage chip, a first external pin connected to the first copper pad, a second external pin connected to the active surface of the high-voltage chip, a copper film layer arranged between the high-voltage chip and the first copper pad, and the high-voltage chip is connected to the first copper pad through the copper film layer; a package body is arranged, and the high-voltage chip, the first copper pad, the first external pin, the second external pin and the copper film layer are arranged in the package body, and the first external pin and the second external pin are exposed on the outer surface of the package body.

[0008] Further, the copper film layer is electroplated to the back surface of the high-voltage chip by electroplating.

[0009] Further, the active surface of the high-voltage chip is connected to the second external pin through a metal wire.

[0010] Further, a redistribution layer is arranged on the active surface of the high-voltage chip, and the high-voltage chip is connected to the second external pin through the redistribution layer.

[0011] Further, the second external pin and the redistribution layer are connected through a metal channel.

[0012] Further, the second external pin and the redistribution layer are connected through a metal channel.

[0013] Further, a second copper pad is arranged between the metal channel and the second external pin, and the metal channel is connected to the second external pin through the second copper pad.

[0014] Compared with the prior art, the present application has the following advantages: by connecting the first copper pad connected to the back surface of the high-voltage chip, the first external pin connected to the first copper pad, and the second external pin connected to the active surface of the high-voltage chip, arranging a copper film layer between the high-voltage chip and the first copper pad, and connecting the high-voltage chip to the first copper pad through the copper film layer, the phenomenon of chip leakage can be effectively avoided, the safety and reliability are improved, the quality and reliability of the chip packaging body are improved, and the high-voltage chip is pressed onto the first copper pad through the copper film layer, so that the copper film layer is not squeezed onto the sidewall and active surface of the chip, the active surface or sidewall of the chip is not conductive with the back surface, and the phenomenon of chip leakage is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a structure schematic view of a high-voltage chip in the prior art;

[0016] Figure 2 It is a structure schematic view of a small-dose glue overflow in the prior art;

[0017] Figure 3 Figure 1 is a schematic view of a structure for the overflow of a multi-dose glue in the prior art;

[0018] Figure 4 Figure 2 is a schematic view of a packaging structure of an embodiment of a high-voltage chip according to the present application;

[0019] Figure 5 Figure 3 is a schematic view of a packaging structure of another embodiment of a high-voltage chip according to the present application. DETAILED DESCRIPTION

[0020] The present application will be described in detail below with reference to specific embodiments, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar components or components having the same or similar functions throughout.

[0021] The directional terms mentioned in the present application, such as up, down, left, right, front, back, inner, outer, front surface, back surface, side surface, etc., are only the directions of the drawings. The embodiments described below by referring to the drawings and the directional terms used are exemplary and are only used to explain the present application, and cannot be understood as a limitation on the present application. In addition, the various specific process and material examples provided by the present application are other processes and / or other materials that can be realized by those skilled in the art.

[0022] Please refer to Figure 4 Figure 2 is a schematic view of a packaging structure of an embodiment of a high-voltage chip according to the present application;

[0023] A packaging structure of a high-voltage chip, comprising a high-voltage chip 10, a first copper pad 20 connected to the back surface of the high-voltage chip 10, a first external pin 30 connected to the first copper pad 20, a second external pin 40 connected to the active surface of the high-voltage chip 10, and a copper film layer 50 provided between the high-voltage chip 10 and the first copper pad 20. The copper film layer 50 is electroplated to the back surface of the high-voltage chip 10 by electroplating.

[0024] The high-voltage chip 10 is connected to the first copper pad 20 through the copper film layer 50. An encapsulation body 60 is provided, and the high-voltage chip 10, the first copper pad 20, the first external pin 30, the second external pin 40, and the copper film layer 50 are all arranged in the encapsulation body 60, and the first external pin 30 and the second external pin 40 are exposed on the outer surface of the encapsulation body 60.

[0025] In this embodiment, a redistribution layer a2 is provided on the active surface of the high-voltage chip 10, and the high-voltage chip 10 is connected to the second external pin 40 through the redistribution layer a2. In other embodiments, the active surface of the high-voltage chip 10 is connected to the second external pin 40 through the provision of a metal wire a1, such as Figure 5 Figure 5 ​A packaging structure schematic diagram of another embodiment of the high-voltage chip.

[0026] In the embodiment, the second outer pin 40 and the redistribution layer a2 are connected through the metal channel a3, the channel 61 is formed between the second outer pin 40 on the encapsulant 60 and the redistribution layer a2 through the laser via, the metal channel a3 is formed on the inner wall of the channel 61 through the electroplating, the second copper pad 70 is arranged between the metal channel a3 and the second outer pin 40, and the metal channel a3 is connected with the second outer pin 40 through the second copper pad 70.

[0027] Through the first copper pad 20 connected with the back surface of the high-voltage chip 10, the first outer pin 30 connected with the first copper pad 20, and the second outer pin 40 connected with the active surface of the high-voltage chip 10, and through the copper film layer 50 arranged between the high-voltage chip 10 and the first copper pad 20, the high-voltage chip 10 is connected with the first copper pad 20 through the copper film layer 50, which can effectively avoid the chip leakage phenomenon, is safe and reliable, improves the quality and reliability of the chip packaging body, and the high-voltage chip 10 is pressed onto the first copper pad 20 through the copper film layer 50, so that the copper film layer 50 will not be pressed onto the sidewall and the active surface of the chip, the active surface or the sidewall of the chip is effectively prevented from being conducted with the back surface, and thus the chip leakage phenomenon is avoided.

[0028] The above only describes the preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A package structure of a high voltage chip, characterized by, The high-voltage chip (10), the first copper pad (20) connected with the back surface of the high-voltage chip (10), the first external pin (30) connected with the first copper pad (20), the second external pin (40) connected with the active surface of the high-voltage chip (10), the copper film layer (50) provided between the high-voltage chip (10) and the first copper pad (20), and the high-voltage chip (10) connected with the first copper pad (20) through the copper film layer (50); a package body (60) is arranged, the high-voltage chip (10), the first copper pad (20), the first external pin (30), the second external pin (40) and the copper film layer (50) are arranged in the package body (60), and the first external pin (30) and the second external pin (40) are exposed on the outer surface of the package body (60), the high-voltage chip (10) is pressed onto the first copper pad (20) through the copper film layer (50), and the copper film layer (50) is electroplated on the back surface of the high-voltage chip (10) through electroplating.

2. The packaging structure of a high-voltage chip according to claim 1, wherein, The active surface of the high-voltage chip (10) is connected with the second external pin (40) through a metal wire (a1).

3. The package structure of a high voltage chip according to claim 1, wherein, The active surface of the high-voltage chip (10) is provided with a rewiring layer (a2), and the high-voltage chip (10) is connected with the second external pin (40) through the rewiring layer (a2).

4. The package structure of a high voltage chip according to claim 3, wherein, The second external pin (40) is connected with the rewiring layer (a2) through a metal channel (a3).

5. The package structure of a high voltage chip according to claim 4, wherein, The second external pin (40) and the rewiring layer (a2) on the package body (60) are connected through a laser via to form a channel (61), and the metal channel (a3) is formed on the inner wall of the channel (61) through electroplating.

6. The package structure of a high voltage chip according to claim 5, wherein, The metal channel (a3) is provided with a second copper pad (70), and the metal channel (a3) is connected with the second external pin (40) through the second copper pad (70).

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