A device and method for CPU interconnection interrupt forwarding

Abstract

The present invention proposes a device and method for CPU interconnection interrupt forwarding, the device includes: multiple clusters and several signal forwarding modules; each cluster includes multiple interconnected central processing units, and each central processing unit is connected to the nearest signal forwarding module; when it is determined that the main central processing unit and the slave central processing unit are located in different clusters, and the main central processing unit wants to send an interrupt signal to the slave central processing unit, the interrupt signal received by the interrupt controller is forwarded to the slave central processing unit according to the address signal sent by the main central processing unit. Based on the device, a method for CPU interconnection interrupt forwarding is also proposed. The method runs on the signal forwarding module, firstly determines whether the main central processing unit and the slave central processing unit are located in the same cluster, and then performs corresponding operations according to the positions of the two central processing units. The present invention is an interrupt forwarding mechanism between CPUs in multi-chip interconnection, and successfully realizes multi-chip interconnection in the case where the interrupt forwarding address is insufficient.

Description

Technical Field

[0001] The present invention belongs to the technical field of server interrupt forwarding, and in particular relates to a device and method for CPU interconnection interrupt forwarding. Background Art

[0002] In a multi-way server, multiple chips need to be interconnected, and the most important of these is the forwarding of interrupts. In the ARM architecture CPU, interrupts are triggered through GIC. The ARM architecture is a 32-bit reduced instruction set (RISC) processor architecture. GIC: Generic Interrupt Controller, an interrupt controller under the ARM architecture. The GIC protocol specifies four types of interrupts, namely SPI, PPI, SGI, and LPI. Among them are SPI (Shared Peripheral Interrupt, a shared peripheral interrupt); PPI (Private Peripheral Interrupt), SGI (Software Generated Interrupt), and LPI (Locality-specific Peripheral Interrupt).

[0003] For multi-chip interconnection, the interrupt forwarding between CPUs is the key point we need to consider. The GIC protocol also stipulates that the interrupt forwarding between CPUs is of SGI type, and SGI forwarding is carried out through affinity routing. Affinity routing is a hierarchical address-based solution used to identify specific PE nodes for interrupt routing. Affinity provides 3 / 4 level addresses, such as Figure 1 The schematic diagram of the architecture of multiple chips forwarding through GIC in the prior art. Each PE has a unique affinity address, and CPUs use this address to "discover" each other and communicate with each other. PE: (Processor Element); Due to the limitation of Feiteng servers, CPUs can only recognize a maximum of 2-bit level 2 addresses, that is, 4 CPUs, which is far from enough for multi-way interconnection. To achieve multi-way interconnection, the problem of insufficient addresses must be solved first. Summary of the invention

[0004] In order to solve the above technical problems, the present invention proposes a device and method for CPU interconnection interrupt forwarding, which can successfully realize multi-chip interconnection when the interrupt forwarding address is insufficient.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A CPU interconnection interrupt forwarding device includes multiple clusters and a number of signal forwarding modules; each cluster includes multiple interconnected central processing units, and each central processing unit is connected to a nearby signal forwarding module;

[0007] The signal forwarding module is used to forward the interrupt signal received by the interrupt controller to the slave CPU according to the address signal sent by the master CPU when it is determined that the master CPU and the slave CPU are in different clusters and the master CPU wants to send an interrupt signal to the slave CPU.

[0008] Furthermore, before executing the interrupt signal forwarding, the signal forwarding module first determines whether the master central processor and the slave central processor are located in the same cluster. If they are located in the same cluster, the interrupt controller is triggered to send an SGI interrupt signal, and an interrupt trigger is completed between the master central processor and the slave central processor;

[0009] If they are located in different clusters, the address signal sent by the main CPU is received, and the register is set to trigger the interrupt controller to send an SGI interrupt signal. According to the address signal, the SGI interrupt signal received by the interrupt controller is forwarded to the slave CPU, and the register is reset.

[0010] Furthermore, when the signal forwarding module receives the address signal sent by the main central processing unit, it locks the current address signal, and when the next address signal arrives, it unlocks the current address signal.

[0011] Furthermore, during the process of executing signal forwarding, the signal forwarding module modifies the ACPI table in the input and output system so that the main central processing unit obtains the CPU interconnection architecture.

[0012] Further, modifying the ACPI table includes modifying system resource information, a multiple APIC description table, and a system local distance information table in the ACPI table.

[0013] Furthermore, it is characterized in that the signal forwarding module adopts an editable logic chip.

[0014] The present invention also proposes a method for CPU interconnection interrupt forwarding, which is implemented based on a CPU interconnection interrupt forwarding device and runs in a signal forwarding module, and includes the following steps:

[0015] Receive an address signal sent from the main central processing unit;

[0016] If it is determined that the main central processor and the slave central processor to be forwarded are located in different clusters, the address signal sent by the main central processor is received, and the register is set to trigger the interrupt controller to send an SGI interrupt signal. According to the address signal, the SGI interrupt signal received from the interrupt controller is forwarded to the slave central processor, and the register is reset.

[0017] Furthermore, the method further includes triggering the interrupt controller to send an SGI interrupt signal if it is determined that the main central processor and the slave central processor to be forwarded are located in the same cluster, thereby completing an interrupt trigger between the main central processor and the slave central processor.

[0018] Furthermore, when receiving the address signal sent from the main central processing unit, the current address signal is locked, and when the next address signal arrives, the current address signal is unlocked.

[0019] Furthermore, in the process of executing signal forwarding, the main central processing unit obtains the CPU interconnection architecture by modifying the ACPI table in the input and output system.

[0020] The effects provided in the content of the invention are only the effects of the embodiments, not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects:

[0021] The present invention proposes a device and method for CPU interconnection interrupt forwarding, the device includes: multiple clusters and several signal forwarding modules; each cluster includes multiple interconnected central processors, and each central processor is connected to the nearest signal forwarding module; the signal forwarding module is used to forward the interrupt signal received by the interrupt controller to the slave central processor according to the address signal sent by the main central processor when judging that the main central processor and the slave central processor are located in different clusters and the main central processor wants to send an interrupt signal to the slave central processor. Based on a device for CPU interconnection interrupt forwarding, a method for CPU interconnection interrupt forwarding is also proposed. The method runs on the signal forwarding module. First, it is judged whether the main central processor and the slave central processor are located in the same cluster. If they are located in the same cluster, the interrupt controller is triggered to send an SGI interrupt signal, and an interrupt trigger is completed between the main central processor and the slave central processor; if they are located in different clusters, the address signal sent by the main central processor is received, and the register is set, the interrupt controller is triggered to send an SGI interrupt signal, and the SGI interrupt signal received by the interrupt controller is forwarded to the slave central processor according to the address signal, and the register is reset. The present invention is an inter-CPU interrupt forwarding mechanism in multi-chip interconnection, which ensures that multi-chip interconnection can be successfully realized in phytium cpu. It can realize the interconnection of 8 or more Phytium2500CPUs. If it is not used, only up to 8 Phytium2500CPUs can be used for interconnection. Similarly, this method can be used for other chip multi-way interconnection requirements. When the interrupt forwarding address is insufficient, it can successfully realize multi-chip interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] like Figure 1 It is a GIC architecture diagram of multi-chip interconnection in the prior art;

[0023] like Figure 2 This is a diagram of the architecture of a device for CPU interconnection interrupt forwarding according to Embodiment 1 of the present invention;

[0024] like Figure 3 This is a flow chart of a method for CPU interconnect interrupt forwarding according to embodiment 2 of the present invention. DETAILED DESCRIPTION

[0025] In order to clearly illustrate the technical features of the present solution, the present invention is described in detail below through specific implementation methods and in conjunction with the accompanying drawings. The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. In addition, the present invention may repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. It should be noted that the components illustrated in the accompanying drawings are not necessarily drawn to scale. The present invention omits the description of known components and processing techniques and processes to avoid unnecessary limitations on the present invention.

[0026] Example 1

[0027] Embodiment 1 of the present invention provides a device for CPU interconnection interrupt forwarding, which can successfully realize multi-chip interconnection when the interrupt forwarding address is insufficient.

[0028] The device includes multiple clusters and several signal forwarding modules; each cluster includes multiple interconnected central processing units, and each central processing unit is connected to the nearest signal forwarding module;

[0029] The signal forwarding module is used to forward the interrupt signal received by the interrupt controller to the slave central processor according to the address signal sent by the master central processor when the master central processor in any cluster communicates with the slave central processor in other clusters.

[0030] Among them: BMC: Baseboard Management Controller

[0031] BIOS: Basic Input Output System

[0032] NC: Network Controller signal forwarding module

[0033] like Figure 2 A device architecture diagram of CPU interconnection interrupt forwarding in Embodiment 1 of the present invention is provided. There are multiple system architecture designs for multi-channel interconnection in this application. Figure 2 The architecture given is only an example, in which NC is a signal repeater. Since the cxl interface of the CPU cannot be directly connected to all other CPUs, it is generally transferred through an NC. NC can be regarded as a "transparent" bridge.

[0034] Figure 2There are 4 clusters listed in the table, each of which includes 4 CPUs, namely CPU0-CPU3. If the signal forwarder, namely NC, is not used to implement forwarding, based on the limitation of the 2500CPU itself, at most 4 CPUs can be directly connected locally. We regard these 4 CPUs as one cluster. For a 16-way system, there are a total of 4 clusters (0-3). Our ultimate goal is to hope that the 16 CPUs can recognize each other, but because the Phytium2500 CPU can only recognize 3 bits in affinity level 2, the CPU can recognize at most 8 system CPUs and can only recognize 3 bits of address at most. Therefore, it is impossible to directly specify the desired CPU when sending SGI, which will cause interrupt forwarding confusion. For example, Cpu0 in cluster0 wants to send an interrupt to cpu0 in Cluster1. The address it originally wants to send is 1000, but due to the limitation of the CPU address bit, it can only recognize the last three bits 000, and then an interrupt sending error will occur.

[0035] Therefore, in order to solve this problem, the CPU sends an address to the NC in advance before sending an interrupt request to the GIC. This address is the address of the CPU that the interrupt wants to go to. After receiving the address, the NC waits for the interrupt signal from the GIC to arrive, and then sends the interrupt signal to the corresponding CPU according to the address.

[0036] Before executing the interrupt signal forwarding, the signal forwarding module first determines whether the main central processor and the slave central processor are located in the same cluster, that is, whether Cpu0 in cluster0 and cpu0 in cluster1 are located in the same cluster. If CPU0 in cluster0 wants to forward the interrupt signal to Cpu1 or CPU3 in cluster0, that is, they are located in the same cluster, the interrupt controller is triggered to send an SGI interrupt signal, and an interrupt trigger is completed between the main central processor, that is, CPU0 in cluster0, and the slave central processors, that is, CPU1-CPU3 in cluster0;

[0037] If CPU0 in a different cluster, i.e., cluster0, wants to forward the interrupt signal to any CPU in cluster1-cluster3, it receives the address signal sent by CPU0 in the master central processor cluster0, sets the register, triggers the interrupt controller to send the SGI interrupt signal, and forwards the SGI interrupt signal received by the interrupt controller to the slave central processor, i.e., any CPU in cluster1-cluster3, according to the address signal, and resets the register.

[0038] In the present application, when the signal forwarding module receives the address signal sent by the main central processing unit, it locks the current address signal, and when the next address signal arrives, it unlocks the current address signal.

[0039] To ensure that the two messages are not interrupted, a lock needs to be added when the first address message is sent to the NC, locking the NC until the second interrupt message arrives, unlocking the NC to ensure that the integrity of an interrupt instruction is not destroyed. There are many ways to lock, and a register can be written to the NC at the same time as the first address message is sent, indicating that the NC knows that this address message needs to wait for the next message to be complete.

[0040] In the process of executing signal forwarding, the signal forwarding module enables the main central processor to obtain the CPU interconnection architecture by modifying the ACPI table in the input and output system.

[0041] Modifying the ACPI table includes modifying the system resource information, the multiple APIC description table, and the system local distance information table in the ACPI table.

[0042] How to let the CPU know its system architecture? This requires modifying the ACPI table (Advanced Configuration and Power Management Interface) in the BIOS, filling in false node and CPU information, and letting the CPU understand the entire system architecture. One goal can be achieved by modifying the srat (System Resource Table), madt (Multiple APIC Description Table), and slit (System Locality Distance Information Table) tables in the ACPI table. After modifying the ACPI table, the Linux kernel also needs to cooperate in modifying the corresponding content.

[0043] What needs to be modified in Linux is to uniformly map the false information reported in the acpi table to NC, so that when the CPU wants to communicate with these devices, it sends the information to NC, and NC then forwards the information to the corresponding device.

[0044] Among them, ACPI stands for Advanced Configuration and Power Management Interface;

[0045] srat (System Resource Table) system resource information;

[0046] madt (Multiple APIC Description Table) multiple APIC description table;

[0047] slit (System Locality Distance Information Table) system local distance information table.

[0048] Because the system configures device information through the ACPI table reported by the BIOS, and the OS only identifies the devices in the system through the ACPI information reported by the BIOS, the BIOS can report false information to make the OS think that these devices exist in the system.

[0049] The signal forwarding module adopts an editable logic chip, namely a single chip microcomputer, CPLD or FPGA.

[0050] Embodiment 1 of the present invention proposes a device for CPU interconnection interrupt forwarding, that is, an interrupt forwarding mechanism between CPUs in multi-chip interconnection, which ensures that multi-chip interconnection can be successfully realized in phytium cpu. It can realize the interconnection of 8 or more phytium2500cpus. If it is not used, only up to 8 phytium2500cpus can be used for interconnection. Similarly, this method can be used in other chip multi-way interconnection requirements, and can successfully realize multi-chip interconnection when the interrupt forwarding address is insufficient.

[0051] Example 2

[0052] Based on a CPU interconnection interrupt forwarding device proposed in Example 1 of the present invention, Example 2 of the present invention further proposes a CPU interconnection interrupt forwarding method. The device includes multiple clusters and several signal forwarding modules; each cluster includes multiple interconnected central processing units, and each central processing unit is connected to the nearest signal forwarding module; when it is determined that the main central processing unit and the slave central processing unit are located in different clusters and the main central processing unit wants to send an interrupt signal to the slave central processing unit, the interrupt signal received by the interrupt controller is forwarded to the slave central processing unit according to the address signal sent by the main central processing unit.

[0053] like Figure 3 This is a flow chart of a method for CPU interconnect interrupt forwarding according to embodiment 2 of the present invention.

[0054] In step S300, the current CPU needs to send an SGI interrupt signal to other CPUs, that is, the master central processor needs to send an SGI interrupt signal to other slave central processors.

[0055] In step S310, it is determined whether the current CPU and other CPUs, ie, the master CPU and the slave CPU, are in the same cluster. If the current CPU and other CPUs are in the same cluster, ie, the master CPU and the slave CPU are in the same cluster, step S350 is executed.

[0056] In step S320, the main CPU sends the destination address of the interrupt signal to be sent to the signal forwarding module and sets the register.

[0057] In step S330, the interrupt controller is triggered to send an SGI interrupt signal.

[0058] In step S340, the SGI interrupt signal reaches the signal forwarding module, which integrates the SGI interrupt signal and the address signal and sends the integrated signal to the destination address; that is, according to the address signal, the SGI interrupt signal received by the interrupt controller is forwarded to the slave central processor and the register is reset.

[0059] When the signal forwarding module receives the address signal sent by the main central processing unit, it locks the current address signal, and unlocks the current address signal when the next address signal arrives.

[0060] To ensure that the two messages are not interrupted, a lock needs to be added when the first address message is sent to the NC, locking the NC until the second interrupt message arrives, unlocking the NC to ensure that the integrity of an interrupt instruction is not destroyed. There are many ways to lock, and a register can be written to the NC at the same time as the first address message is sent, indicating that the NC knows that this address message needs to wait for the next message to be complete.

[0061] In the process of executing signal forwarding, the main central processor obtains the CPU interconnection architecture by modifying the ACPI table in the input and output system.

[0062] Modifying the ACPI table includes modifying the system resource information, the multiple APIC description table, and the system local distance information table in the ACPI table.

[0063] How to let the CPU know its system architecture? This requires modifying the ACPI table (Advanced Configuration and Power Management Interface) in the BIOS, filling in false node and CPU information, and letting the CPU understand the entire system architecture. One goal can be achieved by modifying the srat (System Resource Table), madt (Multiple APIC Description Table), and slit (System Locality Distance Information Table) tables in the ACPI table. After modifying the ACPI table, the Linux kernel also needs to cooperate in modifying the corresponding content.

[0064] What needs to be modified in Linux is to uniformly map the false information reported in the acpi table to NC, so that when the CPU wants to communicate with these devices, it sends the information to NC, and NC then forwards the information to the corresponding device.

[0065] Among them, ACPI stands for Advanced Configuration and Power Management Interface;

[0066] srat (System Resource Table) system resource information;

[0067] madt (Multiple APIC Description Table) multiple APIC description table;

[0068] slit (System Locality Distance Information Table) system local distance information table.

[0069] In step S350, the SGI is triggered to send an SGI interrupt signal.

[0070] In step S360, an interrupt trigger is completed.

[0071] A method for CPU interconnection interrupt forwarding proposed in Example 2 of the present invention, i.e., an interrupt forwarding mechanism between CPUs in multi-chip interconnection, ensures that multi-chip interconnection can be successfully realized in Phytium CPU. It can realize the interconnection of 8 or more Phytium2500CPUs. If it is not used, only up to 8 Phytium2500CPUs can be used for interconnection. Similarly, this method can be used in other chip multi-way interconnection requirements, and can successfully realize multi-chip interconnection when the interrupt forwarding address is insufficient.

[0072] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment that includes a series of elements are inherent to the elements. In the absence of more restrictions, the elements limited by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or equipment that includes the elements. In addition, the above-mentioned technical solution provided in the embodiment of the present application is consistent with the corresponding technical solution in the prior art in principle, and the part is not described in detail, so as not to repeat too much.

[0073] Although the above describes the specific implementation of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. For those skilled in the art, other different forms of modifications or deformations can be made on the basis of the above description. It is not necessary and impossible to list all the implementation methods here. On the basis of the technical solution of the present invention, various modifications or deformations that can be made by those skilled in the art without creative work are still within the scope of protection of the present invention.

Claims

1. A CPU interconnect interrupt forwarding device, characterized in that: include: It includes multiple clusters and several signal forwarding modules; each cluster includes multiple interconnected central processing units, and each central processing unit is connected to the nearest signal forwarding module; The signal forwarding module is used to forward the interrupt signal received by the interrupt controller to the slave central processor according to the address signal sent by the main central processor when it is determined that the main central processor and the slave central processor are located in different clusters and the main central processor intends to send an interrupt signal to the slave central processor; the signal forwarding module enables the main central processor to obtain the CPU interconnection architecture by modifying the ACPI table in the input and output system during the process of executing signal forwarding; Modifying the ACPI table includes modifying the system resource information, the multiple APIC description table and the system local distance information table in the ACPI table.

2. The device for CPU interconnection interrupt forwarding according to claim 1, characterized in that: Before executing the interrupt signal forwarding, the signal forwarding module first determines whether the master central processor and the slave central processor are located in the same cluster. If they are located in the same cluster, the interrupt controller is triggered to send an SGI interrupt signal, and an interrupt trigger is completed between the master central processor and the slave central processor; If they are located in different clusters, the address signal sent by the main CPU is received, and the register is set to trigger the interrupt controller to send an SGI interrupt signal. According to the address signal, the SGI interrupt signal received by the interrupt controller is forwarded to the slave CPU, and the register is reset.

3. The device for CPU interconnection interrupt forwarding according to claim 2, characterized in that: The signal forwarding module locks the current address signal when receiving the address signal sent by the main central processing unit, and unlocks the current address signal when the next address signal arrives.

4. A CPU interconnection interrupt forwarding device according to any one of claims 1 to 3, characterized in that: The signal forwarding module adopts an editable logic chip.

5. A method for CPU interconnection interrupt forwarding, which is implemented based on a CPU interconnection interrupt forwarding device according to any one of claims 1 to 4, characterized in that: Running in the signal forwarding module, including the following steps: Receive an address signal sent from the main central processing unit; If it is determined that the main central processor and the slave central processor to be forwarded are located in different clusters, the address signal sent by the main central processor is received, and the register is set to trigger the interrupt controller to send an SGI interrupt signal. According to the address signal, the SGI interrupt signal received from the interrupt controller is forwarded to the slave central processor, and the register is reset.

6. A method for CPU interconnection interrupt forwarding according to claim 5, characterized in that: The method further includes triggering the interrupt controller to send an SGI interrupt signal if it is determined that the main central processor and the slave central processor to be forwarded are located in the same cluster, and completing an interrupt trigger between the main central processor and the slave central processor.

7. A method for CPU interconnection interrupt forwarding according to claim 5, characterized in that: When receiving the address signal sent from the main central processing unit, the current address signal is locked, and when the next address signal arrives, the current address signal is unlocked.

8. A method for CPU interconnection interrupt forwarding according to claim 5, characterized in that: In the process of executing signal forwarding, the main central processing unit obtains the architecture of the CPU interconnection by modifying the ACPI table in the input and output system.

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