Multi-chip three-dimensional packaging structure and packaging method

Abstract

The invention relates to the technical field of chip packaging, and provides a multi-chip three-dimensional packaging structure and a packaging method. The packaging structure comprises a plurality of molding dielectric layers and a plurality of chip sets, the plurality of chip sets are respectively plastically packaged in the plurality of molding dielectric layers, and the plurality of chip sets are interconnected through plastically packaged through holes in the molding dielectric layers; the plurality of chips of the two adjacent chip sets are inversely arranged on the rewiring layer between the two adjacent molding dielectric layers; at least one of the two adjacent chip groups comprises a plurality of chips with high-speed interfaces and low-speed interfaces, the high-speed interfaces of the plurality of chips of the chip group are connected through an interconnection bridge, and the low-speed interfaces of the chips of the two adjacent chip groups are led out to the plastic package through hole through a rewiring layer between the two adjacent molding dielectric layers. According to the multi-chip three-dimensional packaging method, the interconnection bridge is adopted, and the packaging technology combining the plastic package through hole (TMV) and the rewiring layer (RDL) is used, so that the technical difficulty and the manufacturing cost of multi-chip three-dimensional packaging are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a multi-chip three-dimensional packaging structure and a packaging method. Background Art

[0002] Multi-chip module (MCM) system integration technology realizes 2D horizontal packaging on the packaging substrate through advanced flip-chip process. Its structure is limited by the size of the packaging substrate, and the interconnection path between chips is long, the transmission rate is limited, and the occupied area is large, making it difficult for the system to meet miniaturization requirements.

[0003] The existing 2.5D / 3D packaging technology mainly adopts the TSV (Through Silicon Via) vertical interconnection technology of passive and active silicon adapters, which can improve the interconnection density and reduce the package size. However, as the number of system chips and the pin density increase, the area of ​​the silicon adapter board is getting larger and larger, and the existing silicon adapter board adopts the wafer-level manufacturing process, which limits the size of the chip and still has the problem of large package size. In the prior art, the 2.5D packaging realized by the silicon adapter board requires the silicon adapter board to use the TSV process to realize the electrical interconnection between multiple bare chips, and it is necessary to etch and then implant the silicon adapter board in the packaging substrate. The implantation groove processing accuracy of the silicon adapter board is extremely high, and the TSV process technology is difficult and costly. Summary of the invention

[0004] In order to solve the above technical defects, the present invention provides a multi-chip three-dimensional packaging structure and a packaging method.

[0005] On one hand, the present invention provides a multi-chip three-dimensional packaging structure, comprising a plurality of molded dielectric layers and a plurality of chip groups, wherein the plurality of chip groups are respectively plastic-encapsulated in the plurality of molded dielectric layers, and the plurality of chip groups are interconnected through plastic-encapsulated through holes in the molded dielectric layers;

[0006] Multiple chips of two adjacent chip groups are flip-chip mounted on a redistribution layer between two adjacent molding dielectric layers;

[0007] At least one of the two adjacent chipsets includes multiple chips with high-speed interfaces and low-speed interfaces. The high-speed interfaces of the multiple chips in the chipset are connected through an interconnection bridge, and the low-speed interface of each chip in the two adjacent chipsets is led out to the plastic encapsulation through hole through a rewiring layer between two adjacent molding dielectric layers.

[0008] In the embodiment of the present invention, two adjacent molding dielectric layers and the chip groups in two adjacent molding dielectric layers serve as a stacked plastic encapsulation unit, and two adjacent stacked plastic encapsulation units are connected via metal solder balls.

[0009] In the embodiment of the present invention, chip groups located in different molding medium layers in the same stacked molding unit are vertically interconnected through molding through holes.

[0010] In the embodiment of the present invention, the high-speed interfaces of the chips in the upper molding dielectric layer in the same stacked plastic encapsulation unit are connected via the interconnection bridges in the lower molding dielectric layer.

[0011] In the embodiment of the present invention, the chips in two adjacent molding medium layers in the same stacked plastic packaging unit are connected face to face via metal welding points.

[0012] In the embodiment of the present invention, the material of the interconnection bridge is the same as the semiconductor material of the chip.

[0013] Another aspect of the present invention provides a multi-chip three-dimensional packaging method, comprising:

[0014] Plastic-encapsulating the two chip groups in two molding dielectric layers to form a laminated plastic-encapsulated unit;

[0015] Interconnecting multiple stacked plastic-encapsulated units and encapsulating them into one;

[0016] The two chipsets are encapsulated in two molding medium layers, including:

[0017] Providing a first temporary carrier, and forming a first redistribution layer on a surface of the first temporary carrier;

[0018] Flip-chip connecting the first chip set to the first redistribution layer;

[0019] Plastic-sealing the first chipset to form a first molding dielectric layer;

[0020] Forming a first plastic sealing through hole in the first molded dielectric layer, and forming a second redistribution layer on the upper surface of the first molded dielectric layer;

[0021] removing the first temporary carrier to expose the first redistribution layer;

[0022] Providing a second temporary carrier, and attaching a second redistribution layer to a surface of the second temporary carrier;

[0023] Flip-mounting the second chipset and the interconnection bridge on the first rewiring layer, so that the high-speed interfaces of the chips in the first chipset and the second chipset are connected to the interconnection bridge, and the low-speed interfaces of the chips in the first chipset and the second chipset are connected to the first rewiring layer;

[0024] Plastic-sealing the second chip group to form a second molding dielectric layer;

[0025] A second plastic encapsulation through hole connected to the first redistribution layer is formed in the second molded dielectric layer to achieve interconnection between the chipset in the first molded dielectric layer and the chipset in the second molded dielectric layer.

[0026] In an embodiment of the present invention, forming a first redistribution layer on a surface of a first temporary carrier includes:

[0027] A seed layer is formed on the surface of the first temporary carrier, and a first redistribution layer is formed on the surface of the seed layer.

[0028] In an embodiment of the present invention, a second redistribution layer is formed on the upper surface of the first molding dielectric layer, including:

[0029] Forming a conductive metal layer on the upper surface of the first molding dielectric layer by an electroplating process;

[0030] The conductive metal layer is etched to form a second redistribution layer.

[0031] In an embodiment of the present invention, a plurality of stacked plastic-encapsulated units are interconnected and packaged as one, including:

[0032] Forming solder balls between the rewiring layers of the plurality of stacked plastic encapsulation units to interconnect the plurality of stacked plastic encapsulation units;

[0033] The interconnected multiple stacked plastic encapsulation units are encapsulated into one.

[0034] The present invention adopts a multi-layer molded dielectric layer to stack and package multiple chipsets, and realizes the interconnection of chipsets through the rewiring layer between the molded dielectric layers and the plastic sealing through holes in the molded dielectric layers. Compared with the 2.5D / 3D packaging using TSV, the process technology difficulty and manufacturing cost are reduced; the present invention realizes the interconnection between the high-speed interfaces of multiple chips in the chipset through the interconnection bridge, and realizes the interconnection and lead-out of the low-speed interfaces of chips of different chipsets through the rewiring layer and the plastic sealing through hole, that is, the interconnection of high-speed signals between chips is realized through the interconnection bridge, and the interconnection of low-speed signals is realized through the rewiring layer, so as to ensure the high-quality signal transmission requirements (improve the overall yield of the package), and at the same time reduce the number (area) of interconnection bridges, thereby reducing the overall area of ​​the package body and saving costs.

[0035] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0037] Figure 1Schematic diagram of a multi-chip three-dimensional packaging structure (vertically stacked) provided in Embodiment 1 of the present invention;

[0038] Figure 2 is a schematic diagram of a multi-chip three-dimensional packaging structure (without stacking in the vertical direction) provided in Embodiment 2 of the present invention;

[0039] Figure 3 is a flow chart of a multi-chip three-dimensional packaging method provided by a specific embodiment of the present invention;

[0040] Figures 4a to 4j It is a schematic diagram of a structure formed by various steps of a multi-chip three-dimensional packaging method provided by a specific embodiment of the present invention.

[0041] Description of Reference Numerals

[0042] 1-first chip, 2-second chip, 3-third chip, 4-fourth chip, 5-interconnection bridge,

[0043] 6-first molding dielectric layer, 7-second molding dielectric layer, 8-metal solder joint,

[0044] 9-second plastic sealing through hole, 10-first plastic sealing through hole, 11-second redistribution layer,

[0045] 12 - first redistribution layer, 13 - third redistribution layer, 14 - metal solder balls. DETAILED DESCRIPTION

[0046] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0047] In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. The terms "first", "second", and "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0048] In the present invention, unless otherwise clearly specified and limited, the terms such as "interconnection", "connection", "connection" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] In the process of realizing the present invention, the inventors found that the existing 2.5D / 3D packaging technology mainly adopts the TSV (Through Silicon Via) vertical interconnection technology of passive and active silicon adapters. However, as the number of system chips and the pin density increase, the area of ​​the silicon adapter required is getting larger and larger. The existing silicon adapter adopts the wafer-level manufacturing process, which limits the size of the chip and still has the problem of large package size. With the help of the 2.5D packaging realized by the silicon adapter, the silicon adapter needs to use the TSV process to realize the electrical interconnection between multiple bare chips. It is necessary to etch and then implant the silicon adapter in the packaging substrate. The implantation groove processing accuracy of the silicon adapter is extremely high, and the TSV process technology is difficult and costly.

[0050] In view of the above problems, an embodiment of the present invention provides a multi-chip three-dimensional packaging structure, including multiple molding dielectric layers and multiple chipsets, wherein the multiple chipsets are respectively molded in the multiple molding dielectric layers, and the multiple chipsets are interconnected through molding through holes (Through molding via, referred to as TMV) in the molding dielectric layers; multiple chips of two adjacent chipsets are flipped on a redistribution layer (Re Distribution Layer, referred to as RDL) between two adjacent molding dielectric layers; at least one chipset of the two adjacent chipsets includes multiple chips with high-speed interfaces and low-speed interfaces, the high-speed interfaces of the multiple chips of the chipset are connected through an interconnection bridge, and the low-speed interface of each chip in the two adjacent chipsets is led out to the molding through hole through the redistribution layer between two adjacent molding dielectric layers.

[0051] The present invention adopts a multi-layer molded dielectric layer to stack and package multiple chipsets, and realizes the interconnection of chipsets through the rewiring layer between the molded dielectric layers and the plastic sealing through holes in the molded dielectric layers. Compared with the 2.5D / 3D packaging using TSV, the process technology difficulty and manufacturing cost are reduced; the present invention realizes the interconnection between the high-speed interfaces of multiple chips in the chipset through the interconnection bridge, and realizes the interconnection and lead-out of the low-speed interfaces of chips of different chipsets through the rewiring layer and the plastic sealing through hole, that is, the interconnection of high-speed signals between chips is realized through the interconnection bridge, and the interconnection of low-speed signals is realized through the rewiring layer, so as to ensure the high-quality signal transmission requirements (improve the overall yield of the package), and at the same time reduce the number (area) of interconnection bridges, thereby reducing the overall area of ​​the package body and saving costs.

[0052] Embodiment 1

[0053] Figure 1 Schematic diagram of a multi-chip three-dimensional packaging structure (vertically stacked) provided in this embodiment. Figure 1 As shown, in this embodiment, two adjacent molded dielectric layers and the chip group in the molded dielectric layer serve as a stacked plastic encapsulation unit. Figure 1 Three stacked plastic encapsulation units are shown (the embodiment of the present invention is not limited to the packaging of three stacked plastic encapsulation units), and two adjacent stacked plastic encapsulation units are connected by metal solder balls 14, and the empty space around the metal solder balls 14 can be filled with glue. A stacked plastic encapsulation unit has two molded dielectric layers and two chip groups, and the two chip groups are respectively plastic encapsulated in the two molded dielectric layers. Different chip groups are interconnected through plastic encapsulation through holes in the molded dielectric layers and metal solder balls between the stacked plastic encapsulation units. Chip groups located in different molded dielectric layers (6, 7) in the same stacked plastic encapsulation unit are vertically interconnected through plastic encapsulation through holes (9, 10). Multiple chips in the same stacked plastic encapsulation unit are flip-chip mounted on the first rewiring layer 12 between two adjacent molded dielectric layers.

[0054] Reference Figure 1 Taking the bottom layer of the stacked plastic encapsulation unit as an example, the first chip 1 and the second chip 2 are used as a chipset, and the first chip 1 and the second chip 2 are connected through an interconnection bridge 5. The third chip 3 and the fourth chip 4 are used as another chipset, and the first chip 1 and the second chip 2 and the interconnection bridge 5 are stacked on the third chip 3 and the fourth chip 4. The chips in the two chipsets are connected to each other, the first chip 1 is set on the third chip 3, and the second chip 2 is set on the fourth chip 4. The first chip 1 is connected to the third chip 3 through a metal solder joint, and the second chip 2 is connected to the fourth chip 4 through a metal solder joint 8. The first chip 1 and the second chip 2 are chips with high-speed interfaces (such as I / O interfaces) and low-speed interfaces (including power pins), and the third chip 3 and the fourth chip 4 only have low-speed interfaces. The high-speed interface of the first chip 1 is connected to the high-speed interface of the second chip 2 through the interconnection bridge 5, and the low-speed interfaces of the first chip 1, the second chip 2, the third chip 3 and the fourth chip 4 are led out to the plastic encapsulation through holes (9, 10) through the first rewiring layer 12 between two adjacent molding dielectric layers.

[0055] In this embodiment, the chip groups located in different molding dielectric layers in the same stacked molding unit are vertically interconnected through molding through holes; the chips in two adjacent molding dielectric layers in the same stacked molding unit are connected face to face through metal welding; the high-speed interface of the chip in the upper molding dielectric layer in the same stacked molding unit is connected through an interconnection bridge in the lower molding dielectric layer, which can save the space and area occupied by the interconnection bridge.

[0056] In a specific embodiment, the pins of all chips in the chipset pass through the molded dielectric layer and are connected to the external PCB circuit board in the form of solder balls at the bottom of the molded dielectric layer. For example, the pins of the first chip 1 and the second chip 2 are led out through the first molded dielectric layer 6, and the pins of the third chip 3 and the fourth chip 4 are led out through the second molded dielectric layer 7, and specifically can be led out through the first plastic sealing through hole 10 and the second plastic sealing through hole 9.

[0057] In a specific embodiment, the first chip 1 is interconnected with the third chip 3 through the metal solder joint 8 and / or the first rewiring layer 12. The second chip 2 is interconnected with the fourth chip 4 through the metal solder joint 8 and / or the first rewiring layer 12 (the empty space around the metal solder joint 8 can be filled with glue). The first rewiring layer 12 below the interconnection bridge 5 can also be used for interconnection wiring between two groups of chips, providing an interconnection path for chips with more pins. The low-speed / power pins of the first chip 1 and the second chip 2 are led out through the first rewiring layer 12, and then led out to the upper and lower sides of the package through the plastic through hole TMV, and vertically interconnected with other stacked chip groups through the metal solder ball 14. After a part of the low-speed / power pins of the third chip 3 and the fourth chip 4 are redistributed on the first chip 1 and the second chip 2, they are connected to the metal solder ball 14 through the plastic through hole (TMV) and the rewiring layer (RDL). The metal solder ball 14 can be a tin-lead solder ball, a tin-silver-copper solder ball, etc.

[0058] In this embodiment, the material of the molded dielectric layer may be an epoxy molding compound. The molded dielectric layer can fix the chipset in the absence of a packaging substrate and protect the chips.

[0059] In this embodiment, the interconnection bridge 5 corresponds to the solder joints of the first chip 1 and the second chip 2 one by one. There is no need to use the substrate of the prior art, dig a cavity on the substrate to embed the silicon bridge, and there is no need to realize the pin fan-out through the vias manufactured by the substrate process. Therefore, the package integration density of the present invention does not depend on the substrate process. The present invention not only reduces the difficulty of process manufacturing, but also the interconnection between the upper chips depends entirely on the silicon bridge, which ensures the interconnection density and transmission rate between chips. In a preferred embodiment, the material of the interconnection bridge 5 is the same as the semiconductor material of the chip, and a high-performance, high-integration density silicon-based adapter board or glass-based adapter board can be used. Since the material of the interconnection bridge is the same as the semiconductor material of the chip, the CTE (coefficient of thermal expansion) of the interconnection bridge and the chip is consistent, which reduces the reliability problem between layers.

[0060] The embodiment of the present invention adopts an interconnection bridge and uses a packaging process combining a through-molded via (TMV) and a redistribution layer (RDL), which reduces the technical difficulty and manufacturing cost of multi-chip three-dimensional packaging. In addition, the present invention combines the advantages of EMIB, 3D packaging and Fan-out packaging, reduces the size, increases the interconnection density, and reduces the packaging process difficulty of the interconnection bridge.

[0061] Embodiment 2

[0062] Figure 2 Schematic diagram of a multi-chip three-dimensional packaging structure (no stacking in the vertical direction) provided in this embodiment. Figure 2As shown, in this embodiment, two adjacent molded dielectric layers and the chipset in the molded dielectric layer serve as a stacked plastic encapsulation unit, and there is no further stacked chipset in the vertical direction of the stacked plastic encapsulation unit. The first chip 1 and the second chip 2 are connected by an interconnection bridge 5, and the third chip 3 and the fourth chip 4 serve as another chipset. The first chip 1 and the second chip 2 and the interconnection bridge 5 are stacked on the third chip 3 and the fourth chip 4. The chips in the two chipsets are connected to each other, the first chip 1 is arranged on the third chip 3, and the second chip 2 is arranged on the fourth chip 4. The first chip 1 is connected to the third chip 3 through a metal solder joint, and the second chip 2 is connected to the fourth chip 4 through a metal solder joint 8. The first chip 1 and the second chip 2 are chips with high-speed interfaces (such as I / O interfaces) and low-speed interfaces (including power pins), and the third chip 3 and the fourth chip 4 only have low-speed interfaces. The high-speed interface of the first chip 1 is connected to the high-speed interface of the second chip 2 through an interconnection bridge 5, and the low-speed interfaces of the first chip 1, the second chip 2, the third chip 3 and the fourth chip 4 are led out to the second plastic encapsulation through hole 9 through the first redistribution layer 12 between two adjacent molding dielectric layers.

[0063] In this embodiment, there is only one stacked plastic encapsulation unit, and only TMV and RDL need to be made in the lower package body. The low-speed / power pins of the first chip 1 and the second chip 2 are directly led out from the second plastic encapsulation through hole 9 to the third redistribution layer 13 and the metal solder ball 14 to achieve vertical interconnection with the outside world. The multi-chip three-dimensional packaging structure provided by this embodiment has a simpler overall process.

[0064] The embodiment of the present invention also provides a packaging method corresponding to the above-mentioned multi-chip three-dimensional packaging structure, which includes: plastic-sealing two chip groups in two molding medium layers to form a stacked plastic-sealed unit; interconnecting multiple stacked plastic-sealed units and packaging them into one.

[0065] The two chipsets are encapsulated in two molding dielectric layers, specifically including:

[0066] Providing a first temporary carrier, and forming a first redistribution layer on a surface of the first temporary carrier;

[0067] Flip-chip connecting the first chip set to the first redistribution layer;

[0068] Plastic-sealing the first chipset to form a first molding dielectric layer;

[0069] Forming a first plastic sealing through hole in the first molded dielectric layer, and forming a second redistribution layer on the upper surface of the first molded dielectric layer;

[0070] removing the first temporary carrier to expose the first redistribution layer;

[0071] Providing a second temporary carrier, and attaching a second redistribution layer to a surface of the second temporary carrier;

[0072] Flip-mounting the second chipset and the interconnection bridge on the first rewiring layer, so that the high-speed interfaces of the chips in the first chipset and the second chipset are connected to the interconnection bridge, and the low-speed interfaces of the chips in the first chipset and the second chipset are connected to the first rewiring layer;

[0073] Plastic-sealing the second chip group to form a second molding dielectric layer;

[0074] A second plastic encapsulation through hole connected to the first redistribution layer is formed in the second molded dielectric layer to achieve interconnection between the chipset in the first molded dielectric layer and the chipset in the second molded dielectric layer.

[0075] In the above method, forming a first redistribution layer on the surface of the first temporary carrier specifically includes:

[0076] A seed layer is formed on the surface of the first temporary carrier, and a first redistribution layer is formed on the surface of the seed layer.

[0077] In the above method, forming a second redistribution layer on the upper surface of the first molding dielectric layer specifically includes:

[0078] A conductive metal layer is formed on the upper surface of the first molded dielectric layer by adopting an electroplating process, and the conductive metal layer is etched to form a second rewiring layer.

[0079] In the above method, a plurality of stacked plastic-encapsulated units are interconnected and packaged into one, which specifically includes:

[0080] Solder balls are formed between the rewiring layers of the plurality of stacked plastic-encapsulated units to realize the interconnection of the plurality of stacked plastic-encapsulated units and to package the interconnected plurality of stacked plastic-encapsulated units into one.

[0081] like Figure 3 As shown, a multi-chip three-dimensional packaging method provided by a specific embodiment of the present invention includes the following steps:

[0082] 1. preparing a first redistribution layer on a first temporary carrier with a seed layer;

[0083] 2. Flip-chip soldering the first layer of bare chips to the first redistribution layer on the first temporary carrier;

[0084] 3. Plastic-sealing one side of the first layer of bare chips on the first temporary carrier to form a first molding medium;

[0085] 4. Fabricate TMV in the first molding medium and fabricate a second redistribution layer on the upper surface;

[0086] 5. removing the first temporary carrier and exposing the first redistribution layer;

[0087] 6. Turning over the first molding medium, and attaching the side with the second redistribution layer to the second temporary carrier;

[0088] 7. Flip-chip soldering of the second layer bare chip and interconnect bridge to the second redistribution layer, and bottom filling;

[0089] 8. Plastic encapsulating the second layer of bare chips to form a second molding medium;

[0090] 9. Fabricating TMV on the second molding medium and fabricating a third redistribution layer on the upper surface;

[0091] 10. Remove the second temporary carrier plate;

[0092] 11. Ball planting is performed on the surfaces of the first redistribution layer and the third redistribution layer to form a package.

[0093] Figures 4a to 4j The structure diagram of each step of the multi-chip three-dimensional packaging method provided by a specific embodiment of the present invention is formed. Since the chip heights are inconsistent and the solder joint sizes are also different, this method uses a two-time plastic packaging process and combines the Fan-out RDL first process to reduce the difficulty of assembly. Figure 3 and Figures 4a-4j The steps in this method are:

[0094] A seed layer is formed on a temporary carrier, and a first redistribution layer 12 is formed on the surface of the seed layer. Figure 4a The structure shown;

[0095] The first chip 1 and the second chip 2 are flipped onto the first rewiring layer 12, the low-speed pins and the power ground of the first chip 1 and the second chip 2 are led out, and part of the signal interconnection between the first chip 1 and the second chip 2 is realized through the first rewiring layer 12, so as to form a Figure 4b The structure shown;

[0096] Fill the first molding dielectric layer 6, and perform plastic sealing on the first layer chip and the rewiring layer to form a Figure 4c The structure shown;

[0097] exist Figure 4c The first plastic sealing through hole 10 and the second rewiring layer 11 are made on the structure shown in the figure, the temporary carrier is removed, and the second rewiring layer 11 is exposed by grinding to form the structure shown in the figure. Figure 4d and 4e The structure shown;

[0098] A side of the second rewiring layer 11 is attached to a newly provided temporary carrier, and the second chip group and the interconnection bridge 5 are flip-chip soldered to the second rewiring layer; the second chip group is plastic-encapsulated to form a second molded dielectric layer 7; a plastic-encapsulated through hole is made on the second molded dielectric layer, and a third rewiring layer 13 is made on the upper surface; the upper package body is turned upside down and temporarily bonded again to expose the pins of the first chip 1 and the second chip 2 and the first rewiring layer 12, so as to form a Figure 4f The structure shown;

[0099] The third chip 3, the fourth chip 4 and the interconnection bridge 5 are welded to the corresponding pads of the first chip 1 and the second chip 2 through the metal welding point 8 to form a Figure 4g The structure shown;

[0100] Fill the solder joints with glue to protect the metal solder joints, and fill the second molding dielectric layer 7 through the molding process to protect the lower package body, forming a Figure 4h The structure shown;

[0101] A second plastic sealing through hole 9 and a third rewiring layer 13 are made in the lower package body to realize vertical interconnection of signals, forming a Figure 4i The structure shown;

[0102] Remove the temporary carrier, and plant metal solder balls 14 on the upper and lower sides of the package to form Figure 4j The structure shown.

[0103] The material of the temporary carrier plate can be silicon, glass, metal, etc. The first rewiring layer can be made by electroplating followed by etching. The plastic encapsulation material can be selected from plastic encapsulation materials with different properties according to the product characteristics. The second rewiring layer can be made in the same way as the first rewiring layer.

[0104] The interconnection bridge is one of a silicon adapter board, a glass adapter board, and a silicon wafer. Multiple chip sets are connected through a rewiring layer and / or solder joints. The method for removing the temporary carrier is one of laser debonding, mechanical debonding, and chemical debonding; the method for making plastic sealing through holes is mechanical drilling, laser opening, and electroplating.

[0105] In the above method, according to the form of the product after packaging, the upper, lower and double-sided solder balls can be realized. For POP packaging, the pins of the upper and lower bare chips can be fanned out from the rewiring layer and TMV in the upper and lower molding media respectively; for BGA packaging, the upper or lower fan-out of the pins of the bare chip can be realized in the upper or lower molding media.

[0106] The present invention provides a novel three-dimensional packaging method based on interconnection bridges, which combines the advantages of EMIB and 3D packaging, reduces the size, increases the interconnection density, and reduces the packaging process of the interconnection bridge. On the basis of using the interconnection bridge, the method also utilizes the Z-direction (vertical) space, increases the integration density, and reduces the external input and output interfaces.

[0107] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A multi-chip three-dimensional packaging structure, characterized in that: include: A plurality of molded dielectric layers and a plurality of chip groups, wherein the plurality of chip groups are respectively plastic-encapsulated in the plurality of molded dielectric layers, and the plurality of chip groups are interconnected through plastic-encapsulated through holes in the molded dielectric layers; Multiple chips of two adjacent chip groups are flip-chip mounted on a redistribution layer between two adjacent molding dielectric layers; At least one of the two adjacent chipsets includes a plurality of chips having high-speed interfaces and low-speed interfaces, and the high-speed interfaces of the plurality of chips in the chipset are connected via an interconnection bridge; The low-speed interface of each chip in two adjacent chip groups is led out to the plastic package through hole through the rewiring layer between two adjacent molding dielectric layers.

2. The multi-chip three-dimensional packaging structure according to claim 1, characterized in that: Two adjacent molding dielectric layers and the chip groups in the two adjacent molding dielectric layers serve as a stacked plastic encapsulation unit, and two adjacent stacked plastic encapsulation units are connected via metal solder balls.

3. The multi-chip three-dimensional packaging structure according to claim 2, characterized in that: Chip groups located in different molding medium layers in the same stacked plastic packaging unit are vertically interconnected through plastic packaging through holes.

4. The multi-chip three-dimensional packaging structure according to claim 2, characterized in that: The high-speed interfaces of the chips in the upper molding dielectric layer in the same stacked plastic encapsulation unit are connected via interconnection bridges in the lower molding dielectric layer.

5. The multi-chip three-dimensional packaging structure according to claim 2, characterized in that: The chips in two adjacent molding medium layers in the same stacked plastic packaging unit are connected face to face via metal solder joints.

6. The multi-chip three-dimensional packaging structure according to claim 1, characterized in that: The material of the interconnection bridge is the same as the semiconductor material of the chip.

7. A multi-chip three-dimensional packaging method, characterized in that: include: Plastic-encapsulating the two chip groups in two molding dielectric layers to form a laminated plastic-encapsulated unit; Interconnecting multiple stacked plastic-encapsulated units and encapsulating them into one; The two chipsets are encapsulated in two molding medium layers, including: Providing a first temporary carrier, and forming a first redistribution layer on a surface of the first temporary carrier; Flip-chip connecting the first chip set to the first redistribution layer; Plastic-sealing the first chipset to form a first molding dielectric layer; Forming a first plastic sealing through hole in the first molded dielectric layer, and forming a second redistribution layer on the upper surface of the first molded dielectric layer; removing the first temporary carrier to expose the first redistribution layer; Providing a second temporary carrier, and attaching a second redistribution layer to a surface of the second temporary carrier; Flip-mounting the second chipset and the interconnection bridge on the first rewiring layer, so that the high-speed interfaces of the chips in the first chipset and the second chipset are connected to the interconnection bridge, and the low-speed interfaces of the chips in the first chipset and the second chipset are connected to the first rewiring layer; Plastic-sealing the second chip group to form a second molding dielectric layer; A second plastic encapsulation through hole connected to the first redistribution layer is formed in the second molded dielectric layer to achieve interconnection between the chipset in the first molded dielectric layer and the chipset in the second molded dielectric layer.

8. The multi-chip three-dimensional packaging method according to claim 7, characterized in that: The forming of the first rewiring layer on the surface of the first temporary carrier comprises: A seed layer is formed on the surface of the first temporary carrier, and a first redistribution layer is formed on the surface of the seed layer.

9. The multi-chip three-dimensional packaging method according to claim 7, characterized in that: The forming of a second redistribution layer on the upper surface of the first molding dielectric layer comprises: Forming a conductive metal layer on the upper surface of the first molding dielectric layer by an electroplating process; The conductive metal layer is etched to form a second redistribution layer.

10. The multi-chip three-dimensional packaging method according to claim 7, characterized in that: The method of interconnecting a plurality of stacked plastic-encapsulated units and encapsulating them into one body comprises: Forming solder balls between the rewiring layers of the plurality of stacked plastic encapsulation units to interconnect the plurality of stacked plastic encapsulation units; The interconnected multiple stacked plastic encapsulation units are encapsulated into one.

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