Method for manufacturing zero-layer interlayer film
By performing back-engraving and chemical mechanical grinding processes on the zero-layer interlayer film in semiconductor integrated circuit manufacturing, the butterfly defect problem is solved, the grinding time and residual risk are reduced, and the product yield and process window are improved.
Patent Information
- Application Number
- CN202210187307.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-02-28
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2042-02-28
AI Technical Summary
In semiconductor integrated circuit manufacturing, the butterfly defect of the zero-layer interlayer film affects the subsequent process, resulting in a decrease in metal residue and product yield.
By performing a back engraving process on the top of the hard mask layer of the zero-layer interlayer film, a second depression is formed, and in the first chemical mechanical grinding process, the zero-layer interlayer film is planarized with the hard mask layer as the stop layer.
The time of the first chemical mechanical grinding process is reduced, the zero-layer interlayer film residue on the surface of the hard mask layer is avoided, butterfly defects are eliminated, and product yield and process window are improved.
Smart Images
Figure CN114695098B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a zeroth interlayer film (ILD0). Background Art
[0002] At advanced process nodes, especially below 14nm, the butterfly defect (dishing) of the oxide layer (oxide) after the chemical mechanical polishing (CMP) of ILD0, that is, the zero-layer interlayer film, has become a bottleneck in the subsequent process. The dishing of CMP mainly comes from the recess formed by the deposition of the oxide layer of the zero-layer interlayer film and the loading of the grinding rate of different materials of CMP itself. The loading of the grinding rate is also the different grinding rates of CMP for different materials.
[0003] like Figure 1A to Figure 1B , which is a device structure diagram in each step of the method for manufacturing the zero-th interlayer film according to an embodiment of the present invention; the method for manufacturing the zero-th interlayer film according to an embodiment of the present invention comprises the following steps:
[0004] Step 1: Figure 1A As shown, a semiconductor substrate 103 is provided, and a plurality of first gate structures 104 formed by stacking a first gate dielectric layer and a polysilicon gate are formed on the surface of the semiconductor substrate 103 . Figure 1A In the figure, the first gate dielectric layer and the polysilicon gate are not separately marked.
[0005] The formation area of the first gate structure 104 is defined by a hard mask layer 105 , and the hard mask layer 105 is further stacked on top of the polysilicon gate of the first gate structure 104 .
[0006] The area between the first gate structures 104 is a spacing area.
[0007] Usually, the same semiconductor substrate 103 also includes different device regions. Figure 1A The width and spacing in the middle region 101 are smaller than the width and spacing of the first gate structure 104 in the region 102. The region 101 can be a core device region, and the region 102 can be an input-output (IO) device region.
[0008] Step 2: Figure 1A As shown, a zero-layer interlayer film 106 is grown, and the zero-layer interlayer film 106 completely fills the spacer and extends above the top surface of the hard mask layer 105; the zero-layer interlayer film 106 has an uneven top surface and a recess 107 on the top of the spacer. Figure 1AAs shown, the size of the recess 107 formed in the region 102 is larger.
[0009] Step 3: Figure 1B As shown, the hard mask layer 105 is used as a stop layer, and a chemical mechanical polishing process is adopted to planarize the zero-layer interlayer film 106, so that the top surface of the zero-layer interlayer film 106 is flush with the top surface of the hard mask layer 105 and the zero-layer interlayer film 106 above the top surface of the hard mask layer 105 is completely removed.
[0010] However, in the existing method, a butterfly defect 108 is easily formed after the chemical mechanical polishing process is completed. The reasons for the formation of the butterfly defect 108 include two:
[0011] The first one is the depression 107 , which causes the depression to shift downward, thereby forming the butterfly defect 108 .
[0012] The second is that the chemical mechanical polishing process has different polishing rates for the zero-layer interlayer film 106 and the hard mask layer 105, that is, the polishing loads are different; when the polishing stops on the surface of the hard mask layer 105, in order to completely remove the residue of the zero-layer interlayer film 106 on the surface of the hard mask layer 105, the polishing time will inevitably be increased, so that the zero-layer interlayer film 106 in the spacing area will be further polished, thereby generating the butterfly defect 108.
[0013] When the butterfly defect 108 exists, metal residue will be generated in the butterfly defect 108 in the subsequent metal process, which will eventually cause a short circuit in the line after the metal contact hole process, directly affecting the product yield.
[0014] Existing methods for improving oxide dishing include the following two methods:
[0015] The first method is to increase the oxide deposition, that is, to increase the thickness of the zeroth interlayer film, which can improve Figure 1A The structure of the recess 107 in FIG.
[0016] The second method is to reduce the CMP time, that is, to reduce CMP grinding.
[0017] Although the above two methods can improve oxide dishing to a limited extent, they also bring many side effects, such as:
[0018] The first method will lead to an increase in the CMP polishing time, which will reduce the benefit of thickening the zero-th interlayer film.
[0019] In the second method, less CMP polishing will reduce the window of oxide residue on the SiN, ie, hard mask layer, resulting in the generation of polysilicon residue (dummy poly remove poly residue) during the subsequent polysilicon dummy gate removal. Summary of the invention
[0020] The technical problem to be solved by the present invention is to provide a method for manufacturing a zero-layer interlayer film, which can eliminate butterfly defects on the surface of the zero-layer interlayer film and thereby prevent metal from remaining in the butterfly defects, thereby improving product yield; it can also simultaneously reduce the residue of the zero-layer interlayer film material on the surface of the hard mask layer on the top of the polysilicon gate and simultaneously reduce the grinding time, thereby improving the process window.
[0021] In order to solve the above technical problems, the present invention provides a method for manufacturing a zero-layer interlayer film, comprising the following steps:
[0022] Step 1: provide a semiconductor substrate, and form a plurality of first gate structures formed by stacking a first gate dielectric layer and a polysilicon gate on a surface of the semiconductor substrate.
[0023] The formation area of the first gate structure is defined by a hard mask layer, and the hard mask layer is also stacked on top of the polysilicon gate of the first gate structure.
[0024] The area between the first gate structures is a spacing area.
[0025] Step 2: growing a zeroth interlayer film, wherein the zeroth interlayer film completely fills the spacer and extends above the top surface of the hard mask layer; the zeroth interlayer film has an uneven top surface and a first recess at the top of the spacer.
[0026] Step three, etching back the zeroth interlayer film on the top of the hard mask layer to form a second recess, wherein the bottom surface of the second recess is lower than the bottom surface of the first recess.
[0027] Step 4: Using the hard mask layer as a stop layer, adopt a first chemical mechanical polishing process to planarize the zeroth layer interlayer film, so that the top surface of the zeroth layer interlayer film is flush with the top surface of the hard mask layer and the zeroth layer interlayer film above the top surface of the hard mask layer is completely removed.
[0028] A further improvement is that the sub-steps of step 1 forming the first gate structure include:
[0029] Step 11: sequentially forming the first gate dielectric layer and the polysilicon gate on the surface of the semiconductor substrate.
[0030] Step 12: forming a hard mask layer on the surface of the polysilicon gate.
[0031] Step 13: photolithography is used to define a formation area of the first gate structure, and the hard mask layer, the polysilicon gate and the first gate dielectric layer are sequentially etched to form a plurality of the first gate structures.
[0032] A further improvement is that the sub-step of forming the first gate structure in step 1 further includes:
[0033] Step 14: forming sidewalls on the sides of each of the first gate structures.
[0034] A further improvement is that the hard mask layer is a nitride layer or a stacked layer of an oxide layer and a nitride layer.
[0035] A further improvement is that the material of the sidewall spacer includes an oxide layer or a nitride layer.
[0036] A further improvement is that before performing step 2, the following steps are also included:
[0037] A contact hole etch stop layer composed of a nitride layer is formed, and the contact hole etch stop layer covers the surface of the hard mask layer on the top of the gate, the side of the sidewall and the surface of the semiconductor substrate in the spacer.
[0038] A further improvement is that before performing step three, the method further includes using a second chemical mechanical polishing process to rough grind the zeroth interlayer film to increase the flatness of the top surface of the zeroth interlayer film and reduce the depth of the first recess.
[0039] A further improvement is that, in step three, the second recess is located directly above the first gate structure, and the width of the second recess and the hard mask layer at the bottom are the same and aligned.
[0040] A further improvement is that the semiconductor substrate is a silicon substrate.
[0041] A further improvement is that before step 2, the method further includes the step of forming a source region and a drain region on the surface of the semiconductor substrate at both sides of the first gate structure.
[0042] A further improvement is that after step 4 is completed, the step further includes: replacing the metal gate to form a second gate structure formed by superposition of a second gate dielectric layer and a metal gate.
[0043] A further improvement is that the second gate dielectric layer adopts the first gate dielectric layer, and the metal gate replacement includes the following steps:
[0044] The hard mask layer is removed.
[0045] The polysilicon gate is removed.
[0046] A metal is filled in the removed area of the polysilicon gate to form a metal gate, and the first gate dielectric layer and the metal gate are superimposed to form a second gate structure.
[0047] A further improvement is that the material of the second gate dielectric layer is different from the material of the first gate dielectric layer, and the metal gate replacement includes the following steps:
[0048] The hard mask layer is removed.
[0049] The polysilicon gate is removed.
[0050] The first gate dielectric layer is removed.
[0051] The second gate dielectric layer and the metal gate are sequentially formed in the removed regions of the polysilicon gate and the first gate dielectric layer.
[0052] A further improvement is that the second gate dielectric layer includes a high dielectric constant material layer.
[0053] A further improvement is that the metal gate includes a superimposed metal work function layer and a metal conductive material layer.
[0054] The present invention adds an etching back process for the zeroth interlayer film before performing the first chemical mechanical polishing process on the zeroth interlayer film having the first recess in the spacer region. The etching back process only etches the zeroth interlayer film on the top of the hard mask layer of the first gate structure and forms a second recess. The bottom surface of the second recess is lower than the bottom surface of the first recess. Therefore, the present invention can transfer the recess from the spacer region to the top of the hard mask layer, which enables the present invention to simultaneously achieve the following beneficial effects:
[0055] First, the second recess reduces the amount of the zeroth interlayer film that needs to be polished, thereby reducing the time of the first chemical mechanical polishing process.
[0056] Secondly, the second recess allows the first chemical mechanical polishing to reach the surface of the hard mask layer in advance, thereby avoiding the generation of zero-layer interlayer film material residues on the surface of the hard mask layer, thereby increasing the process window and preventing the generation of polysilicon residue defects when the polysilicon gate is removed due to the zero-layer interlayer film residues, thereby improving the product yield.
[0057] Thirdly, since there is no risk of residual zero-layer interlayer film on the surface of the hard mask layer, the first chemical mechanical polishing time will not be increased to ensure that the zero-layer interlayer film on the surface of the hard mask layer is completely removed. Therefore, the present invention can further reduce the first chemical mechanical polishing time.
[0058] Secondly, the reduction in the first chemical mechanical polishing time can make the surface flatness of the zero-layer interlayer film better, eliminate the butterfly defects on the surface of the zero-layer interlayer film, thereby preventing metal from remaining in the butterfly defects, thereby improving product yield.
[0059] In summary, the present invention can eliminate the zeroth layer of interlayer film material residue on the surface of the hard mask layer at the top of the polysilicon gate, and can also eliminate the butterfly defects in the spacing area at the same time, can reduce the grinding time, can improve the process window and can improve the product yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0060] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0061] Figure 1A-1B It is a device structure diagram in each step of the manufacturing method of the existing zero-th interlayer film;
[0062] Figure 2 is a flow chart of a method for manufacturing a zero-th interlayer film according to an embodiment of the present invention;
[0063] Figure 3A-3D It is a device structure diagram in each step of the method for manufacturing the zero-th interlayer film in an embodiment of the present invention. DETAILED DESCRIPTION
[0064] like Figure 2 As shown, it is a flow chart of a method for manufacturing a zero-layer interlayer film according to an embodiment of the present invention; FIG. 3A to FIG. 3D , which is a device structure diagram in each step of the method for manufacturing the zero-th interlayer film according to an embodiment of the present invention; the method for manufacturing the zero-th interlayer film according to an embodiment of the present invention comprises the following steps:
[0065] Step 1: Figure 3A As shown, a semiconductor substrate 203 is provided, and a plurality of first gate structures 204 formed by stacking a first gate dielectric layer and a polysilicon gate are formed on the surface of the semiconductor substrate 203 . Figure 3A In the figure, the first gate dielectric layer and the polysilicon gate are not separately marked.
[0066] The formation area of the first gate structure 204 is defined by a hard mask layer 205 , and the hard mask layer 205 is further stacked on top of the polysilicon gate of the first gate structure 204 .
[0067] The area between the first gate structures 204 is a spacing area.
[0068] Usually, the same semiconductor substrate 203 also includes different device regions. Figure 3AThe width and spacing in the middle region 201 are smaller than the width and spacing of the first gate structure 204 in the region 202. The region 201 can be a core device region, and the region 202 can be an input-output device region.
[0069] In the embodiment of the present invention, the sub-steps of step 1 of forming the first gate structure 204 include:
[0070] Step 11: forming the first gate dielectric layer and the polysilicon gate in sequence on the surface of the semiconductor substrate 203.
[0071] The semiconductor substrate 203 is a silicon substrate.
[0072] Step 12: forming a hard mask layer 205 on the surface of the polysilicon gate.
[0073] The hard mask layer 205 is a nitride layer or a stacked layer of an oxide layer and a nitride layer.
[0074] Step 13: Photolithography is used to define a formation area of the first gate structure 204 , and the hard mask layer 205 , the polysilicon gate and the first gate dielectric layer are sequentially etched to form a plurality of the first gate structures 204 .
[0075] Later also includes:
[0076] Step 14: forming sidewalls on the sides of each of the first gate structures 204 .
[0077] After forming the sidewall spacer, the method further includes forming a source region and a drain region on the surface of the semiconductor substrate 203 at both sides of the first gate structure 204 .
[0078] The material of the sidewall spacer includes an oxide layer or a nitride layer.
[0079] In some embodiments, before performing the subsequent step 2, the following steps are also included:
[0080] A contact hole etch stop layer composed of a nitride layer is formed, and the contact hole etch stop layer covers the surface of the hard mask layer 205 on the top of the gate, the side of the sidewall and the surface of the semiconductor substrate 203 in the spacer.
[0081] Step 2: Figure 3A As shown, a zero-layer interlayer film 206 is grown, and the zero-layer interlayer film 206 completely fills the spacer and extends above the top surface of the hard mask layer 205; the zero-layer interlayer film 206 has an uneven top surface and a first recess 207 on the top of the spacer. Figure 3A As shown, the size of the first recess 207 formed in the region 202 is larger.
[0082] like Figure 3B As shown, before performing step three, it also includes using a second chemical mechanical polishing process to rough-grind the zero-th layer interlayer film 206 to increase the flatness of the top surface of the zero-th layer interlayer film 206 and reduce the depth of the first recess 207. After the second chemical mechanical polishing process is completed, the first recess is separately marked with a mark 207a.
[0083] Step 3: Figure 3C As shown, the zeroth interlayer film 206 on the top of the hard mask layer 205 is etched back to form a second recess 208 , and the bottom surface of the second recess 208 is lower than the bottom surface of the first recess 207 .
[0084] In the embodiment of the present invention, the second recess 208 is located directly above the first gate structure 204, and the second recess 208 has the same width as and is aligned with the hard mask layer 205 at the bottom. The second recess 208 can be defined by a mask having a pattern opposite to that of the mask of the first gate structure 204.
[0085] Step 4: Figure 3D As shown, with the hard mask layer 205 as a stop layer, the zero-layer interlayer film 206 is planarized by a first chemical mechanical polishing process, so that the top surface of the zero-layer interlayer film 206 is flush with the top surface of the hard mask layer 205 and the zero-layer interlayer film 206 above the top surface of the hard mask layer 205 is completely removed.
[0086] Since the distance from the second recess 208 to the top surface of the hard mask layer 205 becomes smaller, the grinding time of the first chemical mechanical grinding process can be reduced and the residue of the zeroth layer interlayer film 206 on the top surface of the hard mask layer 205 can be avoided at the same time; the grinding time of the first chemical mechanical grinding process must also avoid the generation of butterfly defects. Figure 3D Although there is still a certain depression 209 in the middle, this depression 209 does not bring any adverse effects and is not considered a defect.
[0087] After step 4 is completed, the method further includes: replacing the metal gate to form a second gate structure formed by superposition of a second gate dielectric layer and a metal gate.
[0088] The second gate dielectric layer includes a high dielectric constant material layer.
[0089] The metal gate includes a stacked metal work function layer and a metal conductive material layer.
[0090] In some embodiments, the second gate dielectric layer adopts the first gate dielectric layer, and the metal gate replacement includes the following steps:
[0091] The hard mask layer 205 is removed.
[0092] The polysilicon gate is removed.
[0093] A metal is filled in the removed area of the polysilicon gate to form a metal gate, and the first gate dielectric layer and the metal gate are superimposed to form a second gate structure.
[0094] In some embodiments, the material of the second gate dielectric layer is different from the material of the first gate dielectric layer, and the metal gate replacement includes the following steps:
[0095] The hard mask layer 205 is removed.
[0096] The polysilicon gate is removed.
[0097] The first gate dielectric layer is removed.
[0098] The second gate dielectric layer and the metal gate are sequentially formed in the removed regions of the polysilicon gate and the first gate dielectric layer.
[0099] In the embodiment of the present invention, before the first chemical mechanical polishing process is performed on the zero-layer interlayer film 206 having the first recess 207 in the spacer region, an etching back process is added to the zero-layer interlayer film 206. The etching back process only etches the zero-layer interlayer film 206 on the top of the hard mask layer 205 of the first gate structure 204 and forms a second recess 208. The bottom surface of the second recess 208 is lower than the bottom surface of the first recess 207. This enables the embodiment of the present invention to simultaneously achieve the following beneficial effects:
[0100] First, the second recess 208 reduces the amount of the zeroth interlayer film 206 that needs to be polished, thereby reducing the time of the first chemical mechanical polishing process.
[0101] Secondly, the second recess 208 allows the first chemical mechanical polishing to reach the surface of the hard mask layer 205 in advance, thereby avoiding the generation of zero-layer interlayer film 206 material residue on the surface of the hard mask layer 205, thereby increasing the process window and preventing the generation of polysilicon residue defects when the polysilicon gate is removed due to the zero-layer interlayer film 206 residue, thereby improving the product yield.
[0102] Thirdly, since there is no risk of residual zero-layer interlayer film 206 on the surface of the hard mask layer 205, the first chemical mechanical polishing time will not be increased to ensure that the zero-layer interlayer film 206 on the surface of the hard mask layer 205 is completely removed. Therefore, the present invention can further reduce the first chemical mechanical polishing time.
[0103] Secondly, the reduction of the first chemical mechanical polishing time can make the surface flatness of the zero-layer interlayer film 206 better, eliminate the butterfly defects on the surface of the zero-layer interlayer film 206, thereby preventing metal from remaining in the butterfly defects, thereby improving product yield.
[0104] In summary, the embodiment of the present invention can eliminate the residual material of the zeroth interlayer film 206 on the surface of the hard mask layer 205 at the top of the polysilicon gate, and can also eliminate the butterfly defects in the spacing area at the same time, which can reduce the grinding time, improve the process window and improve the product yield.
[0105] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing a zero-layer interlayer film, characterized in that: The steps include: Step 1, providing a semiconductor substrate, and forming a plurality of first gate structures formed by stacking a first gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate; The formation area of the first gate structure is defined by a hard mask layer, and the hard mask layer is also superimposed on the top of the polysilicon gate of the first gate structure; The area between the first gate structures is a spacing area; Step 2, growing a zero-th interlayer film, wherein the zero-th interlayer film completely fills the spacer and extends above the top surface of the hard mask layer; the zero-th interlayer film has an uneven top surface and a first recess at the top of the spacer; Step 3, etching back the zeroth interlayer film on the top of the hard mask layer to form a second recess, wherein the bottom surface of the second recess is lower than the bottom surface of the first recess; Step 4: Using the hard mask layer as a stop layer, adopt a first chemical mechanical polishing process to planarize the zeroth layer interlayer film, so that the top surface of the zeroth layer interlayer film is flush with the top surface of the hard mask layer and the zeroth layer interlayer film above the top surface of the hard mask layer is completely removed.
2. The method for manufacturing a zero-th interlayer film according to claim 1, wherein: Step 1: The sub-steps of forming the first gate structure include: Step 11, sequentially forming the first gate dielectric layer and the polysilicon gate on the surface of the semiconductor substrate; Step 12, forming a hard mask layer on the surface of the polysilicon gate; Step 13: photolithography is used to define a formation area of the first gate structure, and the hard mask layer, the polysilicon gate and the first gate dielectric layer are sequentially etched to form a plurality of the first gate structures.
3. The method for manufacturing a zero-th interlayer film according to claim 2, wherein: The sub-step of step 1 forming the first gate structure further includes: Step 14: forming sidewalls on the sides of each of the first gate structures.
4. The method for manufacturing a zero-th interlayer film according to claim 2, wherein: The hard mask layer is a nitride layer or a stacked layer of an oxide layer and a nitride layer.
5. The method for manufacturing a zero-th interlayer film according to claim 3, wherein: The material of the sidewall spacer includes an oxide layer or a nitride layer.
6. The method for manufacturing a zero-th interlayer film according to claim 3, wherein: Before proceeding to step 2, the following steps are also included: A contact hole etch stop layer composed of a nitride layer is formed, and the contact hole etch stop layer covers the surface of the hard mask layer on the top of the gate, the side of the sidewall and the surface of the semiconductor substrate in the spacer.
7. The method for manufacturing a zero-th interlayer film according to claim 1, wherein: Before performing step three, the method further includes performing a second chemical mechanical polishing process to coarsely grind the zeroth interlayer film to increase the flatness of the top surface of the zeroth interlayer film and reduce the depth of the first recess.
8. The method for manufacturing a zero-th interlayer film according to claim 1, wherein: In step three, the second recess is located directly above the first gate structure, and the second recess has the same width as the hard mask layer at the bottom and is aligned.
9. The method for manufacturing a zero-th interlayer film according to claim 1, wherein: The semiconductor substrate is a silicon substrate.
10. The method for manufacturing a zero-th interlayer film according to claim 9, wherein: Before step 2, the method further includes forming a source region and a drain region on the surface of the semiconductor substrate at both sides of the first gate structure.
11. The method for manufacturing a zero-th interlayer film according to claim 10, wherein: After step 4 is completed, the method further includes: replacing the metal gate to form a second gate structure formed by superposition of a second gate dielectric layer and a metal gate.
12. The method for manufacturing a zero-th interlayer film according to claim 11, wherein: The second gate dielectric layer adopts the first gate dielectric layer, and the metal gate replacement includes the following steps: removing the hard mask layer; removing the polysilicon gate; A metal is filled in the removed area of the polysilicon gate to form a metal gate, and the first gate dielectric layer and the metal gate are superimposed to form a second gate structure.
13. The method for manufacturing a zero-th interlayer film according to claim 11, wherein: The material of the second gate dielectric layer is different from the material of the first gate dielectric layer, and the metal gate replacement includes the following steps: removing the hard mask layer; removing the polysilicon gate; removing the first gate dielectric layer; The second gate dielectric layer and the metal gate are sequentially formed in the removed regions of the polysilicon gate and the first gate dielectric layer.
14. The method for manufacturing a zero-th interlayer film according to claim 11, wherein: The second gate dielectric layer includes a high dielectric constant material layer.
15. The method for manufacturing a zero-th interlayer film according to claim 11, wherein: The metal gate includes a stacked metal work function layer and a metal conductive material layer.
Citation Information
Patent Citations
A manufacturing method of an interlayer film
CN109037055A
Manufacturing method of metal gate
CN109637927A