Signal generating circuit and operating system

Abstract

The present invention provides a signal generating circuit and operating system for waking up a specific circuit. The circuit includes a detection circuit, a delay circuit, and a judgment circuit. The detection circuit detects whether a wake-up event has occurred and generates a detection signal. The delay circuit delays the detection signal to generate a delayed signal. The judgment circuit determines whether the wake-up event is compliant based on the delayed signal and a power-off signal. If the wake-up event is compliant, the judgment circuit enables a wake-up signal to wake up the specific circuit. If the wake-up event is not compliant, the judgment circuit resets the detection circuit.

Description

Technical Field

[0001] The present invention relates to a signal generating circuit, and more particularly to a signal generating circuit for generating a wake-up signal. Background Art

[0002] With technological advancements, portable electronic devices have become increasingly diverse and versatile. Because portable electronic devices are powered by batteries, which have limited power, they often leave normal mode and enter a power-saving mode when unused for extended periods. When a wake-up event occurs, the device exits power-saving mode and re-enters normal mode. However, if the device cannot immediately detect the wake-up event, it may malfunction. Summary of the Invention

[0003] One embodiment of the present invention provides a signal generating circuit for waking up a specific circuit, and includes a detection circuit, a delay circuit, and a judgment circuit. The detection circuit detects whether a wake-up event has occurred and generates a detection signal. The delay circuit delays the detection signal to generate a delayed signal. The judgment circuit determines whether the wake-up event is compliant based on the delayed signal and a power-off signal. If the wake-up event is compliant, the judgment circuit enables a wake-up signal to wake up the specific circuit. If the wake-up event is not compliant, the judgment circuit resets the detection circuit.

[0004] The present invention further provides an operating system, comprising a processing circuit, a specific circuit, and a signal generating circuit. After executing a standby instruction, the processing circuit enables a power-off signal. The specific circuit enters a standby mode in accordance with the power-off signal. The signal generating circuit is used to wake up the specific circuit and comprises a detection circuit, a delay circuit, and a judgment circuit. The detection circuit detects whether a wake-up event occurs and generates a detection signal. The delay circuit delays the detection signal to generate a delay signal. The judgment circuit determines whether the wake-up event is compliant based on the delay signal and the power-off signal. When the wake-up event is compliant, the judgment circuit enables a wake-up signal to wake up the specific circuit. When the wake-up event is not compliant, the judgment circuit resets the detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 Schematic diagram of the signal generating circuit according to the present invention.

[0006] Figure 2 FIG. 1 is a schematic diagram of a power-off signal according to the present invention.

[0007] Figure 3 FIG. 4 is a schematic diagram of an application of the signal generating circuit of the present invention.

[0008] Explanation of symbols:

[0009] 100, 306: signal generating circuit;

[0010] 102: detection circuit;

[0011] 104: delay circuit;

[0012] 106: judgment circuit;

[0013] 108, 110: logic gates;

[0014] 112: event status register;

[0015] 202, 204: time points;

[0016] 206: time difference;

[0017] 300: operating system;

[0018] 302, 304: processing circuit;

[0019] 308, 310, 312: interrupt source;

[0020] EVN, E1~E3: wake-up events;

[0021] wake_det: detect signal;

[0022] CLR: clear signal;

[0023] regclk: clock signal;

[0024] wake_det_dly: delay signal;

[0025] PR_DN: power off signal;

[0026] SET: set signal;

[0027] Swake: wake-up signal;

[0028] IN: input signal;

[0029] clk: clock signal;

[0030] wfi: wait for interrupt instruction;

[0031] SC1, SC2: control signals. DETAILED DESCRIPTION

[0032] To make the objectives, features, and advantages of the present invention more readily apparent, the following examples are presented and described in detail with reference to the accompanying drawings. This specification provides various examples to illustrate the technical features of various embodiments of the present invention. The configurations of the various components in the examples are for illustrative purposes only and are not intended to limit the present invention. Furthermore, any repetition of reference numerals in the figures of the examples is for simplification and does not imply a correlation between the different examples.

[0033] Figure 1 Schematic diagram of the signal generating circuit of the present invention. As shown, the signal generating circuit 100 includes a detection circuit 102, a delay circuit 104, and a determination circuit 106. The detection circuit 102 is used to detect whether a wake-up event EVN has occurred. When the wake-up event EVN occurs, the detection circuit 102 enables a detection signal wake_det. When the detection circuit 102 does not detect a pulse signal, the detection circuit 102 does not enable the detection signal wake_det. In one possible embodiment, the wake-up event EVN is a pulse signal. In this example, when the detection circuit 102 detects a pulse signal, the detection circuit 102 enables the detection signal wake_det. At this time, the detection signal wake_det is a specific level, such as a high level or a low level. When the detection circuit 102 does not detect a pulse signal, the detection circuit 102 does not enable the detection signal wake_det. At this time, the detection signal wake_det is not at the specific level.

[0034] In other embodiments, the detection circuit 102 further records the wake-up event EVN. Therefore, once the wake-up event EVN occurs, the detection circuit 102 continuously enables the detection signal wake_det until a clear signal CLR is asserted. When the clear signal CLR is asserted, it indicates that the wake-up event EVN was unexpected. Therefore, the detection circuit 102 stops enabling the detection signal wake_det. In another embodiment, when the detection circuit 102 receives a clock signal regclk, it indicates that an external circuit has left a standby mode and entered a normal mode. At this point, since the detection circuit 102 no longer needs to detect whether the wake-up event EVN has occurred, the detection circuit 102 clears the recorded wake-up event EVN.

[0035] The present invention does not limit how the detection circuit 102 stores the wake-up event EVN. In one embodiment, the detection circuit 102 includes a register (not shown). The register pre-stores a value of 0. When the wake-up event EVN occurs, the detection circuit 102 changes the value of the register from 0 to 1. When the wake-up event EVN does not occur, the detection circuit 102 does not change the value of the register from 0. In this example, the detection circuit 102 determines whether to enable the detection signal wake_det based on the value of the register. For example, when the register contains a value of 1, the detection circuit 102 enables the detection signal wake_det. When the register contains a value of 0, the detection circuit 102 does not enable the detection signal wake_det. In other embodiments, when the clear signal CLR is enabled, the detection circuit 102 sets the register to store a value of 0. In some embodiments, when the detection circuit 102 receives the clock signal regclk, the detection circuit 102 also sets the value of the register to 0.

[0036] Delay circuit 104 delays detection signal wake_det to generate a delayed signal wake_det_dly. The present invention is not limited to the architecture of delay circuit 104. In one embodiment, delay circuit 104 has an adjustable delay time. In this case, a user may provide a control signal (not shown) to delay circuit 104 to adjust the delay time of delay circuit 104.

[0037] The determination circuit 106 determines whether the wake-up event EVN is in compliance with the delay signal wake_det_dly and a power-down signal PR_DN. If the wake-up event EVN is in compliance with the requirements, the determination circuit 106 enables a wake-up signal Swake to wake up a specific circuit (not shown). If the wake-up event EVN is not in compliance with the requirements, the determination circuit 106 does not wake up the specific circuit. In this case, the determination circuit 106 may enable a clear signal CLR to reset the detection circuit 102.

[0038] In one embodiment, the determination circuit 106 detects the levels of the delay signal wake_det_dly and the power-down signal PR_DN. When the level of the delay signal wake_det_dly is equal to the level of the power-down signal PR_DN, it indicates that the wake-up event EVN is in compliance. Therefore, the determination circuit 106 enables the wake-up signal Swake. When the level of the delay signal wake_det_dly is not equal to the level of the power-down signal PR_DN, it indicates that the wake-up event EVN is not in compliance. Therefore, the determination circuit 106 disables the wake-up signal Swake and enables the clear signal CLR.

[0039] The present invention does not limit the architecture of the determination circuit 106. In this embodiment, the determination circuit 106 includes logic gates 108 and 110, and an event status register 112. The logic gate 108 determines whether to enable a setting signal SET based on the delay signal wake_det_dly and the power shutdown signal PR_DN. In one embodiment, when the delay signal wake_det_dly and the power shutdown signal PR_DN are at a specific level (e.g., a high level), the logic gate 110 enables the setting signal SET. In this example, when at least one of the delay signal wake_det_dly and the power shutdown signal PR_DN is not at the specific level, the logic gate 110 does not enable the setting signal SET. The present invention does not limit the type of logic gate 110. In this embodiment, the logic gate 110 is an AND gate.

[0040] The event status register 112 enables the wake-up signal Swake based on the set signal SET. In this embodiment, when the set signal SET is enabled, the event status register 112 enables the wake-up signal Swake. In this example, when the set signal SET is disabled, the event status register 112 disables the wake-up signal Swake. In one embodiment, the event status register 112 directly uses the set signal SET as the wake-up signal Swake.

[0041] The present invention does not limit the type of event status register 112. In one possible embodiment, the event status register 112 is a D-type flip-flop. A set terminal of the D-type flip-flop receives the set signal SET. An output terminal of the D-type flip-flop is used to provide the wake-up signal Swake. In this example, the wake-up signal Swake is equal to the set signal SET. Therefore, when the wake-up signal Swake is enabled, the set signal SET is also enabled. When the wake-up signal Swake is not enabled, the set signal SET is also not enabled. In other embodiments, an input terminal of the D-type flip-flop receives an input signal IN, and a clock terminal of the D-type flip-flop receives a clock signal clk. In this example, the input signal IN may be maintained at a low level. When the D-type flip-flop receives the clock signal clk, the D-type flip-flop uses the input signal IN as the wake-up signal Swake to disable the wake-up signal Swake.

[0042] Logic gate 108 determines whether to enable clear signal CLR based on wake-up signal Swake and wake-up event EVN. For example, when wake-up event EVN is compliant, event status register 112 enables wake-up signal Swake. Therefore, logic gate 108 disables clear signal CLR, causing detection circuit 102 to continue enabling detection signal wake_det. However, when wake-up event EVN is not compliant, event status register 112 disables wake-up signal Swake. At this point, since wake-up event EVN has disappeared (because wake-up event EVN is a short pulse), logic gate 108 enables clear signal CLR, causing detection circuit 102 to stop enabling detection signal wake_det. The present invention is not limited to the type of logic gate 108. In one embodiment, logic gate 108 is a NOR gate.

[0043] Figure 2 This is a schematic diagram of the power-down signal PR_DN of the present invention. As shown, at time 202, the software issues a wait-for-interrupt instruction wfi. Consequently, at time 204, the power-down signal PR_DN is enabled, e.g., transitioning from a low level to a high level. Due to circuit delays, there is a time difference 206 between the time 204 when the power-down signal PR_DN is enabled and the time 202 when the wait-for-interrupt instruction wfi is issued.

[0044] In one embodiment, the time difference between the delayed signal wake_det_dly generated by the delay circuit 104 and the detection signal wake_det is equal to the time difference 206. In this example, when the interrupt command wfi is issued, the power-down signal PR_DN is not enabled until a certain period of time (i.e., the time difference 206) has passed. Therefore, the configuration personnel obtain the time difference 206 in advance and then adjust a delay parameter of the delay circuit 104 based on the time difference 206, so that the delayed signal wake_det_dly lags the detection signal wake_det by a time equal to the time difference 206.

[0045] In this embodiment, the signal generating circuit 100 not only determines whether the wake-up event EVN has occurred after time point 204, but also begins determining whether the wake-up event EVN has occurred before time point 204. When the wake-up event EVN occurs before time point 202, the detection circuit 102 enables the detection signal wake_det. The delay circuit 104 delays the detection signal wake_det. Therefore, the delayed signal wake_det_dly may fall between time points 202 and 204. At this time, since the power-down signal PR_DN is not yet enabled, the wake-up event EVN is considered illegal. Therefore, the signal generating circuit 100 ignores the wake-up event EVN before time point 202. When the wake-up event EVN occurs between time points 202 and 204, the delayed signal wake_det_dly generated by the delay circuit 104 falls after time point 204. At this time, since the power-down signal PR_DN is already enabled, the wake-up event EVN is considered legal. Therefore, the signal generating circuit 100 enables the wake-up signal Swake.

[0046] Figure 3 FIG2 is a schematic diagram illustrating an application of the signal generating circuit described in the present invention. In one embodiment, the signal generating circuit is implemented in an operating system 300. The operating system 300 includes processing circuits 302 and 304, a signal generating circuit 306, and interrupt sources 308, 310, and 312. The processing circuit 302 executes a program code. When the processing circuit 302 executes a standby instruction, such as a wait for interrupt (WFI) instruction, the processing circuit 302 enables a power down signal PR_DN. The present invention does not limit the architecture of the processing circuit 302. In one embodiment, the processing circuit 302 is a central processing unit (CPU).

[0047] The processing circuit 304 enters a standby mode according to the enabled power shutdown signal PR_DN. At this time, the processing circuit 304 may suspend generating a control signal SC1. Therefore, the processing circuit 302 also enters a standby mode. When a wake-up signal Swake is enabled, the processing circuit 304 leaves the standby mode and enters a normal mode. In normal mode, the processing circuit 304 re-provides the control signal SC1. Therefore, the processing circuit 302 also enters normal mode. In other embodiments, when the processing circuit 304 enters the standby mode, the processing circuit 302 remains in a normal mode. The present invention does not limit the architecture of the processing circuit 304. In some embodiments, the processing circuit 304 may be a clock generator. In this example, the control signal SC1 is a clock signal used to control the operating speed of the processing circuit 302.

[0048] The signal generating circuit 306 is used to enable the wake-up signal Swake. In the present embodiment, the signal generating circuit 306 is coupled to the interrupt sources 308, 310, and 312 to monitor whether the interrupt sources 308, 310, and 312 generate wake-up events E1 to E3. When any of the wake-up events E1 to E3 occurs, the signal generating circuit 306 enables the wake-up signal Swake. Taking the interrupt source 308 as an example, when the interrupt source 308 completes a specific action, the interrupt source 308 generates the wake-up event E1. Therefore, the signal generating circuit 306 enables the wake-up signal Swake to wake up the processing circuit 304. The present invention does not limit the number of interrupt sources. In other embodiments, the signal generating circuit 306 is coupled to more or fewer interrupt sources.

[0049] The structure of the signal generating circuit 306 is similar to Figure 1 The structure of the signal generating circuit 100 is similar, so it will not be described in detail. Figure 1 The signal generating circuit 100 shown is used to monitor whether a single interrupt source generates a wake-up event. Figure 3 In the embodiment, since the signal generating circuit 306 monitors three interrupt sources, the signal generating circuit 306 has three groups of signal generating circuits 100 therein, which monitor the interrupt sources 308, 310 and 312 respectively.

[0050] In some embodiments, the signal generating circuit 306 enables the corresponding signal generating circuit 100 based on an external signal (not shown). Only enabled signal generating circuits 100 monitor the corresponding interrupt source, while disabled signal generating circuits 100 do not monitor the interrupt source. For example, assume that the signal generating circuit 306 has a first signal generating circuit, a second signal generating circuit, and a third signal generating circuit. The first signal generating circuit is coupled to the interrupt source 308. The second signal generating circuit is coupled to the interrupt source 310. The third signal generating circuit is coupled to the interrupt source 312. In this example, when the first signal generating circuit is enabled and the second and third signal generating circuits are disabled, if the interrupt sources 308, 310, and 312 generate wake-up events E1 to E3, respectively, only wake-up event E1 is capable of enabling the wake-up signal Swake. At this time, even if wake-up events E2 and E3 occur, the second and third signal generating circuits will not enable the wake-up signal Swake. However, if the first to third signal generating circuits are all enabled, as long as any one of the wake-up events E1 - E3 is qualified, the corresponding signal generating circuit will enable the wake-up signal Swake.

[0051] Furthermore, the present invention does not limit the types of interrupt sources 308, 310, and 312. The type of one of interrupt sources 308, 310, and 312 may be the same as the type of another of interrupt sources 308, 310, and 312. In one embodiment, each of interrupt sources 308, 310, and 312 complies with an internet protocol.

[0052] In other embodiments, when the processing circuit 304 enters the normal mode, the processing circuit 304 provides a control signal SC2 to the signal generating circuit 306. Therefore, the signal generating circuit 306 stops monitoring whether the wake-up events E1-E3 occur. At this time, even if the wake-up events E1-E3 occur, the signal generating circuit 306 does not enable the wake-up signal Swake. In one possible embodiment, the control signal SC2 may include Figure 1 However, when the processing circuit 304 enters the standby mode, the processing circuit 304 stops controlling the signal SC2 to the signal generating circuit 306. Therefore, the signal generating circuit 306 starts monitoring whether the wake-up events E1-E3 occur.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) are generally understood by those skilled in the art to which this invention pertains. Furthermore, unless otherwise expressly stated, dictionary definitions of terms should be interpreted as consistent with their meanings in the relevant technical context and should not be interpreted as idealized or overly formal. While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another.

[0054] While the present invention has been disclosed above with reference to preferred embodiments, these are not intended to limit the present invention. Any person skilled in the art may make modifications and variations without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented in physical embodiments using hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A signal generating circuit for waking up a specific circuit, characterized in that: include: a detection circuit for detecting whether a wake-up event occurs and generating a detection signal; a delay circuit, delaying the detection signal to generate a delayed signal; as well as a judgment circuit, for judging whether the wake-up event is compliant according to the delay signal and a power-off signal; When the wake-up event is in compliance, the judgment circuit enables a wake-up signal to wake up the specific circuit; when the wake-up event is not in compliance, the judgment circuit resets the detection circuit. Wherein, the judgment circuit includes: a first logic gate, determining whether to enable a setting signal according to the delay signal and the power-off signal; An event status register uses the setting signal as the wake-up signal when the setting signal is enabled.

2. The signal generating circuit according to claim 1, wherein: When the wake-up event occurs, the detection circuit stores the wake-up event and enables the detection signal; when the wake-up event does not occur, the detection circuit does not enable the detection signal.

3. The signal generating circuit according to claim 2, wherein: When the wake-up event is not compliant, the judgment circuit clears the wake-up event stored in the detection circuit.

4. The signal generating circuit according to claim 2, wherein: When the level of the delay signal is equal to the level of the power-off signal, it indicates that the wake-up event is compliant; when the level of the delay signal is not equal to the level of the power-off signal, it indicates that the wake-up event is not compliant.

5. The signal generating circuit according to claim 2, wherein: The judgment circuit includes: a second logic gate, determining whether to enable a clear signal according to the wake-up signal and the wake-up event; When the clear signal is enabled, the detection circuit clears the stored wake-up event.

6. The signal generating circuit according to claim 5, wherein: When the delay signal and the power-off signal are at a specific level, the first logic gate enables the setting signal, so that the event status register enables the wake-up signal; as well as When at least one of the delay signal and the power-off signal is not at the specific level, the first logic gate disables the setting signal, so that the event status register disables the wake-up signal.

7. The signal generating circuit according to claim 5, wherein: When the event status register enables the wake-up signal, the second logic gate disables the clear signal; when the event status register does not enable the wake-up signal and the wake-up event disappears, the second logic gate enables the clear signal.

8. The signal generating circuit according to claim 5, wherein: The event status register includes: A D-type flip-flop having an input terminal, an output terminal, a clock terminal, and a setting terminal, wherein the setting terminal receives the setting signal, the output terminal provides the wake-up signal, and the input terminal receives an input signal; When the specific circuit is awakened, the clock end receives a first clock signal, so that the D-type flip-flop uses the input signal as the awakening signal, and when the setting signal is enabled, the D-type flip-flop enables the awakening signal.

9. An operating system, characterized in that: include: a processing circuit that enables a power-off signal after executing a standby instruction; a specific circuit, which enters a standby mode according to the power-off signal; as well as a signal generating circuit, used to wake up the specific circuit, and comprising: a detection circuit for detecting whether a wake-up event occurs and generating a detection signal; a delay circuit, delaying the detection signal to generate a delayed signal; and a judgment circuit, configured to judge whether the wake-up event is compliant according to the delay signal and the power-off signal; When the wake-up event is in compliance, the judgment circuit enables a wake-up signal to wake up the specific circuit; when the wake-up event is not in compliance, the judgment circuit resets the detection circuit. Wherein, the judgment circuit includes: a first logic gate, determining whether to enable a setting signal according to the delay signal and the power-off signal; An event status register uses the setting signal as the wake-up signal when the setting signal is enabled.

10. The operating system according to claim 9, wherein: The detection circuit further receives a second clock signal. When the specific circuit is awakened, the detection circuit clears the stored awakening event according to the second clock signal.

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