Computing units comprising asymmetric ferroelectric device pairs and methods of forming the same

Abstract

This disclosure relates to a computing unit including a pair of asymmetric ferroelectric devices and a method for forming the same. A ferroelectric computing unit includes: a first ferroelectric switching device including a first ferroelectric material portion and generating a digital output signal; and a second ferroelectric switching device including a second ferroelectric material portion and generating an analog output signal. The output node of one of the first and second ferroelectric switching devices is electrically connected to the gate electrode of the other to provide mixed-response characteristics of random digital switching and analog switching.

Description

Technical Field

[0001] This disclosure relates to computational units including pairs of asymmetric ferroelectric devices and methods for forming the same. Background Technology

[0002] Device-centric neuromorphic computing is difficult to implement because it requires providing both storage and threshold response capabilities within a physically implemented computing device. Summary of the Invention

[0003] According to one aspect of this disclosure, a ferroelectric device is provided, including a ferroelectric computing unit, the ferroelectric computing unit comprising: a first ferroelectric switching device, the first ferroelectric switching device including a first ferroelectric material portion and generating a digital output signal, the first ferroelectric material portion having a first area size and disposed between a first gate electrode and a first current channel, and the first ferroelectric material portion adjusting the conductivity of the first current channel according to a first bias voltage at the first gate electrode; and a second ferroelectric switching device, the second ferroelectric switching device including a second ferroelectric material portion and generating an analog output signal, the second ferroelectric material portion having a second area size larger than the first area size and disposed between a second gate electrode and a second current channel, and the second ferroelectric material portion adjusting the conductivity of the second current channel according to a second bias voltage at the second gate electrode, wherein the output node of one of the first ferroelectric switching device and the second ferroelectric switching device is electrically connected to the gate electrode of the other of the first ferroelectric switching device and the second ferroelectric switching device.

[0004] According to one aspect of this disclosure, a device including a computing unit is provided, the computing unit comprising: a digital output switching device that generates a digital output signal and includes a first current channel, the first current channel providing regulated conductivity based on a first bias voltage at a first gate electrode located near the first current channel; and an analog output switching device that generates an analog output signal and includes a second current channel, the second current channel providing regulated conductivity based on a second bias voltage at a second gate electrode located near the second current channel, wherein the output node of one of the first ferroelectric switching device and the second ferroelectric switching device is electrically connected to the gate electrode of the other of the first ferroelectric switching device and the second ferroelectric switching device.

[0005] According to one aspect of this disclosure, a method for manufacturing a ferroelectric device including a ferroelectric computing unit is provided, comprising: forming a current channel material layer including charge carriers moving in response to an external electric field on a substrate; forming a ferroelectric material layer and a gate electrode layer on the current channel material layer; patterning the gate electrode layer and the ferroelectric material layer into a first gate stack of a first gate electrode and a first ferroelectric material portion, and a second gate stack of a second gate electrode and a second ferroelectric material portion, wherein a portion of the current channel material layer below the first ferroelectric material portion includes a first current channel, and a portion of the current channel material layer below the second ferroelectric material portion includes a second current channel; and forming a ferroelectric computing unit including a first ferroelectric switching device and a second ferroelectric switching device by electrically connecting the first current channel, the second current channel, the first gate electrode, and the second gate electrode, wherein: the first ferroelectric switching device generates a digital output signal; the second ferroelectric switching device generates an analog output signal; and the output node of one of the first ferroelectric switching device and the second ferroelectric switching device is electrically connected to the gate electrode of the other of the first ferroelectric switching device and the second ferroelectric switching device. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description, which is taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a schematic diagram of a computing unit according to an embodiment of the present disclosure.

[0008] Figure 2A These are exemplary input pulse patterns that can be applied to the computing units of this disclosure.

[0009] Figure 2B This is a schematic vertical cross-sectional view of a ferroelectric field-effect transistor that can be used as a component of the computing unit of this disclosure.

[0010] Figure 3A The response curve of a first ferroelectric switching device, which is a function of the total number of input pulses, according to an embodiment of the present disclosure.

[0011] Figure 3B The response curve of the second ferroelectric switching device, which is a function of the total number of input pulses, according to an embodiment of the present disclosure.

[0012] Figure 3C This is a diagram illustrating the factors affecting the response characteristics of a digital random threshold switching device according to embodiments of the present disclosure.

[0013] Figure 4 This is a schematic diagram illustrating a first configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0014] Figure 5 This is a schematic diagram illustrating a second configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0015] Figure 6 This is a schematic diagram illustrating a third configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0016] Figure 7 This is a schematic diagram illustrating a fourth configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0017] Figure 8 This is a schematic diagram illustrating a fifth configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0018] Figure 9 This is a schematic diagram illustrating a sixth configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0019] Figure 10 This is a schematic diagram illustrating a seventh configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0020] Figure 11 This is a schematic diagram illustrating an eighth configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0021] Figure 12 This is a schematic diagram illustrating a ninth configuration of a ferroelectric computing unit according to an embodiment of the present disclosure.

[0022] Figure 13A This is a vertical cross-sectional view of a first exemplary ferroelectric field-effect transistor that can be used as a ferroelectric switching device according to an embodiment of the present disclosure.

[0023] Figure 13B It is along Figure 13A A vertical cross-sectional view of a first exemplary ferroelectric field-effect transistor with vertical plane B-B'.

[0024] Figure 14A This is a vertical cross-sectional view of a second exemplary ferroelectric field-effect transistor that can be used as a ferroelectric switching device according to an embodiment of the present disclosure.

[0025] Figure 14B It is along Figure 14A A vertical cross-sectional view of a second exemplary ferroelectric field-effect transistor with vertical plane B-B'.

[0026] Figure 15This is a vertical cross-sectional view of a third exemplary ferroelectric field-effect transistor that can be used as a ferroelectric switching device according to embodiments of the present disclosure.

[0027] Figure 16 This is a vertical cross-sectional view of an electrolyte-based ferroelectric switching device according to an embodiment of the present disclosure.

[0028] Figure 17 This is a schematic diagram of a neuromorphic computing device including multiple instances of ferroelectric computing units according to embodiments of the present disclosure.

[0029] Figure 18 This is a flowchart illustrating the general processing steps for manufacturing the ferroelectric computing device of this disclosure. Detailed Implementation

[0030] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "upper," etc.) to facilitate the description of the relationship between one element or feature shown in the figures and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly. Elements with the same reference numerals refer to the same element and are considered to have the same material composition and the same thickness range, unless otherwise explicitly stated.

[0032] Ferroelectric materials are materials that can exhibit spontaneous nonzero electric polarization (i.e., a nonzero total electric dipole moment) when the external electric field is zero. Spontaneous polarization can be reversed by applying a strong external electric field in the opposite direction. Polarization depends not only on the external electric field at the time of measurement but also on the history of that field. Therefore, polarization exhibits a hysteresis loop. The maximum value of polarization is called saturation polarization. The polarization that remains after the external electric field causing saturation polarization is no longer applied (i.e., turned off) is called residual polarization. The magnitude of the electric field that needs to be applied in the opposite direction of residual polarization to achieve zero polarization is called the coercive electrical field. For the purpose of forming storage devices, high residual polarization and a high coercive field are generally desirable. High residual polarization can increase the amplitude of electrical signals. A high coercive field makes storage devices more stable under disturbances caused by noise-level electric fields and interference.

[0033] Generally, the structures and methods of the various embodiments disclosed herein can be used to provide complementary metal-oxide-semiconductor (CMOS) compatible device implementations for neuromorphic computing units. As used herein, "neuromorphic computing" refers to a computing method in which electronic circuitry is used to simulate the neuro-biological architecture found in biological nervous systems. Embodiments of this disclosure can simultaneously utilize both stored responses in the form of analog outputs and random responses in the form of digital outputs, as implemented in devices of the same type, such as ferroelectric field-effect transistors (also known as ferroelectric FETs or FeFETs).

[0034] Generally, there are currently no known methods for device-centric neuromorphic implementations. Previous efforts to simulate neural systems have implemented storage functions through memory cells and threshold response functions through simulated circuits. Using conventional semiconductor circuits to simulate neural behavior limits the advantages of neuromorphic architectures over Boolean / von Neumann architectures, because conventional semiconductor circuits operate on Boolean logic and require multiple devices to be combined into a single circuit to represent the characteristics of neural circuits.

[0035] The various embodiments disclosed herein provide device-based solutions that enable the implementation of neuromorphic architectures and thus offer enhancements in performance, energy efficiency, and device density compared to circuit-centric approaches known in the art. Specifically, the same type of devices (e.g., a pair of ferroelectric devices having the same set of structural components but different sizes) can be used to generate neural response characteristics that can be used in neural computing devices. Various aspects of this disclosure will now be described in detail with reference to the accompanying drawings.

[0036] refer to Figure 1 This illustration shows a computing unit according to an embodiment of the present disclosure. The computing unit may be a neuromorphic computing unit comprising a combination of an analog non-volatile memory (NVM) device with in-memory computing (CiM) capability and a digital random threshold switch device. The analog non-volatile memory device and the digital random threshold switch device may be connected in a sequential stage. Specifically, one of the analog non-volatile memory device and the digital random threshold switch device may be located at an input stage (i.e., a first stage) (where an input signal is provided), and the other of the analog non-volatile memory device and the digital random threshold switch device may be located at an output stage (i.e., a second stage) (where an output signal is generated). In some embodiments, a feedback mechanism may be provided such that the output of the output stage can be fed back to the input stage as an additional input. In one embodiment, the analog non-volatile memory device may be located at the input stage, and the digital random threshold switch device may be located at the output stage. In another embodiment, the digital random threshold switch device may be located at the input stage, and the analog non-volatile memory device may be located at the output stage.

[0037] According to one aspect of this disclosure, a digital random threshold switch generates a digital output having no more than four output states. For example, the digital output may be a binary output, a ternary output, or a quaternary output. In one embodiment, the digital output may be a binary output. In one embodiment, the intensity ratio between each pair of output signals of the digital random threshold switch may be from 1.0 x 10⁻⁶. -9 Up to 1.0x 10 9 Within that range, for example from 1.0 x 10 -6 Up to 1.0x 10 6 From 1.0x 10 -3 Up to 1.0x 10 3 From 1.0x 10 -2 Up to 1.0x 10 2The range is from 0.1 to 10. The strength of the output signal can be measured by the amplitude of the output current or the amplitude of the output voltage. Analog non-volatile memory devices can generate analog output signals, i.e., a signal that can have a sufficient number of states (e.g., at least 10, and typically greater than 1000 and / or greater than 1.0 × 10⁻⁶). 6 (a), such that the amplitude of the output signal is a variable that changes continuously for all practical purposes. For example, when sorting all possible output states in ascending or descending order for output variables (e.g., output voltage or output current), the ratio of the two values ​​of the output variable for any two adjacent output state pairs can be in the range of 0.5 to 2.0, and can be in the range of 0.9 to 1.1.

[0038] One of the analog non-volatile memory devices and the digital random threshold switching device may include an update function block. The update function block can provide reception of input signals and initiate changes to the output of the computing unit. In one embodiment, the analog non-volatile memory device may include an update function block. In another embodiment, the digital random threshold switching device may include an update function block. The analog non-volatile memory device includes a state-holding function block that provides the ability to "remember and learn" from past experience. The digital random threshold switching device includes a threshold switching function block that provides the ability to incorporate randomness into the threshold gating response.

[0039] refer to Figure 2A The diagram illustrates exemplary input pulse patterns that can be applied to the computing units of this disclosure. Input pulses may include voltage pulses. Depending on the size and configuration of the computing unit, the voltage amplitude may range from 0.5V to 50V, for example from 1.0V to 12V, but smaller and larger voltages may also be used. The frequency of the input pulse may range from 1Hz to 100GHz, for example from 60Hz to 1GHz, but lower and higher frequencies may be used. In embodiments where the computing unit of this disclosure includes a ferroelectric device, the period of the input pulse may be equal to or greater than the response time of the ferroelectric material within the ferroelectric device, and may be greater than 10ns and / or greater than 100ns. Alternatively, input pulses may include current pulses.

[0040] refer to Figure 2BThe present invention illustrates a ferroelectric field-effect transistor that can be used as a component of the computing unit of the present disclosure. According to one aspect of the present disclosure, an analog non-volatile memory device and a digital random threshold switching device can be implemented using a pair of physical devices using the same ferroelectric material. In this embodiment, the pair of physical devices can be ferroelectric devices that provide the functionality of a state-holding functional block and a threshold switching functional block through the inherent properties of the ferroelectric material. A ferroelectric-based neuromorphic chip including a neuromorphic functional unit composed of corresponding pairs of ferroelectric devices of different sizes can be used. The sizes can be selected such that the smaller ferroelectric device is used as a digital random threshold switching device, and the larger ferroelectric device is used as an analog non-volatile memory device.

[0041] Generally, the ferroelectric material portion is disposed within the gate stack. The ferroelectric material portion can have a single ferroelectric domain, for example, in a ferroelectric field-effect transistor embodying a digital random threshold switching device, or it can have multiple ferroelectric domains, for example, in a ferroelectric field-effect transistor embodying an analog non-volatile memory device. Each ferroelectric domain can have a corresponding polarization that can point upwards or downwards. Depending on the direction of the polarization of each ferroelectric domain, the threshold voltage of the ferroelectric field-effect transistor can be increased or decreased. Generally, ferroelectric materials are used in the gate stack of ferroelectric field-effect transistors to implement digital random threshold switching devices or analog non-volatile memory devices. Ferroelectric materials can be used to incorporate neuromorphic computing capabilities into general-purpose logic circuits. After incorporating the ferroelectric material into the gate stack, various channel materials can be used for the underlying semiconductor channels. Any channel configuration can be used for the ferroelectric field-effect transistor, including planar, fin, omega, and other configurations.

[0042] According to one aspect of this disclosure, retention tuning of ferroelectric materials can be used to tune the neuronal behavior of the ferroelectric computing devices of this disclosure. Retention tuning includes optimization of reset and forgetting, which can be used to tune the characteristics of threshold switching components. Retention tuning depends on the doping composition of the ferroelectric material, the electrode material, and the annealing conditions used to crystallize the ferroelectric material. The current state of the ferroelectric material, determined by the past history of its states, can have a more sustainable influence on the response threshold over a longer retention time. Generally, the longer the state of the ferroelectric material is retained, the slower the self-resetting process of the random behavior in the ferroelectric material.

[0043] In illustrative examples, the lateral dimension of the ferroelectric material portion in a smaller ferroelectric device can be less than 100 nm, while the lateral dimension of the ferroelectric material portion in a larger ferroelectric device can be greater than 500 nm. The thickness of the ferroelectric material portion can range from 10 nm to 100 nm, but smaller and larger thicknesses are also possible. In one embodiment, the channel width of a ferroelectric field-effect transistor implementing an analog non-volatile memory device can be greater than 500 nm, and the channel width of another ferroelectric field-effect transistor implementing a digital random threshold switching device can be less than 100 nm.

[0044] refer to Figure 3A This shows the target Figure 2A The input pulse pattern is shown, and the response curve of the first ferroelectric switching device is a function of the cumulative number of applied input pulses. The first ferroelectric switching device embodies a digital random threshold switching device. In one embodiment, the first ferroelectric switching device may be a digital random threshold switching device. Figure 2B The diagram illustrates a ferroelectric field-effect transistor (FET) with a channel width and length of less than 100 nm. In one embodiment, the FET may include a superscale FET with a width of less than 100 nm and a length of less than 50 nm. This FET exhibits sudden, random switching between discrete states after a number of input pulses. The number of input pulses required to "fire" the switching device is random, i.e., probabilistically distributed across a series of numbers. In one embodiment, the discrete state may be an output signal (e.g., drain current I0). d The output current has two states with different amplitudes. In the illustrative example, the ratio of the output current between the "on" state and the "off" state can be greater than 100.

[0045] refer to Figure 3B This shows the target Figure 2A The input pulse pattern is shown, along with the response curve of the second ferroelectric switching device as a function of the cumulative number of applied input pulses. The second ferroelectric switching device embodies an analog non-volatile memory device. In one embodiment, the second ferroelectric switching device may be a device with… Figure 2B The illustrated configuration shows a large ferroelectric field-effect transistor with a channel width greater than 100 nm. In one embodiment, the channel length of the large ferroelectric field-effect transistor may be greater than 100 nm. In one embodiment, the second ferroelectric switching device may be a... Figure 2BThe diagram illustrates a large ferroelectric field-effect transistor with a channel width greater than 500 nm. In one embodiment, the channel length of the large ferroelectric field-effect transistor can be greater than 500 nm. Statistically, the probability of complete switching of a ferroelectric device comprising multiple ferroelectric domains decreases exponentially as the area of ​​the ferroelectric material portion increases. Therefore, a large ferroelectric field-effect transistor embodying an analog non-volatile memory device provides a gradual switching response through continuous state changes with increasing number of applied input pulses. In one embodiment, the continuous state changes are driven by an output signal (e.g., drain current I0). d The amplitude of the output current is represented by a continuous change. In an illustrative example, the incremental change in the amplitude of the output current when an input pulse is applied can be less than 100% of the amplitude of the output current immediately following a previous measurement, for example, less than 50%. Generally, the output of the second ferroelectric switching device, which embodies an analog non-volatile memory device, can be an analog signal.

[0046] In one embodiment, the area of ​​the ferroelectric material portion in the ferroelectric field-effect transistor can be a parameter that determines whether the ferroelectric field-effect transistor's response characteristics provide a random threshold switching response or a simulated non-volatile memory response. In one embodiment, the channel length of the ferroelectric material portion in the ferroelectric field-effect transistor can be a parameter that determines whether the ferroelectric field-effect transistor's response characteristics provide a random threshold switching response or a simulated non-volatile memory response. In one embodiment, the channel width of the ferroelectric material portion in the ferroelectric field-effect transistor can be a parameter that determines whether the ferroelectric field-effect transistor's response characteristics provide a random threshold switching response or a simulated non-volatile memory response.

[0047] It should be understood that the difference between the random threshold switching response and the analog non-volatile memory response, which are functions of the size of the ferroelectric material portion in the ferroelectric field-effect transistor (FET), is not abrupt, but rather the characteristics of the FET vary smoothly between the random threshold switching response and the analog non-volatile memory response. Generally, the larger the FET, the less random the switching behavior, and the smoother and more continuous the switching behavior. In some embodiments, the channel length of the FET can be a more controllable parameter than the channel width. Some ratios between the channel length and the channel width may or may not be preferred for each switching characteristic, and the sizes of the first and second FETs can be selected to provide a pair of optimized response characteristics based on the computing unit. Generally, the switching probability of each ferroelectric domain depends on the coercive field Ec of the ferroelectric material portion (which may be in the form of a ferroelectric film) and the voltage amplitude / pulse width of the applied pulse sequence. The criteria used to select specific response characteristics depend on the application using the computing device. The switching probability of the ferroelectric polarization in the ferroelectric particles can be tuned by designing the pattern of the pulse sequence.

[0048] refer to Figure 3C This paper illustrates the factors influencing the response characteristics of digital random threshold switching devices. These factors include the phase, particle size, and orientation of the ferroelectric material. For example, the proportions of ferroelectric material in the 0-phase, 1-phase, and 2-phase are important in determining the response characteristics of the ferroelectric portion in a ferroelectric field-effect transistor. The device variability caused by variations in the phase, particle size, and orientation of the ferroelectric material (as introduced during the manufacturing process of the ferroelectric field-effect transistor) increases the randomness of the response of each ferroelectric field-effect transistor. This characteristic can be advantageously used to increase the randomness of digital random threshold switching devices.

[0049] A first ferroelectric device (e.g., a first ferroelectric field-effect transistor) embodying a digital random threshold switching device and a second ferroelectric device (e.g., a second ferroelectric field-effect transistor) embodying an analog non-volatile memory device can be electrically connected within a computing unit in a variety of ways. Figures 4 to 12 An example configuration is shown in which a first ferroelectric device (including a first "smaller" field-effect transistor having a smaller area for the ferroelectric material portion below the first gate electrode) is electrically connected to a second ferroelectric device (including a second "larger" field-effect transistor having a larger area for the ferroelectric material portion below the second gate electrode). Each first ferroelectric field-effect transistor used as a digital random threshold switching device is labeled "smaller," and each second ferroelectric field-effect transistor used as an analog non-volatile memory device is labeled "larger."

[0050] refer to Figure 4 The diagram illustrates a first configuration of a ferroelectric computing unit. The ferroelectric computing unit includes a first ferroelectric switching device (including a "smaller" ferroelectric field-effect transistor), the first ferroelectric switching device including a first ferroelectric material portion (represented by an "N-shaped" symbol located between the first gate electrode and the first current channel of the "smaller" ferroelectric field-effect transistor) and generating a digital output signal, the first ferroelectric material portion having a first area dimension disposed between the first gate electrode and the first current channel, and the first ferroelectric material portion adjusting the conductivity of the first current channel according to a first bias voltage at the first gate electrode. The ferroelectric computing unit includes a second ferroelectric switching device (including a "larger" ferroelectric field-effect transistor), the second ferroelectric switching device including a second ferroelectric material portion (represented by an "N-shaped" symbol located between the second gate electrode and the second current channel of the "larger" ferroelectric field-effect transistor) and generating an analog output signal, the second ferroelectric material portion having a second area size larger than the first area size and disposed between the second gate electrode and the second current channel, and the second ferroelectric material portion adjusting the conductivity of the second current channel according to a second bias voltage at the second gate electrode.

[0051] Generally, the output node of one of the first ferroelectric switching device and the second ferroelectric switching device is electrically connected to the gate electrode of the other. For example, the output node of the second ferroelectric switching device (including the "larger" ferroelectric field-effect transistor) is electrically connected to the first gate electrode of the first ferroelectric switching device (including the "smaller" ferroelectric field-effect transistor).

[0052] In one embodiment, the input signal for the computing unit (e.g., Figure 2A The input pulse shown can be applied to the second gate electrode of the second ferroelectric switching device. In one embodiment, a first resistor (labeled "R") is connected in series with the first ferroelectric switching device between the power supply node Vdd and the electrical ground node Gnd, and a second resistor (labeled "R") is connected in series with the second ferroelectric switching device between the power supply node Vdd and the electrical ground node Gnd.

[0053] Generally, the first ferroelectric switching device (e.g., a "smaller" ferroelectric field-effect transistor) has random switching characteristics, wherein the determination of the digital output signal is probabilistic within the input voltage range of a first bias voltage (which is applied to the first gate electrode of the "smaller" ferroelectric field-effect transistor). In one embodiment, the digital output signal is selected from a set of no more than four discrete output signals. For example, the ferroelectric material portion of the "smaller" field-effect transistor may include no more than three ferroelectric particles. In one embodiment, the digital output signal is selected from a set of no more than three discrete output signals. For example, the ferroelectric material portion of the "smaller" field-effect transistor may include no more than two ferroelectric particles. In one embodiment, the digital output signal is selected from a set of two discrete output signals. In this embodiment, the digital output signal may be a binary signal. For example, the ferroelectric material portion of the "smaller" field-effect transistor may include a single ferroelectric particle.

[0054] In one embodiment, the first ferroelectric material portion includes ferroelectric material domains having the same ferroelectric polarization and occupying at least 80% of the total volume of the first ferroelectric material portion. In this embodiment, the ferroelectric properties of the dominant ferroelectric particles dominate the response characteristics of the "smaller" ferroelectric field-effect transistor. In one embodiment, the second ferroelectric material portion includes at least five ferroelectric material domains (e.g., at least 10 ferroelectric material particles and / or at least 100 ferroelectric particles) occupying a corresponding volume less than 25% of the total volume of the second ferroelectric material portion.

[0055] In one embodiment, the first ferroelectric material portion and the second ferroelectric material portion have the same thickness and the same material composition. In this embodiment, the first ferroelectric switching device (embodying a digital random threshold switching device) and the second ferroelectric switching device (embodying an analog non-volatile memory device with in-memory computing capabilities) can be formed using the same set of processing steps, wherein a ferroelectric material layer is deposited and patterned to form a first ferroelectric material portion having a first area size and a second ferroelectric material portion having a second area size. A common set of patterning steps (e.g., a combination of photolithography photoresist patterning steps and anisotropic etching processes) can be used to pattern the ferroelectric material layer. In one embodiment, the ratio of the second area size to the first area size is in the range of 4 to 1000, for example, in the range of 10 to 300. The lower limit of the ratio of the second area size to the first area size can be determined by the following condition: the second area size should provide continuous switching at a macroscopic level, and the first area size should provide random switching. The upper limit of the ratio of the second area size to the first area size can be determined by the physical size constraints of the device implementing the second area size.

[0056] In one embodiment, the first ferroelectric switching device includes a first field-effect transistor (e.g., a "smaller" ferroelectric field-effect transistor), wherein the first current channel is a first semiconductor channel and the first ferroelectric material portion is part of a first gate dielectric, and the second ferroelectric switching device includes a second field-effect transistor (e.g., a "larger" ferroelectric field-effect transistor), wherein the second current channel is a second semiconductor channel and the second ferroelectric material portion is part of a second gate dielectric.

[0057] refer to Figure 5 The diagram illustrates a second configuration of a ferroelectric computing unit, which can be derived from a first configuration of the ferroelectric computing unit by swapping the positions of a first ferroelectric switching device (including a "smaller" ferroelectric field-effect transistor) and a second ferroelectric switching device (including a "larger" ferroelectric field-effect transistor). The output node of the first ferroelectric switching device (including the "smaller" ferroelectric field-effect transistor) is electrically connected to the second gate electrode of the second ferroelectric switching device (including the "larger" ferroelectric field-effect transistor).

[0058] In one embodiment, the input signal for the computing unit (e.g., Figure 2A The input pulse shown can be applied to the first gate electrode of the first ferroelectric switching device. In one embodiment, a first resistor (labeled "R") is connected in series with the first ferroelectric switching device between the power supply node Vdd and the electrical ground node Gnd, and a second resistor (labeled "R") is connected in series with the second ferroelectric switching device between the power supply node Vdd and the electrical ground node Gnd.

[0059] refer to Figure 6 A third configuration of the ferroelectric computing unit is shown, which can be derived from the first configuration of the ferroelectric computing unit by electrically connecting the drain region of a second ferroelectric switching device (e.g., a "larger" ferroelectric field-effect transistor) to the input node of the ferroelectric computing unit via an input-side resistor (labeled "R"). In this embodiment, the second gate electrode of the second "larger" ferroelectric field-effect transistor can be connected to the input node of the ferroelectric computing unit and can be connected to the drain region of the second ferroelectric switching device via an input-side resistor. In this embodiment, the first ferroelectric switching device (including the "smaller" ferroelectric field-effect transistor) is activated only when the input signal to the ferroelectric computing unit is turned on, i.e., only when the pulse applied to the second gate electrode has a non-zero voltage.

[0060] Generally, the drain region of one of the first and second ferroelectric switching devices can be connected to the input node of the ferroelectric computing unit via an input-side resistor. In this embodiment, the input node of the ferroelectric computing unit can be directly connected to the gate electrode of either the first or second ferroelectric switching device. Specifically, the drain region of the second ferroelectric switching device can be connected to the input node of the ferroelectric computing unit via an input-side resistor, and the input node of the ferroelectric computing unit can be directly connected to the gate electrode of the second ferroelectric switching device. A first resistor (denoted as "R") can be connected in series with the first ferroelectric switching device between the power supply node Vdd and the ground node Gnd. A second resistor (denoted as "R") can be connected in series with the second ferroelectric switching device between the input-side resistor and the ground node Gnd. Optionally, the body of the "smaller" ferroelectric field-effect transistor can be electrically connected to either the source or drain region of the "smaller" ferroelectric field-effect transistor.

[0061] refer to Figure 7 The diagram illustrates a fourth configuration of the ferroelectric computing unit, which can be derived from a third configuration of the ferroelectric computing unit by swapping the positions of the first ferroelectric switching device (including the "smaller" ferroelectric field-effect transistor) and the second ferroelectric switching device (including the "larger" ferroelectric field-effect transistor). The output node of the first ferroelectric switching device (including the "smaller" ferroelectric field-effect transistor) is electrically connected to the second gate electrode of the second ferroelectric switching device (including the "larger" ferroelectric field-effect transistor).

[0062] In one embodiment, the drain region of the first ferroelectric switching device can be connected to the input node of the ferroelectric computing unit via an input-side resistor, and the input node of the ferroelectric computing unit can be directly connected to the gate electrode of the first ferroelectric switching device. A first resistor (labeled "R") can be connected in series with the first ferroelectric switching device between the input-side resistor and the electrical ground node Gnd. A second resistor (labeled "R") can be connected in series with the second ferroelectric switching device between the power supply node Vdd and the electrical ground node Gnd. Optionally, the body of the "larger" ferroelectric field-effect transistor can be electrically connected to either the source or drain region of the "larger" ferroelectric field-effect transistor.

[0063] refer to Figure 8A fifth configuration of the ferroelectric computing unit is shown, which can be derived from either the first or third configuration of the ferroelectric computing unit by providing a Conditional Input Activation Circuit (CIAC). The CIAC can be a feedback circuit that activates or deactivates the input to the ferroelectric computing unit based on a pre-existing output state of the ferroelectric computing unit. In this embodiment, the input signal of the ferroelectric computing unit is applied to the power node of an inverter circuit comprising two transistors connected in series, wherein the two gates of the two transistors are provided with complementary signals generated from the output node of the ferroelectric computing unit. By using a configuration where the output of the inverter circuit is non-zero only when the input signal of the ferroelectric computing unit is non-zero and when the pre-existing output signal of the ferroelectric computing unit is non-zero, the input of the ferroelectric computing unit can be activated or deactivated based on a pre-existing output state of the ferroelectric computing unit, thereby enabling sequential logic. Generally, the inverter circuit can be replaced by any alternative inverter circuit known in the art.

[0064] refer to Figure 9 The diagram illustrates a sixth configuration of the ferroelectric computing unit, which can be derived from either the second or fourth configuration of the ferroelectric computing unit by providing a conditional input activation circuit (CIAC). The inputs to the ferroelectric computing unit can be activated or deactivated based on a pre-existing output state of the ferroelectric computing unit, thereby enabling sequential logic.

[0065] refer to Figure 10 A seventh configuration of the ferroelectric computing unit can be derived from the third or fourth configuration of the ferroelectric computing unit by attaching a third ferroelectric switching device including a third ferroelectric material portion. The third ferroelectric material portion can be disposed between the third gate electrode and the third current channel of the third ferroelectric switching device, and the third ferroelectric material portion can adjust the conductivity of the third current channel according to the third bias voltage at the third gate electrode. The third ferroelectric switching device generates an additional analog output signal, which is added to the analog output signal of the second ferroelectric switching device. In one embodiment, one of the second and third ferroelectric switching devices may include a p-type field-effect transistor, and the other of the second and third ferroelectric switching devices may include an n-type field-effect transistor. The third gate electrode can be electrically connected to the second gate electrode. In one embodiment, the second and third gate electrodes can be directly connected to the input node of the ferroelectric computing unit. In one embodiment, the second ferroelectric switching device can be implemented as a larger n-type ferroelectric field-effect transistor, and the third ferroelectric switching device can be implemented as a larger p-type ferroelectric field-effect transistor. Optionally, the electrical connections to the power supply node Vdd and the electrical ground node Gnd for the series connection of the first ferroelectric switching device and the resistor can be reversed.

[0066] The combination of the second and third ferroelectric switching devices can be used as an analog non-volatile memory device with in-memory computing capabilities. In this embodiment, by competitively activating and deactivating the corresponding current channels when an input pulse is applied to the ferroelectric computing unit, one of the second and third ferroelectric switching devices can be used to provide an enhancement of the output voltage (i.e., an increase in the combined output), and the other of the second and third ferroelectric switching devices can be used to provide a suppression of the output voltage (i.e., a reduction in the combined output).

[0067] In one embodiment, the enhancement mechanism (i.e., the mechanism for inducing a positive change in the output) and the suppression mechanism (i.e., the mechanism for inducing a negative change in the output) can share the same input signal path and can have output paths that are additively connected (e.g., through a parallel connection connected in series to the same voltage divider element (e.g., a resistor). Generally, different input and output interface / signal integration schemes can be used. Spike-timing-dependent plasticity (STDP) can be achieved by incorporating delayed feedback from the output of the first ferroelectric switching device, allowing the state holder to adapt via an update function. The exact delay length depends on the task at hand and the pulse width / period of the input signal.

[0068] refer to Figure 11 The eighth configuration of the ferroelectric computing unit can be derived from any of the first, second, third, and fourth configurations of the ferroelectric computing unit by connecting the output node of the ferroelectric computing unit to the input node of the ferroelectric computing unit via an amplifier that does not reverse the polarity of the output signal. Depending on the nature of the electrical connection between the first and second ferroelectric switching devices, the feedback circuit can stabilize the state of the output node of the ferroelectric computing unit (i.e., enhance the stability of the signal at the output node), or it can reverse the state of the output node of the ferroelectric computing unit (i.e., flip the output at the output node of the ferroelectric computing unit, thereby generating an oscillating signal (which can oscillate randomly with random changes in the duration of the pulse)).

[0069] refer to Figure 12The ninth configuration of the ferroelectric computing unit can be derived from any of the first, second, third, and fourth configurations of the ferroelectric computing unit by connecting the output node of the ferroelectric computing unit to the input node of the ferroelectric computing unit via an inverter that reverses the polarity of the output signal. Depending on the nature of the electrical connection between the first and second ferroelectric switching devices, the feedback circuit can stabilize the state of the output node of the ferroelectric computing unit (i.e., enhance the stability of the signal at the output node), or it can reverse the state of the output node of the ferroelectric computing unit (i.e., flip the output at the output node of the ferroelectric computing unit, thereby generating an oscillating signal (which can oscillate randomly with random changes in the duration of the pulse)).

[0070] exist Figures 4 to 12 Each ferroelectric calculation unit shown depicts an n-type ferroelectric field-effect transistor. The corresponding n-type ferroelectric field-effect transistor can be replaced with a p-type ferroelectric field-effect transistor (and vice versa), from... Figures 4 to 12 Each example shown generates a mirrored circuit. Furthermore, Figures 4 to 12 All resistors in the circuit can be replaced by passive or active circuit elements that generate voltage. Therefore, Figures 4 to 12 Each resistor in the circuit can be a passive or active component, or it can have voltage amplification capabilities (e.g., an operational amplifier).

[0071] Common Reference Figures 4 to 12 A device including a computing unit is provided. The computing unit includes a digital output switching device (e.g., a first ferroelectric switching device) that generates a digital output signal and includes a first current channel having a first area dimension and providing regulated conductivity based on a first bias voltage at a first gate electrode located near the first current channel. Furthermore, the computing unit includes an analog output switching device (e.g., a second ferroelectric switching device) that generates an analog output signal and includes a second current channel having a second area dimension and providing regulated conductivity based on a second bias voltage at a second gate electrode located near the second current channel. The output node of one of the first and second ferroelectric switching devices is electrically connected to the gate electrode of the other.

[0072] In one embodiment, the digital output switching device includes a first ferroelectric switching device having a first ferroelectric material portion having a first area size, and the analog output switching device includes a second ferroelectric switching device having a second ferroelectric material portion having a second area size.

[0073] In one embodiment, the digital output signal includes two distinct output states, which provide at least 10 (e.g., from 1.0 x 10) 2 Up to 1.0x 10 9 , and / or from 1.0x10 3 Up to 1.0x 10 6 The output voltage ratio or at least 10 (e.g., from 1.0 x 10) 2 Up to 1.0x 10 9 , and / or from 1.0x 10 3 Up to 1.0x 10 6 The output current ratio. In one embodiment, the analog output signal includes at least ten output states, which provide an output voltage ratio of less than 2 (which may be in the range of 0.5 to 2.0 and / or 0.8 to 1.25 and / or 0.9 to 1.1) or an output current ratio of less than 2 (which may be in the range of 0.5 to 2.0 and / or 0.8 to 1.25 and / or 0.9 to 1.1) between any two adjacent pairs of output states selected from a set of output states ordered in ascending order of the magnitude of the output voltage or output current of the at least ten output states.

[0074] In one embodiment, the computing unit includes at least one feature selected from the following features. The first feature may be a first resistor and a first ferroelectric switching device connected in series between a power supply node Vdd and an electrical ground node Gnd, and a second resistor and a second ferroelectric switching device connected in series between a power supply node Vdd and an electrical ground node, such as... Figure 4 , Figure 5 , Figure 11 and Figure 12 As shown. The second feature may be that the drain region of one of the first ferroelectric switching device and the second ferroelectric switching device is connected to the input node of the ferroelectric computing unit through an input-side resistor, such as... Figure 6 , Figure 7 and Figure 10 As shown. The third feature is that the output node of the ferroelectric computing unit is connected to the input node of the ferroelectric computing unit in a manner that stabilizes the state of the output node of the ferroelectric computing unit, such as... Figure 11 and Figure 12 As shown. The fourth feature is that the output node of the ferroelectric computing unit is connected to the input node of the ferroelectric computing unit in a manner that overturns the state of the output node of the ferroelectric computing unit, as shown. Figure 11 and Figure 12 As shown. Additional features are in Figure 8 and Figure 9 As shown in the image.

[0075] Although Figure 2BA planar ferroelectric field-effect transistor is shown, comprising a planar (i.e., two-dimensional) horizontal semiconductor channel between the source and drain regions; however, any other configuration of the ferroelectric field-effect transistor may also be used to implement the ferroelectric computing unit of this disclosure.

[0076] refer to Figure 13A and Figure 13B This diagram illustrates a semiconductor-on-insulator (SOI) ferroelectric field-effect transistor (FET) formed using a semiconductor-on-insulator (SOI) substrate. The SOI FET includes a semiconductor substrate 10, a buried insulator layer 20, and a semiconductor-on-insulator fin including a current channel layer 35, which may be a semiconductor channel layer. The current channel layer 35 may include and / or may consist substantially of: doped silicon, doped silicon-germanium alloy, doped germanium, doped III-V compound semiconductor material, doped II-V compound semiconductor material, semiconductor metal oxide material, or organic semiconductor material. Source region 42 and drain region 48 may be formed at the ends of the current channel layer 35. Source region 42 and drain region 48 may include doped semiconductor material or may include metallization material, such as metal silicide material (e.g., nickel silicide). A gate dielectric including a ferroelectric material portion 52 may be formed over the current channel layer 35. In one embodiment, the gate dielectric may comprise a stack of layers of a nonferroelectric gate dielectric layer 50 and a ferroelectric material portion 52 comprising a film of uniform thickness. The thickness of the ferroelectric material portion 52 may range from 10 nm to 100 nm, but smaller and larger thicknesses may also be used. A gate electrode 54 comprising a gate conductor material may be disposed on the gate dielectric. A source contact via structure 62 may contact the source region 42, and a drain contact via structure 68 may contact the drain region 48. Optionally, amorphous indium gallium zinc oxide (IGGaZO) may be used as a capping material layer (not shown) to serve as an effective capping material for the ferroelectric material portion 52 and may help form a ferroelectric phase in the ferroelectric material portion 52 during an annealing process performed after the formation of the gate electrode 54.

[0077] refer to Figure 14A and Figure 14BThis illustrates a bulk ferroelectric field-effect transistor (FFET) formed using a bulk semiconductor substrate 109. The bulk semiconductor substrate 109 may comprise a single-crystal semiconductor material such as single-crystal silicon. The bulk FFET includes a semiconductor fin 30 (including a portion of the single-crystal semiconductor material) comprising the same semiconductor material as the bulk semiconductor substrate 109 and epitaxially aligned with the bulk semiconductor substrate 109. A shallow trench isolation structure 22 may be formed around the semiconductor fin 30, and a gate stack may be formed across the semiconductor fin 30. The gate stack may include a gate dielectric and a gate electrode 54. The gate dielectric includes a ferroelectric material portion 52. In one embodiment, the gate dielectric may comprise a layer stack of a non-ferroelectric gate dielectric layer 50 and a ferroelectric material portion 52 comprising a film having a uniform thickness. The thickness of the ferroelectric material portion 52 may range from 10 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0078] The portion of the semiconductor fin 30 not masked by the gate stack may be doped with implanted electrical dopant to form source region 32 and drain region 38. The portion of the semiconductor fin 30 not doped with implanted electrical dopant includes a current channel layer 35. A source contact via structure 62 provides electrical contact to source region 32, and a drain contact via structure 68 provides electrical contact to drain region 38. Optionally, amorphous indium gallium zinc oxide (IGZO) may be used as a capping material layer (not shown) as an effective capping material for ferroelectric portion 52 and can help form a ferroelectric phase in ferroelectric portion 52 during an annealing process performed after the formation of gate electrode 54.

[0079] refer to Figure 15This illustrates a ferroelectric field-effect transistor using alternative source and drain regions. A shallow trench isolation structure 12 can be formed in the upper portion of a bulk semiconductor substrate 109. A gate dielectric can be formed on the top surface of the bulk semiconductor substrate 109. A sacrificial gate structure comprising a dielectric material (e.g., silicon nitride) can be formed on the gate dielectric. The volume of the sacrificial gate structure can be the same as the volume occupied by the combination of the ferroelectric material portion 52 and the gate electrode 54. An anisotropic etching process can be performed to form source and drain cavities in the upper portion of the bulk semiconductor substrate 109 that is not occupied by the shallow trench isolation structure 12 and is not masked by the sacrificial gate structure. A selective epitaxial process can be performed to selectively grow source regions 32 and drain regions 38 comprising a single-crystal semiconductor material different from the semiconductor material of the bulk semiconductor substrate 109. For example, the source region 32 and drain region 38 may include a doped silicon-carbide compound or a doped silicon-germanium compound capable of applying mechanical stress to the current channel layer 35, which is a surface portion of the bulk semiconductor substrate 109 located between the source region 32 and the drain region 38. Due to the mechanical stress, the charge carrier mobility in the current channel layer 35 can be enhanced.

[0080] Subsequently, a planarization dielectric layer 70 comprising a planarizable dielectric material (e.g., silicon oxide) can be deposited around the sacrificial gate electrode. The sacrificial gate electrode can be selectively removed relative to the gate dielectric and the planarization dielectric layer 70 by a selective etching process; in embodiments where the sacrificial gate electrode comprises silicon nitride, this selective etching process may include a wet etching process using hot phosphoric acid. By depositing and planarizing the ferroelectric material and the gate electrode material, an L-shaped ferroelectric material portion 52 and a gate electrode 54 can be formed within the gate cavity formed by removing the sacrificial gate electrode. Optionally, amorphous indium gallium zinc oxide (not shown) can be used as a capping material layer to serve as an effective capping material for the ferroelectric material portion 52 and can help form a ferroelectric phase in the ferroelectric material portion 52 during an annealing process, which can be performed after the formation of the gate electrode 54. A contact-level dielectric layer 72 can be formed over the planarization dielectric layer 70. The source contact via structure 62 provides electrical contact to the source region 32, and the drain contact via structure 68 provides electrical contact to the drain region 38. Optionally, a source-side metal-semiconductor alloy portion 41 and a drain-side metal-semiconductor alloy portion 49 may be formed. Subsequently, a line-level dielectric layer 74 may be formed, and source interconnects 82 and drain interconnects 84 may be formed in this line-level dielectric layer 74.

[0081] Generally, any type of field-effect transistor known in the art can be used as a ferroelectric field-effect transistor embodying any of the ferroelectric computing units described above. For example, planar ferroelectric field-effect transistors, fin ferroelectric field-effect transistors, omega ferroelectric field-effect transistors, nanowire ferroelectric field-effect transistors, nanosheet ferroelectric field-effect transistors, and other types of field-effect transistors can be used. Any type of semiconductor material can be used for the current channel layer 35.

[0082] The use of ferroelectric field-effect transistors provides an integration scheme for fabricating the ferroelectric computing units of this disclosure in a manner compatible with standard logic processes in semiconductor manufacturing. However, the conductive medium used to provide the current channel layer is not limited to semiconductor materials, and ions or electrolytes can be used as charge carriers. When the ferroelectric field-effect transistor is used as a ferroelectric switching device, each current channel can be a semiconductor channel.

[0083] refer to Figure 16 This illustration shows an exemplary electrolyte-based ferroelectric switching device according to an embodiment of the present disclosure, comprising, from bottom to top, a first electrode 110, an organic conductive polymer layer 120, a matrix material layer 130 (including an electrolyte 133), a ferroelectric material portion 52 (which includes a ferroelectric material layer having a uniform thickness and having ferroelectric polarization 142 pointing towards or away from the first electrode 110), and a second electrode 150. The first electrode 110 and the second electrode 150 may include conductive materials (e.g., corresponding metallization materials), and / or may be substantially composed of conductive materials (e.g., corresponding metallization materials). The organic conductive polymer layer 120 includes a conductive polymer material capable of transporting electrolyte ions. Exemplary materials that can be used in the organic conductive polymer layer 120 include, but are not limited to, poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS), which is an organic mixed ion-electron conductive polymer material. The PEDOT phase transports holes and has redox activity, while the PSS phase transports ions. The matrix material layer 130 may be a liquid layer or may include a porous solid material comprising pores that provide lateral transport of the electrolyte 133.

[0084] An exemplary electrolyte-based ferroelectric switching device is an electrochemical device in which ferroelectric polarization 142 in the ferroelectric material portion 52 modulates the electrical conduction of the electrolyte 133 through the matrix material layer 130. In this case, each first ferroelectric switching device may include a first electrolyte-based ferroelectric switching device having a first current channel, and each second ferroelectric switching device may include a second electrolyte-based ferroelectric switching device having a second current channel. In this embodiment, the first current channel includes a first matrix material layer containing a first electrolyte and in contact with the first ferroelectric material portion, and the second current channel includes a second matrix material layer containing a second electrolyte and in contact with the second ferroelectric material portion. Generally, the first and second matrix material layers can be formed by patterning the same matrix material layer having a uniform thickness, and the first electrolyte may be the same as the second electrolyte. Generally, each layer within the first ferroelectric switching device may have the same material composition and the same thickness as a corresponding layer within the second ferroelectric switching device. The area of ​​each layer within the second ferroelectric switching device may be 4 to 1000 times larger than the area of ​​a corresponding layer within the first ferroelectric switching device, for example, 10 to 300 times larger.

[0085] refer to Figure 17 This illustration shows an exemplary in-memory computing device including multiple instances of a ferroelectric computing unit 300 according to embodiments of the present disclosure. Each ferroelectric computing unit 300 can be any of the ferroelectric computing units described above. Therefore, in addition to the ferroelectric computing unit 300, additional ferroelectric computing units 300 may be provided, including combinations of corresponding additional first ferroelectric switching devices and corresponding additional second ferroelectric switching devices. The ferroelectric computing units 300 and the additional computing units 300 may be electrically connected to each other to provide a neuromorphic computing device including multiple input nodes.

[0086] refer to Figure 18 The flowchart illustrates the general processing steps for manufacturing the ferroelectric computing unit of this disclosure.

[0087] Common reference steps 1810 and Figures 1 to 17 A current channel material layer comprising charge carriers that move in response to an external electric field can be formed on the substrate.

[0088] Common reference steps 1820 and Figures 1 to 17 A ferroelectric material layer and a gate electrode layer can be formed on top of the current channel material layer.

[0089] Common reference steps 1830 and Figures 1 to 17 The gate electrode layer and the ferroelectric material layer can be patterned into a first gate electrode (e.g., Figures 13A to 15 Gate electrode 54 or Figure 16The second electrode 150) and the first gate stack of the first ferroelectric material portion and the second gate electrode (e.g., Figures 13A to 15 Gate electrode 54 or Figure 16 The second electrode 150) and the second gate stack of the second ferroelectric material portion. The portion of the current channel material layer located below the first ferroelectric material portion includes the first current channel (e.g., Figures 13A to 15 Current channel layer 35 or Figure 16 The matrix material layer 130 in the middle), and the portion of the current channel material layer located below the second ferroelectric material portion includes a second current channel (e.g., Figures 13A to 15 Current channel layer 35 or Figure 16 The matrix material layer 130 in the middle.

[0090] Common reference steps 1840 and Figures 1 to 17 A ferroelectric computing unit comprising a first ferroelectric switching device and a second ferroelectric switching device can be formed by electrically connecting a first current channel, a second current channel, a first gate electrode, and a second gate electrode. The first ferroelectric switching device generates a digital output signal. The second ferroelectric switching device generates an analog output signal. The output node of one of the first and second ferroelectric switching devices is electrically connected to the gate electrode of the other of the first and second ferroelectric switching devices.

[0091] In one embodiment, the first ferroelectric material portion includes ferroelectric material domains having the same ferroelectric polarization and occupying at least 80% of the total volume of the first ferroelectric material portion, and the second ferroelectric material portion includes at least five ferroelectric material domains occupying a corresponding volume of less than 25% of the total volume of the second ferroelectric material portion.

[0092] In one embodiment, the first ferroelectric material portion has a first area size, the second ferroelectric material portion has a second area size, and the ratio of the second area size to the first area size is in the range of 4 to 1000.

[0093] In one embodiment, the first ferroelectric switching device includes a first field-effect transistor, wherein the first current channel is a first semiconductor channel, and the second ferroelectric switching device includes a second field-effect transistor, wherein the second current channel is a second semiconductor channel.

[0094] In one embodiment, the current channel material layer includes a matrix material layer containing an electrolyte.

[0095] Generally, devices of the same type but with different sizes can be used to provide the functions of digital output switching devices for generating digital output signals and analog output switching devices for generating analog output signals. The various ferroelectric computing units disclosed herein can provide neuromorphic computing devices with high performance, small size, and low power consumption.

[0096] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0097] Example 1. A ferroelectric device, comprising a ferroelectric calculation unit, the ferroelectric calculation unit comprising:

[0098] A first ferroelectric switching device includes a first ferroelectric material portion and generates a digital output signal. The first ferroelectric material portion has a first area and is disposed between a first gate electrode and a first current channel. The first ferroelectric material portion adjusts the conductivity of the first current channel according to a first bias voltage at the first gate electrode.

[0099] The second ferroelectric switching device includes a second ferroelectric material portion and generates an analog output signal. The second ferroelectric material portion has a second area size larger than the first area size and is disposed between a second gate electrode and a second current channel. The second ferroelectric material portion adjusts the conductivity of the second current channel according to a second bias voltage at the second gate electrode.

[0100] The output node of one of the first ferroelectric switching devices and the second ferroelectric switching device is electrically connected to the gate electrode of the other of the first ferroelectric switching device and the second ferroelectric switching device.

[0101] Example 2. The ferroelectric device according to Example 1, wherein the first ferroelectric switching device has random switching characteristics, wherein the determination of the digital output signal is probabilistic within the input voltage range of the first bias voltage.

[0102] Example 3. The ferroelectric device according to Example 1, wherein the digital output signal is selected from a set of no more than four discrete output signals.

[0103] Example 4. The ferroelectric device according to Example 1, wherein:

[0104] The first ferroelectric material portion includes ferroelectric material domains having the same ferroelectric polarization and occupying at least 80% of the total volume of the first ferroelectric material portion; and

[0105] The second ferroelectric material portion includes at least five ferroelectric material domains, which occupy a corresponding volume of less than 25% of the total volume of the second ferroelectric material portion.

[0106] Example 5. The ferroelectric device according to Example 1, wherein the first ferroelectric material portion and the second ferroelectric material portion have the same thickness and the same material composition.

[0107] Example 6. The ferroelectric device according to Example 5, wherein the ratio of the second area size to the first area size is in the range of 4 to 1000.

[0108] Example 7. The ferroelectric device according to Example 1, wherein:

[0109] The first ferroelectric switching device includes a first field-effect transistor, wherein the first current channel is a first semiconductor channel, and the first ferroelectric material portion is part of the first gate dielectric; and

[0110] The second ferroelectric switching device includes a second field-effect transistor, wherein the second current channel is a second semiconductor channel, and the second ferroelectric material portion is part of the second gate dielectric.

[0111] Example 8. The ferroelectric device according to Example 1, wherein:

[0112] The first current channel includes a first matrix material layer, the first matrix material layer including a first electrolyte and in contact with the first ferroelectric material portion; and

[0113] The second current channel includes a second matrix material layer, which includes a second electrolyte and is in contact with the second ferroelectric material portion.

[0114] Example 9. The ferroelectric device according to Example 1, wherein the ferroelectric device includes at least one feature selected from the following:

[0115] First feature: The first resistor is connected in series with the first ferroelectric switching device between the power supply node and the electrical ground node, and the second resistor is connected in series with the second ferroelectric switching device between the power supply node and the electrical ground node.

[0116] Second feature: The drain region of one of the first ferroelectric switching device and the second ferroelectric switching device is connected to the input node of the ferroelectric computing unit through an input-side resistor;

[0117] The third feature: the output node of the ferroelectric computing unit is connected to the input node of the ferroelectric computing unit in a manner that stabilizes the state of the output node; and

[0118] Fourth feature: The output node of the ferroelectric computing unit is connected to the input node of the ferroelectric computing unit in a manner that overturns the state of the output node of the ferroelectric computing unit.

[0119] Example 10. The ferroelectric device according to Example 1, wherein the ferroelectric computing unit includes a conditional input activation circuit that activates or deactivates inputs to the ferroelectric computing unit based on a pre-existing output state of the ferroelectric computing unit.

[0120] Example 11. The ferroelectric device according to Example 1, wherein:

[0121] The ferroelectric calculation unit includes a third ferroelectric switching device, which includes a third ferroelectric material portion and generates an additional analog output signal. The third ferroelectric material portion is disposed between a third gate electrode and a third current channel, and the third ferroelectric material portion adjusts the conductivity of the third current channel according to a third bias voltage at the third gate electrode. The additional analog output signal is added to the analog output signal of the second ferroelectric switching device.

[0122] One of the second and third ferroelectric switching devices includes a p-type field-effect transistor, and the other of the second and third ferroelectric switching devices includes an n-type field-effect transistor; and

[0123] The third gate electrode is electrically connected to the second gate electrode.

[0124] Example 12. The ferroelectric device according to Example 1 further includes an additional ferroelectric computing unit, comprising a combination of a corresponding additional first ferroelectric switching device and a corresponding additional second ferroelectric switching device, wherein the ferroelectric computing unit and the additional computing unit are electrically connected to each other to provide a neuromorphic computing device including multiple input nodes.

[0125] Example 13. A device including a computing unit, the computing unit comprising:

[0126] A digital output switching device that generates a digital output signal and includes a first current channel that provides regulated conductivity based on a first bias voltage at a first gate electrode located near the first current channel; and

[0127] An analog output switching device generates an analog output signal and includes a second current channel that provides regulated conductivity based on a second bias voltage at a second gate electrode located near the second current channel.

[0128] The output node of one of the first ferroelectric switching devices and the second ferroelectric switching device is electrically connected to the gate electrode of the other of the first ferroelectric switching device and the second ferroelectric switching device.

[0129] Example 14. The device according to Example 13, wherein:

[0130] The digital output switching device includes a first ferroelectric switching device, the first ferroelectric switching device including a first ferroelectric material portion having a first area size; and

[0131] The analog output switching device includes a second ferroelectric switching device, which includes a second ferroelectric material portion having a second area dimension.

[0132] Example 15. The device according to Example 13, wherein:

[0133] The digital output signal includes two distinct output states, which provide an output voltage ratio of at least 10 or an output current ratio of at least 10; and

[0134] The analog output signal includes at least ten output states, which provide an output voltage ratio of less than 2 or an output current ratio of less than 2 between any two adjacent pairs of output states selected from a set of output states ordered in ascending order of the magnitude of the output voltage or output current of the at least ten output states.

[0135] Example 16. The device according to Example 13, wherein the computing unit includes at least one feature selected from the following:

[0136] First feature: The first resistor is connected in series with the first ferroelectric switching device between the power supply node and the electrical ground node, and the second resistor is connected in series with the second ferroelectric switching device between the power supply node and the electrical ground node.

[0137] Second feature: The drain region of one of the first ferroelectric switching device and the second ferroelectric switching device is connected to the input node of the ferroelectric computing unit through an input-side resistor;

[0138] The third feature: the output node of the ferroelectric computing unit is connected to the input node of the ferroelectric computing unit in a manner that stabilizes the state of the output node; and

[0139] Fourth feature: The output node of the ferroelectric computing unit is connected to the input node of the ferroelectric computing unit in a manner that overturns the state of the output node of the ferroelectric computing unit.

[0140] Example 17. A method for manufacturing a ferroelectric device including a ferroelectric computing unit, comprising:

[0141] A current channel material layer comprising charge carriers that move in response to an external electric field is formed on the substrate;

[0142] A ferroelectric material layer and a gate electrode layer are formed on the current channel material layer;

[0143] The gate electrode layer and the ferroelectric material layer are patterned into a first gate stack of a first gate electrode and a first ferroelectric material portion, and a second gate stack of a second gate electrode and a second ferroelectric material portion, wherein the portion of the current channel material layer below the first ferroelectric material portion includes a first current channel, and the portion of the current channel material layer below the second ferroelectric material portion includes a second current channel; and

[0144] By electrically connecting the first current channel, the second current channel, the first gate electrode, and the second gate electrode, a ferroelectric computing unit including a first ferroelectric switching device and a second ferroelectric switching device is formed, wherein:

[0145] The first ferroelectric switching device generates a digital output signal;

[0146] The second ferroelectric switching device generates an analog output signal; and

[0147] The output node of one of the first ferroelectric switching devices and the second ferroelectric switching device is electrically connected to the gate electrode of the other of the first ferroelectric switching device and the second ferroelectric switching device.

[0148] Example 18. The method described in Example 17, wherein:

[0149] The first ferroelectric material portion includes ferroelectric material domains having the same ferroelectric polarization and occupying at least 80% of the total volume of the first ferroelectric material portion; and

[0150] The second ferroelectric material portion includes at least five ferroelectric material domains, which occupy a corresponding volume of less than 25% of the total volume of the second ferroelectric material portion.

[0151] Example 19. The method described in Example 17, wherein:

[0152] The first ferroelectric material portion has a first area dimension;

[0153] The second ferroelectric material portion has a second area dimension; and

[0154] The ratio of the second area size to the first area size is in the range of 4 to 1000.

[0155] Example 20. The method according to Example 17, wherein the method includes features selected from the following:

[0156] First feature: The first ferroelectric switching device includes a first field-effect transistor, wherein the first current channel is a first semiconductor channel; and the second ferroelectric switching device includes a second field-effect transistor, wherein the second current channel is a second semiconductor channel; and

[0157] Second feature: The current channel material layer includes a matrix material layer containing an electrolyte.

Claims

1. A ferroelectric device comprising a ferroelectric computing unit, the ferroelectric computing unit comprising: a first ferroelectric switching device, the first ferroelectric switching device comprising a first ferroelectric material portion and generating a digital output signal, the first ferroelectric material portion having a first area dimension and disposed between a first gate electrode and a first current channel, and the first ferroelectric material portion adjusting a conductivity of the first current channel according to a first bias voltage at the first gate electrode; and a second ferroelectric switching device, the second ferroelectric switching device comprising a second ferroelectric material portion and generating an analog output signal, the second ferroelectric material portion having a second area dimension greater than the first area dimension and disposed between a second gate electrode and a second current channel, and the second ferroelectric material portion adjusting a conductivity of the second current channel according to a second bias voltage at the second gate electrode, wherein an output node of one of the first and second ferroelectric switching devices is electrically connected to a gate electrode of the other of the first and second ferroelectric switching devices. The first ferroelectric switching device has a stochastic switching characteristic, wherein a determination of the digital output signal is probabilistic over an input voltage range of the first bias voltage.

2. The ferroelectric device of claim 1, wherein, The digital output signal is selected from a set of no more than four discrete output signals.

3. The ferroelectric device of claim 1, wherein, 4. The ferroelectric device of claim 1, wherein: the first ferroelectric material portion comprises a ferroelectric material domain having a same ferroelectric polarization therein and occupying at least 80% of an entire volume of the first ferroelectric material portion; and the second ferroelectric material portion comprises at least five ferroelectric material domains occupying respective volumes that are less than 25% of an entire volume of the second ferroelectric material portion. The first and second ferroelectric material portions have a same thickness and a same material composition.

5. The ferroelectric device of claim 1, wherein, A ratio of the second area dimension to the first area dimension is in a range of 4 to 1000.

6. The ferroelectric device of claim 5, wherein, 7. The ferroelectric device of claim 1, wherein: the first ferroelectric switching device comprises a first field effect transistor, wherein the first current channel is a first semiconductor channel and the first ferroelectric material portion is part of a first gate dielectric; and the second ferroelectric switching device comprises a second field effect transistor, wherein the second current channel is a second semiconductor channel and the second ferroelectric material portion is part of a second gate dielectric.

8. The ferroelectric device of claim 1, wherein: the first current channel comprises a first matrix material layer comprising a first electrolyte and in contact with the first ferroelectric material portion; and the second current channel comprises a second matrix material layer comprising a second electrolyte and in contact with the second ferroelectric material portion. The ferroelectric device comprises at least one feature selected from the following:

9. The ferroelectric device of claim 1, wherein, a. the first ferroelectric material portion comprises a ferroelectric material domain having a same ferroelectric polarization therein and occupying at least 80% of an entire volume of the first ferroelectric material portion; and b. the second ferroelectric material portion comprises at least five ferroelectric material domains occupying respective volumes that are less than 25% of an entire volume of the second ferroelectric material portion. a first resistor is connected in series with the first ferroelectric switching device between a power supply node and an electrical ground node, and a second resistor is connected in series with the second ferroelectric switching device between the power supply node and the electrical ground node; a drain region of one of the first ferroelectric switching device and the second ferroelectric switching device is connected to an input node of the ferroelectric computing unit through an input-side resistor; an output node of the ferroelectric computing unit is connected to an input node of the ferroelectric computing unit in a manner that stabilizes a state of the output node of the ferroelectric computing unit; and an output node of the ferroelectric computing unit is connected to an input node of the ferroelectric computing unit in a manner that destabilizes a state of the output node of the ferroelectric computing unit. The ferroelectric computing unit includes a conditional input activation circuit that activates or deactivates an input to the ferroelectric computing unit based on a pre-existing output state of the ferroelectric computing unit.

10. The ferroelectric device of claim 1, wherein, 11. The ferroelectric device of claim 1, wherein: the ferroelectric computing unit includes a third ferroelectric switching device that includes a third ferroelectric material portion disposed between a third gate electrode and a third current channel, and that generates an additional analog output signal, the third ferroelectric material portion adjusting a conductivity of the third current channel as a function of a third bias voltage at the third gate electrode, the additional analog output signal being summed with the analog output signal of the second ferroelectric switching device; one of the second ferroelectric switching device and the third ferroelectric switching device includes a p-type field effect transistor, and the other of the second ferroelectric switching device and the third ferroelectric switching device includes an n-type field effect transistor; and the third gate electrode is electrically connected to the second gate electrode. The ferroelectric computing unit and the additional ferroelectric computing unit are electrically connected to each other to provide a neuromorphic computing device that includes a plurality of input nodes.

13. A device including a computing unit, the computing unit including:

12. The ferroelectric device of claim 1, further comprising an additional ferroelectric computing unit comprising a combination of a respective additional first ferroelectric switching device and a respective additional second ferroelectric switching device, wherein, a digital output switching device that generates a digital output signal and that includes a first current channel that provides an adjusted conductivity as a function of a first bias voltage at a first gate electrode located proximate to the first current channel; and an analog output switching device that generates an analog output signal and that includes a second current channel that provides an adjusted conductivity as a function of a second bias voltage at a second gate electrode located proximate to the second current channel, wherein an output node of one of the digital output switching device and the analog output switching device is electrically connected to a gate electrode of the other of the digital output switching device and the analog output switching device.

14. The device of claim 13, wherein: the digital output switching device includes a first ferroelectric switching device that includes a first ferroelectric material portion having a first area dimension; and the analog output switching device includes a second ferroelectric switching device that includes a second ferroelectric material portion having a second area dimension that is different than the first area dimension. ​ ​ The analog output switching device includes a second ferroelectric switching device including a second ferroelectric material portion having a second area size.

15. The device of claim 13, wherein: The digital output signal includes two different output states providing an output voltage ratio of at least 10 or an output current ratio of at least 10; and The analog output signal includes at least ten output states providing an output voltage ratio of less than 2 or an output current ratio of less than 2 between any two adjacent output state pairs selected from a set of output states ordered in increasing order of magnitude of output voltage or output current of the at least ten output states.

16. The device of claim 13, wherein the computing unit includes at least one feature selected from the following: a first feature: a first resistor is connected in series with the digital output switching device between a power supply node and an electrical ground node, and a second resistor is connected in series with the analog output switching device between the power supply node and the electrical ground node; a second feature: a drain region of one of the digital output switching device and the analog output switching device is connected to an input node of the computing unit through an input-side resistor; a third feature: an output node of the computing unit is connected to an input node of the computing unit in a manner that stabilizes a state of the output node of the computing unit; and a fourth feature: an output node of the computing unit is connected to an input node of the computing unit in a manner that subverts a state of the output node of the computing unit.

17. A method of manufacturing a ferroelectric device including a ferroelectric computing unit, comprising: forming a current channel material layer including charge carriers that move in response to an external electric field over a substrate; forming a ferroelectric material layer and a gate electrode layer over the current channel material layer; patterning the gate electrode layer and the ferroelectric material layer into a first gate stack of a first gate electrode and a first ferroelectric material portion, and a second gate stack of a second gate electrode and a second ferroelectric material portion, wherein a portion of the current channel material layer under the first ferroelectric material portion includes a first current channel, and a portion of the current channel material layer under the second ferroelectric material portion includes a second current channel; and forming a ferroelectric computing unit including a first ferroelectric switching device and a second ferroelectric switching device by electrically connecting the first current channel, the second current channel, the first gate electrode, and the second gate electrode, wherein: the first ferroelectric switching device generates a digital output signal; the second ferroelectric switching device generates an analog output signal; and an output node of one of the first ferroelectric switching device and the second ferroelectric switching device is electrically connected to a gate electrode of the other of the first ferroelectric switching device and the second ferroelectric switching device.

18. The method of claim 17, wherein: ​ the first ferroelectric material portion includes a ferroelectric material domain having a same ferroelectric polarization therein and occupying at least 80% of an entire volume of the first ferroelectric material portion; and the second ferroelectric material portion includes at least five ferroelectric material domains occupying respective volumes that are less than 25% of an entire volume of the second ferroelectric material portion.

19. The method of claim 17, wherein: the first ferroelectric material portion has a first area dimension; the second ferroelectric material portion has a second area dimension; and a ratio of the second area dimension to the first area dimension is in a range of 4 to 1000.

20. The method of claim 17, wherein, the method includes a feature selected from: a first feature: the first ferroelectric switching device includes a first field effect transistor, wherein the first current channel is a first semiconductor channel, and the second ferroelectric switching device includes a second field effect transistor, wherein the second current channel is a second semiconductor channel; and a second feature: the current channel material layer includes a matrix material layer having an electrolyte contained therein.

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