A double-fault error calculation method for binary all-optical full adder

Abstract

The present invention proposes a method for calculating the double fault errors of a binary all-optical full adder. This fault error calculation involves the field of double fault simulation devices for logic calculation circuits composed of n microring resonators (MRRs), solving the problem of the lack of in-depth evaluation of double fault errors in existing logic calculation circuits composed of n MRRs. The method includes obtaining the correct output result of a fault-free model device and the erroneous output result of a double fault model device, and calculating the absolute error, maximum absolute error, mean absolute error, and mean square error between the correct output result and the erroneous output result. The embodiment of the present invention is used to calculate errors caused by double faults in the actual production and use of a logic calculation circuit composed of n MRRs. Specifically, it is implemented using a double fault simulation device for a binary all-optical full adder composed of three MRRs as an example.

Description

Technical Field

[0001] The present invention relates to a double fault error calculation method for a binary all-optical full adder, and in particular to the field of a double fault simulation device consisting of n MRRs constituting a logic calculation circuit. Background Art

[0002] Recent breakthroughs in silicon photonic device research have made optical networks-on-a-chip a research hotspot. This has also accelerated the convergence of optical devices and integrated circuits, giving rise to a new technological field: integrated optics. The theoretical foundations of integrated optics are optics and optoelectronics, encompassing a wide range of modern optical topics, including wave optics and information optics, nonlinear optics, semiconductor optoelectronics, crystal optics, thin-film optics, waveguide optics, coupled-mode and parametric interaction theory, and thin-film optical waveguide devices and systems. Its technological foundations are primarily thin-film technology and microelectronics. Integrated optics offers advantages such as low susceptibility to electromagnetic interference and high transmission bandwidth, resulting in a wide range of applications, including fiber-optic communications, fiber-optic sensing, optical information processing, optical computing, and optical storage. Microring resonators (MRRs) are key components in integrated optics, but they are sensitive to process drift and temperature, making them prone to failure. Therefore, researchers have developed fault simulation devices to simulate MRR failures and improve the reliability of integrated optics.

[0003] However, there is currently no research method to study and calculate the errors caused by microring resonator failures. Therefore, this patent, based on the establishment of an all-optical full adder fault simulation model using optical devices, realizes the calculation and analysis of the fault errors of the all-optical full adder under actual operating conditions. This has a positive guiding role in the future research and development of optical computing devices with similar functions. Summary of the Invention

[0004] The problem to be solved by the present invention is the lack of deep evaluation of double fault errors in a logic calculation circuit composed of n MRRs, and a double fault error calculation method of a binary all-optical full adder is provided.

[0005] The present invention adopts the following technical solutions to solve the above problems:

[0006] A double-fault error calculation method for a binary all-optical full adder includes a logic calculation circuit composed of n MRRs, wherein the circuit includes N input combinations, each combination generating an m-bit output result. The logic calculation circuit composed of the n MRRs can be divided into a fault-free analog equivalent circuit and a double-fault analog equivalent circuit. A correct output result can be obtained according to the fault-free analog equivalent circuit, while an erroneous output result can be obtained according to the double-fault analog equivalent circuit. Based on the correct and erroneous output results, the absolute error (AE), maximum absolute error (MAXAE), mean absolute error (MAE), and mean squared error (MSE) between the two are calculated.

[0007] The absolute error (AE) between the correct output result and the incorrect output result in each input combination is calculated, and the absolute value |AE| of the AE is taken. The specific expression of |AE| is shown in formula (1):

[0008]

[0009] The i represents the i-th input combination, the i is included in N, the Represents the error output integer value under the i-th input combination, the O i correct Represents the correct output integer value under the i-th input combination, Represents the j-th logical value of the error output under the i-th input combination, the O i correct Represents the j-th logical value of the correct output under the i-th input combination.

[0010] The maximum value of all the |AE|s generated by the N input combinations is calculated as the maximum absolute error (MAXAE), that is, the maximum error caused by double faults in the N input combinations. The specific expression is shown in formula (2):

[0011] MAXAE=max|AE i |=max|O i fault -O i correct | (2)

[0012] The average of all absolute errors generated by the N input combinations is calculated as the mean absolute error (MAE). The specific expression of the MAE is shown in formula (3):

[0013]

[0014] The mean square error (MSE) is calculated based on all the |AE|s generated by the N input combinations. The specific expression of the MSE is shown in formula (4):

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be further described below with reference to the accompanying drawings and examples.

[0017] Figure 1 Flowchart of a double-fault error calculation method for a binary all-optical full adder

[0018] Figure 2 The figure is a schematic diagram of the structure of a fault simulation device for a binary all-optical full adder.

[0019] Figure 3 Schematic diagram of the optical switch MRR structure consisting of two parallel straight waveguides and a silicon-based nanowire microring waveguide.

[0020] Figure 4 Schematic diagram of the optical switch MRR structure consisting of two vertically crossed straight waveguides and a silicon-based nanowire microring waveguide. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0022] Embodiment 1: The embodiment of the present invention provides a method for calculating double fault errors of a binary all-optical full adder. Figure 1 Shown include:

[0023] S101 . Based on a logic calculation circuit composed of n MRRs, enumerate N input combinations of the circuit.

[0024] S102 , calculating respectively the correct output result of the fault-free analog equivalent circuit and the erroneous output result of the double-fault analog equivalent circuit according to N input combinations, and each combination can generate an m-bit output result.

[0025] S103 : Calculate the absolute error (AE) between the correct output result and the incorrect output result in each input combination, and take the absolute value |AE| of the AE.

[0026] Furthermore, the specific expression of |AE| is shown in formula (1):

[0027]

[0028] The i represents the i-th input combination, the i is included in N, the Represents the error output integer value under the i-th input combination, the O i correct Represents the correct output integer value under the i-th input combination, Represents the j-th logical value of the error output under the i-th input combination, the O i correct Represents the j-th logical value of the correct output under the i-th input combination.

[0029] S104 , calculating the maximum value of all the |AE|s generated by the N input combinations as the maximum absolute error (MAXAE).

[0030] Furthermore, the MAXAE represents the maximum error caused by double faults in the N input combinations, and its specific expression is shown in formula (2):

[0031] MAXAE=max|AE i |=max|O i fault -O i correct | (2)

[0032] S105 : Calculate the average of all absolute errors generated by the N input combinations as the mean absolute error (MAE).

[0033] Furthermore, the specific expression of the MAE is shown in formula (3):

[0034]

[0035] S106 , calculating the mean squared error (MSE) based on all the |AE|s generated by the N input combinations.

[0036] Furthermore, the specific expression of the MSE is shown in formula (4):

[0037]

[0038] For example, the fault simulation device of a binary all-optical full adder (CN202120900454.X) in the patent specification is disclosed as " Figure 2 "For example, Figure 2 The device is now defined as a double fault simulation, and the specific operation steps of the double fault error calculation method of the binary all-optical full adder of the present invention in practical application are further supplemented:

[0039] Here we first show the working principle of the microring resonator (MRR) in the fault-free and faulty conditions:

[0040] A modulation voltage signal X is added to the microring resonator. When the modulation voltage signal X is at a low level, the microring resonator resonates. Conversely, when the modulation voltage signal X is at a high level, the microring resonator does not resonate.

[0041] Specifically, if Figure 3 As shown in the figure, the optical signal is input from the input end of the MRR's input optical waveguide. When the modulation voltage signal X is at a low level "0", the MRR resonates, and the optical signal is output from the Drop end of the MRR's download optical waveguide, with a logic state of "1", while the Through end of the MRR's straight optical waveguide has no optical signal output, and the logic state is "0". When the modulation voltage signal X is at a high level "1", the MRR does not resonate, and the optical signal is output from the Through end of the MRR's straight optical waveguide, with a logic state of "1", while the Drop end of the MRR's download optical waveguide has no optical signal output, and the logic state is "0".

[0042] Specifically, if Figure 3 As shown in the figure, assuming that a dead-zero fault occurs in the MRR, an optical signal is input from the input end of the MRR's input optical waveguide and the modulation voltage signal X is in the low-level "0" state. The MRR should be in the resonant-on state, and the Drop end of the download optical waveguide should output an optical signal. However, due to the fault, no optical signal is output, and the optical signal is output from the Through end of the straight optical waveguide.

[0043] Specifically, if Figure 3As shown in the figure, assuming that a deadlock 1 fault occurs in the MRR, an optical signal is input from the input end of the MRR's input optical waveguide and the modulation voltage signal X is in the high level "1" state. The MRR should be in the resonant off state, and the through end of the straight optical waveguide should output an optical signal. However, due to the fault, no optical signal is output, and the optical signal is output from the drop end of the download optical waveguide.

[0044] In addition, if Figure 4 As shown, this is an optical switch MRR composed of two vertical straight waveguides and a silicon-based nanowire microring waveguide. Its principle is similar to Figure 3 The principle is the same and will not be repeated here.

[0045] according to Figure 4 As shown, Figure 2 The through optical waveguide T_2 and the down optical waveguide D_2 of MMR2 are in a perpendicular state, i.e. a crossbar switch. Similarly, the through optical waveguide T_3 and the down optical waveguide D_3 of MMR3 form a crossbar switch.

[0046] Specifically, Figure 2 The function of the medium structure device is a binary all-optical full adder, which contains three MRRs, whose modulation voltage signals are A, B, and C respectively, with a total of 8 input combinations. Figure 2 MRR1, MRR2, and MRR3 are all fault-free, and the states of the modulation voltage signals A, B, and C are 0, 0, and 0, respectively. Therefore, MRR1, MRR2, and MRR3 are all in the resonant on state. Then, the optical signal is input from the input end (CW), and first output from the D1 end of the download optical waveguide of MRR1, while there is no optical signal output from the T1 end of the straight optical waveguide of MRR1; then the optical signal is input from the In2 end of the input optical waveguide of MRR2, and there is no optical signal output from the T2 end of the straight optical waveguide of MRR2, and there is no optical signal output from the T_2 end of the straight optical waveguide of MRR2 and the download optical waveguide D_2 end, while the optical signal is output from the D2 end of the download optical waveguide of MRR2. Therefore, there is no optical signal superposition output from the O1 end of the Y-branch coupler 1, and no optical signal branch output from the O3 end of the Y-branch coupler 2; secondly, the D2 end output The optical signal of the branch output from the O3 end is superimposed with the optical signal without the optical signal and enters the O2 end of the Y branch coupler 3 to output the optical signal. The optical signal is input from the In3 end of the input optical waveguide of MRR3 and output from the D3 end of the download optical waveguide of MRR3, while there is no optical signal output from the T3 end of the straight optical waveguide of MRR3; since there is no optical signal superposition output from the O1 end, there is no optical signal output from the T_3 end of the straight optical waveguide of MRR3 and the D_3 end of the download optical waveguide; therefore, there is no optical signal superposition at both the T3 end and the D_3 end and enters the Y branch coupler 4. Similarly, there is no optical signal superposition at both the T_3 end and the O3 end and enters the Y branch coupler 5; finally, Figure 2 There is no optical signal output at the Y end and the CO end, and the logic state is 0.

[0047] Similarly, when the modulation voltage signals A, B, and C are the remaining seven input combinations and MRR1, MRR2, and MRR3 are all fault-free, both the Y terminal and the CO terminal can output corresponding logic state values.

[0048] Figure 2 When MRR1, MRR2, and MRR3 are all fault-free, the output truth table of the binary all-optical full adder is shown in the following table:

[0049] Table 1. Truth table of the binary all-optical full adder when MRR1, MRR2, and MRR3 are all fault-free

[0050]

[0051] Specifically, assuming Figure 2 MRR1 and MRR2 both have a dead-0 fault, while MRR3 has no fault, and the states of the modulation voltage signals A, B, and C are 0, 0, and 0 respectively. The optical signal is input from the input end (CW). Because MRR1 has a dead-0 fault and the modulation voltage signal state is 0, it is first output from the T1 end of the straight-through optical waveguide of MRR1, while there is no optical signal output from the D1 end of the download optical waveguide of MRR1; then there is no optical signal input from the In2 end of the input optical waveguide of MRR2, but there is an optical signal input from the In_2 end of the input optical waveguide of MRR2, so there is no optical signal output from the T2 end of the straight-through optical waveguide of MRR2 and the D2 end of the download optical waveguide; because MRR2 has a dead-0 fault and the modulation voltage signal state is 0, there is no optical signal output from the D_2 end of the download optical waveguide of MRR2, and the optical signal is output from the T_2 end of the straight-through optical waveguide of MRR2. Therefore, there is no optical signal superposition output from the O1 end of the Y-branch coupler 1, and the Y-branch coupler 2 has an optical signal branch output at the O3 end; secondly, the no optical signal output from the D2 end is superimposed on the optical signal output from the branch at the O3 end and enters the O2 end of the Y branch coupler 3 to output the optical signal. The optical signal is input from the In3 end of the input optical waveguide of MRR3. Since MRR3 has no fault and is in the resonant on state, the optical signal is output from the D3 end of the download optical waveguide of MRR3, and there is no optical signal output from the T3 end of the straight-through optical waveguide of MRR3; since there is no optical signal superposition output from the O1 end, there is no optical signal output from the straight-through optical waveguide T_3 end and the download optical waveguide D_3 end of MRR3; therefore, there is no optical signal superposition at both the T3 end and the D_3 end and enters the Y branch coupler 4, but the no optical signal at the T_3 end and the optical signal output from the branch at the O3 end are superimposed and enter the Y branch coupler 5; finally, Figure 2 There is no light signal output at the Y end, but there is light signal output at the CO end, so the logic states of Y and CO are 0 and 1 respectively.

[0052] Similarly, when the modulation voltage signals A, B, and C are the remaining seven input combinations and MRR1 and MRR2 both have a deadlock 0 fault and MRR3 has no fault, both the Y terminal and the CO terminal can output corresponding error logic state values.

[0053] Figure 2 When both MRR1 and MRR2 in the example have a dead-zero fault, and MRR3 has no fault, the truth table of the binary all-optical full adder is shown in the following table:

[0054] Table 2. Truth table of the binary all-optical full adder when both MRR1 and MRR2 have a dead-zero fault

[0055]

[0056] The results in Tables 1 and 2 are combined into Table 3.

[0057] Table 3. Truth table of binary all-optical full adder with and without faults

[0058]

[0059] Then, according to the results in Table 3, the absolute error (AE), the maximum absolute error (MAXAE), the mean absolute error (MAE), and the mean squared error (MSE) between the correct output result and the incorrect output result are calculated respectively.

[0060] ① According to the results in Table 3, the absolute error (AE) between the correct output result and the incorrect output result in each input combination is calculated using formula (1), and the absolute value is taken, as shown in Table 4 below:

[0061] Table 4. Absolute error AE between correct and incorrect output results for each input combination

[0062]

[0063] ② According to the results in Table 4, use formula (2) to calculate the maximum value of all the |AE| generated by the 8 input combinations: the maximum absolute error value MAXAE, therefore,

[0064] MAXAE=max|AE i |=max|O i fault -O i correct |=2

[0065] ③ According to the results in Table 4, use formula (3) to calculate the average value of all absolute errors generated by the eight input combinations: mean absolute error MAE, therefore,

[0066]

[0067] ③ According to the results in Table 4, the mean square error (MSE) is calculated using formula (4). Therefore,

[0068]

[0069] In summary, MRR1, MRR2 and MRR3 can be combined in pairs to simultaneously cause the same or different fault input combinations, which is similar to the above-mentioned situation where both MRR1 and MRR2 have a sluggish 0 fault while MRR3 has no fault, so it will not be repeated here.

[0070] The technical content and technical features of the present invention have been disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the disclosure of the present invention without departing from the intention of the present invention. Therefore, the scope of protection of the present invention should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention and be covered by the claims of this patent application.

Claims

1. A double fault error calculation method for a binary all-optical full adder, characterized in that: A logic calculation circuit is provided, comprising n MRRs, the circuit including N input combinations, each combination capable of generating an m-bit output result; the logic calculation circuit comprising the n MRRs can be divided into a fault-free analog equivalent circuit and a double-fault analog equivalent circuit, wherein a correct output result can be obtained according to the fault-free analog equivalent circuit, and an incorrect output result can be obtained according to the double-fault analog equivalent circuit; Calculate the absolute error (AE), maximum absolute error (MAXAE), mean absolute error (MAE), and mean squared error (MSE) between the correct output result and the incorrect output result; Absolute error (AE): Calculate the absolute error (AE) between the correct output result and the incorrect output result for each input combination, and take the absolute value |AE| of AE. The specific expression of |AE| is as follows: The i represents the i-th input combination, the i is included in N, the Represents the wrong output integer value under the i-th input combination, Represents the correct output integer value under the i-th input combination, Represents the j-th logical value of the error output under the i-th input combination, The jth logical value of the correct output under the i-th input combination; Maximum absolute error (MAXAE): The maximum value of all the |AE| values ​​generated by the N input combinations is calculated as the maximum absolute error (MAXAE), that is, the maximum error caused by a double fault in the N input combinations. The specific expression of MAXAE is as follows: MAXAE=max|AE i |=max|O i fault -O i correct |; Mean absolute error (MAE): The mean absolute error (MAE) of all absolute errors generated by the N input combinations is calculated as the mean absolute error (MAE). The specific expression of MAE is as follows: Mean squared error (MSE): Calculate the mean squared error (MSE) based on all the |AE|s generated by the N input combinations. The MSE is specifically expressed as follows:

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