Trail or lead digit predictor

Abstract

The present application relates to trailing or leading digit predictors. A method and a leading zero predictor for estimating the number of leading zeros in the result of a fixed-point arithmetic operation, accurate to within one bit of any signed fixed-point number. The leading zero predictor comprises an input encoding circuit that generates an encoded input string from the fixed-point number; a window-based proxy string generation circuit that generates a proxy string by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination, the leading ones of the proxy string being an estimate of the leading ones in the result of the arithmetic operation; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading ones in the proxy string.

Description

[0001] This application is a divisional application of application No. 201610802627.8, filed on September 5, 2016, entitled "Trailing or Leading Digit Predictor". BACKGROUND

[0002] There are many cases in which it is useful to count the number of consecutive ones or zeros in a binary number, either from the left-hand side (i.e., starting with the most significant bit (MSB)) or from the right-hand side (i.e., starting with the least significant bit (LSB)). When counting from the most significant bit, this can be referred to as counting leading ones or zeros (e.g., the binary number 0111 has one leading zero and the binary number 1100 has two leading ones). When counting from the least significant bit, this can be referred to as counting trailing ones or zeros (e.g., the binary number 1100 has two trailing zeros and the binary number 1000 has three trailing zeros).

[0003] Counting leading or trailing zeros includes detecting the first one in the binary number from the MSB or LSB, respectively; or, in other words, detecting the first transition from zero to one from the MSB or LSB. Likewise, counting leading or trailing ones includes detecting the first zero in the binary number from the MSB or LSB, respectively; or, in other words, detecting the first transition from one to zero from the MSB or LSB.

[0004] A leading zero counter (LZC) that counts the number of leading zeros, for example, can be used for normalization in floating point operations (e.g., floating point addition). However, it will be appreciated that a trailing zero counter (TZC) that counts trailing zeros can be used as a leading zero counter by connecting the inputs such that the true MSB of the input binary number is connected to the LSB input of the trailing zero counter or leading zero counter, and vice versa.

[0005] The embodiments described below are provided as examples only and are not limiting of implementations that address any or all of the shortcomings of known trailing or leading zero predictors.

[0006] SUMMARY

[0007] This summary is provided to introduce a series of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

[0008] Described herein are methods and leading zero predictors for estimating the number of leading zeros in the result of a fixed-point arithmetic operation, accurate to within one bit with respect to any signed fixed-point number. The leading zero predictor includes input encoding circuitry that generates an encoded input string from the fixed-point numbers; window-based proxy string generation circuitry that generates a proxy string by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination, the leading ones of the proxy string being an estimate of the leading ones in the result of the arithmetic operation; and counter circuitry configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading ones in the proxy string.

[0009] The first aspect provides a leading zero predictor configured to estimate the number of leading zeros in the result of an arithmetic operation performed on two or more fixed-point numbers, the leading zero predictor comprising: input encoding circuitry configured to generate an encoded input string from the two or more fixed-point numbers; window-based proxy string generation circuitry configured to generate a proxy string by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination, the leading ones of the proxy string being an estimate of the leading ones in the result of the arithmetic operation, the estimate of the leading ones being within one digit position of the leading ones in the actual result of the arithmetic operation with respect to any signed fixed-point number; and counter circuitry configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading ones in the proxy string.

[0010] The second aspect provides a method of estimating the number of leading zeros in the result of an arithmetic operation performed on two or more fixed-point numbers, the method comprising: generating an encoded input string from the two or more fixed-point numbers using input encoding circuitry; generating a proxy string by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination using window-based proxy string generation circuitry, the leading ones of the proxy string being an estimate of the leading ones in the result of the arithmetic operation, the estimate of the leading ones being within one digit position of the leading ones in the actual result of the arithmetic operation with respect to any signed fixed-point number; and estimating the number of leading zeros in the result of the arithmetic operation based on the leading ones in the proxy string using counter circuitry.

[0011] It will be apparent to the skilled person that preferred features can be suitably combined, and can be combined with any aspect of the application.

[0012] The present application provides the following:

[0013] 1) A leading zero predictor (300) configured to estimate the number of leading zeros in the result of an arithmetic operation performed on two or more fixed-point numbers, the leading zero predictor comprising:

[0014] input encoding circuitry (402) configured to generate an encoded input string from the two or more fixed point numbers;

[0015] window-based proxy string generation circuitry (404) configured to generate a proxy string by inspecting successive windows of the encoded input string and setting corresponding bits of the proxy string based on the inspection, a leading one of the proxy string being an estimate of a leading one in a result of the arithmetic operation, the estimate of the leading one being within one digit position of the leading one in an actual result of the arithmetic operation with respect to any signed fixed point number; and

[0016] counter circuitry (304) configured to estimate a number of leading zeros in the result of the arithmetic operation based on the leading one in the proxy string.

[0017] 2) The leading zero predictor (300) of 1), wherein a window of the encoded input string comprises a predetermined number of consecutive positions of the encoded input string.

[0018] 3) The leading zero predictor (300) of 2), wherein the predetermined number is greater than or equal to three.

[0019] 4) The leading zero predictor (300) of 2) or 3), wherein the window-based proxy string generation circuitry (404) is configured to generate an i-th bit of the proxy string based on an i-th window of the encoded input string, the i-th window comprising the predetermined number of consecutive positions of the encoded input string starting from an i-th position of the encoded input string and including the i-th position.

[0020] 5) The leading zero predictor (300) of any of 1) to 3), wherein the window-based proxy string generation circuitry is configured to set an i-th bit of the proxy string to a high value when the corresponding window of the encoded input string comprises a pattern that consistently indicates that one of an i-th bit and an i+1-th bit of the result of the arithmetic operation will be high.

[0021] 6) The leading zero predictor (300) of any of 1) to 3), wherein the input encoding circuitry (402) is configured to set an i-th bit of the encoded input string to one of z, p, or g based on how many of the i-th bits of the fixed point numbers are high.

[0022] 7) The leading zero predictor (300) of 6), wherein there are two fixed-point numbers and the input encoding circuit (402) is configured to set the i-th position of the encoded input string to z when both of the i-th bits of the fixed-point numbers are low, to p when only one of the i-th bits of the fixed-point numbers is high, and to g when both of the i-th bits of the fixed-point numbers are high.

[0023] 8) The leading zero predictor (300) of 6), wherein the window of the encoded input string comprises three consecutive positions of the encoded input string, and the window-based proxy string generation circuit is configured to set the i-th bit of the proxy string to a high value when the corresponding window of the encoded input string comprises ggz, gpg, gpp, gpz, gzg, pgg, pzz, zgz, zpg, zpp, zpz, or zzg, and the window-based proxy string generation circuit is configured to set the i-th bit of the proxy string to a low value when the corresponding window of the encoded input string comprises ggg, ggp, gzp, gzz, pgp, pgz, ppg, ppp, ppz, pzg, pzp, zgg, zgp, zzp, or zzz.

[0024] 9) The leading zero predictor (300) of 6), wherein the window-based proxy string generation circuit (404) is configured to set the i-th bit of the proxy string e_y according to the following equation:

[0025]

[0026] 10) The leading zero predictor (300) of 6), wherein the window-based proxy string generation circuit is configured to set the i-th bit of the negated proxy string according to the following equation:

[0027]

[0028] 11) A method of estimating a number of leading zeros in a result of an arithmetic operation performed on two or more fixed-point numbers, the method comprising:

[0029] generating an encoded input string from the two or more fixed-point numbers using an input encoding circuit;

[0030] generating the proxy string using a window-based proxy string generation circuit by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination, a leading one of the proxy string being an estimate of a leading one in a result of the arithmetic operation, the estimate of the leading one being within one digit position of a leading one in an actual result of the arithmetic operation with respect to any signed fixed-point number (600, 700); and

[0031] estimating a number of leading zeros in the result of the arithmetic operation using a counter circuit based on the leading one in the proxy string.

[0032] 12) The method of 11), wherein the windows of the encoded input string comprise a predetermined number of consecutive positions of the encoded input string and the predetermined number is greater than or equal to three.

[0033] 13) The method of 12), wherein generating the proxy string comprises setting an i-th bit of the proxy string based on an i-th window of the encoded input string, the i-th window comprising the predetermined number of consecutive positions of the encoded input string starting from an i-th position of the encoded input string and including the i-th position.

[0034] 14) The method of any of 11) to 13), wherein generating the proxy string comprises setting an i-th bit of the proxy string to a high value when the corresponding window of the encoded input string comprises a pattern that always indicates that one of an i-th bit and an i+1-th bit of the result of the arithmetic operation will be high.

[0035] 15) The method of any of 11) to 13), wherein generating the encoded input string comprises setting an i-th position of the encoded input string to one of z, p, or g based on how many of an i-th bit of the fixed-point number are high.

[0036] 16) The method of 15), wherein there are two fixed-point numbers and generating the encoded input string comprises setting an i-th position of the encoded input string to z when both of the i-th bits of the fixed-point numbers are low, setting the i-th position of the encoded input string to p when only one of the i-th bits of the fixed-point numbers is high, and setting the i-th position of the encoded input string to g when both of the i-th bits of the fixed-point numbers are high.

[0037] 17) The method of 15), wherein the window of the encoded input string comprises three consecutive positions of the encoded input string, and generating the proxy string comprises setting the ith bit of the proxy string to a high value when the corresponding window of the encoded input string comprises ggz, gpg, gpp, gpz, gzg, pgg, pzz, zgz, zpg, zpp, zpz, or zzg, and setting the ith bit of the proxy string to a low value when the corresponding window of the encoded input string comprises ggg, ggp, gzp, gzz, pgp, pgz, ppg, ppp, ppz, pzg, pzp, zgg, zgp, zzp, or zzz.

[0038] 18) The method of 15), wherein generating the proxy string comprises setting the ith bit of the proxy string e_y according to the following equation:

[0039]

[0040] 19) The method of 15), wherein generating the proxy string comprises setting the ith bit of the negated proxy string

[0041] BRIEF DESCRIPTION OF DRAWINGS

[0042] Embodiments of the present application will be described, by way of example only, with reference to the following drawings:

[0043] Figure 1 is a block diagram of an example fixed-point addition circuit including a leading zero counter;

[0044] Figure 2 is a block diagram of an example fixed-point addition circuit including a leading zero predictor;

[0045] Figure 3 is a block diagram of an example leading zero predictor;

[0046] Figure 4 is a block diagram of an example proxy string generation circuit of Figure 3

[0047] Figure 5 is a schematic diagram illustrating generation of an example encoded input string from two example binary inputs;

[0048] Figure 6 is a flowchart of an example method for generating a proxy string of Figure 4

[0049] Figure 7 ​​​is a flowchart of an example method for setting the i-th bit of a proxy string;

[0050] Figure 8 is a schematic diagram illustrating generation of an example proxy string according to Figure 6 and Figure 7 is a schematic diagram illustrating generation of an example proxy string according to

[0051] Figure 9 is a schematic diagram illustrating a comparison of an example output of a fixed point addition circuit to an example proxy string generated according to Figure 6 and Figure 7 is a schematic diagram illustrating a comparison of an example output of a fixed point addition circuit to an example proxy string generated according to

[0052] Figure 10 is a graph showing area versus latency tradeoff for different single precision floating point addition circuits including the fixed point addition circuit described herein.

[0053] Common reference numerals are used throughout the figures to designate like features. DETAILED DESCRIPTION

[0054] Embodiments of the application are described below by way of example only. These examples represent the best ways of practicing the application currently known to the Applicant, but they are not the only ways in which the application can be practiced. The description sets forth the functions, sequences, and steps for constructing and operating the examples. However, changes can be made within the attributes of the application without departing from the scope of the application as defined in the claims.

[0055] As noted above, there are many applications in which it is useful to know the number of leading or trailing digits (e.g., zeros or ones) in a binary number or string, such as when performing normalization as part of a floating point arithmetic operation, such as a floating point addition operation.

[0056] As known to those skilled in the art, a fixed point number representation is a representation with a fixed number of digits after the decimal point (e.g., the decimal point or the binary point). In contrast, a floating point number representation is a representation of a number in which the decimal point is not fixed (i.e., it can "float"). In other words, the decimal point can be placed anywhere within the representation.

[0057] The most common floating point format is the Institute of Electrical and Electronics Engineers (IEEE) standard for floating point arithmetic (IEEE-754). IEEE-754 specifies that a floating point number is represented by three numbers: a sign, an exponent, and a mantissa (s, exp, mant). Typically, these three numbers (s, exp, mant) are interpreted with respect to a fixed integer bias, as shown in equation (1):

[0058] (-1) s 2 exp-bias 1.mant (1)

[0059] Referring to Figure 1 Fig. 1 illustrates an example of a fixed-point addition circuit 100 that normalizes a result using a leading zero counter (LZC). In particular, the fixed-point addition circuit 100 includes addition logic 102 that adds two fixed-point inputs a and b to produce an output y. The fixed-point addition circuit 100 can form part of a floating-point addition circuit. In these cases, the two inputs a and b are mantissas of two floating-point inputs converted to signed fixed-point numbers.

[0060] In the case that a and b are similar, the output y can be small, such that a normalization operation is performed via an LZC 104 and a left-shift circuit 106 to compensate for any cancellation of leading ones. In particular, the LZC 104 counts the number of leading zeros in the output y. This count is provided to the left-shift circuit 106, which left-shifts the output y to produce a normalized output n y.

[0061] The fixed-point addition circuit 100 can also include a small shift circuit 108 for aligning the inputs a and b with an optional negation circuit 110. If the inputs a and b are negative, their addition (once aligned) can produce a negative fixed-point result, which is negated by the optional negation circuit 110 prior to normalization.

[0062] Having the addition logic 102 in series with the LZC 104 means that the left-shift cannot begin until after the addition operation is complete and the leading zeros in the addition output have been counted.

[0063] A leading zero anticipator (LZA) has been developed to estimate the number of leading zeros in the output from a fixed-point arithmetic operation (e.g., an addition operation) from the inputs, such that the number of leading zeros can be estimated in parallel with the arithmetic operation. Referring now to Figure 2 Fig. 2 illustrates an example of a fixed-point addition circuit 200 that normalizes a result using a LZA instead of an LZC. In particular, the fixed-point addition circuit 200 includes Figure 1 the addition logic 102, the left-shift circuit 106, the small shift circuit 108, and the optional negation circuit 110 of Fig. 1, however, Figure 1 the LZC 104 of Fig. 1 is replaced with a LZA 202.

[0064] Since the LZA generates an estimate (e_count) of the number of leading zeros in the output from the aligned and signed inputs a and b, the LZA 202 can be placed in parallel with the addition logic 102. This means that the LZA 202 does not have access to the output y of the addition logic 102 to assist in the estimate. In particular, the LZA 202 does not have access to the sign of the output y in estimating the number of leading zeros.

[0065] In cases where the LZA 202 can estimate the number of leading zeros in less time than it takes the adder logic 102 to produce the output, the left shift circuit 106 can begin shifting left as soon as the adder logic 102 produces the output y, which is Figure 1 In comparison to the fixed-point adder circuit 100 of Figure 2 In certain cases, the fixed-point adder circuit 200 can also include a second left shift circuit 204 to perform a small left shift on the estimated normalized output (e_n_y) to account for any errors in the estimated count (e_count) generated by the LZA 202. However, the second left shift circuit 204 will typically be slower than the LZC, so, Figure 1 The fixed-point adder circuit 200 of

[0066] As with the fixed-point adder circuit 100 of Figure 1 The fixed-point adder circuit 200 of Figure 2 In these cases, the two inputs a and b are mantissas of two floating-point inputs converted to signed fixed-point numbers, as described above.

[0067] Described herein is an improved LZA that estimates the number of leading zeros in the result or output of a fixed-point arithmetic operation performed on any two signed fixed-point numbers with one bit of precision. In particular, the improved LZA generates a proxy string whose leading ones provide an estimate of the leading ones in the result of the arithmetic operation by evaluating or analyzing a window of three or more consecutive positions of the fixed-point inputs starting from the MSB and setting the corresponding bit of the proxy string based on the analysis; and then determining the number of leading zeros from the estimated position of the leading ones indicated by the proxy string. Specifically, the improved LZA determines whether the positions of the inputs in the window include a pattern that indicates a leading one in the result or output, and if so, sets the corresponding bit of the proxy string to one, and otherwise sets the corresponding bit of the proxy string to zero. In general, the ith window is used to determine whether the ith bit of the estimated proxy string is high or low. In certain cases, instead of using the fixed-point inputs a and b directly, an encoded input string c is generated from the inputs, and a window of consecutive positions or letters of the encoded input string is evaluated.

[0068] It should be noted that bits and / or positions of a string and number are numbered in this document from the most significant bit / position to the least significant bit / position starting with the number zero, such that the most significant bit / position is bit / position zero. However, it will be apparent to those skilled in the art that this is merely a mechanism to identify particular bits / positions of a string or number, and that the bits / positions can be numbered in another way without affecting the operation of the techniques and methods described herein. For example, the bits / positions of a string or number can be numbered from the least significant bit / position to the most significant bit / position in other cases.

[0069] Reference is now made to Figure 3 which illustrates an example implementation of the improved LZA 300. In this example, the LZA 300 includes a proxy string generation circuit 302 that generates a proxy string from inputs a and b. The leading ones of the proxy string provide an estimate of the leading ones in the actual result. The LZA also includes an LZC 304 that counts the number of zeros in the proxy string to provide an estimate of the number of leading zeros in the absolute value of the sum of the inputs.

[0070] The proxy string generation circuit 302 is configured to generate a proxy string e_y of bits from the fixed point inputs a and b by setting particular bits of the proxy string based on a subset or window of bit positions of the inputs a and b. In general, the proxy string generation circuit 302 is configured to generate or set the i-th bit of the proxy string based on a window of the inputs that starts at the i-th position of the inputs and ends at the (i+w-1)-th position of the inputs, where w is the size of the window. For example, when w=3, the 1st bit of the proxy string e_y is based on a window of the inputs that starts at the 1st position of the inputs and ends at the third position. Reference is now made to Figure 4 An example proxy string generation circuit 302 is described.

[0071] The LZC 304 receives the proxy string e_y generated by the proxy string generation circuit 302 and counts or counts the number of leading zeros in the proxy string e_y. The LZC 304 can be any suitable LZC. The count e_count generated by the LZC 304 can then be provided to a left shift circuit of the left shift circuit 106 to shift the actual result or output generated by the fixed point arithmetic circuit to the left. Figure 2

[0072] Reference is now made to Figure 4 which illustrates an example implementation of the proxy string generation circuit 302 of Figure 3 Figure 4 ​​The example proxy string generation circuit 302 includes an input encoding circuit 402 configured to generate an encoded input string c representing two inputs a and b, and a window-based proxy string generation circuit 404 that generates a proxy string e y from the encoded input string c by analyzing windows or subsets of the encoded input string c. As described above, the leading zero count of the proxy string e y provides an estimate of the number of leading zeros in the absolute value of the sum of the inputs a and b.

[0073] The input encoding circuit 402 receives the inputs a and b and generates an encoded input string c of letters that represents the information in the two fixed-point inputs a and b. In particular, since for addition and subtraction operations it is the number of relevant high bits (i.e., bits set to one) in each digit position that is relevant, the input encoding circuit 402 generates the encoded input string c where the i-th position of the string c indicates the number of high bits in the i-th digit position of the inputs a and b. For example, the 7th position of the string c indicates how many of the 7th bits of the input a and the 7th bits of the input b are high (i.e., ones).

[0074] In the case of two inputs, there are only three possible numbers of high bits: zero (both i-th bits of the two inputs are low); one (the i-th bit of one of the inputs is high); or two (both i-th bits of the two inputs are high). For two inputs a and b, these possibilities can be represented by a zero function z i as shown in equation (2), a pass function p i as shown in equation (3), and a generate function g i as shown in equation (4), respectively.

[0075]

[0076]

[0077] g i = a i ∧ b i (4)

[0078] Each position i of the encoded input string c is then assigned one of the letters z, p, and g based on which of equations (2), (3), and (4) is high for that position.

[0079] In some cases, each of the inputs a and b are assumed to have an additional bit that is set to zero. In these cases, the encoded input string c will have additional positions relative to the inputs a and b that are always set to z. For example, if the inputs a and b have eight bits, then the encoded input string c will have nine positions. As described below, the ith bit of the proxy string is generated from the ith window of the encoded input string c, which includes three consecutive positions of the encoded input string starting from the ith position, so adding an additional position to the encoded input string c allows for the additional bit of the proxy string to be generated.

[0080] For example, if a = 100101110 and b = 011101100, then the encoded input string c will be pppgzggpzz, as Figure 5 and shown in Table 1.

[0081] Table 1

[0082]

[0083] Once the encoded input string c has been generated by the input encoding circuit 402, it is provided to the window-based proxy string generation circuit 404. The window-based proxy string generation circuit 404 then generates the proxy string e y by analyzing windows or substrings of the encoded input string c. As described above, the leading zero count of the proxy string e y provides an estimate of the leading zero count of the absolute value of the sum of the fixed-point inputs a and b.

[0084] A window or substring of the encoded input string is a contiguous set of positions of the encoded input string c that has fewer positions than the entire encoded input string c (i.e., is a subset of the encoded input string c). For example, for c = pppgzggpz, a window or substring of size three can include any of ppp, ppg, pgz, gzg, zgg, ggp, and gpz.

[0085] The window-based proxy string generation circuit 404 sets the ith bit or position of the proxy string e y based on the ith window or subset of the encoded input string c. The ith window is considered to be the window that starts at and includes the ith position of the encoded input string c.

[0086] In certain cases, if the i-th window or subset of the encoding input string c includes a pattern that is deemed a predictor of a leading one in the result or output of an arithmetic operation, the window-based proxy string generation circuit 404 is configured to set the i-th bit or position of the proxy string e_y to high (e.g., to one). In certain cases, as described in greater detail below, if the pattern in the i-th window indicates that the i-th or i+1 -st position or bit of the result or output of the fixed-point arithmetic operation is definitely high (e.g., one), then the pattern is deemed a predictor of a leading one in the result or output of an arithmetic operation. The proxy string e_y can also be referred to herein as a mask or representative output of the fixed-point operation circuit.

[0087] To make the position of the leading one in the proxy string accurate to within one bit or position, a window of size w of three or greater is used. The window size indicates the number of positions in the encoding input string c that are encompassed or covered by the window. Thus, a window of size three encompasses three positions of the encoding input string c. As noted above, since the LZA is intended to be placed in parallel with the fixed-point operation circuit (e.g., addition circuit), the sign of the output y of the fixed-point operation circuit is not available to the LZA to help estimate the output. This makes it impossible to use a window of size two to estimate the position of the leading one to within one bit of accuracy for all possible inputs a and b.

[0088] For example, Table 2, Table 3, and Table 4 show inputs a and b that result in encoding input strings ppzgg, ppgz, and ppzgzp, respectively. In Table 2, the window zg does not indicate a leading one. Likewise, in Table 3, the window or substring gz does not indicate a leading one. However, in Table 4, if the estimate is to be accurate to within one bit, then the window or substring gz or zg must indicate a leading one. Thus, a window of size two cannot predict the leading zero or leading one of the result or output of a fixed-point arithmetic operation performed on a signed fixed-point number to within one bit of accuracy.

[0089] Table 2

[0090]

[0091] Table 3

[0092]

[0093] Table 4

[0094]

[0095] However, a window of at least three positions or letters can be used to estimate the position of the leading one in the output of a fixed-point arithmetic operation performed on two signed fixed-point numbers to within one bit (i.e., the estimated position of the leading one is at most one bit away from the actual position of the leading one). Since it is advantageous to evaluate a minimum number of positions or letters, a window of size three will be described herein, but it will be apparent to those skilled in the art that the principles and techniques described herein can be extended to windows having a size greater than three.

[0096] Each window of the encoded input string c is evaluated in order, starting from the MSB, to determine whether the pattern or substring of letters predicts a leading one. For example, if two inputs a and b produce an encoded input string c = p0p1p2z3g4g5… and w = 3, the first window evaluated (0th window) includes p0p1p2, the second window evaluated (1st window) includes p1p2z3, the third window evaluated (2nd window) includes p2z3g4, and so on. If the pattern or substring of letters of the encoded input string in the ith window is deemed to predict a leading one in the result, the ith bit of the proxy string e_y is set high (e.g., set to one); otherwise the ith bit of the proxy string is set low (e.g., set to zero).

[0097] To determine whether a particular pattern or substring of the encoded input string c in the ith window predicts a leading one in the result of the fixed-point arithmetic operation, a determination is made as to whether the particular pattern of letters in the window would result in a high bit in the ith or ith+1 bit of the result or output of the arithmetic operation.

[0098] For a fixed-point addition operation, a determination can be made as to whether a particular pattern or substring of letters (e.g., g, p, and z) predicts a leading one in the result based on whether the sum of the pattern of letters in the window would have a high bit in one of the first two positions and whether the result of the sum plus a carry (i.e., sum + 1) would have a high bit in one of the first two positions (since the sum of the previous bits can produce a carry). For a particular combination or pattern of letters (referred to as a substring) of g, p, and z, only when both the sum and the sum plus a carry (i.e., sum + 1) produce a result with a high bit in one of the first two positions (but not both) can it be determined that the particular combination of g, p, and z (i.e., the substring) indicates that a leading one is predicted or expected in one of the first two positions. Table 5 shows the resulting sum and sum plus a carry (i.e., sum + 1) for each possible pattern or combination of g, p, and z.

[0099] Table 5

[0100]

[0101]

[0102] As can be seen from Table 5, most of the patterns or combinations (i.e., substrings) of g, p, and z produce consistent results, i.e., either both the sum and the sum plus one (i.e., sum + 1) have a one in one of the first two positions, or neither the sum nor the sum plus one (i.e., sum + 1) have a one in one of the first two positions. For these combinations of g, p, and z, it is clear whether they indicate a leading one or not. However, there are a number of patterns or combinations of g, p, and z that do not produce consistent results, i.e., only one of the sum and the sum plus one (i.e., sum + 1) has a one in one of the first two positions. In particular, as can be seen in Table 5, the following combinations (i.e., substrings) of g, p, and z produce inconsistent results: ggp, gzp, pgp, pzp, zgp, and zzp. These will be referred to herein as ambiguous combinations or substrings and are summarized in Table 6.

[0103] Table 6

[0104]

[0105] Since the ambiguous combinations or substrings (i.e., ggp, gzp, pgp, pzp, zgp, and zzp) can produce a leading one in one of the first two positions, the question arises as to whether a leading one can be lost (i.e., not properly identified) if these combinations of g, p, and z are considered to not indicate a leading one. However, it can be shown that for each of the ambiguous combinations or substrings, either none of the results (i.e., sum or sum + 1) indicates a leading one; or if it does indicate a leading one, it will be identified as a leading one by a preceding or following window (so it does not need to be identified in this particular window). Thus, the ambiguous combinations or substrings are not themselves relevant in identifying a leading one in the result or output of an arithmetic operation.

[0106] In particular, if it is assumed that the input is symbol-extended such that the leading window is one of zzz, ppp, or ggg, then the combinations according to each of these leading windows or subsets will be as shown in Table 7.

[0107] Table 7

[0108]

[0109] From Table 5 we can see that the substring gzp, pgp, or zzp does not produce a result with a one in the first bit (sum or sum+1). In other words, each of these combinations produces a result with a one in the second bit (sum or sum+1). Since the second bit is covered by the subsequent window, any leading zero in the gzp, pgp, or zzp combination will be identified in the leading one if the subsequent window indicates a leading one. From Table 6 we can see that the window or subset following gzp, pgp, or zzp will be one of gpx or zpx, where x indicates any of z, p, or g. From Table 4 and Table 7 we can see that gpx and zpx always indicate a leading one. Therefore, any leading one in the gzp, pgp, or zzp combination will be identified by the subsequent window or subset and will not go undetected.

[0110] Referring to the ggp substring, it cannot be the first substring or window, so it must be followed by ggg, zgg, or pgg. If ggp is followed by pgg, the leading zero will be identified by the preceding pgg combination. However, if it is followed by zgg or pgg, the preceding position / bit of the output will always be a one, so the gpp can only indicate a leading digit if the result is negative. When the result is negative, the bits are inverted, so in this case a leading one will occur in the second bit of the window. Since the subsequent window will be gpx, which always indicates a leading one, where x indicates any of z, p, or g, any leading one in the ggpp combination following the zgg or pgg substring will be identified by the subsequent window or subset and will not go undetected. This is shown in Table 8.

[0111] Table 8

[0112]

[0113] Referring to the pzp substring, it also cannot be the first window or substring, so the pzp combination must be followed by gpz, ppz, or zpz substring. If pzp is followed by gpz or zpz, the leading zero will be identified by the preceding gpz or zpz combination (see Table 4), and so the gpz combination is not relevant to detecting a leading one. However, if pzp is followed by a ppz combination, the gpz combination will only indicate a leading digit if the result is negative. In this case, the relevant bit is in the second bit of the window, which will be included in the subsequent window. From Table 6 we can see that the subsequent window will be zpx, which always indicates a leading one, where x indicates any of z, p, or g. Therefore, any leading one in the pzp combination following the ppz combination will be identified by the subsequent window or subset. This is shown in Table 9.

[0114] Table 9

[0115]

[0116] Referring to zgp, it also cannot be the first window, so the zgp combination must be preceded by a gzg, pzg, or zzg combination. If pzp is preceded by gzg or zpz, the leading zeros will be identified by the preceding gzg or zzg combination (see Table 4), and the subsequent zgp combination is irrelevant. However, if the zgp pattern is preceded by a pzg combination, the zzg combination will only indicate a leading one if the result is negative. In this case, the relevant bit is in the second bit of the window, which will be included in the subsequent window. As can be seen from Table 6, the subsequent window will be gpx, which always indicates a leading one, where x indicates any of z, p, or g. Thus, any leading one that occurs from a zgp combination following a zzg combination will be identified by the subsequent window or subset. This is shown in Table 10.

[0117] Table 10

[0118]

[0119]

[0120] Thus, the position of the leading one of the output of the fixed-point addition can be predicted by the window-based proxy string generation circuit 404 to within one bit of precision by identifying the position of the first window that encodes the input string c from the MSB, which includes a pattern that will always produce a one in one of the first two positions of the result. All other patterns or combinations (i.e., those that never produce a one in one of the first two bits or those that only sometimes produce a one in one of the first two bits) are ignored. In particular, the position of the leading one in the result or output of the fixed-point addition can be predicted by the window-based proxy string generation circuit 404 to within one bit of precision by setting the ith bit of the proxy string e_y to high (e.g., one) only if the ith window includes a combination or pattern of letters that will always produce a one in the ith bit or the ith+1 bit of the result; otherwise, the ith bit of the proxy string e_y is set to low (e.g., zero). This is shown in Table 11, which is referred to herein as a truth table.

[0121] Table 11

[0122]

[0123]

[0124] In some cases, the bits / positions of the proxy string can be identified or determined sequentially (e.g., determine the 0th bit / position of the proxy string; then, determine the 1st bit / position of the proxy string; and so on). In these cases, once a bit / position of the proxy string has been set to high, there is no need to determine additional bits. In other cases, the bits of the proxy string can be identified or determined in parallel to improve the speed of the LZA.

[0125] Equation (5) describes an equation for determining the i-th bit of the proxy string e_y when the 0th bit is the most significant bit according to Table 11, which can be implemented by the window-based proxy string generation circuit 404:

[0126]

[0127] In the case where the 0th bit is the least significant bit, then equation (5) can be rewritten as equation (6):

[0128] Optionally, the proxy string e_y can be inverted to count leading ones instead of leading zeros as shown in equation (7):

[0129]

[0130] In the case where the 0th bit is the least significant bit, equation (7) can be written as equation (8):

[0131]

[0132] It will be apparent to those skilled in the art that these are merely examples and other equations and formulas can be used to implement the truth table listed in Table 11. For example, equation (5), equation (6), equation (7), and / or equation (8) can be extended in various ways and coefficients can be set.

[0133] Reference is now made to Figure 6 , Figure 7 and Figure 8 which illustrate example methods for generating a proxy string that can be performed or implemented by the window-based proxy string generation circuit 404. In particular, Figure 6 a flowchart illustrating an example method 600 for generating a proxy string; Figure 7 an example method for generating or setting the i-th bit of a proxy string; and Figure 8 illustrating how the method 600 of Figure 6 and the method 700 of Figure 7 generate a proxy string for an example encoding input string c.

[0134] The method 600 begins at block 602, where the window-based proxy string generation circuit 404 receives an encoded input string c. For example, as shown in Figure 8 FIG. 6A, the window-based proxy string generation circuit 404 can receive an encoded input string c = pppgzggpzz. Once the encoded input string c is received, the method 600 proceeds to blocks 6040 to 604 X-1 where X is the number of bits in the inputs a and b minus 1. For example, if there are 8 bits in the inputs a and b, then X equals 8 - 1 = 7. Each block 604 i sets an i-th bit of the proxy string based on an i-th window of the encoded input string c. For example, block 6040 sets a 0-th bit of the proxy string based on a 0-th window of the encoded input string c. The example method for setting an i-th bit of the proxy string will be described below with reference to Figure 7 Once the bit / position of the proxy string has been set, the method 600 ends 606.

[0135] Reference is now made to Figure 7 FIG. 7, which illustrates a method 700 for setting an i-th bit of the proxy string. The method 700 can be performed at any and / or all of blocks 6040 to 604 X-1 of the method 600. The method 700 begins at block 702, where the window-based proxy string generation circuit 404 identifies an i-th window of the encoded input string c. As described above, the i-th window of the encoded input string includes or comprises an i-th position to an (i+w-1)-th position of the encoded input string c, where w is the size of the window. For example, if the positions of the encoded input string are numbered from 0 to n, where the 0-th position is the most significant bit and n is the number of positions of the encoded input string, then the i-th window includes positions ci+1ci+2...ci+w-1. i For example, with i = 0 and w = 3, the 0-th window includes positions c0c1c2. i+w-1 For example, with i = 0 and w = 3, the 0-th window includes positions c0c1c2.

[0136] In the case where the encoded input string is pppgzggpzz, as shown in Figure 8 FIG. 6A, then as shown in table 802 of Figure 8 FIG. 7, the 0-th window includes ppp; the 1-st window includes ppg; the 2-nd window includes pgz; and so on.

[0137] Once the i-th window has been identified, the method 700 proceeds to block 704.

[0138] At block 704, the window-based proxy string generation circuit 404 determines whether the pattern of letters in the ith window identified in block 702 is a predictor of a leading zero in the result or output of the arithmetic operation. The window-based proxy string generation circuit 404 can determine whether the pattern indicates that it is a predictor of a leading zero according to the truth table. For example, the window-based proxy string generation circuit 404 can implement the truth table of Table 11 in hardware logic. A copy of Table 11 is shown as Table 804 in Figure 8

[0139] As noted above, the truth table of Table 11 only considers a pattern in the ith window to be a predictor of a leading one in the result or output of the arithmetic operation when the pattern will always produce a one in the ith bit or the ith+1 bit (but not both) of the result or output of the arithmetic operation. Using the truth table of Table 11 allows the position of the leading one in the result of the output of the arithmetic operation to be estimated to one bit of precision for any two signed fixed-point numbers.

[0140] If it is determined that the pattern in the ith window is not a predictor of a leading one in the result or output of the arithmetic operation, the method 700 proceeds to block 706. However, if it is determined that the pattern in the ith window is a predictor of a leading one in the result or output of the arithmetic operation, the method 700 proceeds to block 708.

[0141] At block 706, the ith bit / position of the proxy string is set to zero to indicate that the ith bit of the output is not estimated to be a position of a leading zero. For example, as shown in Figure 8 if the 0th window includes ppp and the truth table of Table 11 (e.g., Table 804) is used, the pattern (ppp) is not a predictor of a leading one. Accordingly, the 0th bit of the proxy string (e_y0) is set to zero. Once the ith bit of the proxy string has been set to zero, the method 700 ends.

[0142] At block 708, the ith bit / position of the proxy string is set to one, which indicates that the ith position of the result or output of the arithmetic operation is estimated to be a one. For example, in Figure 8 the 3rd window includes the pattern gzg, which is a predictor pattern according to the truth table of Table 11 (e.g., Table 804), so the 3rd bit of the proxy string (e_y3) is set to one to indicate that it estimates that the 3rd bit / position of the result or output of the arithmetic operation will include a one. Once the ith bit of the proxy string has been set to one, the method 700 ends.

[0143] Reference is now made to Figure 9 ​which illustrates an example of an output generated for an example set of inputs a and b according to the methods described herein and the corresponding proxy string. In this example, the two inputs a and b are 100101110 and 011101100, respectively, which, as shown in Figure 5 results in the encoded input string pppgzggpzz. As shown in Figure 8 this results in the proxy string e_y of 00010011, which has three leading zeros (i.e., the leading one is predicted or estimated to be the fourth bit from the left). The absolute value of the sum of a and b is 000011010, which has four leading zeros (i.e., the leading one is in the fifth bit from the left). Thus, the estimated position of the leading one is off by one bit, which is within the acceptable tolerance.

[0144] Referring now to Figure 10 which illustrates a plot 1000 showing performance improvements in a floating point add circuit including the fixed point add circuit 200 using LZA with a window-based proxy string generation circuit implementing equation (5) or (7) as compared to a floating point add circuit including the fixed point add circuit 100 using LZC. In particular, the plot 1000 shows the area of the floating point add circuit as compared to the convergence time in nanoseconds (i.e., the time to produce the resulting floating point result or output).

[0145] The curve 1002 shows the area and convergence time of a single precision floating point add circuit including the fixed point add circuit 100 using LZC of Figure 1 ; the curve 1004 shows the area and convergence time of a single precision floating point add circuit including the fixed point add circuit 200 with LZA of Figure 2 , which has a window-based proxy string generation circuit implementing equation (5); and the curve 1006 shows the area and convergence time of a single precision floating point add circuit including the fixed point add circuit 200 with LZA of Figure 2 , which has a window-based proxy string generation circuit implementing equation (7).

[0146] Thus, the fixed point add circuit 200 with LZA with a window-based proxy string generation circuit 404 produces a 15% faster floating point add circuit whether implementing equation (5) or equation (7) than the conventional floating point add circuit using the fixed point add circuit 100 with LZC. However, this is at the expense of additional area for the circuit. Thus, the methods and principles described herein can be particularly applicable to time-critical applications.

[0147] The terms "processor" and "computer" are used herein to refer to any device or portion of a device that has processing capability such that it can execute instructions. The term "processor" can include, by way of example, a central processing unit (CPU), a graphics processing unit (GPU or VPU), a physics processing unit (PPU), a radio processing unit (RPU), a digital signal processor (DSP), a general purpose processor, a microprocessor, any processing unit designed to accelerate tasks outside of the CPU, and the like. Those skilled in the art will recognize how such processing capabilities are incorporated into many different devices, and therefore, the term "computer" includes set-top boxes, media players, digital radios, PCs, servers, mobile telephones, personal digital assistants, and many other devices.

[0148] Those skilled in the art will recognize that the storage devices used to store program instructions can be distributed across a network. For example, a remote computer can store an example of the processes described as software. A local or terminal computer can access the remote computer and download a part or all of the software needed to operate the processes. Alternatively, a local computer can download pieces of software as needed, or execute some software instructions and then download additional software instructions to perform further stages of the processes. Those skilled in the art will also recognize that at least a portion of the software instructions can be executed on specialized computer(s) such as DSP(s), programmable logic arrays, and the like.

[0149] The methods described herein can be performed by a computer configured with software, the software being stored in a machine-readable form on a tangible storage medium such as in the form of a computer program comprising computer readable program code for configuring a computer to perform the steps of the methods described, or in the form of a computer program code means adapted to perform all the steps of any of the methods described herein, when the program is run on a computer and where the computer program is implementable on a computer readable storage medium. Examples of tangible (or non-transitory) storage media include magnetic disks, thumb drives, memory cards and the like, and do not include propagated signals. The software can be adapted to be executed on a parallel processor or a serial processor such that the method steps can be performed in any suitable order or simultaneously.

[0150] The hardware components described herein can be generated from a non-transitory computer readable storage medium having computer readable program code thereon.

[0151] It is also intended to include software which "describes" or defines the configuration of hardware, such as HDL (hardware description language) software, as opposed to being intended to cause a machine to perform a function described by the hardware. That is, the computer system can be configured to generate a representation of a digital circuit from data defining circuit elements and rules for combining those circuit elements, where the non-transitory computer-readable storage medium can have stored thereon processor-executable instructions that, when executed at such a computer system, cause the computer system to generate a processing unit as described herein. For example, the non-transitory computer-readable storage medium can have stored thereon computer-readable instructions that, when processed at a computer system for generating a representation of an integrated circuit, cause that computer system to generate a representation of a leading zero predictor as described in examples herein, or to generate a representation of a leading zero predictor configured to perform a method as described in examples herein. The representation of the leading zero predictor can be the leading zero predictor itself, or a representation of the leading zero predictor (e.g., a mask) that can be used to generate the leading zero predictor.

[0152] Memory that stores machine-executable data for implementing the disclosed aspects can be non-transitory media. Non-transitory media can be volatile or non-volatile. Examples of volatile non-transitory media include semiconductor-based memory such as SRAM or DRAM. Examples of technologies that can be used to implement non-volatile memory include optical and magnetic storage technologies, flash memory, phase change memory, resistive RAM.

[0153] A specific reference to "logic" relates to structure that performs one or more functions. Examples of logic include circuitry arranged to perform those functions. For example, such circuitry can include transistors and / or other hardware elements available in a manufacturing process. As examples, such transistors and / or other elements can be used to form circuitry or structures that implement and / or contain memory (such as registers, flip-flops, or latches), logic operators (such as Boolean operators), mathematical operators (such as adders, multipliers, or shifters), and interconnects. Such elements can be provided as custom circuitry or standard cell libraries, macros, or at other levels of abstraction. Such elements can be interconnected in a particular arrangement. Logic can include fixed-function circuitry, and circuitry can be programmed to perform one or more functions; such programming can be provided from firmware or software updates or control mechanisms. Logic identified to perform one function can also include logic that implements constituent part functions or sub-processes. In examples, hardware logic has circuitry that implements a fixed-function operation or multiple operations, state machines, or processes.

[0154] Any ranges or device values given herein can be extended or modified without losing the intended effect, as will be apparent to the skilled person.

[0155] It will be understood that the benefits and advantages described above can relate to one embodiment or can relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.

[0156] Any reference to "one" item or "one" process means one or more of those items or processes. The term "including" is used herein to mean, and is used interchangeably with, the phrase "including but not limited to." The phrase "associated with" is used herein to describe a relationship with respect to which a change in one member of the relationship can cause a change in another member of the relationship. But one member of the relationship or the other member of the relationship can be changed without causing changes in the other member of the relationship. The term "coupled" is used herein to describe one or more electrical or physical connections between two items. The term "circuit" is used herein to describe one or more electrical circuits, which can include fixed function circuitry and / or circuitry that is programmed to perform one or more functions. The term "circuitry" is used herein to describe one or more electrical circuits and / or one or more components of electrical circuits.

[0157] The steps of the methods described herein can be performed in any suitable order or simultaneously, where appropriate. The arrows between blocks in the figures show one example order of method steps, but are not intended to exclude other orders or performing multiple steps in parallel. Furthermore, individual blocks can be removed from any method without departing from the spirit and scope of the subject matter described herein. Aspects of any of the examples described above can be combined with aspects of any of the other described examples to form further examples without losing the sought effect. Where elements of the figures are shown connected by arrows, it will be recognized that these arrows show only one example flow of communication (including data and control messages) between the elements. The flow can be in either direction or in both directions between the elements.

[0158] It should be understood that the foregoing description of preferred embodiments is by way of example only, and various modifications can be made by those skilled in the art. While various embodiments have been described above, it should be understood that they have been presented by way of example only, and various changes in form and details can be made without departing from the spirit or scope of the application.

Claims

1. A leading zero predictor configured to estimate the number of leading zeros in the result of an arithmetic operation performed on two or more fixed-point numbers, the leading zero predictor comprising: An input encoding circuit is configured to generate an encoded input string from the two or more fixed-point numbers, wherein the i-th position of the encoded input string indicates the number of high-order bits in the i-th bit position of the fixed-point number; A window-based proxy string generation circuit is configured as follows: The proxy string is generated by examining a continuous window of the encoded input string and setting the corresponding bit of the proxy string based on the examination. The leading bit of the proxy string is an estimate of the leading bit in the result of the arithmetic operation, and the estimate of the leading bit is within a digit position of the leading bit in the actual result of the arithmetic operation on any signed fixed-point number. as well as When the window corresponding to the encoded input string includes a pattern that always indicates that one of the i-th and (i+1)-th bits of the result of the arithmetic operation will be high, the i-th bit of the proxy string is set to a high value; as well as A counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

2. The leading zero predictor according to claim 1, wherein, The window for encoding the input string includes a predetermined number of consecutive positions of the encoded input string.

3. The leading zero predictor according to claim 2, wherein, The window-based proxy string generation circuit is configured to generate the i-th position of the proxy string based on the i-th window of the encoded input string, the i-th window including the predetermined number of consecutive positions of the encoded input string starting from the i-th position and including the i-th position.

4. The leading zero predictor according to any of the preceding claims, wherein, The input encoding circuit is configured to set the i-th position of the encoded input string to a position based on how many of the i-th bits of the fixed-point number are high. , or one of the.

5. The leading zero predictor according to claim 4, wherein, There are two fixed-point numbers, and the input encoding circuit is configured such that when both of the i-th bits of the fixed-point numbers are low, the i-th position of the encoded input string is set to... When only one of the i-th bits of the fixed-point number is high, the i-th position of the encoded input string is set to... ; and when both of the i-th bits of the fixed-point number are high, the i-th position of the encoded input string is set to .

6. The leading zero predictor according to claim 4, wherein, The window-based proxy string generation circuit is configured to set the proxy string according to the following equation. The i-th position: ,in It is a zero function. For transfer functions, This is a generating function.

7. The leading zero predictor according to claim 4, wherein, The window-based proxy string generation circuit is configured to set the inverted proxy string according to the following equation. The i-th position: ,in It is a zero function. For transfer functions, This is a generating function.

8. A method for estimating the number of leading zeros in the result of an arithmetic operation performed on two or more fixed-point numbers, the method comprising: An input encoding circuit is used to generate an encoded input string from the two or more fixed-point numbers, wherein the i-th position of the encoded input string indicates the number of high-order bits in the i-th position of the fixed-point number; A window-based surrogate string generation circuit is used to generate the surrogate string by examining a continuous window of the encoded input string and setting the corresponding bit of the surrogate string based on the examination. The leading bit of the surrogate string is an estimate of the leading bit in the result of the arithmetic operation, and the estimate of the leading bit is within a digit position (600, 700) of the leading bit in the actual result of the arithmetic operation on any signed fixed-point number. When the window corresponding to the encoded input string includes a pattern that always indicates that one of the i-th and (i+1)-th bits of the result of the arithmetic operation will be high, the i-th bit of the proxy string is set to a high value; as well as Based on the leading zero in the surrogate string, a counter circuit is used to estimate the number of leading zeros in the result of the arithmetic operation.

9. The method according to claim 8, wherein, The window for encoding the input string includes a predetermined number of consecutive positions of the encoded input string.

10. The method according to claim 9, wherein, Generating the proxy string includes setting the i-th position of the proxy string based on the i-th window of the encoded input string, wherein the i-th window includes a predetermined number of consecutive positions of the encoded input string starting from the i-th position and including the i-th position.

11. The method according to any one of claims 8 to 10, wherein, Generating the encoded input string involves determining how many of the i-th bits of the fixed-point number are high, and setting the i-th position of the encoded input string to... , or one of the.

12. The method according to claim 11, wherein, Having two fixed-point numbers and generating the encoded input string includes: when both of the i-th bits of the fixed-point numbers are low, setting the i-th position of the encoded input string to... When only one of the i-th bits of the fixed-point number is high, the i-th position of the encoded input string is set to... ; and when both of the i-th bits of the fixed-point number are high, the i-th position of the encoded input string is set to .

13. The method according to claim 11, wherein, Generating the proxy string includes setting the proxy string according to the following equation. The i-th position: ,in It is a zero function. For transfer functions, This is a generating function.

14. The method according to claim 11, wherein, Generating the proxy string includes setting the inverse of the proxy string according to the following equation. The i-th position: ,in It is a zero function. For transfer functions, This is a generating function.

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